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PDP11: Add initial UC15 support from Bob Supnik

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Paul Koning 2017-02-04 12:19:41 -08:00 • committed by Mark Pizzolato
parent 733653092f
commit 998cf5c122
3 changed files with 87 additions and 29 deletions
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54
PDP11/pdp11_cpu.c
View file

@ -25,6 +25,9 @@
cpu PDP-11 CPU
04-Dec-16 RMS Removed duplicate IDLE entries in MTAB
30-Aug-16 RMS Fixed overloading of -d in ex/mod
14-Mar-16 RMS Added UC15 support
06-Mar-16 RMS Fixed bug in history virtual addressing
30-Dec-15 RMS Added NOBEVENT option for 11/03, 11/23
29-Dec-15 RMS Call build_dib_tab during reset (Mark Pizzolato)
@ -295,9 +298,9 @@ int32 stop_vecabort = 1; /* stop on vec abort */
int32 stop_spabort = 1; /* stop on SP abort */
int32 wait_enable = 0; /* wait state enable */
int32 autcon_enb = 1; /* autoconfig enable */
uint32 cpu_model = MOD_1173; /* CPU model */
uint32 cpu_type = 1u << MOD_1173; /* model as bit mask */
uint32 cpu_opt = SOP_1173; /* CPU options */
uint32 cpu_model = INIMODEL; /* CPU model */
uint32 cpu_type = 1u << INIMODEL; /* model as bit mask */
uint32 cpu_opt = INIOPTNS; /* CPU options */
uint16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
int32 pcq_p = 0; /* PC queue ptr */
REG *pcq_r = NULL; /* PC queue reg ptr */
@ -306,7 +309,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
t_addr cpu_memsize = INIMEMSIZE; /* last mem addr */
int16 inst_pc; /* PC of current instr */
int32 inst_psw; /* PSW at instr. start */
int16 reg_mods; /* reg deltas */
@ -586,6 +588,7 @@ REG cpu_reg[] = {
MTAB cpu_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0, "TYPE", NULL,
NULL, &cpu_show_model },
#if !defined (UC15)
{ MTAB_XTD|MTAB_VDV, MOD_1103, NULL, "11/03", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1104, NULL, "11/04", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1105, NULL, "11/05", &cpu_set_model },
@ -622,8 +625,6 @@ MTAB cpu_mod[] = {
{ MTAB_XTD|MTAB_VDV, OPT_MMU, NULL, "NOMMU", &cpu_clr_opt },
{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "BEVENT", &cpu_set_opt, NULL, NULL, "Enable BEVENT line (11/03, 11/23 only)" },
{ MTAB_XTD|MTAB_VDV, OPT_BVT, NULL, "NOBEVENT", &cpu_clr_opt, NULL, NULL, "Disable BEVENT line (11/03, 11/23 only)" },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size},
{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size},
@ -644,12 +645,22 @@ MTAB cpu_mod[] = {
{ UNIT_MSIZE, 2097152, NULL, "2M", &cpu_set_size},
{ UNIT_MSIZE, 3145728, NULL, "3M", &cpu_set_size},
{ UNIT_MSIZE, 4186112, NULL, "4M", &cpu_set_size},
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
{ MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
&set_autocon, &show_autocon },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
&set_autocon, NULL },
#else
{ MTAB_XTD|MTAB_VDV, MOD_1104, NULL, "11/04", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1105, NULL, "11/05", &cpu_set_model },
{ MTAB_XTD|MTAB_VDV, MOD_1120, NULL, "11/20", &cpu_set_model },
{ UNIT_MSIZE, 16384, NULL, "16K", &cpu_set_size},
{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size},
{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size},
#endif
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
NULL, &show_iospace },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
&cpu_set_hist, &cpu_show_hist },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
@ -703,9 +714,8 @@ sim_vm_pc_value = &pdp11_pc_value;
reason = build_dib_tab (); /* build, chk dib_tab */
if (reason != SCPE_OK)
return reason;
if (MEMSIZE < cpu_tab[cpu_model].maxm) /* mem size < max? */
cpu_memsize = MEMSIZE; /* then okay */
else cpu_memsize = cpu_tab[cpu_model].maxm - IOPAGESIZE;/* max - io page */
if (MEMSIZE >= (cpu_tab[cpu_model].maxm - IOPAGESIZE)) /* mem size >= max - io page? */
MEMSIZE = cpu_tab[cpu_model].maxm - IOPAGESIZE; /* max - io page */
cpu_type = 1u << cpu_model; /* reset type mask */
cpu_bme = (MMR3 & MMR3_BME) && (cpu_opt & OPT_UBM); /* map enabled? */
PC = saved_PC;
@ -2601,7 +2611,7 @@ if (BPT_SUMM_RD &&
sim_brk_test (pa, BPT_RDPHY))) /* read breakpoint? */
ABORT (ABRT_BKPT); /* stop simulation */
if (ADDR_IS_MEM (pa)) /* memory address? */
return (M[pa >> 1]);
return RdMemW (pa);
if ((pa < IOPAGEBASE) || /* not I/O address */
(CPUT (CPUT_J) && (pa >= IOBA_CPU))) { /* or J11 int reg? */
setCPUERR (CPUE_NXM);
@ -2690,7 +2700,7 @@ int32 PReadW (int32 pa)
int32 data;
if (ADDR_IS_MEM (pa)) /* memory address? */
return (M[pa >> 1]);
return RdMemW (pa);
if (pa < IOPAGEBASE) { /* not I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM);
@ -2706,8 +2716,8 @@ int32 PReadB (int32 pa)
{
int32 data;
if (ADDR_IS_MEM (pa))
return (pa & 1? M[pa >> 1] >> 8: M[pa >> 1]) & 0377;
if (ADDR_IS_MEM (pa)) /* memory address? */
return RdMemB (pa);
if (pa < IOPAGEBASE) { /* not I/O address? */
setCPUERR (CPUE_NXM);
ABORT (TRAP_NXM);
@ -2778,7 +2788,7 @@ PWriteW (data, pa);
void PWriteW (int32 data, int32 pa)
{
if (ADDR_IS_MEM (pa)) { /* memory address? */
M[pa >> 1] = data;
WrMemW (pa, data);
return;
}
if (pa < IOPAGEBASE) { /* not I/O address? */
@ -2795,9 +2805,7 @@ return;
void PWriteB (int32 data, int32 pa)
{
if (ADDR_IS_MEM (pa)) { /* memory address? */
if (pa & 1)
M[pa >> 1] = (M[pa >> 1] & 0377) | (data << 8);
else M[pa >> 1] = (M[pa >> 1] & ~0377) | data;
WrMemB (pa, data);
return;
}
if (pa < IOPAGEBASE) { /* not I/O address? */
@ -3444,8 +3452,8 @@ if (sw & SWMASK ('V')) { /* -v */
if (addr >= MAXMEMSIZE)
return SCPE_REL;
}
if (addr < MEMSIZE) {
*vptr = M[addr >> 1] & 0177777;
if (ADDR_IS_MEM (addr)) {
*vptr = RdMemW (addr) & 0177777;
return SCPE_OK;
}
if (addr < IOPAGEBASE)
@ -3466,8 +3474,8 @@ if (sw & SWMASK ('V')) { /* -v */
if (addr >= MAXMEMSIZE)
return SCPE_REL;
}
if (addr < MEMSIZE) {
M[addr >> 1] = val & 0177777;
if (ADDR_IS_MEM (addr)) {
WrMemW (addr, val & 0177777);
return SCPE_OK;
}
if (addr < IOPAGEBASE)

9
PDP11/pdp11_cr.c
View file

@ -1,6 +1,6 @@
/* pdp11_cr.c: CR/CM/CD-11/CD20 card reader simulator
Copyright (c) 2005-2010, John A. Dundas III
Copyright (c) 2005-2016, John A. Dundas III
Portions derived from work by Douglas W. Jones, jones@cs.uiowa.edu
Portions derived from work by Robert M Supnik
@ -100,6 +100,7 @@
ECOs (at least) for Data Buffer status and augmented image mode.
Revision History:
14-Mar-16 RMS Added UC15 support (CR11 only)
23-Feb-13 JGP Added DEC version of the 026 codepage
Fixed the handling of the CR11 error bits after
a control register write.
@ -221,10 +222,12 @@ extern int32 int_req[IPL_HLVL];
#define DFLT_DIS (DEV_QBUS) /* CR11 is programmed I/O only, Qbus OK */
#define DFLT_TYPE (UNIT_CR11) /* Default, but changable */
#define DFLT_CPM 285
#define CR11_ONLY (1)
#if !defined (UC15)
#define CD11_OK (1) /* only on real PDP-11 */
#define CD20_OK (1)
#define AIECO_OK (1) /* Augmented Image ECO optional */
#define CR11_OK (1)
#define CD11_OK (1)
#endif
#endif
/* **** No VM_xxx macros should be referenced after this line **** */

53
PDP11/pdp11_defs.h
View file

@ -27,6 +27,7 @@
and John Wilson in resolving questions about the PDP-11
06-Jan-17 RMS Moved CR11/CD11 to BR6 (Mark Pizzolato)
10-Mar-16 RMS Added UC15 support
30-Dec-15 RMS Added NOBVT option
23-Oct-13 RMS Added cpu_set_boot prototype
02-Sep-13 RMS Added third Massbus adapter and RS drive
@ -97,7 +98,6 @@
#define VASIZE 0200000 /* 2**16 */
#define VAMASK (VASIZE - 1) /* 2**16 - 1 */
#define MEMSIZE64K 0200000 /* 2**16 */
#define INIMEMSIZE 001000000 /* 2**18 */
#define UNIMEMSIZE 001000000 /* 2**18 */
#define UNIMASK (UNIMEMSIZE - 1) /* 2**18 - 1 */
#define IOPAGEBASE 017760000 /* 2**22 - 2**13 */
@ -106,7 +106,6 @@
#define MAXMEMSIZE 020000000 /* 2**22 */
#define PAMASK (MAXMEMSIZE - 1) /* 2**22 - 1 */
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((t_addr) (x)) < cpu_memsize) /* use only in sim! */
#define DMASK 0177777
#define BMASK 0377
@ -543,6 +542,11 @@ typedef struct pdp_dib DIB;
#define IOBA_CTL (IOPAGEBASE + 017520) /* board ctrl */
#define IOLN_CTL 010
#define IOBA_UCA (IOPAGEBASE + 007770) /* UC15 DR11 #1 */
#define IOLN_UCA 006
#define IOBA_UCB (IOPAGEBASE + 007760) /* UC15 DR11 #2 */
#define IOLN_UCB 006
#define IOBA_UBM (IOPAGEBASE + 010200) /* Unibus map */
#define IOLN_UBM (UBM_LNT_LW * sizeof (int32))
#define IOBA_MMR3 (IOPAGEBASE + 012516) /* MMR3 */
@ -590,6 +594,7 @@ typedef struct pdp_dib DIB;
#define IPL_HMIN 4 /* lowest IO int level */
#define INT_V_PIR7 0 /* BR7 */
#define INT_V_UCA 1
#define INT_V_PIR6 0 /* BR6 */
#define INT_V_CLK 1
@ -623,6 +628,7 @@ typedef struct pdp_dib DIB;
#define INT_V_DUPTX 22
#define INT_V_KMCA 23
#define INT_V_KMCB 24
#define INT_V_UCB 25
#define INT_V_PIR4 0 /* BR4 */
#define INT_V_TTI 1
@ -652,6 +658,7 @@ typedef struct pdp_dib DIB;
#define INT_V_PIR1 0 /* BR1 */
#define INT_PIR7 (1u << INT_V_PIR7)
#define INT_UCB (1u << INT_V_UCB)
#define INT_PIR6 (1u << INT_V_PIR6)
#define INT_CLK (1u << INT_V_CLK)
#define INT_PCLK (1u << INT_V_PCLK)
@ -682,6 +689,7 @@ typedef struct pdp_dib DIB;
#define INT_KMCB (1u << INT_V_KMCB)
#define INT_DUPRX (1u << INT_V_DUPRX)
#define INT_DUPTX (1u << INT_V_DUPTX)
#define INT_UCA (1u << INT_V_UCA)
#define INT_PIR4 (1u << INT_V_PIR4)
#define INT_TTI (1u << INT_V_TTI)
#define INT_TTO (1u << INT_V_TTO)
@ -714,7 +722,8 @@ typedef struct pdp_dib DIB;
#define INT_INTERNAL2 (INT_PIR2)
#define INT_INTERNAL1 (INT_PIR1)
#define IPL_CLK 6 /* int pri levels */
#define IPL_UCB 7 /* int pri levels */
#define IPL_CLK 6
#define IPL_PCLK 6
#define IPL_DTA 6
#define IPL_TA 6
@ -743,6 +752,7 @@ typedef struct pdp_dib DIB;
#define IPL_KMCB 5
#define IPL_DUPRX 5
#define IPL_DUPTX 5
#define IPL_UCA 5
#define IPL_PTR 4
#define IPL_PTP 4
#define IPL_TTI 4
@ -779,6 +789,8 @@ typedef struct pdp_dib DIB;
#define VEC_PIRQ 0240
#define VEC_TTI 0060
#define VEC_TTO 0064
#define VEC_UCA 0300
#define VEC_UCB 0310
/* Interrupt macros */
@ -850,4 +862,39 @@ void cpu_set_boot (int32 pc);
#include "pdp11_io_lib.h"
#if defined (UC15) /* UC15 */
#define INIMODEL MOD_1105
#define INIOPTNS SOP_1105
#define INIMEMSIZE 00040000 /* 16KB */
#define ADDR_IS_MEM(x) (((uint32) (x)) < uc15_memsize)
#define RdMemW(pa) uc15_RdMemW (pa)
#define RdMemB(pa) uc15_RdMemB (pa)
#define WrMemW(pa,d) uc15_WrMemW (pa, d)
#define WrMemB(pa, d) uc15_WrMemB (pa, d)
uint32 uc15_memsize;
int32 uc15_RdMemW (int32 pa);
int32 uc15_RdMemB (int32 pa);
void uc15_WrMemW (int32 pa, int32 d);
void uc15_WrMemB (int32 pa, int32 d);
int32 Map_Read18 (uint32 ba, int32 bc, uint32 *buf);
int32 Map_Write18 (uint32 ba, int32 bc, uint32 *buf);
#else /* PDP-11 */
#define INIMODEL MOD_1173
#define INIOPTNS SOP_1173
#define INIMEMSIZE 001000000 /* 2**18 */
#define ADDR_IS_MEM(x) (((t_addr) (x)) < MEMSIZE)
#define RdMemW(pa) (M[(pa) >> 1])
#define RdMemB(pa) ((((pa) & 1)? M[(pa) >> 1] >> 8: M[(pa) >> 1]) & 0377)
#define WrMemW(pa,d) M[(pa) >> 1] = (d)
#define WrMemB(pa,d) M[(pa) >> 1] = ((pa) & 1)? \
((M[(pa) >> 1] & 0377) | (((d) & 0377) << 8)): \
((M[(pa) >> 1] & ~0377) | ((d) & 0377))
#endif
#endif