From 9b458336874e4f648c43df1fb2573d8e0b80638b Mon Sep 17 00:00:00 2001
From: Mark Pizzolato <mark@infocomm.com>
Date: Wed, 18 Nov 2015 10:51:37 -0800
Subject: [PATCH] VAX, PDP11: Add support to, by default, limit console input
 data to about 9600bps.

This is necessary to avoid kernel type ahead buffer overruns when a user
pastes a chunk of data into a console session as described in issue #246

Other console input speeds can be set with SET CONSOLE SPEED=nnn
---
 PDP11/pdp11_stddev.c | 4 ++--
 VAX/vax610_stddev.c  | 4 ++--
 VAX/vax630_stddev.c  | 4 ++--
 VAX/vax730_stddev.c  | 4 ++--
 VAX/vax750_stddev.c  | 4 ++--
 VAX/vax780_stddev.c  | 4 ++--
 VAX/vax_stddev.c     | 4 ++--
 7 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/PDP11/pdp11_stddev.c b/PDP11/pdp11_stddev.c
index d6457a2e..cc53b86d 100644
--- a/PDP11/pdp11_stddev.c
+++ b/PDP11/pdp11_stddev.c
@@ -114,7 +114,7 @@ DIB tti_dib = {
     1, IVCL (TTI), VEC_TTI, { NULL }
     };
 
-UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT };
+UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), TMLN_SPD_9600_BPS };
 
 REG tti_reg[] = {
     { HRDATAD (BUF,       tti_unit.buf,          8, "last data item processed") },
@@ -259,7 +259,7 @@ switch ((PA >> 1) & 01) {                               /* decode PA<1> */
         tti_csr = tti_csr & ~CSR_DONE;
         CLR_INT (TTI);
         *data = tti_unit.buf & 0377;
-        sim_activate_abs (&tti_unit, tti_unit.wait);    /* check soon for more input */
+        sim_activate_after_abs (&tti_unit, tti_unit.wait);  /* check soon for more input */
         return SCPE_OK;
         }                                               /* end switch PA */
 
diff --git a/VAX/vax610_stddev.c b/VAX/vax610_stddev.c
index 2680f602..6d54014c 100644
--- a/VAX/vax610_stddev.c
+++ b/VAX/vax610_stddev.c
@@ -107,7 +107,7 @@ extern int32 con_halt (int32 code, int32 cc);
 
 DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
 
-UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
+UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
 
 REG tti_reg[] = {
     { HRDATAD (BUF,     tti_unit.buf,         16, "last data item processed") },
@@ -239,7 +239,7 @@ if (tti_csr & CSR_DONE) {                               /* Input pending ? */
     tti_csr = tti_csr & ~CSR_DONE;                      /* clr done */
     tti_unit.buf = tti_unit.buf & 0377;                 /* clr errors */
     CLR_INT (TTI);
-    sim_activate_abs (&tti_unit, tti_unit.wait);        /* check soon for more input */
+    sim_activate_after_abs (&tti_unit, tti_unit.wait);  /* check soon for more input */
     }
 return t;
 }
diff --git a/VAX/vax630_stddev.c b/VAX/vax630_stddev.c
index 09ae4b4b..a0bfd7c6 100644
--- a/VAX/vax630_stddev.c
+++ b/VAX/vax630_stddev.c
@@ -82,7 +82,7 @@ extern int32 sysd_hlt_enb (void);
 
 DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
 
-UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
+UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
 
 REG tti_reg[] = {
     { HRDATAD (BUF,     tti_unit.buf,         16, "last data item processed") },
@@ -215,7 +215,7 @@ if (tti_csr & CSR_DONE) {                               /* Input pending ? */
     tti_csr = tti_csr & ~CSR_DONE;                      /* clr done */
     tti_unit.buf = tti_unit.buf & 0377;                 /* clr errors */
     CLR_INT (TTI);
-    sim_activate_abs (&tti_unit, tti_unit.wait);        /* check soon for more input */
+    sim_activate_after_abs (&tti_unit, tti_unit.wait);  /* check soon for more input */
     }
 return t;
 }
diff --git a/VAX/vax730_stddev.c b/VAX/vax730_stddev.c
index 7cac44ba..b6262b45 100644
--- a/VAX/vax730_stddev.c
+++ b/VAX/vax730_stddev.c
@@ -219,7 +219,7 @@ t_stat txdb_misc_wr (int32 data);
    tti_reg      TTI register list
 */
 
-UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
+UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
 
 REG tti_reg[] = {
     { HRDATAD (RXDB,       tti_buf,         16, "last data item processed") },
@@ -480,7 +480,7 @@ if (tti_csr & CSR_DONE) {                               /* Input pending ? */
     tti_csr = tti_csr & ~CSR_DONE;                      /* clr done */
     tti_buf = tti_buf & BMASK;                          /* clr errors */
     tti_int = 0;
-    sim_activate_abs (&tti_unit, tti_unit.wait);        /* check soon for more input */
+    sim_activate_after_abs (&tti_unit, tti_unit.wait);  /* check soon for more input */
     }
 return t;
 }
diff --git a/VAX/vax750_stddev.c b/VAX/vax750_stddev.c
index 5d60413d..e7e1622a 100644
--- a/VAX/vax750_stddev.c
+++ b/VAX/vax750_stddev.c
@@ -211,7 +211,7 @@ extern int32 con_halt (int32 code, int32 cc);
    tti_reg      TTI register list
 */
 
-UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
+UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
 
 REG tti_reg[] = {
     { HRDATAD (RXDB,       tti_buf,         16, "last data item processed") },
@@ -474,7 +474,7 @@ if (tti_csr & CSR_DONE) {                               /* Input pending ? */
     tti_csr = tti_csr & ~CSR_DONE;                      /* clr done */
     tti_buf = tti_buf & BMASK;                          /* clr errors */
     tti_int = 0;
-    sim_activate_abs (&tti_unit, tti_unit.wait);        /* check soon for more input */
+    sim_activate_after_abs (&tti_unit, tti_unit.wait);  /* check soon for more input */
     }
 return t;
 }
diff --git a/VAX/vax780_stddev.c b/VAX/vax780_stddev.c
index ba062149..e9fb5952 100644
--- a/VAX/vax780_stddev.c
+++ b/VAX/vax780_stddev.c
@@ -259,7 +259,7 @@ extern int32 con_halt (int32 code, int32 cc);
    tti_reg      TTI register list
 */
 
-UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
+UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
 
 REG tti_reg[] = {
     { HRDATAD (RXDB,       tti_buf,         16, "last data item processed") },
@@ -444,7 +444,7 @@ if (tti_csr & CSR_DONE) {                               /* Input pending ? */
     tti_csr = tti_csr & ~CSR_DONE;                      /* clr done */
     tti_buf = tti_buf & BMASK;                          /* clr errors */
     tti_int = 0;
-    sim_activate_abs (&tti_unit, tti_unit.wait);        /* check soon for more input */
+    sim_activate_after_abs (&tti_unit, tti_unit.wait);  /* check soon for more input */
     }
 return t;
 }
diff --git a/VAX/vax_stddev.c b/VAX/vax_stddev.c
index c59a87fb..30227dd7 100644
--- a/VAX/vax_stddev.c
+++ b/VAX/vax_stddev.c
@@ -139,7 +139,7 @@ extern int32 fault_PC;
 
 DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
 
-UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT };
+UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS };
 
 REG tti_reg[] = {
     { HRDATAD (BUF,     tti_unit.buf,         16, "last data item processed") },
@@ -278,7 +278,7 @@ if (tti_csr & CSR_DONE) {                               /* Input pending ? */
     tti_csr = tti_csr & ~CSR_DONE;                      /* clr done */
     tti_unit.buf = tti_unit.buf & 0377;                 /* clr errors */
     CLR_INT (TTI);
-    sim_activate_abs (&tti_unit, tti_unit.wait);        /* check soon for more input */
+    sim_activate_after_abs (&tti_unit, tti_unit.wait);  /* check soon for more input */
     }
 return t;
 }