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B5500: Updated u-variable to names, updated to handle new translations.

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This commit is contained in:
Richard Cornwell 2019-01-13 22:39:27 -05:00
parent 0ef5776e52
commit 9b631bffc5
5 changed files with 441 additions and 375 deletions
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189
B5500/b5500_dk.c
View file

@ -29,6 +29,11 @@
/* in u3 is device address */ /* in u3 is device address */
/* in u4 is current buffer position */ /* in u4 is current buffer position */
/* in u5 Bits 30-16 of W */ /* in u5 Bits 30-16 of W */
#define ESU u3
#define ADDR u4
#define CMD u5
#define POS u6
#define URCSTA_SKIP 000017 /* Skip mask */ #define URCSTA_SKIP 000017 /* Skip mask */
#define URCSTA_SINGLE 000020 /* Single space skip. */ #define URCSTA_SINGLE 000020 /* Single space skip. */
#define URCSTA_DOUBLE 000040 /* Double space skip */ #define URCSTA_DOUBLE 000040 /* Double space skip */
@ -153,31 +158,31 @@ t_stat dsk_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
return SCPE_NODEV; return SCPE_NODEV;
/* Check if drive is ready to recieve a command */ /* Check if drive is ready to recieve a command */
if ((uptr->u5 & DK_BSY)) if ((uptr->CMD & DK_BSY))
return SCPE_BUSY; return SCPE_BUSY;
uptr->u5 = chan|DK_BSY; uptr->CMD = chan|DK_BSY;
if (dev == DSK2_DEV) if (dev == DSK2_DEV)
uptr->u5 |= DK_CTRL; uptr->CMD |= DK_CTRL;
uptr->u5 |= (cmd & 077) << 12; uptr->CMD |= (cmd & 077) << 12;
if (cmd & URCSTA_INHIBIT) if (cmd & URCSTA_INHIBIT)
uptr->u5 |= DK_RDCK; uptr->CMD |= DK_RDCK;
else if (cmd & URCSTA_READ) else if (cmd & URCSTA_READ)
uptr->u5 |= DK_RD; uptr->CMD |= DK_RD;
else else
uptr->u5 |= DK_WR; uptr->CMD |= DK_WR;
if (cmd & URCSTA_WC) { if (cmd & URCSTA_WC) {
uptr->u5 |= DK_WC; uptr->CMD |= DK_WC;
if (*wc == 0) if (*wc == 0)
uptr->u5 |= DK_WCZERO; uptr->CMD |= DK_WCZERO;
} }
if (cmd & URCSTA_BINARY) if (cmd & URCSTA_BINARY)
uptr->u5 |= DK_BIN; uptr->CMD |= DK_BIN;
if (loading) { if (loading) {
uptr->u4 = 1; uptr->ADDR = 1;
uptr->u3 = 0; uptr->ESU = 0;
} else { } else {
uptr->u5 |= DK_ADDR; uptr->CMD |= DK_ADDR;
} }
sim_activate(uptr, 100); sim_activate(uptr, 100);
return SCPE_OK; return SCPE_OK;
@ -187,7 +192,7 @@ t_stat dsk_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
/* Handle processing disk controller commands */ /* Handle processing disk controller commands */
t_stat dsk_srv(UNIT * uptr) t_stat dsk_srv(UNIT * uptr)
{ {
int chan = uptr->u5 & DK_CHAN; int chan = uptr->CMD & DK_CHAN;
DEVICE *dptr = find_dev_from_unit(uptr); DEVICE *dptr = find_dev_from_unit(uptr);
int i; int i;
int addr; int addr;
@ -196,13 +201,13 @@ t_stat dsk_srv(UNIT * uptr)
int esu; int esu;
UNIT *eptr; UNIT *eptr;
if ((uptr->u5 & DK_BSY) == 0) if ((uptr->CMD & DK_BSY) == 0)
return SCPE_OK; return SCPE_OK;
/* Read in first word, which a address. */ /* Read in first word, which a address. */
/* Note special read routine since address is not included /* Note special read routine since address is not included
in the word count */ in the word count */
if (uptr->u5 & DK_ADDR) { if (uptr->CMD & DK_ADDR) {
/* Read in 8 characters which are the address */ /* Read in 8 characters which are the address */
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
if (chan_read_disk(chan, &abuf[i], 0)) if (chan_read_disk(chan, &abuf[i], 0))
@ -218,45 +223,45 @@ t_stat dsk_srv(UNIT * uptr)
for (i = 2; i < 8; i++) { for (i = 2; i < 8; i++) {
addr = (addr * 10) + abuf[i]; addr = (addr * 10) + abuf[i];
} }
uptr->u5 &= ~DK_ADDR; uptr->CMD &= ~DK_ADDR;
uptr->u4 = addr; uptr->ADDR = addr;
/* Map to ESU */ /* Map to ESU */
if (u && (dsk_unit[u].flags & DFX) == 0) if (u && (dsk_unit[u].flags & DFX) == 0)
esu += 10; esu += 10;
sim_debug(DEBUG_DETAIL, dptr, "Disk access %d %s %02o %d,%d\n\r", u, sim_debug(DEBUG_DETAIL, dptr, "Disk access %d %s %02o %d,%d\n\r", u,
(uptr->u5 & DK_RDCK) ? "rcheck" : (uptr->CMD & DK_RDCK) ? "rcheck" :
(uptr->u5 & DK_RD) ? "read" : (uptr->CMD & DK_RD) ? "read" :
(uptr->u5 & DK_WR)? "write" : "nop", (uptr->u5 >> 9) & 077, (uptr->CMD & DK_WR)? "write" : "nop", (uptr->CMD >> 9) & 077,
esu, addr); esu, addr);
uptr->u3 = esu; uptr->ESU = esu;
eptr = &esu_unit[uptr->u3]; eptr = &esu_unit[uptr->ESU];
/* Check if valid */ /* Check if valid */
if ((eptr->flags & UNIT_DIS) || (eptr->flags & UNIT_ATT) == 0) { if ((eptr->flags & UNIT_DIS) || (eptr->flags & UNIT_ATT) == 0) {
/* Set not ready and end channel */ /* Set not ready and end channel */
chan_set_notrdy(chan); chan_set_notrdy(chan);
uptr->u5 = 0; uptr->CMD = 0;
return SCPE_OK; return SCPE_OK;
} }
/* Check if Read Check or Write Check */ /* Check if Read Check or Write Check */
if ((uptr->u5 & (DK_WCZERO|DK_WC|DK_SECMASK)) == (DK_WCZERO|DK_WC)) { if ((uptr->CMD & (DK_WCZERO|DK_WC|DK_SECMASK)) == (DK_WCZERO|DK_WC)) {
if (uptr->u4 >= eptr->wait) if (uptr->ADDR >= eptr->wait)
chan_set_eof(chan); chan_set_eof(chan);
if (uptr->u5 & DK_WR) { if (uptr->CMD & DK_WR) {
sim_debug(DEBUG_DETAIL, dptr, "Disk write int %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk write int %d %d %o\n\r",
uptr->u3, uptr->u4, uptr->u5); uptr->ESU, uptr->ADDR, uptr->CMD);
} }
if (uptr->u5 & DK_RD) { if (uptr->CMD & DK_RD) {
sim_debug(DEBUG_DETAIL, dptr, "Disk read int %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk read int %d %d %o\n\r",
uptr->u3, uptr->u4, uptr->u5); uptr->ESU, uptr->ADDR, uptr->CMD);
if (eptr->flags & MODIB) if (eptr->flags & MODIB)
chan_set_error(chan); chan_set_error(chan);
} }
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = 0; uptr->CMD = 0;
return SCPE_OK; return SCPE_OK;
} }
@ -265,21 +270,21 @@ t_stat dsk_srv(UNIT * uptr)
} }
/* Kick off actual transfer to ESU */ /* Kick off actual transfer to ESU */
if (((uptr->u5 & DK_ADDR) == 0) && if (((uptr->CMD & DK_ADDR) == 0) &&
((uptr->u5 & (DK_RDCK|DK_RD|DK_WR)) != 0)) { ((uptr->CMD & (DK_RDCK|DK_RD|DK_WR)) != 0)) {
eptr = &esu_unit[uptr->u3]; eptr = &esu_unit[uptr->ESU];
/* Wait until unit is ready for new access */ /* Wait until unit is ready for new access */
if ((eptr->u5 & DK_BSY) == 0) { if ((eptr->CMD & DK_BSY) == 0) {
eptr->u3 = (uptr->u5 & DK_WR) ? 0 : DK_SEC_SIZE; eptr->POS = (uptr->CMD & DK_WR) ? 0 : DK_SEC_SIZE;
eptr->u4 = uptr->u4; /* Disk address */ eptr->ADDR = uptr->ADDR; /* Disk address */
eptr->u5 = uptr->u5; /* Command */ eptr->CMD = uptr->CMD; /* Command */
if (uptr->u5 & DK_RDCK) { if (uptr->CMD & DK_RDCK) {
uptr->u5 = 0; uptr->CMD = 0;
chan_set_end(chan); chan_set_end(chan);
} else } else
uptr->u5 &= ~(DK_RDCK|DK_RD|DK_WR); uptr->CMD &= ~(DK_RDCK|DK_RD|DK_WR);
sim_activate(eptr, 8000); sim_activate(eptr, 8000);
return SCPE_OK; return SCPE_OK;
} }
@ -289,51 +294,51 @@ t_stat dsk_srv(UNIT * uptr)
} }
void esu_set_end(UNIT *uptr, int err) { void esu_set_end(UNIT *uptr, int err) {
int chan = uptr->u5 & DK_CHAN; int chan = uptr->CMD & DK_CHAN;
int dsk = ((uptr->u5 & DK_CTRL) != 0); int dsk = ((uptr->CMD & DK_CTRL) != 0);
DEVICE *dptr = find_dev_from_unit(uptr); DEVICE *dptr = find_dev_from_unit(uptr);
sim_debug(DEBUG_DETAIL, dptr, "Disk done %d %d %o\n\r", uptr->u3, sim_debug(DEBUG_DETAIL, dptr, "Disk done %d %d %o\n\r", uptr->POS,
uptr->u4, uptr->u5); uptr->ADDR, uptr->CMD);
if (err) if (err)
chan_set_error(chan); chan_set_error(chan);
uptr->u5 = 0; uptr->CMD = 0;
dsk_unit[dsk].u5 = 0; dsk_unit[dsk].CMD = 0;
chan_set_end(chan); chan_set_end(chan);
} }
/* Handle processing esu controller commands */ /* Handle processing esu controller commands */
t_stat esu_srv(UNIT * uptr) t_stat esu_srv(UNIT * uptr)
{ {
int chan = uptr->u5 & DK_CHAN; int chan = uptr->CMD & DK_CHAN;
DEVICE *dptr = find_dev_from_unit(uptr); DEVICE *dptr = find_dev_from_unit(uptr);
int u = uptr - esu_unit; int u = uptr - esu_unit;
int dsk = ((uptr->u5 & DK_CTRL) != 0); int dsk = ((uptr->CMD & DK_CTRL) != 0);
int wc; int wc;
/* Process for each unit */ /* Process for each unit */
if (uptr->u5 & DK_RD) { if (uptr->CMD & DK_RD) {
/* Check if at start of segment */ /* Check if at start of segment */
if (uptr->u3 >= DK_SEC_SIZE) { if (uptr->POS >= DK_SEC_SIZE) {
int da = (uptr->u4 * DK_SEC_SIZE); int da = (uptr->ADDR * DK_SEC_SIZE);
/* Check if end of operation */ /* Check if end of operation */
if ((uptr->u5 & (DK_SECMASK)) == 0) { if ((uptr->CMD & (DK_SECMASK)) == 0) {
esu_set_end(uptr, 0); esu_set_end(uptr, 0);
return SCPE_OK; return SCPE_OK;
} }
/* Check if over end of disk */ /* Check if over end of disk */
if (uptr->u4 >= uptr->wait) { if (uptr->ADDR >= uptr->wait) {
sim_debug(DEBUG_DETAIL, dptr, "Disk read over %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk read over %d %d %o\n\r",
uptr->u3, uptr->u4, uptr->u5); uptr->POS, uptr->ADDR, uptr->CMD);
chan_set_eof(chan); chan_set_eof(chan);
esu_set_end(uptr, 0); esu_set_end(uptr, 0);
return SCPE_OK; return SCPE_OK;
} }
sim_debug(DEBUG_DETAIL, dptr, "Disk read %d %d %d %o %d\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk read %d %d %d %o %d\n\r",
u,uptr->u3, uptr->u4, uptr->u5, da); u,uptr->POS, uptr->ADDR, uptr->CMD, da);
if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) { if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) {
esu_set_end(uptr, 1); esu_set_end(uptr, 1);
@ -342,80 +347,80 @@ t_stat esu_srv(UNIT * uptr)
wc = sim_fread(&dsk_buffer[dsk][0], 1, DK_SEC_SIZE, wc = sim_fread(&dsk_buffer[dsk][0], 1, DK_SEC_SIZE,
uptr->fileref); uptr->fileref);
for (; wc < DK_SEC_SIZE; wc++) for (; wc < DK_SEC_SIZE; wc++)
dsk_buffer[dsk][wc] = (uptr->u5 & DK_BIN) ? 0 :020; dsk_buffer[dsk][wc] = (uptr->CMD & DK_BIN) ? 0 :020;
uptr->u3 = 0; uptr->POS = 0;
uptr->u4++; /* Advance disk address */ uptr->ADDR++; /* Advance disk address */
uptr->u5 -= DK_SECT; uptr->CMD -= DK_SECT;
} }
/* Transfer one Character */ /* Transfer one Character */
if (chan_write_char(chan, &dsk_buffer[dsk][uptr->u3], 0)) { if (chan_write_char(chan, &dsk_buffer[dsk][uptr->POS], 0)) {
esu_set_end(uptr, 0); esu_set_end(uptr, 0);
return SCPE_OK; return SCPE_OK;
} }
uptr->u3++; uptr->POS++;
} }
if (uptr->u5 & DK_RDCK) { if (uptr->CMD & DK_RDCK) {
if (uptr->u3 >= DK_SEC_SIZE) { if (uptr->POS >= DK_SEC_SIZE) {
/* Check if over end of disk */ /* Check if over end of disk */
if (uptr->u4 >= uptr->wait) { if (uptr->ADDR >= uptr->wait) {
sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk over %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk over %d %d %o\n\r",
uptr->u3, uptr->u4, uptr->u5); uptr->POS, uptr->ADDR, uptr->CMD);
uptr->u5 = 0; uptr->CMD = 0;
IAR |= IRQ_14 << dsk; IAR |= IRQ_14 << dsk;
return SCPE_OK; return SCPE_OK;
} }
sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk %d %d %d %o\n\r", u, sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk %d %d %d %o\n\r", u,
uptr->u3, uptr->u4, uptr->u5); uptr->POS, uptr->ADDR, uptr->CMD);
uptr->u4++; /* Advance disk address */ uptr->ADDR++; /* Advance disk address */
uptr->u5 -= DK_SECT; uptr->CMD -= DK_SECT;
uptr->u3 = 0; uptr->POS = 0;
/* Check if end of operation */ /* Check if end of operation */
if ((uptr->u5 & (DK_SECMASK)) == 0) { if ((uptr->CMD & (DK_SECMASK)) == 0) {
uptr->u5 = 0; uptr->CMD = 0;
IAR |= IRQ_14 << dsk; IAR |= IRQ_14 << dsk;
return SCPE_OK; return SCPE_OK;
} }
} }
/* Check if at end of segment */ /* Check if at end of segment */
uptr->u3++; uptr->POS++;
} }
/* Process for each unit */ /* Process for each unit */
if (uptr->u5 & DK_WR) { if (uptr->CMD & DK_WR) {
/* Check if end of operation */ /* Check if end of operation */
if ((uptr->u5 & (DK_SECMASK)) == 0) { if ((uptr->CMD & (DK_SECMASK)) == 0) {
esu_set_end(uptr, 0); esu_set_end(uptr, 0);
return SCPE_OK; return SCPE_OK;
} }
/* Transfer one Character */ /* Transfer one Character */
if (chan_read_char(chan, &dsk_buffer[dsk][uptr->u3], 0)) { if (chan_read_char(chan, &dsk_buffer[dsk][uptr->POS], 0)) {
if (uptr->u3 != 0) { if (uptr->POS != 0) {
while (uptr->u3 < DK_SEC_SIZE) while (uptr->POS < DK_SEC_SIZE)
dsk_buffer[dsk][uptr->u3++] = (uptr->u5 & DK_BIN) ? 0 :020; dsk_buffer[dsk][uptr->POS++] = (uptr->CMD & DK_BIN) ? 0 :020;
} }
} }
uptr->u3++; uptr->POS++;
/* Check if at end of segment */ /* Check if at end of segment */
if (uptr->u3 >= DK_SEC_SIZE) { if (uptr->POS >= DK_SEC_SIZE) {
int da = (uptr->u4 * DK_SEC_SIZE); int da = (uptr->ADDR * DK_SEC_SIZE);
/* Check if over end of disk */ /* Check if over end of disk */
if (uptr->u4 >= uptr->wait) { if (uptr->ADDR >= uptr->wait) {
sim_debug(DEBUG_DETAIL, dptr, "Disk write over %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk write over %d %d %o\n\r",
uptr->u3, uptr->u4, uptr->u5); uptr->POS, uptr->ADDR, uptr->CMD);
chan_set_eof(chan); chan_set_eof(chan);
esu_set_end(uptr, 0); esu_set_end(uptr, 0);
return SCPE_OK; return SCPE_OK;
} }
sim_debug(DEBUG_DETAIL, dptr, "Disk write %d %d %d %o %d\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk write %d %d %d %o %d\n\r",
u, uptr->u3, uptr->u4, uptr->u5, da); u, uptr->POS, uptr->ADDR, uptr->CMD, da);
if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) { if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) {
esu_set_end(uptr, 1); esu_set_end(uptr, 1);
return SCPE_OK; return SCPE_OK;
@ -427,9 +432,9 @@ t_stat esu_srv(UNIT * uptr)
esu_set_end(uptr, 1); esu_set_end(uptr, 1);
return SCPE_OK; return SCPE_OK;
} }
uptr->u3 = 0; uptr->POS = 0;
uptr->u4++; /* Advance disk address */ uptr->ADDR++; /* Advance disk address */
uptr->u5 -= DK_SECT; uptr->CMD -= DK_SECT;
} }
} }
sim_activate(uptr, (uptr->flags & MODIB) ? 500 :300); sim_activate(uptr, (uptr->flags & MODIB) ? 500 :300);
@ -457,11 +462,11 @@ dsk_boot(int32 unit_num, DEVICE * dptr)
int i; int i;
for(i = 0; i < 20; i++) { for(i = 0; i < 20; i++) {
esu_unit[i].u5 = 0; esu_unit[i].CMD = 0;
sim_cancel(&esu_unit[i]); sim_cancel(&esu_unit[i]);
} }
dsk_unit[0].u5 = 0; dsk_unit[0].CMD = 0;
dsk_unit[1].u5 = 0; dsk_unit[1].CMD = 0;
sim_cancel(&dsk_unit[0]); sim_cancel(&dsk_unit[0]);
sim_cancel(&dsk_unit[1]); sim_cancel(&dsk_unit[1]);

46
B5500/b5500_dr.c
View file

@ -29,9 +29,11 @@
UNIT_BUFABLE | UNIT_MUSTBUF UNIT_BUFABLE | UNIT_MUSTBUF
/* in u3 is device address */
/* in u4 is current address */ /* in u4 is current address */
/* in u5 Bits 30-16 of W */ /* in u5 Bits 30-16 of W */
#define ADDR u4
#define CMD u5
#define DR_CHAN 000003 /* Channel number */ #define DR_CHAN 000003 /* Channel number */
#define DR_RD 000004 /* Executing a read command */ #define DR_RD 000004 /* Executing a read command */
#define DR_WR 000010 /* Executing a write command */ #define DR_WR 000010 /* Executing a write command */
@ -94,17 +96,17 @@ t_stat drm_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc, uint8 rd_flg)
} }
/* Check if drive is ready to recieve a command */ /* Check if drive is ready to recieve a command */
if ((uptr->u5 & DR_RDY) == 0) if ((uptr->CMD & DR_RDY) == 0)
return SCPE_BUSY; return SCPE_BUSY;
uptr->u5 = chan; uptr->CMD = chan;
if (rd_flg) if (rd_flg)
uptr->u5 |= DR_RD; uptr->CMD |= DR_RD;
else else
uptr->u5 |= DR_WR; uptr->CMD |= DR_WR;
uptr->u4 = cmd << 3; uptr->ADDR = cmd << 3;
sim_debug(DEBUG_CMD, &drm_dev, "Drum access %s %06o\n\r", sim_debug(DEBUG_CMD, &drm_dev, "Drum access %s %06o\n\r",
(uptr->u5 & DR_RD) ? "read" : "write", uptr->u4); (uptr->CMD & DR_RD) ? "read" : "write", uptr->ADDR);
sim_activate(uptr, 100); sim_activate(uptr, 100);
return SCPE_OK; return SCPE_OK;
} }
@ -113,22 +115,22 @@ t_stat drm_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc, uint8 rd_flg)
/* Handle processing disk controller commands */ /* Handle processing disk controller commands */
t_stat drm_srv(UNIT * uptr) t_stat drm_srv(UNIT * uptr)
{ {
int chan = uptr->u5 & DR_CHAN; int chan = uptr->CMD & DR_CHAN;
uint8 *ch = &(((uint8 *)uptr->filebuf)[uptr->u4]); uint8 *ch = &(((uint8 *)uptr->filebuf)[uptr->ADDR]);
/* Process for each unit */ /* Process for each unit */
if (uptr->u5 & DR_RD) { if (uptr->CMD & DR_RD) {
/* Transfer one Character */ /* Transfer one Character */
if (chan_write_drum(chan, ch, 0)) { if (chan_write_drum(chan, ch, 0)) {
uptr->u5 = DR_RDY; uptr->CMD = DR_RDY;
chan_set_end(chan); chan_set_end(chan);
return SCPE_OK; return SCPE_OK;
} }
uptr->u4++; uptr->ADDR++;
if (uptr->u4 > ((int32)uptr->capac << 3)) { if (uptr->ADDR > ((int32)uptr->capac << 3)) {
sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n\r"); sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n\r");
uptr->u5 = DR_RDY; uptr->CMD = DR_RDY;
chan_set_error(chan); chan_set_error(chan);
chan_set_end(chan); chan_set_end(chan);
return SCPE_OK; return SCPE_OK;
@ -137,17 +139,17 @@ t_stat drm_srv(UNIT * uptr)
} }
/* Process for each unit */ /* Process for each unit */
if (uptr->u5 & DR_WR) { if (uptr->CMD & DR_WR) {
/* Transfer one Character */ /* Transfer one Character */
if (chan_read_drum(chan, ch, 0)) { if (chan_read_drum(chan, ch, 0)) {
uptr->u5 = DR_RDY; uptr->CMD = DR_RDY;
chan_set_end(chan); chan_set_end(chan);
return SCPE_OK; return SCPE_OK;
} }
uptr->u4++; uptr->ADDR++;
if (uptr->u4 > ((int32)uptr->capac << 3)) { if (uptr->ADDR > ((int32)uptr->capac << 3)) {
sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n\r"); sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n\r");
uptr->u5 = DR_RDY; uptr->CMD = DR_RDY;
chan_set_error(chan); chan_set_error(chan);
chan_set_end(chan); chan_set_end(chan);
return SCPE_OK; return SCPE_OK;
@ -178,7 +180,7 @@ drm_attach(UNIT * uptr, CONST char *file)
if ((r = attach_unit(uptr, file)) != SCPE_OK) if ((r = attach_unit(uptr, file)) != SCPE_OK)
return r; return r;
uptr->u5 |= DR_RDY; uptr->CMD |= DR_RDY;
uptr->hwmark = uptr->capac; uptr->hwmark = uptr->capac;
if (u) if (u)
iostatus |= DRUM2_FLAG; iostatus |= DRUM2_FLAG;
@ -194,7 +196,7 @@ drm_detach(UNIT * uptr)
int u = uptr - drm_unit; int u = uptr - drm_unit;
if ((r = detach_unit(uptr)) != SCPE_OK) if ((r = detach_unit(uptr)) != SCPE_OK)
return r; return r;
uptr->u5 = 0; uptr->CMD = 0;
if (u) if (u)
iostatus &= ~DRUM2_FLAG; iostatus &= ~DRUM2_FLAG;
else else
@ -225,7 +227,7 @@ set_auxmem(UNIT * uptr, int32 val, CONST char *cptr, void *desc) {
uptr->filebuf = calloc(uptr->capac, 8); uptr->filebuf = calloc(uptr->capac, 8);
uptr->flags |= UNIT_BUF; uptr->flags |= UNIT_BUF;
} }
uptr->u5 = DR_RDY; uptr->CMD = DR_RDY;
if (u) if (u)
iostatus |= DRUM2_FLAG; iostatus |= DRUM2_FLAG;
else else

58
B5500/b5500_dtc.c
View file

@ -53,9 +53,11 @@
/* Buffer wrong state = DEV_EOF D27 */ /* Buffer wrong state = DEV_EOF D27 */
/* Buffer Busy = DEV_ERROR D28 */ /* Buffer Busy = DEV_ERROR D28 */
/* DTC not ready or buffer, DEV_NOTRDY D30 */ /* DTC not ready or buffer, DEV_NOTRDY D30 */
/* in u3 is device address */
/* in u4 is current address */ /* in u4 is current address */
/* in u5 Line number */ /* in u5 Line number */
#define LINE u4
#define CMD u5
#define DTC_CHAN 000003 /* Channel number */ #define DTC_CHAN 000003 /* Channel number */
#define DTC_RD 000004 /* Executing a read command */ #define DTC_RD 000004 /* Executing a read command */
#define DTC_WR 000010 /* Executing a write command */ #define DTC_WR 000010 /* Executing a write command */
@ -225,34 +227,34 @@ t_stat dtc_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
return SCPE_UNATT; return SCPE_UNATT;
/* Check if drive is ready to recieve a command */ /* Check if drive is ready to recieve a command */
if ((uptr->u5 & DTC_RDY) == 0) if ((uptr->CMD & DTC_RDY) == 0)
return SCPE_BUSY; return SCPE_BUSY;
uptr->u5 = chan; uptr->CMD = chan;
ttu = (*wc & DTCSTA_TTU) >> 5; ttu = (*wc & DTCSTA_TTU) >> 5;
buf = (*wc & DTCSTA_BUF); buf = (*wc & DTCSTA_BUF);
/* Set the Terminal unit. */ /* Set the Terminal unit. */
if (ttu == 0) if (ttu == 0)
uptr->u4 = -1; uptr->LINE = -1;
else { else {
uptr->u4 = buf + ((ttu-1) * 15); uptr->LINE = buf + ((ttu-1) * 15);
} }
if (*wc & DTCSTA_GM) if (*wc & DTCSTA_GM)
uptr->u5 |= DTC_IGNGM; uptr->CMD |= DTC_IGNGM;
if (cmd & DTCSTA_READ) if (cmd & DTCSTA_READ)
uptr->u5 |= DTC_RD; uptr->CMD |= DTC_RD;
else if (cmd & DTCSTA_INHIBIT) else if (cmd & DTCSTA_INHIBIT)
uptr->u5 |= DTC_INQ; uptr->CMD |= DTC_INQ;
else else
uptr->u5 |= DTC_WR; uptr->CMD |= DTC_WR;
if (cmd & DTCSTA_BINARY) if (cmd & DTCSTA_BINARY)
uptr->u5 |= DTC_BIN; uptr->CMD |= DTC_BIN;
sim_debug(DEBUG_CMD, &dtc_dev, "Datacomm access %s %06o %d %04o\n", sim_debug(DEBUG_CMD, &dtc_dev, "Datacomm access %s %06o %d %04o\n",
(uptr->u5 & DTC_RD) ? "read" : ((uptr->u5 & DTC_INQ) ? "inq" : (uptr->CMD & DTC_RD) ? "read" : ((uptr->CMD & DTC_INQ) ? "inq" :
((uptr->u5 & DTC_WR) ? "write" : "unknown")), ((uptr->CMD & DTC_WR) ? "write" : "unknown")),
uptr->u5, uptr->u4, *wc); uptr->CMD, uptr->LINE, *wc);
sim_activate(uptr, 5000); sim_activate(uptr, 5000);
return SCPE_OK; return SCPE_OK;
} }
@ -261,16 +263,16 @@ t_stat dtc_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
/* Handle processing terminal controller commands */ /* Handle processing terminal controller commands */
t_stat dtc_srv(UNIT * uptr) t_stat dtc_srv(UNIT * uptr)
{ {
int chan = uptr->u5 & DTC_CHAN; int chan = uptr->CMD & DTC_CHAN;
uint8 ch; uint8 ch;
int ttu; int ttu;
int buf; int buf;
int i; int i;
int line = uptr->u4; int line = uptr->LINE;
/* Process interrage command */ /* Process interrage command */
if (uptr->u5 & DTC_INQ) { if (uptr->CMD & DTC_INQ) {
if (line == -1) { if (line == -1) {
buf = -1; buf = -1;
for(i = 0; i < DTC_MLINES; i++) { for(i = 0; i < DTC_MLINES; i++) {
@ -333,7 +335,7 @@ t_stat dtc_srv(UNIT * uptr)
sim_debug(DEBUG_DETAIL, &dtc_dev, " abnormal "); sim_debug(DEBUG_DETAIL, &dtc_dev, " abnormal ");
} }
dtc_lstatus[line] &= ~BufIRQ; dtc_lstatus[line] &= ~BufIRQ;
chan_set_wc(uptr->u4, 0); chan_set_wc(uptr->LINE, 0);
chan_set_end(chan); chan_set_end(chan);
sim_debug(DEBUG_DETAIL, &dtc_dev, " %03o ", dtc_lstatus[line]); sim_debug(DEBUG_DETAIL, &dtc_dev, " %03o ", dtc_lstatus[line]);
} }
@ -345,18 +347,18 @@ t_stat dtc_srv(UNIT * uptr)
} }
chan_set_wc(chan, (ttu << 5) | line); chan_set_wc(chan, (ttu << 5) | line);
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm inqury %d %d\n", sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm inqury %d %d\n",
ttu, line); ttu, line);
} }
/* Process for each unit */ /* Process for each unit */
if (uptr->u5 & DTC_WR) { if (uptr->CMD & DTC_WR) {
if (line > dtc_desc.lines || line == -1 || dtc_lstatus[line] & BufDisco) { if (line > dtc_desc.lines || line == -1 || dtc_lstatus[line] & BufDisco) {
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write invalid %d\n", sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write invalid %d\n",
line); line);
chan_set_notrdy(chan); chan_set_notrdy(chan);
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
return SCPE_OK; return SCPE_OK;
} }
/* Validate that we can send data to buffer */ /* Validate that we can send data to buffer */
@ -375,7 +377,7 @@ t_stat dtc_srv(UNIT * uptr)
case BufOutBusy: case BufOutBusy:
chan_set_eof(chan); chan_set_eof(chan);
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write busy %d %d\n", sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm write busy %d %d\n",
line, i); line, i);
return SCPE_OK; return SCPE_OK;
@ -423,7 +425,7 @@ t_stat dtc_srv(UNIT * uptr)
line -= 15; line -= 15;
chan_set_wc(chan, (ttu << 5) | line); chan_set_wc(chan, (ttu << 5) | line);
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
return SCPE_OK; return SCPE_OK;
} else { } else {
dtc_lstatus[line] = BufWrite; dtc_lstatus[line] = BufWrite;
@ -434,13 +436,13 @@ t_stat dtc_srv(UNIT * uptr)
sim_activate(uptr, 5000); sim_activate(uptr, 5000);
} }
if (uptr->u5 & DTC_RD) { if (uptr->CMD & DTC_RD) {
if (line > dtc_desc.lines || line == -1 || dtc_lstatus[line] & BufDisco) { if (line > dtc_desc.lines || line == -1 || dtc_lstatus[line] & BufDisco) {
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm read nothing %d\n", sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm read nothing %d\n",
line); line);
chan_set_notrdy(chan); chan_set_notrdy(chan);
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
return SCPE_OK; return SCPE_OK;
} }
/* Validate that we can send data to buffer */ /* Validate that we can send data to buffer */
@ -461,7 +463,7 @@ t_stat dtc_srv(UNIT * uptr)
case BufWrite: case BufWrite:
chan_set_eof(chan); chan_set_eof(chan);
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm read busy %d %d\n", sim_debug(DEBUG_DETAIL, &dtc_dev, "Datacomm read busy %d %d\n",
line, i); line, i);
return SCPE_OK; return SCPE_OK;
@ -500,7 +502,7 @@ t_stat dtc_srv(UNIT * uptr)
line -= 15; line -= 15;
chan_set_wc(chan, (ttu << 5) | line); chan_set_wc(chan, (ttu << 5) | line);
chan_set_end(chan); chan_set_end(chan);
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
IAR |= IRQ_12; IAR |= IRQ_12;
return SCPE_OK; return SCPE_OK;
} else { } else {
@ -771,7 +773,7 @@ dtc_attach(UNIT * uptr, CONST char *cptr)
for (i = 0; i < DTC_MLINES; i++) { for (i = 0; i < DTC_MLINES; i++) {
dtc_lstatus[i] = BufNotReady; /* Device not connected */ dtc_lstatus[i] = BufNotReady; /* Device not connected */
} }
uptr->u5 = DTC_RDY; uptr->CMD = DTC_RDY;
iostatus |= DTC_FLAG; iostatus |= DTC_FLAG;
return SCPE_OK; return SCPE_OK;
} }
@ -788,7 +790,7 @@ dtc_detach(UNIT * uptr)
for (i = 0; i < dtc_desc.lines; i++) for (i = 0; i < dtc_desc.lines; i++)
dtc_ldsc[i].rcve = 0; /* disable rcv */ dtc_ldsc[i].rcve = 0; /* disable rcv */
sim_cancel(uptr); /* stop poll */ sim_cancel(uptr); /* stop poll */
uptr->u5 = 0; uptr->CMD = 0;
iostatus &= ~DTC_FLAG; iostatus &= ~DTC_FLAG;
return r; return r;
} }

153
B5500/b5500_mt.c
View file

@ -42,10 +42,13 @@
#define BUFFSIZE 10240 #define BUFFSIZE 10240
#define UNIT_MT UNIT_ATTABLE | UNIT_DISABLE | UNIT_ROABLE #define UNIT_MT UNIT_ATTABLE | UNIT_DISABLE | UNIT_ROABLE
#define HT 500 /* Time per char high density */ #define HT 500 /* Time per char high density */
/* in u3 is device address */
/* in u4 is current buffer position */ /* in u4 is current buffer position */
/* in u5 Bits 30-16 of W */ /* in u5 Bits 30-16 of W */
#define CMD u5
#define POS u6
#define URCSTA_SKIP 000017 /* Skip mask */ #define URCSTA_SKIP 000017 /* Skip mask */
#define URCSTA_SINGLE 000020 /* Single space skip. */ #define URCSTA_SINGLE 000020 /* Single space skip. */
#define URCSTA_DOUBLE 000040 /* Double space skip */ #define URCSTA_DOUBLE 000040 /* Double space skip */
@ -171,41 +174,41 @@ mt_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
return SCPE_UNATT; return SCPE_UNATT;
/* Not there until loading done */ /* Not there until loading done */
if ((uptr->u5 & MT_LOADED)) if ((uptr->CMD & MT_LOADED))
return SCPE_UNATT; return SCPE_UNATT;
/* Check if drive is ready to recieve a command */ /* Check if drive is ready to recieve a command */
if ((uptr->u5 & MT_BSY) != 0) if ((uptr->CMD & MT_BSY) != 0)
return SCPE_BUSY; return SCPE_BUSY;
/* Determine actual command */ /* Determine actual command */
uptr->u5 &= ~(MT_RDY|MT_CHAN|MT_CMD|MT_BIN); uptr->CMD &= ~(MT_RDY|MT_CHAN|MT_CMD|MT_BIN);
uptr->u5 |= chan; uptr->CMD |= chan;
if (cmd & URCSTA_BINARY) if (cmd & URCSTA_BINARY)
uptr->u5 |= MT_BIN; uptr->CMD |= MT_BIN;
if (cmd & URCSTA_READ) { if (cmd & URCSTA_READ) {
if ((cmd & URCSTA_WC) && *wc == 0) if ((cmd & URCSTA_WC) && *wc == 0)
uptr->u5 |= MT_FSR; uptr->CMD |= MT_FSR;
else else
uptr->u5 |= MT_RD; uptr->CMD |= MT_RD;
} else { } else {
/* Erase gap not supported on sim, treat as /* Erase gap not supported on sim, treat as
write of null record */ write of null record */
if ((cmd & URCSTA_WC) && *wc == 0) if ((cmd & URCSTA_WC) && *wc == 0)
uptr->u5 |= MT_INT; uptr->CMD |= MT_INT;
else else
uptr->u5 |= MT_WR; uptr->CMD |= MT_WR;
} }
*wc = 0; /* So no overide occurs */ *wc = 0; /* So no overide occurs */
/* Convert command to correct type */ /* Convert command to correct type */
if (cmd & URCSTA_DIRECT) if (cmd & URCSTA_DIRECT)
uptr->u5 |= MT_BACK; uptr->CMD |= MT_BACK;
uptr->u6 = 0; uptr->POS = 0;
CLR_BUF(uptr); CLR_BUF(uptr);
sim_debug(DEBUG_CMD, &mt_dev, "Command %d %o %o\n", unit, uptr->u5, cmd); sim_debug(DEBUG_CMD, &mt_dev, "Command %d %o %o\n", unit, uptr->CMD, cmd);
if ((uptr->u5 & MT_IDLE) == 0) { if ((uptr->CMD & MT_IDLE) == 0) {
sim_activate(uptr,50000); sim_activate(uptr,50000);
} }
return SCPE_OK; return SCPE_OK;
@ -223,18 +226,18 @@ t_stat mt_error(UNIT * uptr, int chan, t_stat r, DEVICE * dptr)
case MTSE_EOM: /* end of medium */ case MTSE_EOM: /* end of medium */
sim_debug(DEBUG_EXP, dptr, "EOT "); sim_debug(DEBUG_EXP, dptr, "EOT ");
if (uptr->u5 & MT_BOT) { if (uptr->CMD & MT_BOT) {
chan_set_blank(chan); chan_set_blank(chan);
} else { } else {
uptr->u5 &= ~MT_BOT; uptr->CMD &= ~MT_BOT;
uptr->u5 |= MT_EOT; uptr->CMD |= MT_EOT;
chan_set_eot(chan); chan_set_eot(chan);
} }
break; break;
case MTSE_TMK: /* tape mark */ case MTSE_TMK: /* tape mark */
sim_debug(DEBUG_EXP, dptr, "MARK "); sim_debug(DEBUG_EXP, dptr, "MARK ");
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->CMD &= ~(MT_BOT|MT_EOT);
chan_set_eof(chan); chan_set_eof(chan);
break; break;
@ -251,8 +254,8 @@ t_stat mt_error(UNIT * uptr, int chan, t_stat r, DEVICE * dptr)
sim_debug(DEBUG_EXP, dptr, "ERROR %d ", r); sim_debug(DEBUG_EXP, dptr, "ERROR %d ", r);
break; break;
case MTSE_BOT: /* beginning of tape */ case MTSE_BOT: /* beginning of tape */
uptr->u5 &= ~MT_EOT; uptr->CMD &= ~MT_EOT;
uptr->u5 |= MT_BOT; uptr->CMD |= MT_BOT;
chan_set_bot(chan); /* Set flag */ chan_set_bot(chan); /* Set flag */
sim_debug(DEBUG_EXP, dptr, "BOT "); sim_debug(DEBUG_EXP, dptr, "BOT ");
break; break;
@ -260,8 +263,8 @@ t_stat mt_error(UNIT * uptr, int chan, t_stat r, DEVICE * dptr)
default: default:
sim_debug(DEBUG_EXP, dptr, "%d ", r); sim_debug(DEBUG_EXP, dptr, "%d ", r);
} }
uptr->u5 &= ~(MT_CMD|MT_BIN); uptr->CMD &= ~(MT_CMD|MT_BIN);
uptr->u5 |= MT_RDY|MT_IDLE; uptr->CMD |= MT_RDY|MT_IDLE;
chan_set_end(chan); chan_set_end(chan);
return SCPE_OK; return SCPE_OK;
} }
@ -269,9 +272,9 @@ t_stat mt_error(UNIT * uptr, int chan, t_stat r, DEVICE * dptr)
/* Handle processing of tape requests. */ /* Handle processing of tape requests. */
t_stat mt_srv(UNIT * uptr) t_stat mt_srv(UNIT * uptr)
{ {
int chan = uptr->u5 & MT_CHAN; int chan = uptr->CMD & MT_CHAN;
int unit = uptr - mt_unit; int unit = uptr - mt_unit;
int cmd = uptr->u5 & MT_CMD; int cmd = uptr->CMD & MT_CMD;
DEVICE *dptr = find_dev_from_unit(uptr); DEVICE *dptr = find_dev_from_unit(uptr);
t_mtrlnt reclen; t_mtrlnt reclen;
t_stat r = SCPE_ARG; /* Force error if not set */ t_stat r = SCPE_ARG; /* Force error if not set */
@ -281,26 +284,26 @@ t_stat mt_srv(UNIT * uptr)
/* Simulate tape load delay */ /* Simulate tape load delay */
if (uptr->u5 & MT_LOADED) { if (uptr->CMD & MT_LOADED) {
uptr->u5 &= ~MT_LOADED; uptr->CMD &= ~MT_LOADED;
uptr->u5 |= MT_BSY|MT_RDY; uptr->CMD |= MT_BSY|MT_RDY;
sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Loaded\n", unit); sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Loaded\n", unit);
sim_activate(uptr, 50000); sim_activate(uptr, 50000);
return SCPE_OK; return SCPE_OK;
} }
if (uptr->u5 & MT_BSY) { if (uptr->CMD & MT_BSY) {
uptr->u5 &= ~MT_BSY; uptr->CMD &= ~MT_BSY;
sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Online\n", unit); sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Online\n", unit);
iostatus |= 1 << (uptr - mt_unit); iostatus |= 1 << (uptr - mt_unit);
if (uptr->u5 & MT_IDLE) if (uptr->CMD & MT_IDLE)
sim_activate(uptr, 50000); sim_activate(uptr, 50000);
return SCPE_OK; return SCPE_OK;
} }
if (uptr->u5 & MT_IDLE) { if (uptr->CMD & MT_IDLE) {
uptr->u5 &= ~MT_IDLE; uptr->CMD &= ~MT_IDLE;
if (uptr->u5 & MT_RDY) { if (uptr->CMD & MT_RDY) {
sim_debug(DEBUG_DETAIL, dptr, "Unit=%d idling\n", unit); sim_debug(DEBUG_DETAIL, dptr, "Unit=%d idling\n", unit);
return SCPE_OK; return SCPE_OK;
} }
@ -312,8 +315,8 @@ t_stat mt_srv(UNIT * uptr)
case MT_INT: case MT_INT:
if (sim_tape_wrp(uptr)) if (sim_tape_wrp(uptr))
chan_set_wrp(chan); chan_set_wrp(chan);
uptr->u5 &= ~(MT_CMD|MT_BIN); uptr->CMD &= ~(MT_CMD|MT_BIN);
uptr->u5 |= MT_RDY; uptr->CMD |= MT_RDY;
chan_set_end(chan); chan_set_end(chan);
sim_debug(DEBUG_DETAIL, dptr, "Status\n"); sim_debug(DEBUG_DETAIL, dptr, "Status\n");
return SCPE_OK; return SCPE_OK;
@ -322,7 +325,7 @@ t_stat mt_srv(UNIT * uptr)
/* If at end of record, fill buffer */ /* If at end of record, fill buffer */
if (BUF_EMPTY(uptr)) { if (BUF_EMPTY(uptr)) {
sim_debug(DEBUG_DETAIL, dptr, "Read unit=%d %s ", unit, sim_debug(DEBUG_DETAIL, dptr, "Read unit=%d %s ", unit,
(uptr->u5 & MT_BIN)? "bin": "bcd"); (uptr->CMD & MT_BIN)? "bin": "bcd");
if (sim_tape_eot(uptr)) { if (sim_tape_eot(uptr)) {
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_EOM, dptr); return mt_error(uptr, chan, MTSE_EOM, dptr);
@ -340,12 +343,12 @@ t_stat mt_srv(UNIT * uptr)
} }
return mt_error(uptr, chan, r, dptr); return mt_error(uptr, chan, r, dptr);
} else { } else {
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->CMD &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
} }
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
uptr->u6 = 0; uptr->POS = 0;
if ((uptr->u5 & MT_BIN) == 0) if ((uptr->CMD & MT_BIN) == 0)
mode = 0100; mode = 0100;
else else
mode = 0; mode = 0;
@ -357,10 +360,10 @@ t_stat mt_srv(UNIT * uptr)
} }
} }
} }
ch = mt_buffer[chan][uptr->u6++] & 0177; ch = mt_buffer[chan][uptr->POS++] & 0177;
/* 00 characters are not transfered in BCD mode */ /* 00 characters are not transfered in BCD mode */
if (ch == 0) { if (ch == 0) {
if (((uint32)uptr->u6) >= uptr->hwmark) { if (((uint32)uptr->POS) >= uptr->hwmark) {
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
} else { } else {
@ -370,14 +373,14 @@ t_stat mt_srv(UNIT * uptr)
} }
if (chan_write_char(chan, &ch, if (chan_write_char(chan, &ch,
(((uint32)uptr->u6) >= uptr->hwmark) ? 1 : 0)) { (((uint32)uptr->POS) >= uptr->hwmark) ? 1 : 0)) {
sim_debug(DEBUG_DATA, dptr, "Read unit=%d %d EOR\n", unit, sim_debug(DEBUG_DATA, dptr, "Read unit=%d %d EOR\n", unit,
uptr->hwmark-uptr->u6); uptr->hwmark-uptr->POS);
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
} else { } else {
sim_debug(DEBUG_DATA, dptr, "Read data unit=%d %d %03o\n", sim_debug(DEBUG_DATA, dptr, "Read data unit=%d %d %03o\n",
unit, uptr->u6, ch); unit, uptr->POS, ch);
sim_activate(uptr, HT); sim_activate(uptr, HT);
} }
return SCPE_OK; return SCPE_OK;
@ -386,7 +389,7 @@ t_stat mt_srv(UNIT * uptr)
/* If at end of record, fill buffer */ /* If at end of record, fill buffer */
if (BUF_EMPTY(uptr)) { if (BUF_EMPTY(uptr)) {
sim_debug(DEBUG_DETAIL, dptr, "Read back unit=%d %s ", unit, sim_debug(DEBUG_DETAIL, dptr, "Read back unit=%d %s ", unit,
(uptr->u5 & MT_BIN)? "bin": "bcd"); (uptr->CMD & MT_BIN)? "bin": "bcd");
if (sim_tape_bot(uptr)) { if (sim_tape_bot(uptr)) {
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_BOT, dptr); return mt_error(uptr, chan, MTSE_BOT, dptr);
@ -399,18 +402,18 @@ t_stat mt_srv(UNIT * uptr)
(void)chan_write_char(chan, &ch, 1); (void)chan_write_char(chan, &ch, 1);
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
} else { } else {
uptr->u5 |= MT_BSY; uptr->CMD |= MT_BSY;
sim_debug(DEBUG_DETAIL, dptr, "r=%d\n", r); sim_debug(DEBUG_DETAIL, dptr, "r=%d\n", r);
sim_activate(uptr, 100); sim_activate(uptr, 100);
} }
return mt_error(uptr, chan, r, dptr); return mt_error(uptr, chan, r, dptr);
} else { } else {
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->CMD &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
} }
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
uptr->u6 = uptr->hwmark; uptr->POS = uptr->hwmark;
if ((uptr->u5 & MT_BIN) == 0) if ((uptr->CMD & MT_BIN) == 0)
mode = 0100; mode = 0100;
else else
mode = 0; mode = 0;
@ -422,10 +425,10 @@ t_stat mt_srv(UNIT * uptr)
} }
} }
} }
ch = mt_buffer[chan][--uptr->u6] & 0177; ch = mt_buffer[chan][--uptr->POS] & 0177;
/* 00 characters are not transfered in BCD mode */ /* 00 characters are not transfered in BCD mode */
if (ch == 0) { if (ch == 0) {
if (uptr->u6 <= 0) { if (uptr->POS <= 0) {
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
} else { } else {
@ -434,27 +437,27 @@ t_stat mt_srv(UNIT * uptr)
} }
} }
if (chan_write_char(chan, &ch, (uptr->u6 > 0) ? 0 : 1)) { if (chan_write_char(chan, &ch, (uptr->POS > 0) ? 0 : 1)) {
sim_debug(DEBUG_DATA, dptr, "Read back unit=%d %d EOR\n", sim_debug(DEBUG_DATA, dptr, "Read back unit=%d %d EOR\n",
unit, uptr->hwmark-uptr->u6); unit, uptr->hwmark-uptr->POS);
sim_activate(uptr, 100); sim_activate(uptr, 100);
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
} else { } else {
sim_debug(DEBUG_DATA, dptr, "Read back data unit=%d %d %03o\n", sim_debug(DEBUG_DATA, dptr, "Read back data unit=%d %d %03o\n",
unit, uptr->u6, ch); unit, uptr->POS, ch);
sim_activate(uptr, HT); sim_activate(uptr, HT);
} }
return SCPE_OK; return SCPE_OK;
case MT_WR: /* Write */ case MT_WR: /* Write */
/* Check if write protected */ /* Check if write protected */
if (uptr->u6 == 0 && sim_tape_wrp(uptr)) { if (uptr->POS == 0 && sim_tape_wrp(uptr)) {
sim_activate(uptr, 100); sim_activate(uptr, 100);
return mt_error(uptr, chan, MTSE_WRP, dptr); return mt_error(uptr, chan, MTSE_WRP, dptr);
} }
if (chan_read_char(chan, &ch, if (chan_read_char(chan, &ch,
(uptr->u6 > BUFFSIZE) ? 1 : 0)) { (uptr->POS > BUFFSIZE) ? 1 : 0)) {
reclen = uptr->u6; reclen = uptr->POS;
/* If no transfer, then either erase */ /* If no transfer, then either erase */
if (reclen == 0) { if (reclen == 0) {
sim_debug(DEBUG_DETAIL, dptr, "Erase\n"); sim_debug(DEBUG_DETAIL, dptr, "Erase\n");
@ -467,24 +470,24 @@ t_stat mt_srv(UNIT * uptr)
} else { } else {
sim_debug(DEBUG_DETAIL, dptr, sim_debug(DEBUG_DETAIL, dptr,
"Write unit=%d Block %d %s chars\n", unit, reclen, "Write unit=%d Block %d %s chars\n", unit, reclen,
(uptr->u5 & MT_BIN)? "bin": "bcd"); (uptr->CMD & MT_BIN)? "bin": "bcd");
r = sim_tape_wrrecf(uptr, &mt_buffer[chan][0], reclen); r = sim_tape_wrrecf(uptr, &mt_buffer[chan][0], reclen);
} }
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->CMD &= ~(MT_BOT|MT_EOT);
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, r, dptr); /* Record errors */ return mt_error(uptr, chan, r, dptr); /* Record errors */
} else { } else {
/* Copy data to buffer */ /* Copy data to buffer */
ch &= 077; ch &= 077;
ch |= parity_table[ch]; ch |= parity_table[ch];
if ((uptr->u5 & MT_BIN)) if ((uptr->CMD & MT_BIN))
ch ^= 0100; ch ^= 0100;
/* Don't write out even parity zeros */ /* Don't write out even parity zeros */
if (ch != 0) if (ch != 0)
mt_buffer[chan][uptr->u6++] = ch; mt_buffer[chan][uptr->POS++] = ch;
sim_debug(DEBUG_DATA, dptr, "Write data unit=%d %d %03o\n", sim_debug(DEBUG_DATA, dptr, "Write data unit=%d %d %03o\n",
unit, uptr->u6, ch); unit, uptr->POS, ch);
uptr->hwmark = uptr->u6; uptr->hwmark = uptr->POS;
} }
sim_activate(uptr, HT); sim_activate(uptr, HT);
return SCPE_OK; return SCPE_OK;
@ -494,7 +497,7 @@ t_stat mt_srv(UNIT * uptr)
/* If at end of record, fill buffer */ /* If at end of record, fill buffer */
sim_debug(DEBUG_DETAIL, dptr, "Space unit=%d ", unit); sim_debug(DEBUG_DETAIL, dptr, "Space unit=%d ", unit);
if (sim_tape_eot(uptr)) { if (sim_tape_eot(uptr)) {
uptr->u5 &= ~MT_BOT; uptr->CMD &= ~MT_BOT;
sim_debug(DEBUG_DETAIL, dptr, "EOT\n"); sim_debug(DEBUG_DETAIL, dptr, "EOT\n");
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_EOM, dptr); return mt_error(uptr, chan, MTSE_EOM, dptr);
@ -510,7 +513,7 @@ t_stat mt_srv(UNIT * uptr)
reclen = 10; reclen = 10;
} }
} }
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->CMD &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
sim_activate(uptr, uptr->hwmark * HT); sim_activate(uptr, uptr->hwmark * HT);
@ -539,7 +542,7 @@ t_stat mt_srv(UNIT * uptr)
sim_debug(DEBUG_DETAIL, dptr, "r=%d ", r); sim_debug(DEBUG_DETAIL, dptr, "r=%d ", r);
} }
} }
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->CMD &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
sim_activate(uptr, uptr->hwmark * HT); sim_activate(uptr, uptr->hwmark * HT);
@ -551,13 +554,13 @@ t_stat mt_srv(UNIT * uptr)
case MT_REW: /* Rewind */ case MT_REW: /* Rewind */
sim_debug(DEBUG_DETAIL, dptr, "Rewind unit=%d pos=%d\n", unit, sim_debug(DEBUG_DETAIL, dptr, "Rewind unit=%d pos=%d\n", unit,
uptr->pos); uptr->pos);
uptr->u5 &= ~(MT_CMD | MT_BIN | MT_IDLE | MT_RDY); uptr->CMD &= ~(MT_CMD | MT_BIN | MT_IDLE | MT_RDY);
uptr->u5 |= MT_BSY|MT_RDY; uptr->CMD |= MT_BSY|MT_RDY;
iostatus &= ~(1 << (uptr - mt_unit)); iostatus &= ~(1 << (uptr - mt_unit));
sim_activate(uptr, (uptr->pos/100) + 100); sim_activate(uptr, (uptr->pos/100) + 100);
r = sim_tape_rewind(uptr); r = sim_tape_rewind(uptr);
uptr->u5 &= ~MT_EOT; uptr->CMD &= ~MT_EOT;
uptr->u5 |= MT_BOT; uptr->CMD |= MT_BOT;
chan_set_end(chan); chan_set_end(chan);
return r; return r;
} }
@ -572,7 +575,7 @@ mt_attach(UNIT * uptr, CONST char *file)
if ((r = sim_tape_attach_ex(uptr, file, 0, 0)) != SCPE_OK) if ((r = sim_tape_attach_ex(uptr, file, 0, 0)) != SCPE_OK)
return r; return r;
uptr->u5 |= MT_LOADED|MT_BOT; uptr->CMD |= MT_LOADED|MT_BOT;
sim_activate(uptr, 50000); sim_activate(uptr, 50000);
return SCPE_OK; return SCPE_OK;
} }
@ -580,7 +583,7 @@ mt_attach(UNIT * uptr, CONST char *file)
t_stat t_stat
mt_detach(UNIT * uptr) mt_detach(UNIT * uptr)
{ {
uptr->u5 = 0; uptr->CMD = 0;
iostatus &= ~(1 << (uptr - mt_unit)); iostatus &= ~(1 << (uptr - mt_unit));
return sim_tape_detach(uptr); return sim_tape_detach(uptr);
} }
@ -599,10 +602,10 @@ mt_reset(DEVICE *dptr)
mt_unit[i].dynflags = MT_DENS_556 << UNIT_V_DF_TAPE; mt_unit[i].dynflags = MT_DENS_556 << UNIT_V_DF_TAPE;
if ((mt_unit[i].flags & UNIT_ATT) == 0) if ((mt_unit[i].flags & UNIT_ATT) == 0)
iostatus &= ~(1 << i); iostatus &= ~(1 << i);
else if (mt_unit[i].u5 & (MT_LOADED|MT_RDY)) { else if (mt_unit[i].CMD & (MT_LOADED|MT_RDY)) {
iostatus |= 1 << i; iostatus |= 1 << i;
mt_unit[i].u5 &= ~(MT_LOADED); mt_unit[i].CMD &= ~(MT_LOADED);
mt_unit[i].u5 |= MT_RDY; mt_unit[i].CMD |= MT_RDY;
} }
} }
return SCPE_OK; return SCPE_OK;

370
B5500/b5500_urec.c
View file

@ -37,6 +37,11 @@
#define TMR_RTC 0 #define TMR_RTC 0
#define LINENUM u3
#define POS u4
#define CMD u5
#define CARDIMG up7
/* std devices. data structures /* std devices. data structures
@ -46,7 +51,7 @@
cdr_mod Card Reader modifiers list cdr_mod Card Reader modifiers list
*/ */
/* Device status information stored in u5 */ /* Device status information stored in CMD */
#define URCSTA_CHMASK 0003 /* Mask of I/O channel to send data on */ #define URCSTA_CHMASK 0003 /* Mask of I/O channel to send data on */
#define URCSTA_CARD 0004 /* Unit has card in buffer */ #define URCSTA_CARD 0004 /* Unit has card in buffer */
#define URCSTA_FULL 0004 /* Unit has full buffer */ #define URCSTA_FULL 0004 /* Unit has full buffer */
@ -229,7 +234,7 @@ cdr_ini(DEVICE *dptr) {
int i; int i;
for(i = 0; i < NUM_DEVS_CDR; i++) { for(i = 0; i < NUM_DEVS_CDR; i++) {
cdr_unit[i].u5 = 0; cdr_unit[i].CMD = 0;
sim_cancel(&cdr_unit[i]); sim_cancel(&cdr_unit[i]);
} }
return SCPE_OK; return SCPE_OK;
@ -257,14 +262,14 @@ t_stat card_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
return SCPE_UNATT; return SCPE_UNATT;
/* Are we currently tranfering? */ /* Are we currently tranfering? */
if (uptr->u5 & URCSTA_ACTIVE) if (uptr->CMD & URCSTA_ACTIVE)
return SCPE_BUSY; return SCPE_BUSY;
/* Check if we ran out of cards */ /* Check if we ran out of cards */
if (uptr->u5 & URCSTA_EOF) { if (uptr->CMD & URCSTA_EOF) {
/* If end of file, return to system */ /* If end of file, return to system */
if (sim_card_input_hopper_count(uptr) != 0) if (sim_card_input_hopper_count(uptr) != 0)
uptr->u5 &= ~URCSTA_EOF; uptr->CMD &= ~URCSTA_EOF;
else { else {
/* Clear unit ready */ /* Clear unit ready */
iostatus &= ~(CARD1_FLAG << u); iostatus &= ~(CARD1_FLAG << u);
@ -273,16 +278,16 @@ t_stat card_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
} }
if (cmd & URCSTA_BINARY) { if (cmd & URCSTA_BINARY) {
uptr->u5 |= URCSTA_BIN; uptr->CMD |= URCSTA_BIN;
*wc = 20; *wc = 20;
} else { } else {
uptr->u5 &= ~URCSTA_BIN; uptr->CMD &= ~URCSTA_BIN;
*wc = 10; *wc = 10;
} }
uptr->u5 &= ~URCSTA_CHMASK; uptr->CMD &= ~URCSTA_CHMASK;
uptr->u5 |= URCSTA_ACTIVE|chan; uptr->CMD |= URCSTA_ACTIVE|chan;
uptr->u4 = 0; uptr->POS = 0;
sim_activate(uptr, 500000); sim_activate(uptr, 500000);
return SCPE_OK; return SCPE_OK;
@ -294,11 +299,11 @@ t_stat card_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
uptr = &cdp_unit[0]; uptr = &cdp_unit[0];
if ((uptr->flags & UNIT_ATT) == 0) if ((uptr->flags & UNIT_ATT) == 0)
return SCPE_UNATT; return SCPE_UNATT;
if (uptr->u5 & URCSTA_ACTIVE) if (uptr->CMD & URCSTA_ACTIVE)
return SCPE_BUSY; return SCPE_BUSY;
uptr->u5 &= ~URCSTA_CHMASK; uptr->CMD &= ~URCSTA_CHMASK;
uptr->u5 |= URCSTA_ACTIVE|chan; uptr->CMD |= URCSTA_ACTIVE|chan;
uptr->u4 = 0; uptr->POS = 0;
*wc = 10; *wc = 10;
sim_activate(uptr, 500000); sim_activate(uptr, 500000);
@ -311,43 +316,43 @@ t_stat card_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
/* Handle transfer of data for card reader */ /* Handle transfer of data for card reader */
t_stat t_stat
cdr_srv(UNIT *uptr) { cdr_srv(UNIT *uptr) {
int chan = URCSTA_CHMASK & uptr->u5; int chan = URCSTA_CHMASK & uptr->CMD;
int u = (uptr - cdr_unit); int u = (uptr - cdr_unit);
uint16 *image = (uint16 *)(uptr->up7); uint16 *image = (uint16 *)(uptr->CARDIMG);
if (uptr->u5 & URCSTA_EOF) { if (uptr->CMD & URCSTA_EOF) {
sim_debug(DEBUG_DETAIL, &cdr_dev, "cdr %d %d unready\n", u, chan); sim_debug(DEBUG_DETAIL, &cdr_dev, "cdr %d %d unready\n", u, chan);
iostatus &= ~(CARD1_FLAG << u); iostatus &= ~(CARD1_FLAG << u);
uptr->u5 &= ~ URCSTA_EOF; uptr->CMD &= ~ URCSTA_EOF;
return SCPE_OK; return SCPE_OK;
} }
/* Check if new card requested. */ /* Check if new card requested. */
if (uptr->u4 == 0 && uptr->u5 & URCSTA_ACTIVE && if (uptr->POS == 0 && uptr->CMD & URCSTA_ACTIVE &&
(uptr->u5 & URCSTA_CARD) == 0) { (uptr->CMD & URCSTA_CARD) == 0) {
switch(sim_read_card(uptr, image)) { switch(sim_read_card(uptr, image)) {
case CDSE_EMPTY: case CDSE_EMPTY:
iostatus &= ~(CARD1_FLAG << u); iostatus &= ~(CARD1_FLAG << u);
uptr->u5 &= ~(URCSTA_ACTIVE); uptr->CMD &= ~(URCSTA_ACTIVE);
iostatus &= ~(CARD1_FLAG << u); iostatus &= ~(CARD1_FLAG << u);
chan_set_notrdy(chan); chan_set_notrdy(chan);
break; break;
case CDSE_EOF: case CDSE_EOF:
/* If end of file, return to system */ /* If end of file, return to system */
uptr->u5 &= ~(URCSTA_ACTIVE); uptr->CMD &= ~(URCSTA_ACTIVE);
uptr->u5 |= URCSTA_EOF; uptr->CMD |= URCSTA_EOF;
chan_set_notrdy(chan); chan_set_notrdy(chan);
sim_activate(uptr, 500); sim_activate(uptr, 500);
break; break;
case CDSE_ERROR: case CDSE_ERROR:
chan_set_error(chan); chan_set_error(chan);
uptr->u5 &= ~(URCSTA_ACTIVE); uptr->CMD &= ~(URCSTA_ACTIVE);
uptr->u5 |= URCSTA_EOF; uptr->CMD |= URCSTA_EOF;
chan_set_end(chan); chan_set_end(chan);
break; break;
case CDSE_OK: case CDSE_OK:
uptr->u5 |= URCSTA_CARD; uptr->CMD |= URCSTA_CARD;
sim_activate(uptr, 500); sim_activate(uptr, 500);
break; break;
} }
@ -356,57 +361,90 @@ cdr_srv(UNIT *uptr) {
/* Copy next column over */ /* Copy next column over */
if (uptr->u5 & URCSTA_CARD && if (uptr->CMD & URCSTA_CARD &&
uptr->u4 < ((uptr->u5 & URCSTA_BIN) ? 160 : 80)) { uptr->POS < ((uptr->CMD & URCSTA_BIN) ? 160 : 80)) {
uint8 ch = 0; uint8 ch = 0;
int u = (uptr - cdr_unit); int u = (uptr - cdr_unit);
if (uptr->u5 & URCSTA_BIN) { if (uptr->CMD & URCSTA_BIN) {
ch = (image[uptr->u4 >> 1] >> ((uptr->u4 & 1)? 0 : 6)) & 077; ch = (image[uptr->POS >> 1] >> ((uptr->POS & 1)? 0 : 6)) & 077;
} else { } else {
ch = sim_hol_to_bcd(image[uptr->u4]); ch = sim_hol_to_bcd(image[uptr->POS]);
/* Remap some characters from 029 to BCL */ /* Remap some characters from 029 to BCL */
/* Sim_hol_to_bcd translates cards by looking at the zones
* 12 - 11 and 10 and setting the two most significant
* digits of the BCD word to 11xxxx, 10xxxx, 01xxxx
* next if 8 is punched it add in 001000 then adds the one
* other digit if it is punched to make the lower four bits
* of the BCD number.
*
* A code of 10 only is returned as 1010 or 10.
* Some of these codes need to be changed because of overlap
* and minor variations in Burroughs code to IBM029 code.
*/
sim_debug(DEBUG_DATA, &cdr_dev, "cdr %d: Char > %03o ", u, ch);
switch(ch) { switch(ch) {
case 0: ch = 020; break; /* Translate blanks */ case 0: ch = 020; break; /* Translate blanks */
case 10: /* Check if 0 punch of 82 punch */ case 012: if (image[uptr->POS] == 0x082) /* 8-2 punch to 015 */
if (image[uptr->u4] != 0x200) { ch = 015;
ch = 0;
if (uptr->u4 == 0)
chan_set_parity(chan);
}
break; break;
case 0111: case 016: ch = 035; break; /* Translate = */
ch = 0; case 017: if (image[uptr->POS] == 0x006) /* Translate " */
/* Handle invalid punch */ ch = 037;
chan_set_parity(chan); break;
case 036: ch = 016; break;
case 037: ch = 0; /* Handle ? */
if (uptr->POS == 0)
chan_set_parity(chan);
break;
case 052: if (image[uptr->POS] == 0x482) /* Translate ! not equal */
ch = 032;
break;
case 072: if (image[uptr->POS] == 0xA00) /* Translate [ */
ch = 074;
else
ch = 036;
break; /* Translate */
case 074: ch = 076; break; /* Translate < */
case 076: ch = 072; break; /* Translate + */
case 0177:
if (image[uptr->POS] == 0x405) /* Translate { */
ch = 057;
else if (image[uptr->POS] == 0x805) /* Translate } */
ch = 017;
else {
ch = 0;
/* Handle invalid punch */
chan_set_parity(chan);
}
break; /* Translate ? to error*/ break; /* Translate ? to error*/
} }
} }
sim_debug(DEBUG_DATA, &cdr_dev, "cdr %d: Char > %03o '%c' %d\n", u, ch, sim_debug(DEBUG_DATA, &cdr_dev, "-> %03o '%c' %d\n", ch,
sim_six_to_ascii[ch & 077], uptr->u4); sim_six_to_ascii[ch & 077], uptr->POS);
if(chan_write_char(chan, &ch, 0)) { if(chan_write_char(chan, &ch, 0)) {
uptr->u5 &= ~(URCSTA_ACTIVE|URCSTA_CARD); uptr->CMD &= ~(URCSTA_ACTIVE|URCSTA_CARD);
chan_set_end(chan); chan_set_end(chan);
/* Drop ready a bit after the last card is read */ /* Drop ready a bit after the last card is read */
if (sim_card_eof(uptr)) { if (sim_card_eof(uptr)) {
uptr->u5 |= URCSTA_EOF; uptr->CMD |= URCSTA_EOF;
sim_activate(uptr, 100); sim_activate(uptr, 100);
} }
} else { } else {
uptr->u4++; uptr->POS++;
sim_activate(uptr, 100); sim_activate(uptr, 100);
} }
} }
/* Check if last column */ /* Check if last column */
if (uptr->u5 & URCSTA_CARD && if (uptr->CMD & URCSTA_CARD &&
uptr->u4 == ((uptr->u5 & URCSTA_BIN) ? 160 : 80)) { uptr->POS == ((uptr->CMD & URCSTA_BIN) ? 160 : 80)) {
uptr->u5 &= ~(URCSTA_ACTIVE|URCSTA_CARD); uptr->CMD &= ~(URCSTA_ACTIVE|URCSTA_CARD);
chan_set_end(chan); chan_set_end(chan);
/* Drop ready a bit after the last card is read */ /* Drop ready a bit after the last card is read */
if (sim_card_eof(uptr)) { if (sim_card_eof(uptr)) {
uptr->u5 |= URCSTA_EOF; uptr->CMD |= URCSTA_EOF;
} }
} }
return SCPE_OK; return SCPE_OK;
@ -423,7 +461,7 @@ cdr_boot(int32 unit_num, DEVICE * dptr)
if ((uptr->flags & UNIT_ATT) == 0) if ((uptr->flags & UNIT_ATT) == 0)
return SCPE_UNATT; /* attached? */ return SCPE_UNATT; /* attached? */
dev = (uptr == &cdr_unit[0]) ? CARD1_DEV : CARD2_DEV; dev = (uptr == &cdr_unit[0]) ? CARD1_DEV : CARD2_DEV;
uptr->u5 &= ~URCSTA_ACTIVE; uptr->CMD &= ~URCSTA_ACTIVE;
desc = ((t_uint64)dev) << DEV_V | DEV_IORD| DEV_BIN | 020LL; desc = ((t_uint64)dev) << DEV_V | DEV_IORD| DEV_BIN | 020LL;
/* Read in one record */ /* Read in one record */
return chan_boot(desc); return chan_boot(desc);
@ -437,11 +475,10 @@ cdr_attach(UNIT * uptr, CONST char *file)
if ((r = sim_card_attach(uptr, file)) != SCPE_OK) if ((r = sim_card_attach(uptr, file)) != SCPE_OK)
return r; return r;
if (uptr->up7 == 0) if (uptr->CARDIMG == 0)
uptr->up7 = malloc(sizeof(uint16)*80); uptr->CARDIMG = malloc(sizeof(uint16)*80);
uptr->u5 &= URCSTA_BUSY; uptr->CMD &= URCSTA_BUSY;
uptr->u4 = 0; uptr->POS = 0;
uptr->u6 = 0;
iostatus |= (CARD1_FLAG << u); iostatus |= (CARD1_FLAG << u);
return SCPE_OK; return SCPE_OK;
} }
@ -451,9 +488,9 @@ cdr_detach(UNIT * uptr)
{ {
int u = uptr-cdr_unit; int u = uptr-cdr_unit;
if (uptr->up7 != 0) if (uptr->CARDIMG != 0)
free(uptr->up7); free(uptr->CARDIMG);
uptr->up7 = 0; uptr->CARDIMG = 0;
iostatus &= ~(CARD1_FLAG << u); iostatus &= ~(CARD1_FLAG << u);
return sim_card_detach(uptr); return sim_card_detach(uptr);
} }
@ -488,7 +525,7 @@ cdp_ini(DEVICE *dptr) {
int i; int i;
for(i = 0; i < NUM_DEVS_CDP; i++) { for(i = 0; i < NUM_DEVS_CDP; i++) {
cdp_unit[i].u5 = 0; cdp_unit[i].CMD = 0;
sim_cancel(&cdp_unit[i]); sim_cancel(&cdp_unit[i]);
} }
return SCPE_OK; return SCPE_OK;
@ -496,13 +533,13 @@ cdp_ini(DEVICE *dptr) {
t_stat t_stat
cdp_srv(UNIT *uptr) { cdp_srv(UNIT *uptr) {
int chan = URCSTA_CHMASK & uptr->u5; int chan = URCSTA_CHMASK & uptr->CMD;
int u = (uptr - cdp_unit); int u = (uptr - cdp_unit);
uint16 *image = (uint16 *)(uptr->up7); uint16 *image = (uint16 *)(uptr->CARDIMG);
if (uptr->u5 & URCSTA_BUSY) { if (uptr->CMD & URCSTA_BUSY) {
/* Done waiting, punch card */ /* Done waiting, punch card */
if (uptr->u5 & URCSTA_FULL) { if (uptr->CMD & URCSTA_FULL) {
sim_debug(DEBUG_DETAIL, &cdp_dev, "cdp %d %d punch\n", u, chan); sim_debug(DEBUG_DETAIL, &cdp_dev, "cdp %d %d punch\n", u, chan);
switch(sim_punch_card(uptr, image)) { switch(sim_punch_card(uptr, image)) {
case CDSE_EOF: case CDSE_EOF:
@ -518,31 +555,48 @@ cdp_srv(UNIT *uptr) {
case CDSE_OK: case CDSE_OK:
break; break;
} }
uptr->u5 &= ~URCSTA_FULL; uptr->CMD &= ~URCSTA_FULL;
chan_set_end(chan); chan_set_end(chan);
} }
uptr->u5 &= ~URCSTA_BUSY; uptr->CMD &= ~URCSTA_BUSY;
} }
/* Copy next column over */ /* Copy next column over */
if (uptr->u5 & URCSTA_ACTIVE && uptr->u4 < 80) { if (uptr->CMD & URCSTA_ACTIVE && uptr->POS < 80) {
uint8 ch = 0; uint8 ch = 0;
uint16 hol;
if(chan_read_char(chan, &ch, 0)) { if(chan_read_char(chan, &ch, 0)) {
uptr->u5 |= URCSTA_BUSY|URCSTA_FULL; uptr->CMD |= URCSTA_BUSY|URCSTA_FULL;
uptr->u5 &= ~URCSTA_ACTIVE; uptr->CMD &= ~URCSTA_ACTIVE;
} else { } else {
sim_debug(DEBUG_DATA, &cdp_dev, "cdp %d: Char %d < %02o\n", u, hol = 0;
uptr->u4, ch); switch (ch & 077) {
image[uptr->u4++] = sim_bcd_to_hol(ch & 077); case 015: hol = 0x082; break; /* : */
case 016: hol = 0x20A; break; /* > */
case 017: hol = 0x805; break; /* } */
case 032: hol = 0x482; break; /* ! */
case 035: hol = 0X00A; break; /* = */
case 036: hol = 0x882; break; /* ] */
case 037: hol = 0x006; break; /* " */
case 057: hol = 0x405; break; /* { */
case 072: hol = 0x80A; break; /* + */
case 074: hol = 0xA00; break; /* [ */
case 076: hol = 0x822; break; /* < */
default:
hol = sim_bcd_to_hol(ch & 077);
}
sim_debug(DEBUG_DATA, &cdp_dev, "cdp %d: Char %d < %02o %03x\n", u,
uptr->POS, ch, hol);
image[uptr->POS++] = hol;
} }
sim_activate(uptr, 10); sim_activate(uptr, 10);
} }
/* Check if last column */ /* Check if last column */
if (uptr->u5 & URCSTA_ACTIVE && uptr->u4 == 80) { if (uptr->CMD & URCSTA_ACTIVE && uptr->POS == 80) {
uptr->u5 |= URCSTA_BUSY|URCSTA_FULL; uptr->CMD |= URCSTA_BUSY|URCSTA_FULL;
uptr->u5 &= ~URCSTA_ACTIVE; uptr->CMD &= ~URCSTA_ACTIVE;
} }
return SCPE_OK; return SCPE_OK;
} }
@ -555,9 +609,9 @@ cdp_attach(UNIT * uptr, CONST char *file)
if ((r = sim_card_attach(uptr, file)) != SCPE_OK) if ((r = sim_card_attach(uptr, file)) != SCPE_OK)
return r; return r;
if (uptr->up7 == 0) { if (uptr->CARDIMG == 0) {
uptr->up7 = calloc(80, sizeof(uint16)); uptr->CARDIMG = calloc(80, sizeof(uint16));
uptr->u5 = 0; uptr->CMD = 0;
iostatus |= PUNCH_FLAG; iostatus |= PUNCH_FLAG;
} }
return SCPE_OK; return SCPE_OK;
@ -566,13 +620,13 @@ cdp_attach(UNIT * uptr, CONST char *file)
t_stat t_stat
cdp_detach(UNIT * uptr) cdp_detach(UNIT * uptr)
{ {
uint16 *image = (uint16 *)(uptr->up7); uint16 *image = (uint16 *)(uptr->CARDIMG);
if (uptr->u5 & URCSTA_FULL) if (uptr->CMD & URCSTA_FULL)
sim_punch_card(uptr, image); sim_punch_card(uptr, image);
if (uptr->up7 != 0) if (uptr->CARDIMG != 0)
free(uptr->up7); free(uptr->CARDIMG);
uptr->up7 = 0; uptr->CARDIMG = 0;
iostatus &= ~PUNCH_FLAG; iostatus &= ~PUNCH_FLAG;
return sim_card_detach(uptr); return sim_card_detach(uptr);
} }
@ -604,7 +658,7 @@ lpr_ini(DEVICE *dptr) {
int i; int i;
for(i = 0; i < NUM_DEVS_LPR; i++) { for(i = 0; i < NUM_DEVS_LPR; i++) {
lpr_unit[i].u5 = 0; lpr_unit[i].CMD = 0;
sim_cancel(&lpr_unit[i]); sim_cancel(&lpr_unit[i]);
} }
return SCPE_OK; return SCPE_OK;
@ -628,7 +682,7 @@ lpr_setlpp(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
if (i < 20 || i > 100) if (i < 20 || i > 100)
return SCPE_ARG; return SCPE_ARG;
uptr->capac = i; uptr->capac = i;
uptr->u4 = 0; uptr->LINENUM = 0;
return SCPE_OK; return SCPE_OK;
} }
@ -651,17 +705,17 @@ print_line(UNIT * uptr, int unit)
char out[150]; /* Temp conversion buffer */ char out[150]; /* Temp conversion buffer */
int i; int i;
int chan = uptr->u5 & URCSTA_CHMASK; int chan = uptr->CMD & URCSTA_CHMASK;
if ((uptr->flags & (UNIT_ATT)) == 0) if ((uptr->flags & (UNIT_ATT)) == 0)
return; /* attached? */ return; /* attached? */
if (uptr->u3 > 0) { if (uptr->POS > 0) {
/* Try to convert to text */ /* Try to convert to text */
memset(out, 0, sizeof(out)); memset(out, 0, sizeof(out));
/* Scan each column */ /* Scan each column */
for (i = 0; i < uptr->u3; i++) { for (i = 0; i < uptr->POS; i++) {
int bcd = lpr_data[unit].lbuff[i] & 077; int bcd = lpr_data[unit].lbuff[i] & 077;
out[i] = con_to_ascii[bcd]; out[i] = con_to_ascii[bcd];
@ -672,73 +726,73 @@ print_line(UNIT * uptr, int unit)
out[i+1] = '\0'; out[i+1] = '\0';
sim_debug(DEBUG_DETAIL, &lpr_dev, "lpr print %s\n", out); sim_debug(DEBUG_DETAIL, &lpr_dev, "lpr print %s\n", out);
if (uptr->u5 & (URCSTA_DOUBLE << URCSTA_CMD_V)) { if (uptr->CMD & (URCSTA_DOUBLE << URCSTA_CMD_V)) {
out[++i] = '\r'; out[++i] = '\r';
out[++i] = '\n'; out[++i] = '\n';
uptr->u4 ++; uptr->LINENUM ++;
} }
out[++i] = '\r'; out[++i] = '\r';
out[++i] = '\n'; out[++i] = '\n';
uptr->u4++; uptr->LINENUM++;
out[++i] = '\0'; out[++i] = '\0';
/* Print out buffer */ /* Print out buffer */
sim_fwrite(&out, 1, i, uptr->fileref); sim_fwrite(&out, 1, i, uptr->fileref);
uptr->u5 &= ~URCSTA_EOF; uptr->CMD &= ~URCSTA_EOF;
} }
switch ((uptr->u5 >> URCSTA_CMD_V) & URCSTA_SKIP) { switch ((uptr->CMD >> URCSTA_CMD_V) & URCSTA_SKIP) {
case 0: /* No special skip */ case 0: /* No special skip */
break; break;
case 1: case 1:
case 2: /* Skip to top of form */ case 2: /* Skip to top of form */
case 12: case 12:
uptr->u4 = uptr->capac+1; uptr->LINENUM = uptr->capac+1;
break; break;
case 3: /* Even lines */ case 3: /* Even lines */
if ((uptr->u4 & 1) == 1) { if ((uptr->LINENUM & 1) == 1) {
sim_fwrite("\r", 1, 1, uptr->fileref); sim_fwrite("\r", 1, 1, uptr->fileref);
sim_fwrite("\n", 1, 1, uptr->fileref); sim_fwrite("\n", 1, 1, uptr->fileref);
uptr->u4++; uptr->LINENUM++;
uptr->u5 &= ~URCSTA_EOF; uptr->CMD &= ~URCSTA_EOF;
} }
break; break;
case 4: /* Odd lines */ case 4: /* Odd lines */
if ((uptr->u4 & 1) == 0) { if ((uptr->LINENUM & 1) == 0) {
sim_fwrite("\r", 1, 1, uptr->fileref); sim_fwrite("\r", 1, 1, uptr->fileref);
sim_fwrite("\n", 1, 1, uptr->fileref); sim_fwrite("\n", 1, 1, uptr->fileref);
uptr->u4++; uptr->LINENUM++;
uptr->u5 &= ~URCSTA_EOF; uptr->CMD &= ~URCSTA_EOF;
} }
break; break;
case 5: /* Half page */ case 5: /* Half page */
while((uptr->u4 != (uptr->capac/2)) || while((uptr->LINENUM != (uptr->capac/2)) ||
(uptr->u4 != (uptr->capac))) { (uptr->LINENUM != (uptr->capac))) {
sim_fwrite("\r", 1, 1, uptr->fileref); sim_fwrite("\r", 1, 1, uptr->fileref);
sim_fwrite("\n", 1, 1, uptr->fileref); sim_fwrite("\n", 1, 1, uptr->fileref);
uptr->u4++; uptr->LINENUM++;
if (((uint32)uptr->u4) > uptr->capac) { if (((uint32)uptr->LINENUM) > uptr->capac) {
uptr->u4 = 1; uptr->LINENUM = 1;
break; break;
} }
uptr->u5 &= ~URCSTA_EOF; uptr->CMD &= ~URCSTA_EOF;
} }
break; break;
case 6: /* 1/4 Page */ case 6: /* 1/4 Page */
while((uptr->u4 != (uptr->capac/4)) || while((uptr->LINENUM != (uptr->capac/4)) ||
(uptr->u4 != (uptr->capac/2)) || (uptr->LINENUM != (uptr->capac/2)) ||
(uptr->u4 != (uptr->capac/2+uptr->capac/4)) || (uptr->LINENUM != (uptr->capac/2+uptr->capac/4)) ||
(uptr->u4 != (uptr->capac))) { (uptr->LINENUM != (uptr->capac))) {
sim_fwrite("\r", 1, 1, uptr->fileref); sim_fwrite("\r", 1, 1, uptr->fileref);
sim_fwrite("\n", 1, 1, uptr->fileref); sim_fwrite("\n", 1, 1, uptr->fileref);
uptr->u4++; uptr->LINENUM++;
if (((uint32)uptr->u4) > uptr->capac) { if (((uint32)uptr->LINENUM) > uptr->capac) {
uptr->u4 = 1; uptr->LINENUM = 1;
break; break;
} }
uptr->u5 &= ~URCSTA_EOF; uptr->CMD &= ~URCSTA_EOF;
} }
break; break;
case 7: /* User defined, now 1 line */ case 7: /* User defined, now 1 line */
@ -748,14 +802,14 @@ print_line(UNIT * uptr, int unit)
case 11: case 11:
sim_fwrite("\r", 1, 1, uptr->fileref); sim_fwrite("\r", 1, 1, uptr->fileref);
sim_fwrite("\n", 1, 1, uptr->fileref); sim_fwrite("\n", 1, 1, uptr->fileref);
uptr->u4++; uptr->LINENUM++;
break; break;
} }
if (((uint32)uptr->u4) > uptr->capac) { if (((uint32)uptr->LINENUM) > uptr->capac) {
uptr->u4 = 1; uptr->LINENUM = 1;
uptr->u5 |= URCSTA_EOF; uptr->CMD |= URCSTA_EOF;
sim_fwrite("\f", 1, 1, uptr->fileref); sim_fwrite("\f", 1, 1, uptr->fileref);
sim_fseek(uptr->fileref, 0, SEEK_CUR); sim_fseek(uptr->fileref, 0, SEEK_CUR);
sim_debug(DEBUG_DETAIL, &lpr_dev, "lpr %d page\n", unit); sim_debug(DEBUG_DETAIL, &lpr_dev, "lpr %d page\n", unit);
@ -779,7 +833,7 @@ t_stat lpr_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
uptr = &lpr_unit[u]; uptr = &lpr_unit[u];
/* Are we currently tranfering? */ /* Are we currently tranfering? */
if (uptr->u5 & URCSTA_BUSY) if (uptr->CMD & URCSTA_BUSY)
return SCPE_BUSY; return SCPE_BUSY;
if ((uptr->flags & UNIT_ATT) == 0) if ((uptr->flags & UNIT_ATT) == 0)
@ -789,13 +843,13 @@ t_stat lpr_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
*wc = (cmd & URCSTA_DIRECT) ? 17 : 15; *wc = (cmd & URCSTA_DIRECT) ? 17 : 15;
/* Remember not to drop the FULL */ /* Remember not to drop the FULL */
uptr->u5 &= ~((077 << URCSTA_CMD_V) | URCSTA_CHMASK); uptr->CMD &= ~((077 << URCSTA_CMD_V) | URCSTA_CHMASK);
uptr->u5 |= URCSTA_BUSY|chan; uptr->CMD |= URCSTA_BUSY|chan;
uptr->u5 |= (cmd & (URCSTA_SKIP|URCSTA_SINGLE|URCSTA_DOUBLE)) uptr->CMD |= (cmd & (URCSTA_SKIP|URCSTA_SINGLE|URCSTA_DOUBLE))
<< URCSTA_CMD_V; << URCSTA_CMD_V;
uptr->u3 = 0; uptr->POS = 0;
sim_debug(DEBUG_CMD, &lpr_dev, "%d: Cmd WRS %d %02o %o\n", u, chan, sim_debug(DEBUG_CMD, &lpr_dev, "%d: Cmd WRS %d %02o %o\n", u, chan,
cmd & (URCSTA_SKIP|URCSTA_SINGLE|URCSTA_DOUBLE),uptr->u5); cmd & (URCSTA_SKIP|URCSTA_SINGLE|URCSTA_DOUBLE),uptr->CMD);
sim_activate(uptr, 100); sim_activate(uptr, 100);
return SCPE_OK; return SCPE_OK;
} }
@ -803,31 +857,31 @@ t_stat lpr_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
/* Handle transfer of data for printer */ /* Handle transfer of data for printer */
t_stat t_stat
lpr_srv(UNIT *uptr) { lpr_srv(UNIT *uptr) {
int chan = URCSTA_CHMASK & uptr->u5; int chan = URCSTA_CHMASK & uptr->CMD;
int u = (uptr - lpr_unit); int u = (uptr - lpr_unit);
if (uptr->u5 & URCSTA_FULL) { if (uptr->CMD & URCSTA_FULL) {
sim_debug(DEBUG_CMD, &lpr_dev, "lpr %d: done\n", u); sim_debug(DEBUG_CMD, &lpr_dev, "lpr %d: done\n", u);
uptr->u5 &= ~URCSTA_FULL; uptr->CMD &= ~URCSTA_FULL;
IAR |= (IRQ_3 << u); IAR |= (IRQ_3 << u);
} }
/* Copy next column over */ /* Copy next column over */
if ((uptr->u5 & URCSTA_BUSY) != 0) { if ((uptr->CMD & URCSTA_BUSY) != 0) {
if(chan_read_char(chan, &lpr_data[u].lbuff[uptr->u3], 0)) { if(chan_read_char(chan, &lpr_data[u].lbuff[uptr->POS], 0)) {
/* Done waiting, print line */ /* Done waiting, print line */
print_line(uptr, u); print_line(uptr, u);
memset(&lpr_data[u].lbuff[0], 0, 144); memset(&lpr_data[u].lbuff[0], 0, 144);
uptr->u5 |= URCSTA_FULL; uptr->CMD |= URCSTA_FULL;
uptr->u5 &= ~URCSTA_BUSY; uptr->CMD &= ~URCSTA_BUSY;
chan_set_wc(chan, (uptr->u3/8)); chan_set_wc(chan, (uptr->POS/8));
chan_set_end(chan); chan_set_end(chan);
sim_activate(uptr, 20000); sim_activate(uptr, 20000);
return SCPE_OK; return SCPE_OK;
} else { } else {
sim_debug(DEBUG_DATA, &lpr_dev, "lpr %d: Char < %02o\n", u, sim_debug(DEBUG_DATA, &lpr_dev, "lpr %d: Char < %02o\n", u,
lpr_data[u].lbuff[uptr->u3]); lpr_data[u].lbuff[uptr->POS]);
uptr->u3++; uptr->POS++;
} }
sim_activate(uptr, 50); sim_activate(uptr, 50);
} }
@ -842,9 +896,9 @@ lpr_attach(UNIT * uptr, CONST char *file)
if ((r = attach_unit(uptr, file)) != SCPE_OK) if ((r = attach_unit(uptr, file)) != SCPE_OK)
return r; return r;
uptr->u5 = 0; uptr->CMD = 0;
uptr->u4 = 0; uptr->LINENUM = 0;
uptr->u3 = 0; uptr->POS = 0;
iostatus |= PRT1_FLAG << u; iostatus |= PRT1_FLAG << u;
return SCPE_OK; return SCPE_OK;
} }
@ -853,7 +907,7 @@ t_stat
lpr_detach(UNIT * uptr) lpr_detach(UNIT * uptr)
{ {
int u = (uptr - lpr_unit); int u = (uptr - lpr_unit);
if (uptr->u5 & URCSTA_FULL) if (uptr->CMD & URCSTA_FULL)
print_line(uptr, u); print_line(uptr, u);
iostatus &= ~(PRT1_FLAG << u); iostatus &= ~(PRT1_FLAG << u);
return detach_unit(uptr); return detach_unit(uptr);
@ -904,7 +958,7 @@ lpr_description(DEVICE *dptr)
t_stat t_stat
con_ini(DEVICE *dptr) { con_ini(DEVICE *dptr) {
UNIT *uptr = &con_unit[0]; UNIT *uptr = &con_unit[0];
uptr->u5 = 0; uptr->CMD = 0;
iostatus |= SPO_FLAG; iostatus |= SPO_FLAG;
if (!sim_is_active(uptr)) if (!sim_is_active(uptr))
sim_activate(uptr, 1000); sim_activate(uptr, 1000);
@ -917,28 +971,28 @@ con_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
UNIT *uptr = &con_unit[0]; UNIT *uptr = &con_unit[0];
/* Are we currently tranfering? */ /* Are we currently tranfering? */
if (uptr->u5 & (URCSTA_READ|URCSTA_FILL|URCSTA_BUSY|URCSTA_INPUT)) if (uptr->CMD & (URCSTA_READ|URCSTA_FILL|URCSTA_BUSY|URCSTA_INPUT))
return SCPE_BUSY; return SCPE_BUSY;
if (cmd & URCSTA_READ) { if (cmd & URCSTA_READ) {
if (uptr->u5 & (URCSTA_INPUT|URCSTA_FILL)) if (uptr->CMD & (URCSTA_INPUT|URCSTA_FILL))
return SCPE_BUSY; return SCPE_BUSY;
/* Activate input so we can get response */ /* Activate input so we can get response */
uptr->u5 = 0; uptr->CMD = 0;
uptr->u5 |= URCSTA_INPUT|chan; uptr->CMD |= URCSTA_INPUT|chan;
sim_putchar('I'); sim_putchar('I');
sim_putchar(' '); sim_putchar(' ');
sim_debug(DEBUG_CMD, &con_dev, ": Cmd RDS\n"); sim_debug(DEBUG_CMD, &con_dev, ": Cmd RDS\n");
uptr->u3 = 0; uptr->POS = 0;
} else { } else {
if (uptr->u5 & (URCSTA_INPUT|URCSTA_FILL)) if (uptr->CMD & (URCSTA_INPUT|URCSTA_FILL))
return SCPE_BUSY; return SCPE_BUSY;
sim_putchar('R'); sim_putchar('R');
sim_putchar(' '); sim_putchar(' ');
sim_debug(DEBUG_CMD, &con_dev, ": Cmd WRS\n"); sim_debug(DEBUG_CMD, &con_dev, ": Cmd WRS\n");
uptr->u5 = 0; uptr->CMD = 0;
uptr->u5 |= URCSTA_FILL|chan; uptr->CMD |= URCSTA_FILL|chan;
uptr->u3 = 0; uptr->POS = 0;
} }
return SCPE_OK; return SCPE_OK;
} }
@ -948,18 +1002,18 @@ t_stat
con_srv(UNIT *uptr) { con_srv(UNIT *uptr) {
t_stat r; t_stat r;
uint8 ch; uint8 ch;
int chan = uptr->u5 & URCSTA_CHMASK; int chan = uptr->CMD & URCSTA_CHMASK;
uptr->u5 &= ~URCSTA_BUSY; /* Clear busy */ uptr->CMD &= ~URCSTA_BUSY; /* Clear busy */
/* Copy next column over */ /* Copy next column over */
if (uptr->u5 & URCSTA_FILL) { if (uptr->CMD & URCSTA_FILL) {
if(chan_read_char(chan, &ch, 0)) { if(chan_read_char(chan, &ch, 0)) {
sim_putchar('\r'); sim_putchar('\r');
sim_putchar('\n'); sim_putchar('\n');
sim_debug(DEBUG_EXP, &con_dev, "\n\r"); sim_debug(DEBUG_EXP, &con_dev, "\n\r");
uptr->u5 &= ~URCSTA_FILL; uptr->CMD &= ~URCSTA_FILL;
chan_set_end(chan); chan_set_end(chan);
} else { } else {
ch &= 077; ch &= 077;
@ -968,7 +1022,7 @@ con_srv(UNIT *uptr) {
} }
} }
if (uptr->u5 & URCSTA_READ) { if (uptr->CMD & URCSTA_READ) {
ch = con_data[0].ibuff[con_data[0].outptr++]; ch = con_data[0].ibuff[con_data[0].outptr++];
if(chan_write_char(chan, &ch, if(chan_write_char(chan, &ch,
@ -976,7 +1030,7 @@ con_srv(UNIT *uptr) {
sim_putchar('\r'); sim_putchar('\r');
sim_putchar('\n'); sim_putchar('\n');
sim_debug(DEBUG_EXP, &con_dev, "\n\r"); sim_debug(DEBUG_EXP, &con_dev, "\n\r");
uptr->u5 &= ~URCSTA_READ; uptr->CMD &= ~URCSTA_READ;
chan_set_end(chan); chan_set_end(chan);
} }
} }
@ -984,7 +1038,7 @@ con_srv(UNIT *uptr) {
r = sim_poll_kbd(); r = sim_poll_kbd();
if (r & SCPE_KFLAG) { if (r & SCPE_KFLAG) {
ch = r & 0377; ch = r & 0377;
if (uptr->u5 & URCSTA_INPUT) { if (uptr->CMD & URCSTA_INPUT) {
/* Handle end of buffer */ /* Handle end of buffer */
switch (ch) { switch (ch) {
case 033: case 033:
@ -992,8 +1046,8 @@ con_srv(UNIT *uptr) {
/* Fall through */ /* Fall through */
case '\r': case '\r':
case '\n': case '\n':
uptr->u5 &= ~URCSTA_INPUT; uptr->CMD &= ~URCSTA_INPUT;
uptr->u5 |= URCSTA_READ; uptr->CMD |= URCSTA_READ;
break; break;
case '\b': case '\b':
case 0x7f: case 0x7f:
@ -1025,7 +1079,7 @@ con_srv(UNIT *uptr) {
} }
} }
if (uptr->u5 & (URCSTA_FILL|URCSTA_READ)) if (uptr->CMD & (URCSTA_FILL|URCSTA_READ))
sim_activate(uptr, 1000); sim_activate(uptr, 1000);
else else
sim_clock_coschedule_tmr (con_unit, TMR_RTC, 1); sim_clock_coschedule_tmr (con_unit, TMR_RTC, 1);