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Intel-Systems, IBMPC: Standardize to CRLF line endings and spaces for tabs

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This commit is contained in:
Bill Beech 2017-03-13 19:42:55 -07:00 • committed by Mark Pizzolato
parent 18efafe927
commit a221ac4055
40 changed files with 13418 additions and 13418 deletions
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4
Intel-Systems/common/ieprom.c
View file

@ -49,7 +49,7 @@ uint8 EPROM_get_mbyte(uint16 addr);
/* external function prototypes */ /* external function prototypes */
extern uint8 i8255_C[4]; //port c byte I/O extern uint8 i8255_C[4]; //port c byte I/O
extern uint8 xack; /* XACK signal */ extern uint8 xack; /* XACK signal */
/* SIMH EPROM Standard I/O Data Structures */ /* SIMH EPROM Standard I/O Data Structures */
@ -82,7 +82,7 @@ DEVICE EPROM_dev = {
NULL, //examine NULL, //examine
NULL, //deposit NULL, //deposit
// &EPROM_reset, //reset // &EPROM_reset, //reset
NULL, //reset NULL, //reset
NULL, //boot NULL, //boot
&EPROM_attach, //attach &EPROM_attach, //attach
NULL, //detach NULL, //detach

4
Intel-Systems/common/ipceprom.c
View file

@ -48,7 +48,7 @@ uint8 EPROM_get_mbyte(uint16 addr);
/* external function prototypes */ /* external function prototypes */
extern uint8 xack; /* XACK signal */ extern uint8 xack; /* XACK signal */
extern UNIT ipc_cont_unit[]; extern UNIT ipc_cont_unit[];
/* SIMH EPROM Standard I/O Data Structures */ /* SIMH EPROM Standard I/O Data Structures */
@ -82,7 +82,7 @@ DEVICE EPROM_dev = {
NULL, //examine NULL, //examine
NULL, //deposit NULL, //deposit
// &EPROM_reset, //reset // &EPROM_reset, //reset
NULL, //reset NULL, //reset
NULL, //boot NULL, //boot
&EPROM_attach, //attach &EPROM_attach, //attach
NULL, //detach NULL, //detach

2
Intel-Systems/common/ipcmultibus.c
View file

@ -264,7 +264,7 @@ uint16 reg_dev(uint8 (*routine)(t_bool io, uint8 data), uint16 port, uint8 devnu
dev_table[port].routine = routine; dev_table[port].routine = routine;
dev_table[port].devnum = devnum; dev_table[port].devnum = devnum;
} }
return 0; return 0;
} }
/* get a byte from memory */ /* get a byte from memory */

12
Intel-Systems/common/isbc201.c
View file

@ -185,8 +185,8 @@
/* external globals */ /* external globals */
extern uint16 port; //port called in dev_table[port] extern uint16 port; //port called in dev_table[port]
extern int32 PCX; extern int32 PCX;
/* external function prototypes */ /* external function prototypes */
@ -472,7 +472,7 @@ uint8 isbc2010(t_bool io, uint8 data)
if (io == 0) { /* read ststus*/ if (io == 0) { /* read ststus*/
if (DEBUG) if (DEBUG)
sim_printf("\n isbc201-%d: 0x78 returned status=%02X PCX=%04X", sim_printf("\n isbc201-%d: 0x78 returned status=%02X PCX=%04X",
fdcnum, fdc201[fdcnum].stat, PCX); fdcnum, fdc201[fdcnum].stat, PCX);
return fdc201[fdcnum].stat; return fdc201[fdcnum].stat;
} }
} }
@ -495,7 +495,7 @@ uint8 isbc2011(t_bool io, uint8 data)
fdc201[fdcnum].iopb = data; fdc201[fdcnum].iopb = data;
if (DEBUG) if (DEBUG)
sim_printf("\n isbc201-%d: 0x79 IOPB low=%02X PCX=%04X", sim_printf("\n isbc201-%d: 0x79 IOPB low=%02X PCX=%04X",
fdcnum, data, PCX); fdcnum, data, PCX);
} }
} }
return 0; return 0;
@ -527,12 +527,12 @@ uint8 isbc2013(t_bool io, uint8 data)
if ((fdcnum = isbc201_get_dn()) != 0xFF) { if ((fdcnum = isbc201_get_dn()) != 0xFF) {
if (io == 0) { /* read data port */ if (io == 0) { /* read data port */
if (fdc201[fdcnum].rtype == 0) { if (fdc201[fdcnum].rtype == 0) {
if (DEBUG) if (DEBUG)
sim_printf("\n isbc201-%d: 0x7B returned rbyte0=%02X PCX=%04X", sim_printf("\n isbc201-%d: 0x7B returned rbyte0=%02X PCX=%04X",
fdcnum, fdc201[fdcnum].rbyte0, PCX); fdcnum, fdc201[fdcnum].rbyte0, PCX);
return fdc201[fdcnum].rbyte0; return fdc201[fdcnum].rbyte0;
} else { } else {
if (fdc201[fdcnum].rdychg) { if (fdc201[fdcnum].rdychg) {
if (DEBUG) if (DEBUG)
sim_printf("\n isbc201-%d: 0x7B returned rbyte1=%02X PCX=%04X", sim_printf("\n isbc201-%d: 0x7B returned rbyte1=%02X PCX=%04X",

10
Intel-Systems/common/isbc202.c
View file

@ -495,7 +495,7 @@ uint8 isbc2020(t_bool io, uint8 data)
if (io == 0) { /* read ststus*/ if (io == 0) { /* read ststus*/
if (DEBUG) if (DEBUG)
sim_printf("\n isbc202-%d: 0x78 returned status=%02X PCX=%04X", sim_printf("\n isbc202-%d: 0x78 returned status=%02X PCX=%04X",
fdcnum, fdc202[fdcnum].stat, PCX); fdcnum, fdc202[fdcnum].stat, PCX);
return fdc202[fdcnum].stat; return fdc202[fdcnum].stat;
} }
} }
@ -535,7 +535,7 @@ uint8 isbc2022(t_bool io, uint8 data)
fdc202[fdcnum].iopb |= (data << 8); fdc202[fdcnum].iopb |= (data << 8);
if (DEBUG) if (DEBUG)
sim_printf("\n isbc202-%d: 0x7A IOPB=%04X PCX=%04X", sim_printf("\n isbc202-%d: 0x7A IOPB=%04X PCX=%04X",
fdcnum, fdc202[fdcnum].iopb, PCX); fdcnum, fdc202[fdcnum].iopb, PCX);
isbc202_diskio(fdcnum); isbc202_diskio(fdcnum);
if (fdc202[fdcnum].intff) if (fdc202[fdcnum].intff)
fdc202[fdcnum].stat |= FDCINT; fdc202[fdcnum].stat |= FDCINT;
@ -550,12 +550,12 @@ uint8 isbc2023(t_bool io, uint8 data)
if ((fdcnum = isbc202_get_dn()) != 0xFF) { if ((fdcnum = isbc202_get_dn()) != 0xFF) {
if (io == 0) { /* read data port */ if (io == 0) { /* read data port */
if (fdc202[fdcnum].rtype == 0) { if (fdc202[fdcnum].rtype == 0) {
if (DEBUG) if (DEBUG)
sim_printf("\n isbc202-%d: 0x7B returned rbyte0=%02X PCX=%04X", sim_printf("\n isbc202-%d: 0x7B returned rbyte0=%02X PCX=%04X",
fdcnum, fdc202[fdcnum].rbyte0, PCX); fdcnum, fdc202[fdcnum].rbyte0, PCX);
return fdc202[fdcnum].rbyte0; return fdc202[fdcnum].rbyte0;
} else { } else {
if (fdc202[fdcnum].rdychg) { if (fdc202[fdcnum].rdychg) {
if (DEBUG) if (DEBUG)
sim_printf("\n isbc202-%d: 0x7B returned rbyte1=%02X PCX=%04X", sim_printf("\n isbc202-%d: 0x7B returned rbyte1=%02X PCX=%04X",
@ -567,7 +567,7 @@ uint8 isbc2023(t_bool io, uint8 data)
fdcnum, 0, PCX); fdcnum, 0, PCX);
return 0; return 0;
} }
} }
} else { /* write data port */ } else { /* write data port */
; //stop diskette operation ; //stop diskette operation
} }

10
Intel-Systems/common/zx200a.c
View file

@ -520,7 +520,7 @@ uint8 zx200a0(t_bool io, uint8 data)
if (io == 0) { /* read ststus*/ if (io == 0) { /* read ststus*/
if (DEBUG) if (DEBUG)
sim_printf("\n zx-200a0-%d: 0x78/88 returned status=%02X PCX=%04X", sim_printf("\n zx-200a0-%d: 0x78/88 returned status=%02X PCX=%04X",
fdcnum, zx200a[fdcnum].stat, PCX); fdcnum, zx200a[fdcnum].stat, PCX);
return zx200a[fdcnum].stat; return zx200a[fdcnum].stat;
} }
} }
@ -560,7 +560,7 @@ uint8 zx200a2(t_bool io, uint8 data)
zx200a[fdcnum].iopb |= (data << 8); zx200a[fdcnum].iopb |= (data << 8);
if (DEBUG) if (DEBUG)
sim_printf("\n zx-200a2-%d: 0x7A/8A IOPB=%04X PCX=%04X", sim_printf("\n zx-200a2-%d: 0x7A/8A IOPB=%04X PCX=%04X",
fdcnum, zx200a[fdcnum].iopb, PCX); fdcnum, zx200a[fdcnum].iopb, PCX);
zx200a_diskio(fdcnum); zx200a_diskio(fdcnum);
if (zx200a[fdcnum].intff) if (zx200a[fdcnum].intff)
zx200a[fdcnum].stat |= FDCINT; zx200a[fdcnum].stat |= FDCINT;
@ -575,12 +575,12 @@ uint8 zx200a3(t_bool io, uint8 data)
if ((fdcnum = zx200_get_dn()) != 0xFF) { if ((fdcnum = zx200_get_dn()) != 0xFF) {
if (io == 0) { /* read data port */ if (io == 0) { /* read data port */
if (zx200a[fdcnum].rtype == 0) { if (zx200a[fdcnum].rtype == 0) {
if (DEBUG) if (DEBUG)
sim_printf("\n zx200a3-%d: 0x7B/8B returned rbyte0=%02X PCX=%04X", sim_printf("\n zx200a3-%d: 0x7B/8B returned rbyte0=%02X PCX=%04X",
fdcnum, zx200a[fdcnum].rbyte0, PCX); fdcnum, zx200a[fdcnum].rbyte0, PCX);
return zx200a[fdcnum].rbyte0; return zx200a[fdcnum].rbyte0;
} else { } else {
if (zx200a[fdcnum].rdychg) { if (zx200a[fdcnum].rdychg) {
if (DEBUG) if (DEBUG)
sim_printf("\n zx200a3-%d: 0x7B/8B returned rbyte1=%02X PCX=%04X", sim_printf("\n zx200a3-%d: 0x7B/8B returned rbyte1=%02X PCX=%04X",
@ -592,7 +592,7 @@ uint8 zx200a3(t_bool io, uint8 data)
fdcnum, 0, PCX); fdcnum, 0, PCX);
return 0; return 0;
} }
} }
} else { /* write data port */ } else { /* write data port */
; //stop diskette operation ; //stop diskette operation
} }

30
Intel-Systems/imds-225/system_defs.h
View file

@ -28,7 +28,7 @@
#include <stdio.h> #include <stdio.h>
#include <ctype.h> #include <ctype.h>
#include "sim_defs.h" /* simulator defns */ #include "sim_defs.h" /* simulator defns */
#define IPC 0 #define IPC 0
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
@ -69,17 +69,17 @@
//board definitions for the multibus //board definitions for the multibus
/* set the base I/O address for the iSBC 201 */ /* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x88 #define SBC201_BASE 0x88
#define SBC201_INT INT_1 #define SBC201_INT INT_1
#define SBC201_NUM 0 #define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */ /* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78 #define SBC202_BASE 0x78
#define SBC202_INT INT_1 #define SBC202_INT INT_1
#define SBC202_NUM 1 #define SBC202_NUM 1
/* set the base I/O address for the iSBC 208 */ /* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40 #define SBC208_BASE 0x40
#define SBC208_INT INT_1 #define SBC208_INT INT_1
#define SBC208_NUM 0 #define SBC208_NUM 0
@ -111,10 +111,10 @@
/* Memory */ /* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */ #define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */ #define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */ #define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
/* debug definitions */ /* debug definitions */
@ -130,11 +130,11 @@
/* Simulator stop codes */ /* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */ #define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */ #define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */ #define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */ #define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */ #define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */ #define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */ #define STOP_XACK 7 /* XACK error */

12
Intel-Systems/isys8010/isbc8010.c
View file

@ -87,14 +87,14 @@ uint8 get_mbyte(uint16 addr)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr < (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit.u3) && ((uint16)addr < (EPROM_unit.u3 + EPROM_unit.capac))) {
return EPROM_get_mbyte(addr); return EPROM_get_mbyte(addr);
} }
} /* if local RAM handle it */ } /* if local RAM handle it */
if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */ if ((RAM_DISABLE && (i8255_C[0] & 0x20)) || (RAM_DISABLE == 0)) { /* RAM enabled */
if ((addr >= RAM_unit.u3) && ((uint16)addr < (RAM_unit.u3 + RAM_unit.capac))) { if ((addr >= RAM_unit.u3) && ((uint16)addr < (RAM_unit.u3 + RAM_unit.capac))) {
return RAM_get_mbyte(addr); return RAM_get_mbyte(addr);
} }
} /* otherwise, try the multibus */ } /* otherwise, try the multibus */
return multibus_get_mbyte(addr); return multibus_get_mbyte(addr);
} }

30
Intel-Systems/isys8010/system_defs.h
View file

@ -28,7 +28,7 @@
#include <stdio.h> #include <stdio.h>
#include <ctype.h> #include <ctype.h>
#include "sim_defs.h" /* simulator defns */ #include "sim_defs.h" /* simulator defns */
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
@ -57,17 +57,17 @@
//board definitions for the multibus //board definitions for the multibus
/* set the base I/O address for the iSBC 201 */ /* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x88 #define SBC201_BASE 0x88
#define SBC201_INT INT_1 #define SBC201_INT INT_1
#define SBC201_NUM 1 #define SBC201_NUM 1
/* set the base I/O address for the iSBC 202 */ /* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78 #define SBC202_BASE 0x78
#define SBC202_INT INT_1 #define SBC202_INT INT_1
#define SBC202_NUM 1 #define SBC202_NUM 1
/* set the base I/O address for the iSBC 208 */ /* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40 #define SBC208_BASE 0x40
#define SBC208_INT INT_1 #define SBC208_INT INT_1
#define SBC208_NUM 0 #define SBC208_NUM 0
@ -101,10 +101,10 @@
/* Memory */ /* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */ #define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */ #define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */ #define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
/* debug definitions */ /* debug definitions */
@ -120,11 +120,11 @@
/* Simulator stop codes */ /* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */ #define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */ #define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */ #define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */ #define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */ #define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */ #define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */ #define STOP_XACK 7 /* XACK error */

30
Intel-Systems/isys8020/system_defs.h
View file

@ -28,7 +28,7 @@
#include <stdio.h> #include <stdio.h>
#include <ctype.h> #include <ctype.h>
#include "sim_defs.h" /* simulator defns */ #include "sim_defs.h" /* simulator defns */
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
@ -61,17 +61,17 @@
//board definitions for the multibus //board definitions for the multibus
/* set the base I/O address for the iSBC 201 */ /* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x78 #define SBC201_BASE 0x78
#define SBC201_INT INT_1 #define SBC201_INT INT_1
#define SBC201_NUM 0 #define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */ /* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78 #define SBC202_BASE 0x78
#define SBC202_INT INT_1 #define SBC202_INT INT_1
#define SBC202_NUM 1 #define SBC202_NUM 1
/* set the base I/O address for the iSBC 208 */ /* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40 #define SBC208_BASE 0x40
#define SBC208_INT INT_1 #define SBC208_INT INT_1
#define SBC208_NUM 0 #define SBC208_NUM 0
@ -105,10 +105,10 @@
/* Memory */ /* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */ #define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */ #define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */ #define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
/* debug definitions */ /* debug definitions */
@ -124,11 +124,11 @@
/* Simulator stop codes */ /* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */ #define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */ #define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */ #define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */ #define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */ #define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */ #define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */ #define STOP_XACK 7 /* XACK error */

12
Intel-Systems/isys8024/isbc8024.c
View file

@ -95,14 +95,14 @@ uint8 get_mbyte(uint16 addr)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr < (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit.u3) && ((uint16)addr < (EPROM_unit.u3 + EPROM_unit.capac))) {
return EPROM_get_mbyte(addr); return EPROM_get_mbyte(addr);
} }
} /* if local RAM handle it */ } /* if local RAM handle it */
if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */ if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */
if ((addr >= RAM_unit.u3) && ((uint16)addr < (RAM_unit.u3 + RAM_unit.capac))) { if ((addr >= RAM_unit.u3) && ((uint16)addr < (RAM_unit.u3 + RAM_unit.capac))) {
return RAM_get_mbyte(addr); return RAM_get_mbyte(addr);
} }
} /* otherwise, try the multibus */ } /* otherwise, try the multibus */
return multibus_get_mbyte(addr); return multibus_get_mbyte(addr);
} }

30
Intel-Systems/isys8024/system_defs.h
View file

@ -28,7 +28,7 @@
#include <stdio.h> #include <stdio.h>
#include <ctype.h> #include <ctype.h>
#include "sim_defs.h" /* simulator defns */ #include "sim_defs.h" /* simulator defns */
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
@ -65,12 +65,12 @@
//board definitions for the multibus //board definitions for the multibus
/* set the base I/O address for the iSBC 201 */ /* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x78 #define SBC201_BASE 0x78
#define SBC201_INT INT_1 #define SBC201_INT INT_1
#define SBC201_NUM 0 #define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */ /* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78 #define SBC202_BASE 0x78
#define SBC202_INT INT_1 #define SBC202_INT INT_1
#define SBC202_NUM 1 #define SBC202_NUM 1
@ -80,7 +80,7 @@
#define ZX200A_NUM 0 #define ZX200A_NUM 0
/* set the base I/O address for the iSBC 208 */ /* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40 #define SBC208_BASE 0x40
#define SBC208_INT INT_1 #define SBC208_INT INT_1
#define SBC208_NUM 0 #define SBC208_NUM 0
@ -109,10 +109,10 @@
/* Memory */ /* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */ #define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */ #define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */ #define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
/* debug definitions */ /* debug definitions */
@ -128,11 +128,11 @@
/* Simulator stop codes */ /* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */ #define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */ #define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */ #define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */ #define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */ #define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */ #define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */ #define STOP_XACK 7 /* XACK error */

12
Intel-Systems/isys8030/isbc8030.c
View file

@ -93,14 +93,14 @@ uint8 get_mbyte(uint16 addr)
{ {
/* if local EPROM handle it */ /* if local EPROM handle it */
if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */ if ((ROM_DISABLE && (i8255_C[0] & 0x20)) || (ROM_DISABLE == 0)) { /* EPROM enabled */
if ((addr >= EPROM_unit.u3) && ((uint16)addr < (EPROM_unit.u3 + EPROM_unit.capac))) { if ((addr >= EPROM_unit.u3) && ((uint16)addr < (EPROM_unit.u3 + EPROM_unit.capac))) {
return EPROM_get_mbyte(addr); return EPROM_get_mbyte(addr);
} }
} /* if local RAM handle it */ } /* if local RAM handle it */
if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */ if ((RAM_DISABLE && (i8255_C[0] & 0x10)) || (RAM_DISABLE == 0)) { /* RAM enabled */
if ((addr >= RAM_unit.u3) && ((uint16)addr < (RAM_unit.u3 + RAM_unit.capac))) { if ((addr >= RAM_unit.u3) && ((uint16)addr < (RAM_unit.u3 + RAM_unit.capac))) {
return RAM_get_mbyte(addr); return RAM_get_mbyte(addr);
} }
} /* otherwise, try the multibus */ } /* otherwise, try the multibus */
return multibus_get_mbyte(addr); return multibus_get_mbyte(addr);
} }

30
Intel-Systems/isys8030/system_defs.h
View file

@ -28,7 +28,7 @@
#include <stdio.h> #include <stdio.h>
#include <ctype.h> #include <ctype.h>
#include "sim_defs.h" /* simulator defns */ #include "sim_defs.h" /* simulator defns */
#define SET_XACK(VAL) (xack = VAL) #define SET_XACK(VAL) (xack = VAL)
@ -68,12 +68,12 @@
//board definitions for the multibus //board definitions for the multibus
/* set the base I/O address for the iSBC 201 */ /* set the base I/O address for the iSBC 201 */
#define SBC201_BASE 0x78 #define SBC201_BASE 0x78
#define SBC201_INT INT_1 #define SBC201_INT INT_1
#define SBC201_NUM 0 #define SBC201_NUM 0
/* set the base I/O address for the iSBC 202 */ /* set the base I/O address for the iSBC 202 */
#define SBC202_BASE 0x78 #define SBC202_BASE 0x78
#define SBC202_INT INT_1 #define SBC202_INT INT_1
#define SBC202_NUM 1 #define SBC202_NUM 1
@ -83,7 +83,7 @@
#define ZX200A_NUM 0 #define ZX200A_NUM 0
/* set the base I/O address for the iSBC 208 */ /* set the base I/O address for the iSBC 208 */
#define SBC208_BASE 0x40 #define SBC208_BASE 0x40
#define SBC208_INT INT_1 #define SBC208_INT INT_1
#define SBC208_NUM 0 #define SBC208_NUM 0
@ -112,10 +112,10 @@
/* Memory */ /* Memory */
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */ #define MAXMEMSIZE 0x10000 /* 8080 max memory size */
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */ #define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */ #define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
/* debug definitions */ /* debug definitions */
@ -131,11 +131,11 @@
/* Simulator stop codes */ /* Simulator stop codes */
#define STOP_RSRV 1 /* must be 1 */ #define STOP_RSRV 1 /* must be 1 */
#define STOP_HALT 2 /* HALT */ #define STOP_HALT 2 /* HALT */
#define STOP_IBKPT 3 /* breakpoint */ #define STOP_IBKPT 3 /* breakpoint */
#define STOP_OPCODE 4 /* Invalid Opcode */ #define STOP_OPCODE 4 /* Invalid Opcode */
#define STOP_IO 5 /* I/O error */ #define STOP_IO 5 /* I/O error */
#define STOP_MEM 6 /* Memory error */ #define STOP_MEM 6 /* Memory error */
#define STOP_XACK 7 /* XACK error */ #define STOP_XACK 7 /* XACK error */