diff --git a/PDP10/ks10_cty.c b/PDP10/ks10_cty.c index ceba154c..2962b8c8 100644 --- a/PDP10/ks10_cty.c +++ b/PDP10/ks10_cty.c @@ -127,8 +127,10 @@ t_stat ctyi_svc (UNIT *uptr) if (Mem_read_word(CTY_IN, &buffer, 0)) return SCPE_OK; sim_debug(DEBUG_DETAIL, &cty_dev, "CTY Read %012llo\n", buffer); - if (buffer & CTY_CHAR) + if (buffer & CTY_CHAR) { + cty_interrupt(); return SCPE_OK; + } ch = sim_poll_kbd (); if (ch & SCPE_KFLAG) { ch = 0177 & sim_tt_inpcvt(ch, TT_GET_MODE (cty_unit[0].flags)); diff --git a/PDP10/ks10_kmc.c b/PDP10/ks10_kmc.c index ed879c78..9bc089fc 100644 --- a/PDP10/ks10_kmc.c +++ b/PDP10/ks10_kmc.c @@ -627,7 +627,7 @@ DEVICE kmc_dev = { NULL, /* attach routine */ NULL, /* detach routine */ &kmc_dib, /* context */ - KMC_DIS /* Flags */ + DEV_DIS /* Flags */ | DEV_DISABLE | DEV_DEBUG, 0, /* debug control */ diff --git a/PDP10/ks10_uba.c b/PDP10/ks10_uba.c index 00c6293f..990cd598 100644 --- a/PDP10/ks10_uba.c +++ b/PDP10/ks10_uba.c @@ -169,12 +169,6 @@ uba_write(t_addr addr, int ctl, uint64 data, int access) (void)(dptr->reset)(dptr); } } - for (i = 0; i < 128; i++) { - if ((uba_irq_ctlr[i] & VECT_CTR) == ctl) { - uba_irq_ctlr[i] = 0; - clr_interrupt(i << 2); - } - } uba_status[ubm] |= (uint32)(0277 & data); return 0; } else if ((addr & 077) == 1) { @@ -208,12 +202,14 @@ uba_read_npr(t_addr addr, uint16 ctl, uint64 *data) { int ubm = uba_device[ctl]; uint32 map = uba_map[ubm][(077) & (addr >> 11)]; + t_addr oaddr = addr; if ((addr & 0400000) != 0) return 0; if ((map & MAP_VALID) == 0) return 0; addr = (map & PAGE_MASK) | (addr >> 2) & 0777; *data = M[addr]; + sim_debug(DEBUG_DATA, &cpu_dev, "Rd NPR %08o %08o %012llo\n", oaddr, addr, *data); return 1; } @@ -302,7 +298,7 @@ uba_read_npr_word(t_addr addr, uint16 ctl, uint16 *data) return 0; addr = (map & PAGE_MASK) | (addr >> 2) & 0777; wd = M[addr]; - sim_debug(DEBUG_EXP, &cpu_dev, "RD NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map); + sim_debug(DEBUG_DATA, &cpu_dev, "RD NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map); if ((oaddr & 02) == 0) wd >>= 18; *data = (uint16)(wd & 0177777); @@ -326,7 +322,7 @@ uba_write_npr_word(t_addr addr, uint16 ctl, uint16 data) msk = 0177777; buf = (uint64)(data & msk); wd = M[addr]; - sim_debug(DEBUG_EXP, &cpu_dev, "WR NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map); + sim_debug(DEBUG_DATA, &cpu_dev, "WR NPR W %08o %08o %012llo m=%o\n", oaddr, addr, wd, map); if ((oaddr & 02) == 0) { buf <<= 18; msk <<= 18; diff --git a/PDP10/kx10_cpu.c b/PDP10/kx10_cpu.c index 3ed7efc7..f48f8ce6 100644 --- a/PDP10/kx10_cpu.c +++ b/PDP10/kx10_cpu.c @@ -644,10 +644,11 @@ MTAB cpu_mod[] = { /* Simulator debug controls */ DEBTAB cpu_debug[] = { {"IRQ", DEBUG_IRQ, "Debug IRQ requests"}, +#if !KS {"CONI", DEBUG_CONI, "Show coni instructions"}, {"CONO", DEBUG_CONO, "Show cono instructions"}, {"DATAIO", DEBUG_DATAIO, "Show datai and datao instructions"}, -#if KS +#else {"DATA", DEBUG_DATA, "Show data transfers"}, {"DETAIL", DEBUG_DETAIL, "Show details about device"}, {"EXP", DEBUG_EXP, "Show exception information"}, @@ -4644,10 +4645,10 @@ st_pi: dev_irq[f] = 0; break; } -#if DEBUG - sim_debug(DEBUG_IRQ, &cpu_dev, "vect irq %o %06o\n", pi_enc, AB); -#endif } +#if DEBUG + sim_debug(DEBUG_IRQ, &cpu_dev, "vect irq %o %06o\n", pi_enc, AB); +#endif } #if KS_ITS pi_act |= pi_mask; @@ -6509,7 +6510,7 @@ ld_exe: AR |= BR & MQ; MB = AR & FMASK; if (Mem_write(0, 0)) - goto last; + goto last; } FLAGS &= ~BYTI; BYF5 = 0; @@ -8167,8 +8168,6 @@ mul_done: if (sim_interval <= 0) { if ((reason = sim_process_event()) != SCPE_OK) { f_pc_inh = 1; - f_load_pc = 0; - f_inst_fetch = 0; set_reg(AC, AR); break; } @@ -8177,8 +8176,6 @@ mul_done: pi_rq = check_irq_level(); if (pi_rq) { f_pc_inh = 1; - f_load_pc = 0; - f_inst_fetch = 0; set_reg(AC, AR); break; } @@ -11367,8 +11364,6 @@ its_wr: if (sim_interval <= 0) { if ((reason = sim_process_event()) != SCPE_OK) { f_pc_inh = 1; - f_load_pc = 0; - f_inst_fetch = 0; set_reg(AC, AR); break; } @@ -11377,8 +11372,6 @@ its_wr: pi_rq = check_irq_level(); if (pi_rq) { f_pc_inh = 1; - f_load_pc = 0; - f_inst_fetch = 0; set_reg(AC, AR); break; } @@ -11879,6 +11872,7 @@ last: PC = MB & RMASK; xct_flag = 0; f_load_pc = 1; + f_inst_fetch = 1; f_pc_inh = 1; } #endif @@ -11944,6 +11938,7 @@ last: xct_flag = 0; f_load_pc = 1; f_pc_inh = 1; + f_inst_fetch = 1; if (pi_cycle) { pi_cycle = 0; FM[(7 << 4) | 2] = fault_data; diff --git a/PDP10/kx10_defs.h b/PDP10/kx10_defs.h index 27fe635f..dd7f4b63 100644 --- a/PDP10/kx10_defs.h +++ b/PDP10/kx10_defs.h @@ -584,7 +584,6 @@ void uba_set_irq(DIB *dibp, int vect); void uba_clr_irq(DIB *dibp, int vect); t_addr uba_get_vect(t_addr addr, int lvl, int dev); void uba_set_parity(uint16 ctl); -uint16 uba_rh_vect(struct pdp_dib *dibp); int uba_rh_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access); int uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access); void uba_reset(); diff --git a/PDP10/kx10_rh.c b/PDP10/kx10_rh.c index 6de74142..002c0042 100644 --- a/PDP10/kx10_rh.c +++ b/PDP10/kx10_rh.c @@ -331,6 +331,8 @@ uba_rh_write(DEVICE *dptr, t_addr addr, uint16 data, int32 access) { rhc->cs2 |= CS2_NED; r = 0; } + if ((data & CS1_GO) == 0 && (rhc->cs1 & CS1_IE) != 0 && rhc->attn != 0) + uba_set_irq(rhc->dib, rhc->dib->uba_vect); sim_debug(DEBUG_DETAIL, dptr, "RH%o write %06o %06o %o\n", rhc->drive, addr, data, access); return r; @@ -411,12 +413,6 @@ uba_rh_read(DEVICE *dptr, t_addr addr, uint16 *data, int32 access) { return r; } -uint16 -uba_rh_vect(struct pdp_dib *dibp) -{ - return dibp->uba_vect; -} - #else /* 0-37 mass bus register. 70 SBAR, block address. @@ -812,7 +808,6 @@ void rh_reset(DEVICE *dptr, struct rh_if *rhc) rhc->wcr = 0; rhc->cda = 0; rhc->drive = 0; -// rhc->xfer_drive = -1; #if KS rhc->dib = (DIB *)dptr->ctxt; rhc->cs1 = 0; @@ -820,6 +815,7 @@ void rh_reset(DEVICE *dptr, struct rh_if *rhc) rhc->dba = 0; rhc->dbb = 0; rhc->error = 0; + uba_clr_irq(rhc->dib, rhc->dib->uba_vect); #endif } @@ -828,10 +824,10 @@ void rh_setattn(struct rh_if *rhc, int unit) { rhc->attn |= 1<status & BUSY) == 0 && (rhc->cs1 & CS1_IE) != 0) + if ((rhc->cs1 & CS1_IE) != 0) uba_set_irq(rhc->dib, rhc->dib->uba_vect); #else - if ((rhc->status & BUSY) == 0 && (rhc->status & IADR_ATTN) != 0) + if ((rhc->status & IADR_ATTN) != 0) set_interrupt(rhc->devnum, rhc->status); #endif }