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Adding register descriptions to VAX processor devices

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This commit is contained in:
Mark Pizzolato 2013-01-16 17:26:30 -08:00
parent d12bc07d3a
commit a60d9070db
19 changed files with 345 additions and 311 deletions
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8
VAX/vax610_io.c
View file

@ -51,10 +51,10 @@ t_stat qba_reset (DEVICE *dptr);
UNIT qba_unit = { UDATA (NULL, 0, 0) };
REG qba_reg[] = {
{ HRDATA (IPL17, int_req[3], 32), REG_RO },
{ HRDATA (IPL16, int_req[2], 32), REG_RO },
{ HRDATA (IPL15, int_req[1], 32), REG_RO },
{ HRDATA (IPL14, int_req[0], 32), REG_RO },
{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO },
{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO },
{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO },
{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};

4
VAX/vax610_mem.c
View file

@ -62,8 +62,8 @@ DIB mctl_dib = {
UNIT mctl_unit = { UDATA (NULL, 0, 0) };
REG mctl_reg[] = {
{ DRDATA (COUNT, mctl_count, 16) },
{ BRDATA (CSR, mctl_csr, DEV_RDX, 16, MAX_MCTL_COUNT) },
{ DRDATAD (COUNT, mctl_count, 16, "Memory Module Count") },
{ BRDATAD (CSR, mctl_csr, DEV_RDX, 16, MAX_MCTL_COUNT, "control/status registers") },
{ NULL }
};

46
VAX/vax610_stddev.c
View file

@ -103,13 +103,14 @@ DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (BUF, tti_unit.buf, 16) },
{ HRDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") },
{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
@ -141,13 +142,14 @@ DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } };
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ HRDATA (BUF, tto_unit.buf, 8) },
{ HRDATA (CSR, tto_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTO], INT_V_TTO) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") },
{ HRDATAD (CSR, tto_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") },
{ FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ NULL }
};
@ -179,11 +181,17 @@ DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } };
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };
REG clk_reg[] = {
{ HRDATA (CSR, clk_csr, 16) },
{ FLDATA (INT, int_req[IPL_CLK], INT_V_CLK) },
{ FLDATA (IE, clk_csr, CSR_V_IE) },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT },
{ HRDATAD (CSR, clk_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") },
{ FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};

6
VAX/vax610_sysdev.c
View file

@ -96,9 +96,9 @@ extern int32 eval_int (void);
UNIT sysd_unit = { UDATA (NULL, 0, 0) };
REG sysd_reg[] = {
{ HRDATA (CONISP, conisp, 32) },
{ HRDATA (CONPC, conpc, 32) },
{ HRDATA (CONPSL, conpsl, 32) },
{ HRDATAD (CONISP, conisp, 32, "console ISP") },
{ HRDATAD (CONPC, conpc, 32, "console PD") },
{ HRDATAD (CONPSL, conpsl, 32, "console PSL") },
{ BRDATA (BOOTCMD, cpu_boot_cmd, 16, 8, CBUFSIZE), REG_HRO },
{ NULL }
};

12
VAX/vax630_io.c
View file

@ -93,12 +93,12 @@ DIB qba_dib = { IOBA_AUTO, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
UNIT qba_unit = { UDATA (NULL, 0, 0) };
REG qba_reg[] = {
{ HRDATA (IPC, qb_ipc, 16) },
{ HRDATA (IPL17, int_req[3], 32), REG_RO },
{ HRDATA (IPL16, int_req[2], 32), REG_RO },
{ HRDATA (IPL15, int_req[1], 32), REG_RO },
{ HRDATA (IPL14, int_req[0], 32), REG_RO },
{ BRDATA (MAP, qb_map, 16, 32, QBNMAPR) },
{ HRDATAD (IPC, qb_ipc, 16, "interprocessor communications register") },
{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO },
{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO },
{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO },
{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO },
{ BRDATAD (MAP, qb_map, 16, 32, QBNMAPR, "map registers") },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};

46
VAX/vax630_stddev.c
View file

@ -78,13 +78,14 @@ DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (BUF, tti_unit.buf, 16) },
{ HRDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") },
{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
@ -116,13 +117,14 @@ DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } };
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ HRDATA (BUF, tto_unit.buf, 8) },
{ HRDATA (CSR, tto_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTO], INT_V_TTO) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") },
{ HRDATAD (CSR, tto_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") },
{ FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ NULL }
};
@ -154,11 +156,17 @@ DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } };
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };
REG clk_reg[] = {
{ HRDATA (CSR, clk_csr, 16) },
{ FLDATA (INT, int_req[IPL_CLK], INT_V_CLK) },
{ FLDATA (IE, clk_csr, CSR_V_IE) },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT },
{ HRDATAD (CSR, clk_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") },
{ FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};

14
VAX/vax630_sysdev.c
View file

@ -251,13 +251,13 @@ DEVICE nvr_dev = {
UNIT sysd_unit = { UDATA (NULL, 0, 0) };
REG sysd_reg[] = {
{ HRDATA (CONISP, conisp, 32) },
{ HRDATA (CONPC, conpc, 32) },
{ HRDATA (CONPSL, conpsl, 32) },
{ HRDATA (BDR, ka_bdr, 16) },
{ HRDATA (MSER, ka_mser, 8) },
{ HRDATA (CEAR, ka_cear, 8) },
{ HRDATA (DEAR, ka_dear, 8) },
{ HRDATAD (CONISP, conisp, 32, "console ISP") },
{ HRDATAD (CONPC, conpc, 32, "console PD") },
{ HRDATAD (CONPSL, conpsl, 32, "console PSL") },
{ HRDATAD (BDR, ka_bdr, 16, "KA630 boot diag") },
{ HRDATAD (MSER, ka_mser, 8, "KA630 mem sys err") },
{ HRDATAD (CEAR, ka_cear, 8, "KA630 cpu err") },
{ HRDATAD (DEAR, ka_dear, 8, "KA630 dma err") },
{ NULL }
};

6
VAX/vax730_defs.h
View file

@ -126,8 +126,10 @@
#define MEMSIZE (cpu_unit.capac)
#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }
{ UNIT_MSIZE, (2u << 20), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (3u << 20), NULL, "2M", &cpu_set_size }, \
{ UNIT_MSIZE, (4u << 20), NULL, "4M", &cpu_set_size }, \
{ UNIT_MSIZE, (5u << 20), NULL, "5M", &cpu_set_size }
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", NULL, \
NULL, &cpu_show_model },

6
VAX/vax730_mem.c
View file

@ -87,9 +87,9 @@ DIB mctl_dib = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
UNIT mctl_unit = { UDATA (NULL, 0, 0) };
REG mctl_reg[] = {
{ HRDATA (CSR0, mcsr0, 32) },
{ HRDATA (CSR1, mcsr1, 32) },
{ HRDATA (CSR2, mcsr2, 32) },
{ HRDATAD (CSR0, mcsr0, 32, "ECC syndrome bits") },
{ HRDATAD (CSR1, mcsr1, 32, "CPU error control/check bits") },
{ HRDATAD (CSR2, mcsr2, 32, "Unibus error control/check bits") },
{ NULL }
};

62
VAX/vax730_stddev.c
View file

@ -237,13 +237,13 @@ t_bool td_test_xfr (UNIT *uptr, int32 state);
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (RXDB, tti_buf, 16) },
{ HRDATA (RXCS, tti_csr, 16) },
{ FLDATA (INT, tti_int, 0) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
@ -271,13 +271,13 @@ DEVICE tti_dev = {
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ HRDATA (TXDB, tto_buf, 16) },
{ HRDATA (TXCS, tto_csr, 16) },
{ FLDATA (INT, tto_int, 0) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT + REG_NZ },
{ HRDATAD (TXDB, tto_buf, 16, "last data item processed") },
{ HRDATAD (TXCS, tto_csr, 16, "control/status register") },
{ FLDATAD (INT, tto_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT + REG_NZ },
{ NULL }
};
@ -301,9 +301,15 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = {
{ DRDATA (TODR, todr_reg, 32), PV_LEFT },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), REG_HIDDEN + REG_NZ + PV_LEFT },
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};
@ -318,13 +324,13 @@ DEVICE clk_dev = {
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
REG tmr_reg[] = {
{ HRDATA (ICCS, tmr_iccs, 32) },
{ HRDATA (ICR, tmr_icr, 32) },
{ HRDATA (NICR, tmr_nicr, 32) },
{ HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") },
{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
{ FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN },
{ FLDATA (INT, tmr_int, 0) },
{ NULL }
};
@ -350,13 +356,13 @@ UNIT td_unit[] = {
};
REG td_reg[] = {
{ HRDATA (ECODE, td_ecode, 8) },
{ HRDATA (BLK, td_block, 8) },
{ DRDATA (STATE, td_state, 4), REG_RO },
{ DRDATA (BPTR, td_obptr, 7) },
{ DRDATA (CTIME, td_cwait, 24), PV_LEFT },
{ DRDATA (STIME, td_swait, 24), PV_LEFT },
{ DRDATA (XTIME, td_xwait, 24), PV_LEFT },
{ HRDATAD (ECODE, td_ecode, 8, "end packet success code") },
{ HRDATAD (BLK, td_block, 8, "current block number") },
{ DRDATAD (STATE, td_state, 4, "state"), REG_RO },
{ DRDATAD (BPTR, td_obptr, 7, "output buffer pointer") },
{ DRDATAD (CTIME, td_cwait, 24, "command time"), PV_LEFT },
{ DRDATAD (STIME, td_swait, 24, "seek, per block"), PV_LEFT },
{ DRDATAD (XTIME, td_xwait, 24, "tr set time"), PV_LEFT },
{ NULL }
};

12
VAX/vax730_uba.c
View file

@ -140,12 +140,12 @@ DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 };
UNIT uba_unit = { UDATA (0, 0, 0) };
REG uba_reg[] = {
{ HRDATA (IPL14, int_req[0], 32), REG_RO },
{ HRDATA (IPL15, int_req[1], 32), REG_RO },
{ HRDATA (IPL16, int_req[2], 32), REG_RO },
{ HRDATA (IPL17, int_req[3], 32), REG_RO },
{ HRDATA (CSR, uba_csr, 32) },
{ BRDATA (MAP, uba_map, 16, 32, 496) },
{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO },
{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO },
{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO },
{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO },
{ HRDATAD (CSR, uba_csr, 32, "control/status register") },
{ BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};

62
VAX/vax750_stddev.c
View file

@ -237,13 +237,13 @@ extern int32 con_halt (int32 code, int32 cc);
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (RXDB, tti_buf, 16) },
{ HRDATA (RXCS, tti_csr, 16) },
{ FLDATA (INT, tti_int, 0) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
@ -271,13 +271,13 @@ DEVICE tti_dev = {
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ HRDATA (TXDB, tto_buf, 16) },
{ HRDATA (TXCS, tto_csr, 16) },
{ FLDATA (INT, tto_int, 0) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT + REG_NZ },
{ HRDATAD (TXDB, tto_buf, 16, "last data item processed") },
{ HRDATAD (TXCS, tto_csr, 16, "control/status register") },
{ FLDATAD (INT, tto_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT + REG_NZ },
{ NULL }
};
@ -301,12 +301,14 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = {
{ DRDATA (TODR, todr_reg, 32), PV_LEFT },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), REG_HIDDEN + REG_NZ + PV_LEFT },
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATA (LATENCY, sim_asynch_latency, 32), PV_LEFT },
{ DRDATA (INST_LATENCY, sim_asynch_inst_latency, 32), PV_LEFT },
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};
@ -322,13 +324,13 @@ DEVICE clk_dev = {
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
REG tmr_reg[] = {
{ HRDATA (ICCS, tmr_iccs, 32) },
{ HRDATA (ICR, tmr_icr, 32) },
{ HRDATA (NICR, tmr_nicr, 32) },
{ HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") },
{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
{ FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN },
{ FLDATA (INT, tmr_int, 0) },
{ NULL }
};
@ -352,13 +354,13 @@ UNIT td_unit = { UDATA (&td_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, TD_SIZE) };
REG td_reg[] = {
{ HRDATA (ECODE, td_ecode, 8) },
{ HRDATA (BLK, td_block, 8) },
{ DRDATA (STATE, td_state, 4), REG_RO },
{ DRDATA (BPTR, td_obptr, 7) },
{ DRDATA (CTIME, td_cwait, 24), PV_LEFT },
{ DRDATA (STIME, td_swait, 24), PV_LEFT },
{ DRDATA (XTIME, td_xwait, 24), PV_LEFT },
{ HRDATAD (ECODE, td_ecode, 8, "end packet success code") },
{ HRDATAD (BLK, td_block, 8, "current block number") },
{ DRDATAD (STATE, td_state, 4, "state"), REG_RO },
{ DRDATAD (BPTR, td_obptr, 7, "output buffer pointer") },
{ DRDATAD (CTIME, td_cwait, 24, "command time"), PV_LEFT },
{ DRDATAD (STIME, td_swait, 24, "seek, per block"), PV_LEFT },
{ DRDATAD (XTIME, td_xwait, 24, "tr set time"), PV_LEFT },
{ NULL }
};

20
VAX/vax750_uba.c
View file

@ -137,16 +137,16 @@ DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 };
UNIT uba_unit = { UDATA (0, 0, 0) };
REG uba_reg[] = {
{ HRDATA (IPL14, int_req[0], 32), REG_RO },
{ HRDATA (IPL15, int_req[1], 32), REG_RO },
{ HRDATA (IPL16, int_req[2], 32), REG_RO },
{ HRDATA (IPL17, int_req[3], 32), REG_RO },
{ HRDATA (CSR1, uba_csr1, 32) },
{ HRDATA (CSR2, uba_csr2, 32) },
{ HRDATA (CSR3, uba_csr3, 32) },
{ FLDATA (INT, uba_int, 0) },
{ FLDATA (NEXINT, nexus_req[IPL_UBA], TR_UBA) },
{ BRDATA (MAP, uba_map, 16, 32, 496) },
{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO },
{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO },
{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO },
{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO },
{ HRDATAD (CSR1, uba_csr1, 32, "Control/Status register for BDP #1") },
{ HRDATAD (CSR2, uba_csr2, 32, "Control/Status register for BDP #2") },
{ HRDATAD (CSR3, uba_csr3, 32, "Control/Status register for BDP #3") },
{ FLDATAD (INT, uba_int, 0, "Interrupt pending") },
{ FLDATAD (NEXINT, nexus_req[IPL_UBA], TR_UBA, "Nexus interrupt pending") },
{ BRDATAD (MAP, uba_map, 16, 32, 496, "Unibus map registers") },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};

74
VAX/vax780_stddev.c
View file

@ -254,13 +254,13 @@ extern int32 con_halt (int32 code, int32 cc);
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (RXDB, tti_buf, 16) },
{ HRDATA (RXCS, tti_csr, 16) },
{ FLDATA (INT, tti_int, 0) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
@ -288,13 +288,13 @@ DEVICE tti_dev = {
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ HRDATA (TXDB, tto_buf, 16) },
{ HRDATA (TXCS, tto_csr, 16) },
{ FLDATA (INT, tto_int, 0) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT + REG_NZ },
{ HRDATAD (TXDB, tto_buf, 16, "last data item processed") },
{ HRDATAD (TXCS, tto_csr, 16, "control/status register") },
{ FLDATAD (INT, tto_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT + REG_NZ },
{ NULL }
};
@ -318,12 +318,14 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = {
{ DRDATA (TODR, todr_reg, 32), PV_LEFT },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), REG_HIDDEN + REG_NZ + PV_LEFT },
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATA (LATENCY, sim_asynch_latency, 32), PV_LEFT },
{ DRDATA (INST_LATENCY, sim_asynch_inst_latency, 32), PV_LEFT },
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};
@ -339,13 +341,13 @@ DEVICE clk_dev = {
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
REG tmr_reg[] = {
{ HRDATA (ICCS, tmr_iccs, 32) },
{ HRDATA (ICR, tmr_icr, 32) },
{ HRDATA (NICR, tmr_nicr, 32) },
{ HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") },
{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
{ FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN },
{ FLDATA (INT, tmr_int, 0) },
{ NULL }
};
@ -369,19 +371,19 @@ UNIT fl_unit = { UDATA (&fl_svc,
UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF, FL_SIZE) };
REG fl_reg[] = {
{ HRDATA (FNC, fl_fnc, 8) },
{ HRDATA (ES, fl_esr, 8) },
{ HRDATA (ECODE, fl_ecode, 8) },
{ HRDATA (TA, fl_track, 8) },
{ HRDATA (SA, fl_sector, 8) },
{ DRDATA (STATE, fl_state, 4), REG_RO },
{ DRDATA (BPTR, fl_bptr, 7) },
{ DRDATA (CTIME, fl_cwait, 24), PV_LEFT },
{ DRDATA (STIME, fl_swait, 24), PV_LEFT },
{ DRDATA (XTIME, fl_xwait, 24), PV_LEFT },
{ FLDATA (STOP_IOE, fl_stopioe, 0) },
{ BRDATA (DBUF, fl_buf, 16, 8, FL_NUMBY) },
{ BRDATA (COMM, comm_region, 16, 8, COMM_LNT) },
{ HRDATAD (FNC, fl_fnc, 8, "function select") },
{ HRDATAD (ES, fl_esr, 8, "error status") },
{ HRDATAD (ECODE, fl_ecode, 8, "error code") },
{ HRDATAD (TA, fl_track, 8, "track address") },
{ HRDATAD (SA, fl_sector, 8, "sector address") },
{ DRDATAD (STATE, fl_state, 4, "protocol state"), REG_RO },
{ DRDATAD (BPTR, fl_bptr, 7, "data buffer pointer") },
{ DRDATAD (CTIME, fl_cwait, 24, "command initiation delay"), PV_LEFT },
{ DRDATAD (STIME, fl_swait, 24, "seek time delay, per track"), PV_LEFT },
{ DRDATAD (XTIME, fl_xwait, 24, "transfer time delay, per byte"), PV_LEFT },
{ FLDATAD (STOP_IOE, fl_stopioe, 0, "stop on I/O error") },
{ BRDATAD (DBUF, fl_buf, 16, 8, FL_NUMBY, "data buffer") },
{ BRDATAD (COMM, comm_region, 16, 8, COMM_LNT, "comm region") },
{ NULL }
};

36
VAX/vax7x0_mba.c
View file

@ -281,15 +281,15 @@ DIB mba0_dib = { TR_MBA0, 0, &mba_rdreg, &mba_wrreg, 0, NVCL (MBA0) };
UNIT mba0_unit = { UDATA (NULL, 0, 0) };
REG mba0_reg[] = {
{ HRDATA (CNFR, mba_cnf[0], 32) },
{ HRDATA (CR, mba_cr[0], 4) },
{ HRDATA (SR, mba_sr[0], 32) },
{ HRDATA (VA, mba_va[0], 17) },
{ HRDATA (BC, mba_bc[0], 16) },
{ HRDATA (DR, mba_dr[0], 32) },
{ HRDATA (SMR, mba_dr[0], 32) },
{ BRDATA (MAP, mba_map[0], 16, 32, MBA_NMAPR) },
{ FLDATA (NEXINT, nexus_req[IPL_MBA0], TR_MBA0) },
{ HRDATAD (CNFR, mba_cnf[0], 32, "config register") },
{ HRDATAD (CR, mba_cr[0], 4, "control register") },
{ HRDATAD (SR, mba_sr[0], 32, "status register") },
{ HRDATAD (VA, mba_va[0], 17, "virtual address register") },
{ HRDATAD (BC, mba_bc[0], 16, "byte count register") },
{ HRDATAD (DR, mba_dr[0], 32, "diag register") },
{ HRDATAD (SMR, mba_dr[0], 32, "sel map register") },
{ BRDATAD (MAP, mba_map[0], 16, 32, MBA_NMAPR, "map registers") },
{ FLDATAD (NEXINT, nexus_req[IPL_MBA0], TR_MBA0, "nexus interrupt request") },
{ NULL }
};
@ -310,15 +310,15 @@ MTAB mba1_mod[] = {
};
REG mba1_reg[] = {
{ HRDATA (CNFR, mba_cnf[1], 32) },
{ HRDATA (CR, mba_cr[1], 4) },
{ HRDATA (SR, mba_sr[1], 32) },
{ HRDATA (VA, mba_va[1], 17) },
{ HRDATA (BC, mba_bc[1], 16) },
{ HRDATA (DR, mba_dr[1], 32) },
{ HRDATA (SMR, mba_dr[1], 32) },
{ BRDATA (MAP, mba_map[1], 16, 32, MBA_NMAPR) },
{ FLDATA (NEXINT, nexus_req[IPL_MBA1], TR_MBA1) },
{ HRDATAD (CNFR, mba_cnf[1], 32, "config register") },
{ HRDATAD (CR, mba_cr[1], 4, "control register") },
{ HRDATAD (SR, mba_sr[1], 32, "status register") },
{ HRDATAD (VA, mba_va[1], 17, "virtual address register") },
{ HRDATAD (BC, mba_bc[1], 16, "byte count register") },
{ HRDATAD (DR, mba_dr[1], 32, "diag register") },
{ HRDATAD (SMR, mba_dr[1], 32, "sel map register") },
{ BRDATAD (MAP, mba_map[1], 16, 32, MBA_NMAPR, "map registers") },
{ FLDATAD (NEXINT, nexus_req[IPL_MBA1], TR_MBA1, "nexus interrupt request") },
{ NULL }
};

56
VAX/vax860_stddev.c
View file

@ -274,13 +274,13 @@ UNIT tti_unit[] = {
};
REG tti_reg[] = {
{ HRDATA (RXDB, tti_buf, 32) },
{ HRDATA (RXCS, tti_csr, 32) },
{ FLDATA (INT, tti_int, 0) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ URDATA (POS, tti_unit[0].pos, 10, T_ADDR_W, 0, 4, PV_LEFT) },
{ URDATA (TIME, tti_unit[0].wait, 10, 24, 0, 4, PV_LEFT) },
{ HRDATAD (RXDB, tti_buf, 16, "last data item processed") },
{ HRDATAD (RXCS, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, tti_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ URDATAD (POS, tti_unit[0].pos, 10, T_ADDR_W, 0, 4, PV_LEFT, "number of characters input") },
{ URDATAD (TIME, tti_unit[0].wait, 10, 24, 0, 4, PV_LEFT, "input polling interval") },
{ NULL }
};
@ -313,13 +313,13 @@ UNIT tto_unit[] = {
};
REG tto_reg[] = {
{ URDATA (TXDB, tto_unit[0].buf, 16, 32, 0, 4, 0) },
{ HRDATA (TXCS, tto_csr, 32) },
{ FLDATA (INT, tto_int, 0) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ URDATA (POS, tto_unit[0].pos, 10, T_ADDR_W, 0, 4, PV_LEFT) },
{ URDATA (TIME, tto_unit[0].wait, 10, 24, 0, 4, PV_LEFT + REG_NZ) },
{ URDATAD (TXDB, tto_unit[0].buf, 16, 32, 0, 4, 0, "last data item processed") },
{ HRDATAD (TXCS, tto_csr, 16, "control/status register") },
{ FLDATAD (INT, tto_int, 0, "interrupt pending flag") },
{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ URDATAD (POS, tto_unit[0].pos, 10, T_ADDR_W, 0, 4, PV_LEFT, "number of characters output") },
{ URDATAD (TIME, tto_unit[0].wait, 10, 24, 0, 4, PV_LEFT + REG_NZ, "time from I/O initiation to interrupt") },
{ NULL }
};
@ -343,12 +343,14 @@ DEVICE tto_dev = {
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = {
{ DRDATA (TODR, todr_reg, 32), PV_LEFT },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), REG_HIDDEN + REG_NZ + PV_LEFT },
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATA (LATENCY, sim_asynch_latency, 32), PV_LEFT },
{ DRDATA (INST_LATENCY, sim_asynch_inst_latency, 32), PV_LEFT },
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};
@ -364,13 +366,13 @@ DEVICE clk_dev = {
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
REG tmr_reg[] = {
{ HRDATA (ICCS, tmr_iccs, 32) },
{ HRDATA (ICR, tmr_icr, 32) },
{ HRDATA (NICR, tmr_nicr, 32) },
{ HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") },
{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
{ FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN },
{ FLDATA (INT, tmr_int, 0) },
{ NULL }
};
@ -393,10 +395,10 @@ DEVICE tmr_dev = {
UNIT rlcs_unit = { UDATA (&rlcs_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_ROABLE, RL02_SIZE) };
REG rlcs_reg[] = {
{ HRDATA (CSR, rlcs_csr, 16) },
{ HRDATA (MP, rlcs_mp, 16) },
{ DRDATA (BCNT, rlcs_bcnt, 7) },
{ DRDATA (STIME, rlcs_swait, 24), PV_LEFT },
{ HRDATAD (CSR, rlcs_csr, 16, "control/status register") },
{ HRDATAD (MP, rlcs_mp, 16, "") },
{ DRDATAD (BCNT, rlcs_bcnt, 7, "byte count register") },
{ DRDATAD (STIME, rlcs_swait, 24, "command time"), PV_LEFT },
{ NULL }
};

20
VAX/vax_io.c
View file

@ -147,16 +147,16 @@ DIB qba_dib = { IOBA_AUTO, IOLN_DBL, &dbl_rd, &dbl_wr, 0 };
UNIT qba_unit = { UDATA (NULL, 0, 0) };
REG qba_reg[] = {
{ HRDATA (SCR, cq_scr, 16) },
{ HRDATA (DSER, cq_dser, 8) },
{ HRDATA (MEAR, cq_mear, 13) },
{ HRDATA (SEAR, cq_sear, 20) },
{ HRDATA (MBR, cq_mbr, 29) },
{ HRDATA (IPC, cq_ipc, 16) },
{ HRDATA (IPL17, int_req[3], 32), REG_RO },
{ HRDATA (IPL16, int_req[2], 32), REG_RO },
{ HRDATA (IPL15, int_req[1], 32), REG_RO },
{ HRDATA (IPL14, int_req[0], 32), REG_RO },
{ HRDATAD (SCR, cq_scr, 16, "system configuration register") },
{ HRDATAD (DSER, cq_dser, 8, "DMA system error register") },
{ HRDATAD (MEAR, cq_mear, 13, "master error address register") },
{ HRDATAD (SEAR, cq_sear, 20, "slave error address register") },
{ HRDATAD (MBR, cq_mbr, 29, "Qbus map base register") },
{ HRDATAD (IPC, cq_ipc, 16, "interprocessor communications register") },
{ HRDATAD (IPL17, int_req[3], 32, "IPL 17 interrupt flags"), REG_RO },
{ HRDATAD (IPL16, int_req[2], 32, "IPL 16 interrupt flags"), REG_RO },
{ HRDATAD (IPL15, int_req[1], 32, "IPL 15 interrupt flags"), REG_RO },
{ HRDATAD (IPL14, int_req[0], 32, "IPL 14 interrupt flags"), REG_RO },
{ FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
{ NULL }
};

52
VAX/vax_stddev.c
View file

@ -134,13 +134,14 @@ DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (BUF, tti_unit.buf, 16) },
{ HRDATA (CSR, tti_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTI], INT_V_TTI) },
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") },
{ HRDATAD (CSR, tti_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTI], INT_V_TTI, "interrupt pending flag") },
{ FLDATAD (ERR, tti_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ NULL }
};
@ -172,13 +173,14 @@ DIB tto_dib = { 0, 0, NULL, NULL, 1, IVCL (TTO), SCB_TTO, { NULL } };
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT };
REG tto_reg[] = {
{ HRDATA (BUF, tto_unit.buf, 8) },
{ HRDATA (CSR, tto_csr, 16) },
{ FLDATA (INT, int_req[IPL_TTO], INT_V_TTO) },
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ HRDATAD (BUF, tto_unit.buf, 8, "last data item processed") },
{ HRDATAD (CSR, tto_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_TTO], INT_V_TTO, "interrupt pending flag") },
{ FLDATAD (ERR, tto_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, tto_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, tto_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ NULL }
};
@ -210,18 +212,18 @@ DIB clk_dib = { 0, 0, NULL, NULL, 1, IVCL (CLK), SCB_INTTIM, { NULL } };
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE+UNIT_FIX, sizeof(TOY)), CLK_DELAY };/* 100Hz */
REG clk_reg[] = {
{ HRDATA (CSR, clk_csr, 16) },
{ FLDATA (INT, int_req[IPL_CLK], INT_V_CLK) },
{ FLDATA (IE, clk_csr, CSR_V_IE) },
{ DRDATA (TODR, todr_reg, 32), PV_LEFT },
{ FLDATA (BLOW, todr_blow, 0) },
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (POLL, tmr_poll, 24), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATA (TPS, clk_tps, 8), REG_NZ + PV_LEFT },
{ HRDATAD (CSR, clk_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_CLK], INT_V_CLK, "interrupt pending flag") },
{ FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (TODR, todr_reg, 32, "time-of-day register"), PV_LEFT },
{ FLDATAD (BLOW, todr_blow, 0, "TODR battery low indicator") },
{ DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT },
{ DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO },
{ DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT },
#if defined (SIM_ASYNCH_IO)
{ DRDATA (ASYNCH, sim_asynch_enabled, 1), PV_LEFT },
{ DRDATA (LATENCY, sim_asynch_latency, 32), PV_LEFT },
{ DRDATA (INST_LATENCY, sim_asynch_inst_latency, 32), PV_LEFT },
{ DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT },
{ DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT },
{ DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT },
#endif
{ NULL }
};

86
VAX/vax_sysdev.c
View file

@ -355,13 +355,14 @@ DIB csi_dib = { 0, 0, NULL, NULL, 1, IVCL (CSI), SCB_CSI, { NULL } };
UNIT csi_unit = { UDATA (NULL, 0, 0), KBD_POLL_WAIT };
REG csi_reg[] = {
{ ORDATA (BUF, csi_unit.buf, 8) },
{ ORDATA (CSR, csi_csr, 16) },
{ FLDATA (INT, int_req[IPL_CSI], INT_V_CSI) },
{ FLDATA (DONE, csi_csr, CSR_V_DONE) },
{ FLDATA (IE, csi_csr, CSR_V_IE) },
{ DRDATA (POS, csi_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, csi_unit.wait, 24), REG_NZ + PV_LEFT },
{ ORDATAD (BUF, csi_unit.buf, 8, "last data item processed") },
{ ORDATAD (CSR, csi_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_CSI], INT_V_CSI, "interrupt pending flag") },
{ FLDATAD (DONE, csi_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (ERR, csi_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (IE, csi_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, csi_unit.pos, 32, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, csi_unit.wait, 24, "input polling interval"), REG_NZ + PV_LEFT },
{ NULL }
};
@ -390,13 +391,14 @@ DIB cso_dib = { 0, 0, NULL, NULL, 1, IVCL (CSO), SCB_CSO, { NULL } };
UNIT cso_unit = { UDATA (&cso_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT };
REG cso_reg[] = {
{ ORDATA (BUF, cso_unit.buf, 8) },
{ ORDATA (CSR, cso_csr, 16) },
{ FLDATA (INT, int_req[IPL_CSO], INT_V_CSO) },
{ FLDATA (DONE, cso_csr, CSR_V_DONE) },
{ FLDATA (IE, cso_csr, CSR_V_IE) },
{ DRDATA (POS, cso_unit.pos, 32), PV_LEFT },
{ DRDATA (TIME, cso_unit.wait, 24), PV_LEFT },
{ ORDATAD (BUF, cso_unit.buf, 8, "last data item processed") },
{ ORDATAD (CSR, cso_csr, 16, "control/status register") },
{ FLDATAD (INT, int_req[IPL_CSO], INT_V_CSO, "interrupt pending flag") },
{ FLDATAD (ERR, cso_csr, CSR_V_ERR, "error flag (CSR<15>)") },
{ FLDATAD (DONE, cso_csr, CSR_V_DONE, "device done flag (CSR<7>)") },
{ FLDATAD (IE, cso_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, cso_unit.pos, 32, "number of characters output"), PV_LEFT },
{ DRDATAD (TIME, cso_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ NULL }
};
@ -431,34 +433,34 @@ UNIT sysd_unit[] = {
};
REG sysd_reg[] = {
{ HRDATA (CADR, CADR, 8) },
{ HRDATA (MSER, MSER, 8) },
{ HRDATA (CONPC, conpc, 32) },
{ HRDATA (CONPSL, conpsl, 32) },
{ BRDATA (CMCSR, cmctl_reg, 16, 32, CMCTLSIZE >> 2) },
{ HRDATA (CACR, ka_cacr, 8) },
{ HRDATA (BDR, ka_bdr, 8) },
{ HRDATA (BASE, ssc_base, 29) },
{ HRDATA (CNF, ssc_cnf, 32) },
{ HRDATA (BTO, ssc_bto, 32) },
{ HRDATA (OTP, ssc_otp, 4) },
{ HRDATA (TCSR0, tmr_csr[0], 32) },
{ HRDATA (TIR0, tmr_tir[0], 32) },
{ HRDATA (TNIR0, tmr_tnir[0], 32) },
{ HRDATA (TIVEC0, tmr_tivr[0], 9) },
{ HRDATA (TINC0, tmr_inc[0], 32) },
{ HRDATA (TSAV0, tmr_sav[0], 32) },
{ HRDATA (TCSR1, tmr_csr[1], 32) },
{ HRDATA (TIR1, tmr_tir[1], 32) },
{ HRDATA (TNIR1, tmr_tnir[1], 32) },
{ HRDATA (TIVEC1, tmr_tivr[1], 9) },
{ HRDATA (TINC1, tmr_inc[1], 32) },
{ HRDATA (TSAV1, tmr_sav[1], 32) },
{ HRDATA (ADSM0, ssc_adsm[0], 32) },
{ HRDATA (ADSK0, ssc_adsk[0], 32) },
{ HRDATA (ADSM1, ssc_adsm[1], 32) },
{ HRDATA (ADSK1, ssc_adsk[1], 32) },
{ BRDATA (CDGDAT, cdg_dat, 16, 32, CDASIZE >> 2) },
{ HRDATAD (CADR, CADR, 8, "cache disable register") },
{ HRDATAD (MSER, MSER, 8, "memory system error register") },
{ HRDATAD (CONPC, conpc, 32, "PC at console halt") },
{ HRDATAD (CONPSL, conpsl, 32, "PSL at console halt") },
{ BRDATAD (CMCSR, cmctl_reg, 16, 32, CMCTLSIZE >> 2, "CMCTL control and status registers") },
{ HRDATAD (CACR, ka_cacr, 8, "second-level cache control register") },
{ HRDATAD (BDR, ka_bdr, 8, "front panel jumper register") },
{ HRDATAD (BASE, ssc_base, 29, "SSC base address register") },
{ HRDATAD (CNF, ssc_cnf, 32, "SSC configuration register") },
{ HRDATAD (BTO, ssc_bto, 32, "SSC bus timeout register") },
{ HRDATAD (OTP, ssc_otp, 4, "SSC output port") },
{ HRDATAD (TCSR0, tmr_csr[0], 32, "SSC timer 0 control/status register") },
{ HRDATAD (TIR0, tmr_tir[0], 32, "SSC timer 0 interval register") },
{ HRDATAD (TNIR0, tmr_tnir[0], 32, "SSC timer 0 next interval register") },
{ HRDATAD (TIVEC0, tmr_tivr[0], 9, "SSC timer 0 interrupt vector register") },
{ HRDATAD (TINC0, tmr_inc[0], 32, "SSC timer 0 tir increment") },
{ HRDATAD (TSAV0, tmr_sav[0], 32, "SSC timer 0 saved inst cnt") },
{ HRDATAD (TCSR1, tmr_csr[1], 32, "SSC timer 1 control/status register") },
{ HRDATAD (TIR1, tmr_tir[1], 32, "SSC timer 1 interval register") },
{ HRDATAD (TNIR1, tmr_tnir[1], 32, "SSC timer 1 next interval register") },
{ HRDATAD (TIVEC1, tmr_tivr[1], 9, "SSC timer 1 interrupt vector register") },
{ HRDATAD (TINC1, tmr_inc[1], 32, "SSC timer 1 tir increment") },
{ HRDATAD (TSAV1, tmr_sav[1], 32, "SSC timer 1 saved inst cnt") },
{ HRDATAD (ADSM0, ssc_adsm[0], 32, "SSC address match 0 address") },
{ HRDATAD (ADSK0, ssc_adsk[0], 32, "SSC address match 0 mask") },
{ HRDATAD (ADSM1, ssc_adsm[1], 32, "SSC address match 1 address") },
{ HRDATAD (ADSK1, ssc_adsk[1], 32, "SSC address match 1 mask") },
{ BRDATAD (CDGDAT, cdg_dat, 16, 32, CDASIZE >> 2, "cache diagnostic data store") },
{ NULL }
};