From a6c07052a76ff96050a31e2855652308865c505c Mon Sep 17 00:00:00 2001 From: Bill Beech Date: Sun, 3 May 2015 22:08:07 -0700 Subject: [PATCH] ISYS8010: Changed printf to sim_printf. --- Intel-Systems/common/i8008.c | 22 +++---- Intel-Systems/common/i8080.c | 40 ++++++------- Intel-Systems/common/i8088.c | 26 ++++----- Intel-Systems/common/i8251.c | 10 ++-- Intel-Systems/common/i8255.c | 52 ++++++++--------- Intel-Systems/common/i8259.c | 46 +++++++-------- Intel-Systems/common/i8273.c | 8 +-- Intel-Systems/common/i8274.c | 12 ++-- Intel-Systems/common/iSBC80-10.c | 4 +- Intel-Systems/common/iSBC80-20.c | 4 +- Intel-Systems/common/iSBC80-30.c | 4 +- Intel-Systems/common/ieprom.c | 12 ++-- Intel-Systems/common/ijedec.c | 98 ++++++++++++++++---------------- Intel-Systems/common/iram16.c | 30 +++++----- Intel-Systems/common/iram8.c | 2 +- Intel-Systems/common/isbc064.c | 2 +- Intel-Systems/common/isbc064b.c | 36 ++++++------ Intel-Systems/common/isbc064x.c | 36 ++++++------ Intel-Systems/common/isbc208.c | 54 +++++++++--------- Intel-Systems/common/mds-800.c | 4 +- Intel-Systems/common/multibus.c | 20 +++---- Intel-Systems/common/pata.c | 12 ++-- 22 files changed, 267 insertions(+), 267 deletions(-) diff --git a/Intel-Systems/common/i8008.c b/Intel-Systems/common/i8008.c index 6a840d90..48b30c86 100644 --- a/Intel-Systems/common/i8008.c +++ b/Intel-Systems/common/i8008.c @@ -338,7 +338,7 @@ int32 sim_instr (void) // } if (i8008_dev.dctrl & DEBUG_reg) { dumpregs(); - printf("\n"); + sim_printf("\n"); } if (sim_interval <= 0) { /* check clock queue */ @@ -348,14 +348,14 @@ int32 sim_instr (void) sim_interval--; /* countdown clock */ if (int_req > 0) { /* interrupt? */ -// printf("\ni8008: int_req=%04X", int_req); +// sim_printf("\ni8008: int_req=%04X", int_req); ; } else { /* 8008 */ if (IE) { /* enabled? */ push_word(PC); /* do an RST 7 */ PC = 0x0038; int_req &= ~INT_R; -// printf("\ni8008: int_req=%04X", int_req); +// sim_printf("\ni8008: int_req=%04X", int_req); } } /* end interrupt */ @@ -369,7 +369,7 @@ int32 sim_instr (void) if (uptr->flags & UNIT_TRACE) { dumpregs(); - printf("\n"); + sim_printf("\n"); } IR = OP = fetch_byte(0); /* instruction fetch */ @@ -1690,9 +1690,9 @@ uint32 fetch_m(void) /* dump the registers */ void dumpregs(void) { - printf(" A=%02X B=%02X C=%02X D=%04X E=%02X H=%04X L=%02X\n", + sim_printf(" A=%02X B=%02X C=%02X D=%04X E=%02X H=%04X L=%02X\n", A, B, C, D, E, H, L); - printf(" CF=%d ZF=%d SF=%d PF=%d\n", + sim_printf(" CF=%d ZF=%d SF=%d PF=%d\n", CF, ZF, SF, PF); } @@ -1705,10 +1705,10 @@ int32 fetch_byte(int32 flag) if (i8008_dev.dctrl & DEBUG_asm || uptr->flags & UNIT_TRACE) { /* display source code */ switch (flag) { case 0: /* opcode fetch */ - printf("OP=%02X %04X %s", val, PC, opcode[val]); + sim_printf("OP=%02X %04X %s", val, PC, opcode[val]); break; case 1: /* byte operand fetch */ - printf("0%02XH", val); + sim_printf("0%02XH", val); break; } } @@ -1725,7 +1725,7 @@ int32 fetch_word(void) val = get_mbyte(PC) & BYTE_R; /* fetch low byte */ val |= get_mbyte(PC + 1) << 8; /* fetch high byte */ if (i8008_dev.dctrl & DEBUG_asm || uptr->flags & UNIT_TRACE) /* display source code */ - printf("0%04XH", val); + sim_printf("0%04XH", val); PC = (PC + 2) & ADDRMASK; /* increment PC */ val &= WORD_R14; return val; @@ -1825,7 +1825,7 @@ t_stat i8008_reset (DEVICE *dptr) for (i = 0; i < 7; i++) stack_frame[i] = 0; sim_brk_types = sim_brk_dflt = SWMASK ('E'); - printf(" 8008: Reset\n"); + sim_printf(" 8008: Reset\n"); return SCPE_OK; } @@ -1866,7 +1866,7 @@ int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag) addr++; cnt++; } /* end while */ - printf ("%d Bytes loaded.\n", cnt); + sim_printf ("%d Bytes loaded.\n", cnt); return (SCPE_OK); } diff --git a/Intel-Systems/common/i8080.c b/Intel-Systems/common/i8080.c index 5386b897..2ae56616 100644 --- a/Intel-Systems/common/i8080.c +++ b/Intel-Systems/common/i8080.c @@ -394,9 +394,9 @@ int32 sim_instr (void) uptr = i8080_dev.units; if (i8080_dev.dctrl & DEBUG_flow) { if (uptr->flags & UNIT_8085) - printf("CPU = 8085\n"); + sim_printf("CPU = 8085\n"); else - printf("CPU = 8080\n"); + sim_printf("CPU = 8080\n"); } /* Main instruction fetch/decode loop */ @@ -408,7 +408,7 @@ int32 sim_instr (void) // } if (i8080_dev.dctrl & DEBUG_reg) { dumpregs(); - printf("\n"); + sim_printf("\n"); } if (sim_interval <= 0) { /* check clock queue */ @@ -418,7 +418,7 @@ int32 sim_instr (void) sim_interval--; /* countdown clock */ if (int_req > 0) { /* interrupt? */ -// printf("\ni8080: int_req=%04X IM=%04X", int_req, IM); +// sim_printf("\ni8080: int_req=%04X IM=%04X", int_req, IM); if (uptr->flags & UNIT_8085) { /* 8085 */ if (int_req & ITRAP) { /* int */ push_word(PC); @@ -448,7 +448,7 @@ int32 sim_instr (void) push_word(PC); /* do an RST 7 */ PC = 0x0038; int_req &= ~INT_R; -// printf("\ni8080: int_req=%04X", int_req); +// sim_printf("\ni8080: int_req=%04X", int_req); } } } /* end interrupt */ @@ -466,13 +466,13 @@ int32 sim_instr (void) if (uptr->flags & UNIT_TRACE) { dumpregs(); - printf("\n"); + sim_printf("\n"); } IR = OP = fetch_byte(0); /* instruction fetch */ if (GET_XACK(1) == 0) { /* no XACK for instruction fetch */ reason = STOP_XACK; - printf("Stopped for XACK-1 PC=%04X\n", --PC); + sim_printf("Stopped for XACK-1 PC=%04X\n", --PC); continue; } @@ -879,12 +879,12 @@ int32 sim_instr (void) case 0xFB: /* EI */ IM |= IE; -// printf("\nEI: pc=%04X", PC - 1); +// sim_printf("\nEI: pc=%04X", PC - 1); break; case 0xF3: /* DI */ IM &= ~IE; -// printf("\nDI: pc=%04X", PC - 1); +// sim_printf("\nDI: pc=%04X", PC - 1); break; case 0xDB: /* IN */ @@ -908,7 +908,7 @@ int32 sim_instr (void) loop_end: if (GET_XACK(1) == 0) { /* no XACK for instruction fetch */ reason = STOP_XACK; - printf("Stopped for XACK-2 PC=%04X\n", --PC); + sim_printf("Stopped for XACK-2 PC=%04X\n", --PC); continue; } @@ -924,9 +924,9 @@ loop_end: /* dump the registers */ void dumpregs(void) { - printf(" A=%02X BC=%04X DE=%04X HL=%04X SP=%04X IM=%02X XACK=%d\n", + sim_printf(" A=%02X BC=%04X DE=%04X HL=%04X SP=%04X IM=%02X XACK=%d\n", A, BC, DE, HL, SP, IM, xack); - printf(" CF=%d ZF=%d AF=%d SF=%d PF=%d\n", + sim_printf(" CF=%d ZF=%d AF=%d SF=%d PF=%d\n", GET_FLAG(CF) ? 1 : 0, GET_FLAG(ZF) ? 1 : 0, GET_FLAG(AF) ? 1 : 0, @@ -942,10 +942,10 @@ int32 fetch_byte(int32 flag) if (i8080_dev.dctrl & DEBUG_asm || uptr->flags & UNIT_TRACE) { /* display source code */ switch (flag) { case 0: /* opcode fetch */ - printf("OP=%02X %04X %s", val, PC, opcode[val]); + sim_printf("OP=%02X %04X %s", val, PC, opcode[val]); break; case 1: /* byte operand fetch */ - printf("0%02XH", val); + sim_printf("0%02XH", val); break; } } @@ -962,7 +962,7 @@ int32 fetch_word(void) val = get_mbyte(PC) & BYTE_R; /* fetch low byte */ val |= get_mbyte(PC + 1) << 8; /* fetch high byte */ if (i8080_dev.dctrl & DEBUG_asm || uptr->flags & UNIT_TRACE) /* display source code */ - printf("0%04XH", val); + sim_printf("0%04XH", val); PC = (PC + 2) & ADDRMASK; /* increment PC */ val &= WORD_R; return val; @@ -1087,7 +1087,7 @@ int32 getreg(int32 reg) { switch (reg) { case 0: /* reg B */ -// printf("reg=%04X BC=%04X ret=%04X\n", +// sim_printf("reg=%04X BC=%04X ret=%04X\n", // reg, BC, (BC >>8) & 0xff); return ((BC >>8) & BYTE_R); case 1: /* reg C */ @@ -1115,9 +1115,9 @@ void putreg(int32 reg, int32 val) { switch (reg) { case 0: /* reg B */ -// printf("reg=%04X val=%04X\n", reg, val); +// sim_printf("reg=%04X val=%04X\n", reg, val); BC = BC & BYTE_R; -// printf("BC&0x00ff=%04X val<<8=%04X\n", BC, val<<8); +// sim_printf("BC&0x00ff=%04X val<<8=%04X\n", BC, val<<8); BC = BC | (val <<8); break; case 1: /* reg C */ @@ -1247,7 +1247,7 @@ t_stat i8080_reset (DEVICE *dptr) int_req = 0; IM = 0; sim_brk_types = sim_brk_dflt = SWMASK ('E'); - printf(" 8080: Reset\n"); + sim_printf(" 8080: Reset\n"); // fpd = fopen("trace.txt", "w"); return SCPE_OK; } @@ -1289,7 +1289,7 @@ int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag) addr++; cnt++; } /* end while */ - printf ("%d Bytes loaded.\n", cnt); + sim_printf ("%d Bytes loaded.\n", cnt); return (SCPE_OK); } diff --git a/Intel-Systems/common/i8088.c b/Intel-Systems/common/i8088.c index 3a7bf3bd..c38a5274 100644 --- a/Intel-Systems/common/i8088.c +++ b/Intel-Systems/common/i8088.c @@ -576,12 +576,12 @@ int32 sim_instr (void) while (reason == 0) { /* loop until halted */ if (i8088_dev.dctrl & DEBUG_asm) - printf("\n"); + sim_printf("\n"); if (i8088_dev.dctrl & DEBUG_reg) { - printf("Regs: AX=%04X BX=%04X CX=%04X DX=%04X SP=%04X BP=%04X SI=%04X DI=%04X IP=%04X\n", + sim_printf("Regs: AX=%04X BX=%04X CX=%04X DX=%04X SP=%04X BP=%04X SI=%04X DI=%04X IP=%04X\n", AX, BX, CX, DX, SP, BP, SI, DI, IP); - printf("Segs: CS=%04X DS=%04X ES=%04X SS=%04X ", CS, DS, ES, SS); - printf("Flags: %04X\n", PSW); + sim_printf("Segs: CS=%04X DS=%04X ES=%04X SS=%04X ", CS, DS, ES, SS); + sim_printf("Flags: %04X\n", PSW); } if (sim_interval <= 0) { /* check clock queue */ @@ -3163,11 +3163,11 @@ int32 fetch_byte(int32 flag) if (i8088_dev.dctrl & DEBUG_asm) { /* display source code */ switch (flag) { case 0: /* opcode fetch */ -// printf("%04X:%04X %s", CS, IP, opcode[val]); - printf("%04X:%04X %02X", CS, IP, val); +// sim_printf("%04X:%04X %s", CS, IP, opcode[val]); + sim_printf("%04X:%04X %02X", CS, IP, val); break; case 1: /* byte operand fetch */ - printf(" %02X", val); + sim_printf(" %02X", val); break; } } @@ -3182,8 +3182,8 @@ int32 fetch_word(void) val = get_smbyte(SEG_CS, IP) & 0xFF; /* fetch low byte */ val |= get_smbyte(SEG_CS, IP + 1) << 8; /* fetch high byte */ if (i8088_dev.dctrl & DEBUG_asm) -// printf("0%04XH", val); - printf(" %04X", val); +// sim_printf("0%04XH", val); + sim_printf(" %04X", val); IP = INC_IP2; /* increment IP */ return val; } @@ -3428,7 +3428,7 @@ uint32 get_ea(uint32 mrr) break; } if (i8088_dev.dctrl & DEBUG_level1) - printf("get_ea: MRR=%02X MOD=%02X REG=%02X R/M=%02X DISP=%04X EA=%04X\n", + sim_printf("get_ea: MRR=%02X MOD=%02X REG=%02X R/M=%02X DISP=%04X EA=%04X\n", mrr, MOD, REG, RM, DISP, EA); return EA; } @@ -4510,7 +4510,7 @@ int32 get_smbyte(int32 segreg, int32 addr) abs_addr = addr + (get_rword(segreg) << 4); val = get_mbyte(abs_addr); -// printf("get_smbyte: seg=%04X addr=%04X abs_addr=%08X get_mbyte=%02X\n", +// sim_printf("get_smbyte: seg=%04X addr=%04X abs_addr=%08X get_mbyte=%02X\n", // get_rword(segreg), addr, abs_addr, val); return val; } @@ -4556,7 +4556,7 @@ t_stat i8088_reset (DEVICE *dptr) saved_PC = 0; int_req = 0; sim_brk_types = sim_brk_dflt = SWMASK ('E'); - printf(" 8088 Reset\n"); + sim_printf(" 8088 Reset\n"); return SCPE_OK; } @@ -4597,7 +4597,7 @@ int32 sim_load (FILE *fileref, char *cptr, char *fnam, int flag) addr++; cnt++; } /* end while */ - printf ("%d Bytes loaded.\n", cnt); + sim_printf ("%d Bytes loaded.\n", cnt); return (SCPE_OK); } diff --git a/Intel-Systems/common/i8251.c b/Intel-Systems/common/i8251.c index 5298fd77..269fcea5 100644 --- a/Intel-Systems/common/i8251.c +++ b/Intel-Systems/common/i8251.c @@ -203,7 +203,7 @@ t_stat i8251_reset (DEVICE *dptr, int32 base) reg_dev(i8251d, base + 2); reg_dev(i8251s, base + 3); i8251_reset1(); - printf(" 8251: Registered at %02X\n", base); + sim_printf(" 8251: Registered at %02X\n", base); sim_activate (&i8251_unit, i8251_unit.wait); /* activate unit */ return SCPE_OK; } @@ -214,18 +214,18 @@ t_stat i8251_reset (DEVICE *dptr, int32 base) int32 i8251s(int32 io, int32 data) { -// printf("\nio=%d data=%04X\n", io, data); +// sim_printf("\nio=%d data=%04X\n", io, data); if (io == 0) { /* read status port */ return i8251_unit.u3; } else { /* write status port */ if (i8251_unit.u6) { /* if mode, set cmd */ i8251_unit.u5 = data; - printf("8251: Command Instruction=%02X\n", data); + sim_printf("8251: Command Instruction=%02X\n", data); if (data & SD) /* reset port! */ i8251_reset1(); } else { /* set mode */ i8251_unit.u4 = data; - printf("8251: Mode Instruction=%02X\n", data); + sim_printf("8251: Mode Instruction=%02X\n", data); i8251_unit.u6 = 1; /* set cmd received */ } return (0); @@ -251,7 +251,7 @@ void i8251_reset1(void) i8251_unit.u6 = 0; i8251_unit.buf = 0; i8251_unit.pos = 0; - printf(" 8251: Reset\n"); + sim_printf(" 8251: Reset\n"); } /* end of i8251.c */ diff --git a/Intel-Systems/common/i8255.c b/Intel-Systems/common/i8255.c index 32090368..c175cce6 100644 --- a/Intel-Systems/common/i8255.c +++ b/Intel-Systems/common/i8255.c @@ -186,9 +186,9 @@ int32 i8255s0(int32 io, int32 data) } else { /* write status port */ if (data & 0x80) { /* mode instruction */ i8255_unit[0].u3 = data; - printf("8255-0: Mode Instruction=%02X\n", data); + sim_printf("8255-0: Mode Instruction=%02X\n", data); if (data & 0x64) - printf(" Mode 1 and 2 not yet implemented\n"); + sim_printf(" Mode 1 and 2 not yet implemented\n"); } else { /* bit set */ bit = (data & 0x0E) >> 1; /* get bit number */ if (data & 0x01) { /* set bit */ @@ -207,7 +207,7 @@ int32 i8255a0(int32 io, int32 data) return (i8255_unit[0].u4); } else { /* write data port */ i8255_unit[0].u4 = data; - printf("8255-0: Port A = %02X\n", data); + sim_printf("8255-0: Port A = %02X\n", data); } return 0; } @@ -218,7 +218,7 @@ int32 i8255b0(int32 io, int32 data) return (i8255_unit[0].u5); } else { /* write data port */ i8255_unit[0].u5 = data; - printf("8255-0: Port B = %02X\n", data); + sim_printf("8255-0: Port B = %02X\n", data); } return 0; } @@ -229,7 +229,7 @@ int32 i8255c0(int32 io, int32 data) return (i8255_unit[0].u6); } else { /* write data port */ i8255_unit[0].u6 = data; - printf("8255-0: Port C = %02X\n", data); + sim_printf("8255-0: Port C = %02X\n", data); } return 0; } @@ -243,9 +243,9 @@ int32 i8255s1(int32 io, int32 data) } else { /* write status port */ if (data & 0x80) { /* mode instruction */ i8255_unit[1].u3 = data; - printf("8255-1: Mode Instruction=%02X\n", data); + sim_printf("8255-1: Mode Instruction=%02X\n", data); if (data & 0x64) - printf(" Mode 1 and 2 not yet implemented\n"); + sim_printf(" Mode 1 and 2 not yet implemented\n"); } else { /* bit set */ bit = (data & 0x0E) >> 1; /* get bit number */ if (data & 0x01) { /* set bit */ @@ -264,7 +264,7 @@ int32 i8255a1(int32 io, int32 data) return (i8255_unit[1].u4); } else { /* write data port */ i8255_unit[1].u4 = data; - printf("8255-1: Port A = %02X\n", data); + sim_printf("8255-1: Port A = %02X\n", data); } return 0; } @@ -275,7 +275,7 @@ int32 i8255b1(int32 io, int32 data) return (i8255_unit[1].u5); } else { /* write data port */ i8255_unit[1].u5 = data; - printf("8255-1: Port B = %02X\n", data); + sim_printf("8255-1: Port B = %02X\n", data); } return 0; } @@ -286,7 +286,7 @@ int32 i8255c1(int32 io, int32 data) return (i8255_unit[1].u6); } else { /* write data port */ i8255_unit[1].u6 = data; - printf("8255-1: Port C = %02X\n", data); + sim_printf("8255-1: Port C = %02X\n", data); } return 0; } @@ -300,9 +300,9 @@ int32 i8255s2(int32 io, int32 data) } else { /* write status port */ if (data & 0x80) { /* mode instruction */ i8255_unit[2].u3 = data; - printf("8255-2: Mode Instruction=%02X\n", data); + sim_printf("8255-2: Mode Instruction=%02X\n", data); if (data & 0x64) - printf(" Mode 1 and 2 not yet implemented\n"); + sim_printf(" Mode 1 and 2 not yet implemented\n"); } else { /* bit set */ bit = (data & 0x0E) >> 1; /* get bit number */ if (data & 0x01) { /* set bit */ @@ -321,7 +321,7 @@ int32 i8255a2(int32 io, int32 data) return (i8255_unit[2].u4); } else { /* write data port */ i8255_unit[2].u4 = data; - printf("8255-2: Port A = %02X\n", data); + sim_printf("8255-2: Port A = %02X\n", data); } return 0; } @@ -332,7 +332,7 @@ int32 i8255b2(int32 io, int32 data) return (i8255_unit[2].u5); } else { /* write data port */ i8255_unit[2].u5 = data; - printf("8255-2: Port B = %02X\n", data); + sim_printf("8255-2: Port B = %02X\n", data); } return 0; } @@ -343,7 +343,7 @@ int32 i8255c2(int32 io, int32 data) return (i8255_unit[2].u6); } else { /* write data port */ i8255_unit[2].u6 = data; - printf("8255-2: Port C = %02X\n", data); + sim_printf("8255-2: Port C = %02X\n", data); } return 0; } @@ -357,9 +357,9 @@ int32 i8255s3(int32 io, int32 data) } else { /* write status port */ if (data & 0x80) { /* mode instruction */ i8255_unit[3].u3 = data; - printf("8255-3: Mode Instruction=%02X\n", data); + sim_printf("8255-3: Mode Instruction=%02X\n", data); if (data & 0x64) - printf("\n Mode 1 and 2 not yet implemented\n"); + sim_printf("\n Mode 1 and 2 not yet implemented\n"); } else { /* bit set */ bit = (data & 0x0E) >> 1; /* get bit number */ if (data & 0x01) { /* set bit */ @@ -378,7 +378,7 @@ int32 i8255a3(int32 io, int32 data) return (i8255_unit[3].u4); } else { /* write data port */ i8255_unit[3].u4 = data; - printf("8255-3: Port A = %02X\n", data); + sim_printf("8255-3: Port A = %02X\n", data); } return 0; } @@ -389,7 +389,7 @@ int32 i8255b3(int32 io, int32 data) return (i8255_unit[3].u5); } else { /* write data port */ i8255_unit[3].u5 = data; - printf("8255-3: Port B = %02X\n", data); + sim_printf("8255-3: Port B = %02X\n", data); } return 0; } @@ -400,7 +400,7 @@ int32 i8255c3(int32 io, int32 data) return (i8255_unit[3].u6); } else { /* write data port */ i8255_unit[3].u6 = data; - printf("8255-3: Port C = %02X\n", data); + sim_printf("8255-3: Port C = %02X\n", data); } return 0; } @@ -419,7 +419,7 @@ t_stat i8255_reset (DEVICE *dptr, int32 base) i8255_unit[0].u4 = 0xFF; /* Port A */ i8255_unit[0].u5 = 0xFF; /* Port B */ i8255_unit[0].u6 = 0xFF; /* Port C */ - printf(" 8255-0: Reset\n"); + sim_printf(" 8255-0: Reset\n"); break; case 1: reg_dev(i8255a1, base); @@ -430,7 +430,7 @@ t_stat i8255_reset (DEVICE *dptr, int32 base) i8255_unit[1].u4 = 0xFF; /* Port A */ i8255_unit[1].u5 = 0xFF; /* Port B */ i8255_unit[1].u6 = 0xFF; /* Port C */ - printf(" 8255-1: Reset\n"); + sim_printf(" 8255-1: Reset\n"); break; case 2: reg_dev(i8255a2, base); @@ -441,7 +441,7 @@ t_stat i8255_reset (DEVICE *dptr, int32 base) i8255_unit[2].u4 = 0xFF; /* Port A */ i8255_unit[2].u5 = 0xFF; /* Port B */ i8255_unit[2].u6 = 0xFF; /* Port C */ - printf(" 8255-2: Reset\n"); + sim_printf(" 8255-2: Reset\n"); break; case 3: reg_dev(i8255a3, base); @@ -452,12 +452,12 @@ t_stat i8255_reset (DEVICE *dptr, int32 base) i8255_unit[3].u4 = 0xFF; /* Port A */ i8255_unit[3].u5 = 0xFF; /* Port B */ i8255_unit[3].u6 = 0xFF; /* Port C */ - printf(" 8255-3: Reset\n"); + sim_printf(" 8255-3: Reset\n"); break; default: - printf(" 8255: Bad device\n"); + sim_printf(" 8255: Bad device\n"); } - printf(" 8255-%d: Registered at %02X\n", i8255_cnt, base); + sim_printf(" 8255-%d: Registered at %02X\n", i8255_cnt, base); i8255_cnt++; return SCPE_OK; } diff --git a/Intel-Systems/common/i8259.c b/Intel-Systems/common/i8259.c index 0e2173a5..a17edf38 100644 --- a/Intel-Systems/common/i8259.c +++ b/Intel-Systems/common/i8259.c @@ -140,11 +140,11 @@ int32 i8259a0(int32 io, int32 data) i8259_ocw3[0] = data; break; default: - printf("8259b-0: OCW Error %02X\n", data); + sim_printf("8259b-0: OCW Error %02X\n", data); break; } } - printf("8259a-0: data = %02X\n", data); + sim_printf("8259a-0: data = %02X\n", data); icw_num0++; /* step ICW number */ } i8259_dump(0); @@ -168,10 +168,10 @@ int32 i8259b0(int32 io, int32 data) if (i8259_icw1[0] & 0x01) i8259_icw4[0] = data; else - printf("8259b-0: ICW4 not enabled - data=%02X\n", data); + sim_printf("8259b-0: ICW4 not enabled - data=%02X\n", data); break; default: - printf("8259b-0: ICW Error %02X\n", data); + sim_printf("8259b-0: ICW Error %02X\n", data); break; } icw_num0++; @@ -209,11 +209,11 @@ int32 i8259a1(int32 io, int32 data) i8259_ocw3[1] = data; break; default: - printf("8259b-1: OCW Error %02X\n", data); + sim_printf("8259b-1: OCW Error %02X\n", data); break; } } - printf("8259a-1: data = %02X\n", data); + sim_printf("8259a-1: data = %02X\n", data); icw_num1++; /* step ICW number */ } i8259_dump(1); @@ -237,10 +237,10 @@ int32 i8259b1(int32 io, int32 data) if (i8259_icw1[1] & 0x01) i8259_icw4[1] = data; else - printf("8259b-1: ICW4 not enabled - data=%02X\n", data); + sim_printf("8259b-1: ICW4 not enabled - data=%02X\n", data); break; default: - printf("8259b-1: ICW Error %02X\n", data); + sim_printf("8259b-1: ICW Error %02X\n", data); break; } icw_num1++; @@ -254,17 +254,17 @@ int32 i8259b1(int32 io, int32 data) void i8259_dump(int32 dev) { - printf("Device %d\n", dev); - printf(" IRR = %02X\n", i8259_unit[dev].u3); - printf(" ISR = %02X\n", i8259_unit[dev].u4); - printf(" IMR = %02X\n", i8259_unit[dev].u5); - printf(" ICW1 = %02X\n", i8259_icw1[dev]); - printf(" ICW2 = %02X\n", i8259_icw2[dev]); - printf(" ICW3 = %02X\n", i8259_icw3[dev]); - printf(" ICW4 = %02X\n", i8259_icw4[dev]); - printf(" OCW1 = %02X\n", i8259_ocw1[dev]); - printf(" OCW2 = %02X\n", i8259_ocw2[dev]); - printf(" OCW3 = %02X\n", i8259_ocw3[dev]); + sim_printf("Device %d\n", dev); + sim_printf(" IRR = %02X\n", i8259_unit[dev].u3); + sim_printf(" ISR = %02X\n", i8259_unit[dev].u4); + sim_printf(" IMR = %02X\n", i8259_unit[dev].u5); + sim_printf(" ICW1 = %02X\n", i8259_icw1[dev]); + sim_printf(" ICW2 = %02X\n", i8259_icw2[dev]); + sim_printf(" ICW3 = %02X\n", i8259_icw3[dev]); + sim_printf(" ICW4 = %02X\n", i8259_icw4[dev]); + sim_printf(" OCW1 = %02X\n", i8259_ocw1[dev]); + sim_printf(" OCW2 = %02X\n", i8259_ocw2[dev]); + sim_printf(" OCW3 = %02X\n", i8259_ocw3[dev]); } /* Reset routine */ @@ -280,7 +280,7 @@ t_stat i8259_reset (DEVICE *dptr, int32 base) i8259_unit[0].u3 = 0x00; /* IRR */ i8259_unit[0].u4 = 0x00; /* ISR */ i8259_unit[0].u5 = 0x00; /* IMR */ - printf(" 8259-0: Reset\n"); + sim_printf(" 8259-0: Reset\n"); break; case 1: reg_dev(i8259a1, base); @@ -290,13 +290,13 @@ t_stat i8259_reset (DEVICE *dptr, int32 base) i8259_unit[1].u3 = 0x00; /* IRR */ i8259_unit[1].u4 = 0x00; /* ISR */ i8259_unit[1].u5 = 0x00; /* IMR */ - printf(" 8259-1: Reset\n"); + sim_printf(" 8259-1: Reset\n"); break; default: - printf(" 8259: Bad device\n"); + sim_printf(" 8259: Bad device\n"); break; } - printf(" 8259-%d: Registered at %02X\n", i8259_cnt, base); + sim_printf(" 8259-%d: Registered at %02X\n", i8259_cnt, base); i8259_cnt++; return SCPE_OK; } diff --git a/Intel-Systems/common/i8273.c b/Intel-Systems/common/i8273.c index c51e3066..03b4dd3f 100644 --- a/Intel-Systems/common/i8273.c +++ b/Intel-Systems/common/i8273.c @@ -201,7 +201,7 @@ t_stat i8273_reset (DEVICE *dptr) rr0 = 0; /* status register */ rr1 = 0; /* error register */ rr2 = 0; /* read interrupt vector */ - printf(" 8273 Reset\n"); + sim_printf(" 8273 Reset\n"); return SCPE_OK; } @@ -226,13 +226,13 @@ int32 i8273s(int32 io, int32 data) i8273_unit.u6 = 0; i8273_unit.buf = 0; i8273_unit.pos = 0; - printf("8273 Reset\n"); + sim_printf("8273 Reset\n"); } else if (i8273_unit.u6) { i8273_unit.u5 = data; - printf("8273 Command Instruction=%02X\n", data); + sim_printf("8273 Command Instruction=%02X\n", data); } else { i8273_unit.u4 = data; - printf("8273 Mode Instruction=%02X\n", data); + sim_printf("8273 Mode Instruction=%02X\n", data); i8273_unit.u6++; } return (0); diff --git a/Intel-Systems/common/i8274.c b/Intel-Systems/common/i8274.c index a6749a02..357352f3 100644 --- a/Intel-Systems/common/i8274.c +++ b/Intel-Systems/common/i8274.c @@ -239,7 +239,7 @@ t_stat i8274_reset (DEVICE *dptr) { wr0a = wr1a = wr2a = wr3a = wr4a = wr5a = wr6a = wr7a = rr0a = rr1a = rr2a = 0; wr0b = wr1b = wr2b = wr3b = wr4b = wr5b = wr6b = wr7b = rr0b = rr1b = rr2b = 0; - printf(" 8274 Reset\n"); + sim_printf(" 8274 Reset\n"); return SCPE_OK; } @@ -274,7 +274,7 @@ int32 i8274As(int32 io, int32 data) if ((wr0a & 0x38) == 0x18) { /* channel reset */ wr0a = wr1a = wr2a = wr3a = wr4a = wr5a = 0; wr6a = wr7a = rr0a = rr1a = rr2a = 0; - printf("8274 Channel A reset\n"); + sim_printf("8274 Channel A reset\n"); } break; case 1: /* wr1a */ @@ -299,7 +299,7 @@ int32 i8274As(int32 io, int32 data) wr7a = data; break; } - printf("8274 Command WR%dA=%02X\n", wr0a & 0x7, data); + sim_printf("8274 Command WR%dA=%02X\n", wr0a & 0x7, data); return 0; } } @@ -323,13 +323,13 @@ int32 i8274Bs(int32 io, int32 data) return i8274_unit.u3; } else { /* write status port */ if (data == 0x40) { /* reset port! */ - printf("8274 Reset\n"); + sim_printf("8274 Reset\n"); } else if (i8274_unit.u6) { i8274_unit.u5 = data; - printf("8274 Command Instruction=%02X\n", data); + sim_printf("8274 Command Instruction=%02X\n", data); } else { i8274_unit.u4 = data; - printf("8274 Mode Instruction=%02X\n", data); + sim_printf("8274 Mode Instruction=%02X\n", data); i8274_unit.u6++; } return (0); diff --git a/Intel-Systems/common/iSBC80-10.c b/Intel-Systems/common/iSBC80-10.c index d8194b95..0c14028e 100644 --- a/Intel-Systems/common/iSBC80-10.c +++ b/Intel-Systems/common/iSBC80-10.c @@ -84,7 +84,7 @@ extern t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size); t_stat SBC_reset (DEVICE *dptr) { - printf("Initializing iSBC-80/10:\n"); + sim_printf("Initializing iSBC-80/10:\n"); i8080_reset (NULL); i8255_reset (NULL, I8255_BASE_0); i8255_reset (NULL, I8255_BASE_1); @@ -127,7 +127,7 @@ void put_mbyte(int32 addr, int32 val) { /* if local EPROM handle it */ if ((i8255_unit.u5 & 0x01) && (addr >= EPROM_unit.u3) && (addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { - printf("Write to R/O memory address %04X - ignored\n", addr); + sim_printf("Write to R/O memory address %04X - ignored\n", addr); return; } /* if local RAM handle it */ if ((i8255_unit.u5 & 0x02) && (addr >= RAM_unit.u3) && (addr <= (RAM_unit.u3 + RAM_unit.capac))) { diff --git a/Intel-Systems/common/iSBC80-20.c b/Intel-Systems/common/iSBC80-20.c index 609b9842..e116c7f0 100644 --- a/Intel-Systems/common/iSBC80-20.c +++ b/Intel-Systems/common/iSBC80-20.c @@ -84,7 +84,7 @@ extern t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size); t_stat SBC_reset (DEVICE *dptr) { - printf("Initializing iSBC-80/20\n"); + sim_printf("Initializing iSBC-80/20\n"); i8080_reset(NULL); i8259_reset(NULL, I8259_BASE); i8255_reset(NULL, I8255_BASE_0); @@ -128,7 +128,7 @@ void put_mbyte(int32 addr, int32 val) { /* if local EPROM handle it */ if ((i8255_unit.u6 & 0x01) && (addr >= EPROM_unit.u3) && (addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { - printf("Write to R/O memory address %04X - ignored\n", addr); + sim_printf("Write to R/O memory address %04X - ignored\n", addr); return; } /* if local RAM handle it */ if ((i8255_unit.u6 & 0x02) && (addr >= RAM_unit.u3) && (addr <= (RAM_unit.u3 + RAM_unit.capac))) { diff --git a/Intel-Systems/common/iSBC80-30.c b/Intel-Systems/common/iSBC80-30.c index 1afebab0..6362f863 100644 --- a/Intel-Systems/common/iSBC80-30.c +++ b/Intel-Systems/common/iSBC80-30.c @@ -84,7 +84,7 @@ extern t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size); t_stat SBC_reset (DEVICE *dptr) { - printf("Initializing iSBC-80/20\n"); + sim_printf("Initializing iSBC-80/20\n"); i8080_reset(NULL); i8259_reset(NULL, I8259_BASE); i8255_reset(NULL, I8255_BASE_0); @@ -128,7 +128,7 @@ void put_mbyte(int32 addr, int32 val) { /* if local EPROM handle it */ if ((i8255_unit.u6 & 0x01) && (addr >= EPROM_unit.u3) && (addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { - printf("Write to R/O memory address %04X - ignored\n", addr); + sim_printf("Write to R/O memory address %04X - ignored\n", addr); return; } /* if local RAM handle it */ if ((i8255_unit.u6 & 0x02) && (addr >= RAM_unit.u3) && (addr <= (RAM_unit.u3 + RAM_unit.capac))) { diff --git a/Intel-Systems/common/ieprom.c b/Intel-Systems/common/ieprom.c index 62eb1734..cf3779e1 100644 --- a/Intel-Systems/common/ieprom.c +++ b/Intel-Systems/common/ieprom.c @@ -122,8 +122,8 @@ t_stat EPROM_attach (UNIT *uptr, char *cptr) sim_debug (DEBUG_read, &EPROM_dev, "\tOpen file %s\n", EPROM_unit.filename); fp = fopen(EPROM_unit.filename, "rb"); /* open EPROM file */ if (fp == NULL) { - printf("EPROM: Unable to open ROM file %s\n", EPROM_unit.filename); - printf("\tNo ROM image loaded!!!\n"); + sim_printf("EPROM: Unable to open ROM file %s\n", EPROM_unit.filename); + sim_printf("\tNo ROM image loaded!!!\n"); return SCPE_OK; } sim_debug (DEBUG_read, &EPROM_dev, "\tRead file\n"); @@ -133,13 +133,13 @@ t_stat EPROM_attach (UNIT *uptr, char *cptr) *(uint8 *)(EPROM_unit.filebuf + j++) = c & 0xFF; c = fgetc(fp); if (j >= EPROM_unit.capac) { - printf("\tImage is too large - Load truncated!!!\n"); + sim_printf("\tImage is too large - Load truncated!!!\n"); break; } } sim_debug (DEBUG_read, &EPROM_dev, "\tClose file\n"); fclose(fp); - printf("EPROM: %d bytes of ROM image %s loaded\n", j, EPROM_unit.filename); + sim_printf("EPROM: %d bytes of ROM image %s loaded\n", j, EPROM_unit.filename); sim_debug (DEBUG_flow, &EPROM_dev, "EPROM_attach: Done\n"); return SCPE_OK; } @@ -154,12 +154,12 @@ t_stat EPROM_reset (DEVICE *dptr, int32 size) if ((EPROM_unit.flags & UNIT_ATT) == 0) { /* if unattached */ EPROM_unit.capac = size; /* set EPROM size to 0 */ sim_debug (DEBUG_flow, &EPROM_dev, "Done1\n"); -// printf(" EPROM: Available [%04X-%04XH]\n", +// sim_printf(" EPROM: Available [%04X-%04XH]\n", // 0, EPROM_unit.capac - 1); return SCPE_OK; } if ((EPROM_unit.flags & UNIT_ATT) == 0) { - printf("EPROM: No file attached\n"); + sim_printf("EPROM: No file attached\n"); } sim_debug (DEBUG_flow, &EPROM_dev, "Done2\n"); return SCPE_OK; diff --git a/Intel-Systems/common/ijedec.c b/Intel-Systems/common/ijedec.c index 036c3294..f5c63212 100644 --- a/Intel-Systems/common/ijedec.c +++ b/Intel-Systems/common/ijedec.c @@ -193,14 +193,14 @@ t_stat JEDEC_attach (UNIT *uptr, char *cptr) t_stat r; if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_attach: Entered with cptr=%s\n", cptr); + sim_printf("\tJEDEC_attach: Entered with cptr=%s\n", cptr); if ((r = attach_unit (uptr, cptr)) != SCPE_OK) { if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_attach: Error\n"); + sim_printf("\tJEDEC_attach: Error\n"); return r; } if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_attach: Done\n"); + sim_printf("\tJEDEC_attach: Done\n"); return (JEDEC_reset (NULL)); } @@ -211,7 +211,7 @@ t_stat JEDEC_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc) UNIT *uptr1; if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_set_mode: Entered with val=%08XH, unit=%d\n", val, uptr->u6); + sim_printf("\tJEDEC_set_mode: Entered with val=%08XH, unit=%d\n", val, uptr->u6); uptr1 = JEDEC_dev.units + JEDEC_NUM - 1; /* top unit holds this configuration */ if (val) { /* 16-bit mode */ uptr1->u5 |= D16BIT; @@ -219,8 +219,8 @@ t_stat JEDEC_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc) uptr1->u5 &= ~D16BIT; } if (JEDEC_dev.dctrl & DEBUG_flow) - printf("JEDEC%d->u5=%08XH\n", JEDEC_NUM - 1, uptr1->u5); - printf("\tJEDEC_set_mode: Done\n"); + sim_printf("JEDEC%d->u5=%08XH\n", JEDEC_NUM - 1, uptr1->u5); + sim_printf("\tJEDEC_set_mode: Done\n"); } /* JEDEC set type = none, 8krom, 16krom, 32krom, 8kram or 32kram */ @@ -231,7 +231,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) UNIT *uptr1; if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_set_size: Entered with val=%d, unit=%d\n", val, uptr->u6); + sim_printf("\tJEDEC_set_size: Entered with val=%d, unit=%d\n", val, uptr->u6); uptr1 = JEDEC_dev.units + JEDEC_NUM - 1; /* top unit holds u5 configuration */ uptr->u4 = val; switch(val) { @@ -240,7 +240,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) uptr->u5 &= ~RAM; /* ROM */ if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ uptr->u3 = 0; /* base address */ - printf("JEDEC site size set to 8KB\n"); + sim_printf("JEDEC site size set to 8KB\n"); for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */ uptr1 = JEDEC_dev.units + i; uptr1->capac = 0; @@ -251,10 +251,10 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) uptr->capac = 0x2000; uptr1->u5 &= ~RAM; /* ROM */ basadr = 0x100000 - (uptr->capac * JEDEC_NUM); - printf("JEDEC site base address = %06XH\n", basadr); + sim_printf("JEDEC site base address = %06XH\n", basadr); if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ uptr->u3 = basadr + (uptr->capac * uptr->u6); /* base address */ - printf("JEDEC site size set to 8KB\n"); + sim_printf("JEDEC site size set to 8KB\n"); for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */ uptr1 = JEDEC_dev.units + i; uptr1->capac = 0; @@ -262,7 +262,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) } else { if (uptr1->capac != uptr->capac) { uptr->capac = 0; - printf("JEDEC site size precludes use of this device\n"); + sim_printf("JEDEC site size precludes use of this device\n"); } } break; @@ -270,10 +270,10 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) uptr->capac = 0x4000; uptr1->u5 &= ~RAM; /* ROM */ basadr = 0x100000 - (uptr->capac * JEDEC_NUM); - printf("JEDEC site base address = %06XH\n", basadr); + sim_printf("JEDEC site base address = %06XH\n", basadr); if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ uptr->u3 = basadr + (uptr->capac * uptr->u6); /* base address */ - printf("JEDEC site size set to 16KB\n"); + sim_printf("JEDEC site size set to 16KB\n"); for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */ uptr1 = JEDEC_dev.units + i; uptr1->capac = 0; @@ -281,7 +281,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) } else { if (uptr1->capac != uptr->capac) { uptr->capac = 0; - printf("JEDEC site size precludes use of this device\n"); + sim_printf("JEDEC site size precludes use of this device\n"); } } break; @@ -289,10 +289,10 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) uptr->capac = 0x8000; uptr1->u5 &= ~RAM; /* ROM */ basadr = 0x100000 - (uptr->capac * JEDEC_NUM); - printf("JEDEC site base address = %06XH\n", basadr); + sim_printf("JEDEC site base address = %06XH\n", basadr); if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ uptr->u3 = basadr + (uptr->capac * uptr->u6); /* base address */ - printf("JEDEC site size set to 32KB\n"); + sim_printf("JEDEC site size set to 32KB\n"); for (i = 0; i < JEDEC_NUM-1; i++) { /* clear all units but last unit */ uptr1 = JEDEC_dev.units + i; uptr1->capac = 0; @@ -300,18 +300,18 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) } else { if (uptr1->capac != uptr->capac) { uptr->capac = 0; - printf("JEDEC site size precludes use of this device\n"); + sim_printf("JEDEC site size precludes use of this device\n"); } } break; case UNIT_8KRAM: uptr->capac = 0x2000; if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ - printf("JEDEC%d cannot be SRAM\n", uptr->u6); + sim_printf("JEDEC%d cannot be SRAM\n", uptr->u6); } else { if (uptr1->capac != uptr->capac) { uptr->capac = 0; - printf("JEDEC site size precludes use of this device\n"); + sim_printf("JEDEC site size precludes use of this device\n"); } else { uptr->u5 |= RAM; /* RAM */ } @@ -320,11 +320,11 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) case UNIT_32KRAM: uptr->capac = 0x8000; if (uptr->u6 == JEDEC_NUM - 1) {/* top unit ? */ - printf("JEDEC%d cannot be SRAM\n", uptr->u6); + sim_printf("JEDEC%d cannot be SRAM\n", uptr->u6); } else { if (uptr1->capac != uptr->capac) { uptr->capac = 0; - printf("JEDEC site size precludes use of this device\n"); + sim_printf("JEDEC site size precludes use of this device\n"); } else { uptr->u5 |= RAM; /* RAM */ } @@ -332,7 +332,7 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) break; default: if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_set_size: Error\n"); + sim_printf("\tJEDEC_set_size: Error\n"); return SCPE_ARG; } if (JEDEC_buf[uptr->u6]) { /* any change requires a new buffer */ @@ -340,14 +340,14 @@ t_stat JEDEC_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) JEDEC_buf[uptr->u6] = NULL; } if (JEDEC_dev.dctrl & DEBUG_flow) { - printf("\tJEDEC%d->capac=%04XH\n", uptr->u6, uptr->capac); - printf("\tJEDEC%d->u3[Base addr]=%06XH\n", uptr->u6, uptr->u3); - printf("\tJEDEC%d->u4[val]=%06XH\n", uptr->u6, uptr->u4); - printf("\tJEDEC%d->u5[Flags]=%06XH\n", uptr->u6, uptr->u5); - printf("\tJEDEC%d->u6[unit #]=%06XH\n", uptr->u6, uptr->u6); + sim_printf("\tJEDEC%d->capac=%04XH\n", uptr->u6, uptr->capac); + sim_printf("\tJEDEC%d->u3[Base addr]=%06XH\n", uptr->u6, uptr->u3); + sim_printf("\tJEDEC%d->u4[val]=%06XH\n", uptr->u6, uptr->u4); + sim_printf("\tJEDEC%d->u5[Flags]=%06XH\n", uptr->u6, uptr->u5); + sim_printf("\tJEDEC%d->u6[unit #]=%06XH\n", uptr->u6, uptr->u6); uptr1 = JEDEC_dev.units + JEDEC_NUM - 1; /* top unit holds u5 configuration */ - printf("\tJEDEC%d->u5[Flags]=%06XH\n", JEDEC_NUM - 1, uptr1->u5); - printf("\tJEDEC_set_size: Done\n"); + sim_printf("\tJEDEC%d->u5[Flags]=%06XH\n", JEDEC_NUM - 1, uptr1->u5); + sim_printf("\tJEDEC_set_size: Done\n"); } return SCPE_OK; } @@ -363,14 +363,14 @@ t_stat JEDEC_reset (DEVICE *dptr) static int flag = 1; if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_reset: Entered\n"); + sim_printf("\tJEDEC_reset: Entered\n"); for (i = 0; i < JEDEC_NUM; i++) { /* handle all umits */ uptr = JEDEC_dev.units + i; if (uptr->capac == 0) { /* if not configured */ - printf(" JEDEC%d: Not configured\n", i); + sim_printf(" JEDEC%d: Not configured\n", i); if (flag) { - printf(" ALL: \"set JEDEC3 None | 8krom | 16krom | 32krom | 8kram | 32kram\"\n"); - printf(" EPROM: \"att JEDEC3 \"\n"); + sim_printf(" ALL: \"set JEDEC3 None | 8krom | 16krom | 32krom | 8kram | 32kram\"\n"); + sim_printf(" EPROM: \"att JEDEC3 \"\n"); flag = 0; } uptr->capac = 0; @@ -381,7 +381,7 @@ t_stat JEDEC_reset (DEVICE *dptr) uptr->u6 = i; /* unit number - only set here! */ } if (uptr->capac) { /* if configured */ - printf(" JEDEC%d: Initializing %2XKB %s [%04X-%04XH]\n", + sim_printf(" JEDEC%d: Initializing %2XKB %s [%04X-%04XH]\n", i, uptr->capac / 0x400, uptr->u5 ? "Ram" : "Rom", @@ -391,15 +391,15 @@ t_stat JEDEC_reset (DEVICE *dptr) JEDEC_buf[uptr->u6] = malloc(uptr->capac); if (JEDEC_buf[uptr->u6] == NULL) { if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_reset: Malloc error\n"); + sim_printf("\tJEDEC_reset: Malloc error\n"); return SCPE_MEM; } } if ((uptr->u5 & 0x0001) == 0) { /* ROM - load file */ fp = fopen(uptr->filename, "rb"); if (fp == NULL) { - printf("\tUnable to open ROM file %s\n", uptr->filename); - printf("\tNo ROM image loaded!!!\n"); + sim_printf("\tUnable to open ROM file %s\n", uptr->filename); + sim_printf("\tNo ROM image loaded!!!\n"); } else { j = 0; c = fgetc(fp); @@ -407,18 +407,18 @@ t_stat JEDEC_reset (DEVICE *dptr) *(JEDEC_buf[uptr->u6] + j++) = c & 0xFF; c = fgetc(fp); if (j >= JEDEC_unit[uptr->u6].capac) { - printf("\tImage is too large - Load truncated!!!\n"); + sim_printf("\tImage is too large - Load truncated!!!\n"); break; } } fclose(fp); - printf("\t%d bytes of ROM image %s loaded\n", j, uptr->filename); + sim_printf("\t%d bytes of ROM image %s loaded\n", j, uptr->filename); } } } } if (JEDEC_dev.dctrl & DEBUG_flow) - printf("\tJEDEC_reset: Done\n"); + sim_printf("\tJEDEC_reset: Done\n"); return SCPE_OK; } @@ -436,22 +436,22 @@ int32 JEDEC_get_mbyte(int32 addr) UNIT *uptr; if (JEDEC_dev.dctrl & DEBUG_read) - printf("\tJEDEC_get_mbyte: Entered\n"); + sim_printf("\tJEDEC_get_mbyte: Entered\n"); for (i = 0; i < JEDEC_NUM; i++) { /* test all umits for address */ uptr = JEDEC_dev.units + i; org = uptr->u3; len = uptr->capac - 1; if ((addr >= org) && (addr <= org + len)) { if (JEDEC_dev.dctrl & DEBUG_read) - printf("\tJEDEC%d Addr=%06XH Org=%06XH Len=%06XH\n", i, addr, org, len); + sim_printf("\tJEDEC%d Addr=%06XH Org=%06XH Len=%06XH\n", i, addr, org, len); val = *(JEDEC_buf[uptr->u6] + (addr - org)); if (JEDEC_dev.dctrl & DEBUG_read) - printf("\tJEDEC_get_mbyte: Exit with [%0XH]\n", val & 0xFF); + sim_printf("\tJEDEC_get_mbyte: Exit with [%0XH]\n", val & 0xFF); return (val & 0xFF); } } if (JEDEC_dev.dctrl & DEBUG_read) - printf("\tJEDEC_get_mbyte: Exit - Out of range\n", addr); + sim_printf("\tJEDEC_get_mbyte: Exit - Out of range\n", addr); return 0xFF; } @@ -463,24 +463,24 @@ void JEDEC_put_mbyte(int32 addr, int32 val) UNIT *uptr; if (JEDEC_dev.dctrl & DEBUG_write) - printf("\tJEDEC_put_mbyte: Entered\n"); + sim_printf("\tJEDEC_put_mbyte: Entered\n"); for (i = 0; i < JEDEC_NUM; i++) { /* test all umits for address */ uptr = JEDEC_dev.units + i; org = uptr->u3; len = uptr->capac - 1; if ((addr >= org) && (addr < org + len)) { if (JEDEC_dev.dctrl & DEBUG_write) - printf("\tJEDEC%d Org=%06XH Len=%06XH\n", i, org, len); + sim_printf("\tJEDEC%d Org=%06XH Len=%06XH\n", i, org, len); if (uptr->u5 & RAM) { /* can't write to ROM */ *(JEDEC_buf[uptr->u6] + (addr - org)) = val & 0xFF; if (JEDEC_dev.dctrl & DEBUG_write) - printf("\tJEDEC_put_mbyte: Exit with [%06XH]=%02XH\n", addr, val); + sim_printf("\tJEDEC_put_mbyte: Exit with [%06XH]=%02XH\n", addr, val); } else - printf("\tJEDEC_put_mbyte: Write to ROM ignored\n"); + sim_printf("\tJEDEC_put_mbyte: Write to ROM ignored\n"); } } if (JEDEC_dev.dctrl & DEBUG_write) - printf("\tJEDEC_put_mbyte: Exit - Out of range\n"); + sim_printf("\tJEDEC_put_mbyte: Exit - Out of range\n"); } /* end of iJEDEC.c */ diff --git a/Intel-Systems/common/iram16.c b/Intel-Systems/common/iram16.c index 6333d971..0732c6c8 100644 --- a/Intel-Systems/common/iram16.c +++ b/Intel-Systems/common/iram16.c @@ -105,10 +105,10 @@ uint8 *RAM_buf = NULL; /* RAM buffer pointer */ t_stat RAM_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) { if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_set_size: val=%d\n", val); + sim_printf("RAM_set_size: val=%d\n", val); if ((val < UNIT_NONE) || (val > UNIT_16K)) { if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_set_size: Size error\n"); + sim_printf("RAM_set_size: Size error\n"); return SCPE_ARG; } RAM_unit.capac = 0x4000 * val; /* set size */ @@ -119,7 +119,7 @@ t_stat RAM_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) RAM_buf = NULL; } if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_set_size: Done\n"); + sim_printf("RAM_set_size: Done\n"); return (RAM_reset (NULL)); /* force reset after reconfig */ } @@ -131,27 +131,27 @@ t_stat RAM_reset (DEVICE *dptr) FILE *fp; if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_reset: \n"); + sim_printf("RAM_reset: \n"); if (RAM_unit.capac == 0) { /* if undefined */ - printf(" RAM: defaulted for 16KB\n"); - printf(" \"set RAM 16KB\"\n"); + sim_printf(" RAM: defaulted for 16KB\n"); + sim_printf(" \"set RAM 16KB\"\n"); RAM_unit.capac = 0x4000; RAM_unit.u3 = 0; RAM_unit.u4 = 1; } - printf(" RAM: Initializing [%04X-%04XH]\n", + sim_printf(" RAM: Initializing [%04X-%04XH]\n", RAM_unit.u3, RAM_unit.u3 + RAM_unit.capac - 1); if (RAM_buf == NULL) { /* no buffer allocated */ RAM_buf = malloc(RAM_unit.capac); if (RAM_buf == NULL) { if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_reset: Malloc error\n"); + sim_printf("RAM_reset: Malloc error\n"); return SCPE_MEM; } } if (RAM_dev.dctrl & DEBUG_flow) - printf("RAM_reset: Done\n"); + sim_printf("RAM_reset: Done\n"); return SCPE_OK; } @@ -168,15 +168,15 @@ int32 RAM_get_mbyte(int32 addr) org = RAM_unit.u3; len = RAM_unit.capac - 1; if (RAM_dev.dctrl & DEBUG_read) - printf("RAM_get_mbyte: addr=%04X", addr); + sim_printf("RAM_get_mbyte: addr=%04X", addr); if ((addr >= org) && (addr <= org + len)) { val = *(RAM_buf + (addr - org)); if (RAM_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_printf(" val=%04X\n", val); return (val & 0xFF); } if (RAM_dev.dctrl & DEBUG_read) - printf(" Out of range\n", addr); + sim_printf(" Out of range\n", addr); return 0xFF; } @@ -189,15 +189,15 @@ void RAM_put_mbyte(int32 addr, int32 val) org = RAM_unit.u3; len = RAM_unit.capac - 1; if (RAM_dev.dctrl & DEBUG_write) - printf("RAM_put_mbyte: addr=%04X, val=%02X", addr, val); + sim_printf("RAM_put_mbyte: addr=%04X, val=%02X", addr, val); if ((addr >= org) && (addr < org + len)) { *(RAM_buf + (addr - org)) = val & 0xFF; if (RAM_dev.dctrl & DEBUG_write) - printf("\n"); + sim_printf("\n"); return; } if (RAM_dev.dctrl & DEBUG_write) - printf(" Out of range\n", val); + sim_printf(" Out of range\n", val); } /* end of iram.c */ diff --git a/Intel-Systems/common/iram8.c b/Intel-Systems/common/iram8.c index f6c51401..0515a735 100644 --- a/Intel-Systems/common/iram8.c +++ b/Intel-Systems/common/iram8.c @@ -109,7 +109,7 @@ t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size) return SCPE_MEM; } } -// printf(" RAM: Available [%04X-%04XH]\n", +// sim_printf(" RAM: Available [%04X-%04XH]\n", // RAM_unit.u3, // RAM_unit.u3 + RAM_unit.capac - 1); sim_debug (DEBUG_flow, &RAM_dev, "RAM_reset: Done\n"); diff --git a/Intel-Systems/common/isbc064.c b/Intel-Systems/common/isbc064.c index b6204ec8..752eec29 100644 --- a/Intel-Systems/common/isbc064.c +++ b/Intel-Systems/common/isbc064.c @@ -101,7 +101,7 @@ t_stat isbc064_reset (DEVICE *dptr) if ((isbc064_dev.flags & DEV_DIS) == 0) { isbc064_unit.capac = SBC064_SIZE; isbc064_unit.u3 = SBC064_BASE; - printf("iSBC 064: Available[%04X-%04XH]\n", + sim_printf("iSBC 064: Available[%04X-%04XH]\n", isbc064_unit.u3, isbc064_unit.u3 + isbc064_unit.capac - 1); } diff --git a/Intel-Systems/common/isbc064b.c b/Intel-Systems/common/isbc064b.c index c23c5e6a..4fdd8b95 100644 --- a/Intel-Systems/common/isbc064b.c +++ b/Intel-Systems/common/isbc064b.c @@ -110,10 +110,10 @@ t_stat isbc064_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) uint32 i; if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_set_size: val=%04X\n", val); + sim_printf("isbc064_set_size: val=%04X\n", val); if ((val <= 0) || (val > MAXMEMSIZE)) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_set_size: Memory size error\n"); + sim_printf("isbc064_set_size: Memory size error\n"); return SCPE_ARG; } isbc064_unit.capac = val; @@ -126,7 +126,7 @@ t_stat isbc064_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) MB_buf = NULL; } if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_set_size: Done\n"); + sim_printf("isbc064_set_size: Done\n"); return SCPE_OK; } @@ -135,10 +135,10 @@ t_stat isbc064_set_size (UNIT *uptr, int32 val, char *cptr, void *desc) t_stat isbc064_set_base (UNIT *uptr, int32 val, char *cptr, void *desc) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_set_base: val=%04X\n", val); + sim_printf("isbc064_set_base: val=%04X\n", val); if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0)) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_set_base: Base address error\n"); + sim_printf("isbc064_set_base: Base address error\n"); return SCPE_ARG; } isbc064_unit.u3 = val; @@ -147,7 +147,7 @@ t_stat isbc064_set_base (UNIT *uptr, int32 val, char *cptr, void *desc) MB_buf = NULL; } if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_set_base: Done\n"); + sim_printf("isbc064_set_base: Done\n"); return (isbc064_reset (NULL)); } @@ -156,22 +156,22 @@ t_stat isbc064_set_base (UNIT *uptr, int32 val, char *cptr, void *desc) t_stat isbc064_reset (DEVICE *dptr) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: \n"); + sim_printf("isbc064_reset: \n"); if ((isbc064_dev.flags & DEV_DIS) == 0) { - printf("Initializing %s [%04X-%04XH]\n", "iSBC-064", + sim_printf("Initializing %s [%04X-%04XH]\n", "iSBC-064", isbc064_unit.u3, isbc064_unit.u3 + isbc064_unit.capac - 1); if (MB_buf == NULL) { MB_buf = malloc(isbc064_unit.capac); if (MB_buf == NULL) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Malloc error\n"); + sim_printf("isbc064_reset: Malloc error\n"); return SCPE_MEM; } } } if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Done\n"); + sim_printf("isbc064_reset: Done\n"); return SCPE_OK; } @@ -190,20 +190,20 @@ int32 isbc064_get_mbyte(int32 addr) org = isbc064_unit.u3; len = isbc064_unit.capac - 1; if (isbc064_dev.dctrl & DEBUG_read) - printf("isbc064_get_mbyte: addr=%04X", addr); + sim_printf("isbc064_get_mbyte: addr=%04X", addr); if ((addr >= org) && (addr <= org + len)) { val = *(MB_buf + (addr - org)); if (isbc064_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_printf(" val=%04X\n", val); return (val & 0xFF); } else { if (isbc064_dev.dctrl & DEBUG_read) - printf(" Out of range\n"); + sim_printf(" Out of range\n"); return 0xFF; /* multibus has active high pullups */ } } if (isbc064_dev.dctrl & DEBUG_read) - printf(" Disabled\n"); + sim_printf(" Disabled\n"); return 0xFF; /* multibus has active high pullups */ } @@ -229,20 +229,20 @@ void isbc064_put_mbyte(int32 addr, int32 val) org = isbc064_unit.u3; len = isbc064_unit.capac - 1; if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: addr=%04X, val=%02X", addr, val); + sim_printf("isbc064_put_mbyte: addr=%04X, val=%02X", addr, val); if ((addr >= org) && (addr < org + len)) { *(MB_buf + (addr - org)) = val & 0xFF; if (isbc064_dev.dctrl & DEBUG_write) - printf("\n"); + sim_printf("\n"); return; } else { if (isbc064_dev.dctrl & DEBUG_write) - printf(" Out of range\n"); + sim_printf(" Out of range\n"); return; } } if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: Disabled\n"); + sim_printf("isbc064_put_mbyte: Disabled\n"); } /* put a word into memory */ diff --git a/Intel-Systems/common/isbc064x.c b/Intel-Systems/common/isbc064x.c index 2685ec5f..753e7e83 100644 --- a/Intel-Systems/common/isbc064x.c +++ b/Intel-Systems/common/isbc064x.c @@ -95,13 +95,13 @@ DEVICE isbc064_dev = { t_stat isbc064_reset (DEVICE *dptr) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: \n"); + sim_printf("isbc064_reset: \n"); if ((isbc064_dev.flags & DEV_DIS) == 0) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Size=%04X\n", isbc064_unit.capac - 1); + sim_printf("isbc064_reset: Size=%04X\n", isbc064_unit.capac - 1); if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Base address=%04X\n", isbc064_unit.u3); - printf("iSBC 064: Available[%04X-%04XH]\n", + sim_printf("isbc064_reset: Base address=%04X\n", isbc064_unit.u3); + sim_printf("iSBC 064: Available[%04X-%04XH]\n", isbc064_unit.u3, isbc064_unit.u3 + isbc064_unit.capac - 1); } @@ -109,12 +109,12 @@ t_stat isbc064_reset (DEVICE *dptr) isbc064_unit.filebuf = malloc(isbc064_unit.capac); if (isbc064_unit.filebuf == NULL) { if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Malloc error\n"); + sim_printf("isbc064_reset: Malloc error\n"); return SCPE_MEM; } } if (isbc064_dev.dctrl & DEBUG_flow) - printf("isbc064_reset: Done\n"); + sim_printf("isbc064_reset: Done\n"); return SCPE_OK; } @@ -129,25 +129,25 @@ int32 isbc064_get_mbyte(int32 addr) org = isbc064_unit.u3; len = isbc064_unit.capac; if (isbc064_dev.dctrl & DEBUG_read) - printf("isbc064_get_mbyte: addr=%04X", addr); + sim_printf("isbc064_get_mbyte: addr=%04X", addr); if (isbc064_dev.dctrl & DEBUG_read) - printf("isbc064_put_mbyte: org=%04X, len=%04X\n", org, len); + sim_printf("isbc064_put_mbyte: org=%04X, len=%04X\n", org, len); if ((addr >= org) && (addr < (org + len))) { SET_XACK(1); /* good memory address */ if (isbc064_dev.dctrl & DEBUG_xack) - printf("isbc064_get_mbyte: Set XACK for %04X\n", addr); + sim_printf("isbc064_get_mbyte: Set XACK for %04X\n", addr); val = *(uint8 *)(isbc064_unit.filebuf + (addr - org)); if (isbc064_dev.dctrl & DEBUG_read) - printf(" val=%04X\n", val); + sim_printf(" val=%04X\n", val); return (val & 0xFF); } else { if (isbc064_dev.dctrl & DEBUG_read) - printf(" Out of range\n"); + sim_printf(" Out of range\n"); return 0xFF; /* multibus has active high pullups */ } } if (isbc064_dev.dctrl & DEBUG_read) - printf(" Disabled\n"); + sim_printf(" Disabled\n"); return 0xFF; /* multibus has active high pullups */ } @@ -173,25 +173,25 @@ void isbc064_put_mbyte(int32 addr, int32 val) org = isbc064_unit.u3; len = isbc064_unit.capac; if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: addr=%04X, val=%02X\n", addr, val); + sim_printf("isbc064_put_mbyte: addr=%04X, val=%02X\n", addr, val); if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: org=%04X, len=%04X\n", org, len); + sim_printf("isbc064_put_mbyte: org=%04X, len=%04X\n", org, len); if ((addr >= org) && (addr < (org + len))) { SET_XACK(1); /* good memory address */ if (isbc064_dev.dctrl & DEBUG_xack) - printf("isbc064_put_mbyte: Set XACK for %04X\n", addr); + sim_printf("isbc064_put_mbyte: Set XACK for %04X\n", addr); *(uint8 *)(isbc064_unit.filebuf + (addr - org)) = val & 0xFF; if (isbc064_dev.dctrl & DEBUG_xack) - printf("isbc064_put_mbyte: Return\n"); + sim_printf("isbc064_put_mbyte: Return\n"); return; } else { if (isbc064_dev.dctrl & DEBUG_write) - printf(" Out of range\n"); + sim_printf(" Out of range\n"); return; } } if (isbc064_dev.dctrl & DEBUG_write) - printf("isbc064_put_mbyte: Disabled\n"); + sim_printf("isbc064_put_mbyte: Disabled\n"); } /* put a word into memory */ diff --git a/Intel-Systems/common/isbc208.c b/Intel-Systems/common/isbc208.c index 26a3ba4b..ef95b6da 100644 --- a/Intel-Systems/common/isbc208.c +++ b/Intel-Systems/common/isbc208.c @@ -684,7 +684,7 @@ t_stat isbc208_svc (UNIT *uptr) sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: Entered execution phase\n"); switch (cmd) { case READ: /* 0x06 */ -// printf("READ-e: fddst=%02X", fddst[uptr->u6]); +// sim_printf("READ-e: fddst=%02X", fddst[uptr->u6]); h = i8272_w3; // h = 0 or 1 hed = i8272_w3 << 2; // hed = 0 or 4 [h << 2] sec = i8272_w4; // sector number (1-XX) @@ -693,7 +693,7 @@ t_stat isbc208_svc (UNIT *uptr) ssize = 128 << secn; // size of sector (bytes) bpt = ssize * spt; // bytes/track bpc = bpt * 2; // bytes/cylinder -// printf(" d=%d h=%d c=%d s=%d\n", drv, h, cyl, sec); +// sim_printf(" d=%d h=%d c=%d s=%d\n", drv, h, cyl, sec); sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC read: h=%d, hed=%d, sec=%d, secn=%d, spt=%d, ssize=%04X, bpt=%04X, bpc=%04X\n", h, hed, sec, secn, spt, ssize, bpt, bpc); @@ -736,10 +736,10 @@ t_stat isbc208_svc (UNIT *uptr) i8272_msr |= (RQM + DIO + CB); /* enter result phase */ rsp = wsp = 0; /* reset indexes */ set_irq(SBC208_INT); /* set interrupt */ -// printf("READ-x: fddst=%02X\n", fddst[uptr->u6]); +// sim_printf("READ-x: fddst=%02X\n", fddst[uptr->u6]); break; case WRITE: /* 0x05 */ -// printf("WRITE-e: fddst=%02X\n", fddst[uptr->u6]); +// sim_printf("WRITE-e: fddst=%02X\n", fddst[uptr->u6]); h = i8272_w3; // h = 0 or 1 hed = i8272_w3 << 2; // hed = 0 or 4 [h << 2] sec = i8272_w4; // sector number (1-XX) @@ -766,9 +766,9 @@ t_stat isbc208_svc (UNIT *uptr) // i8272_r1 = NW; // set not writable in ST1 // i8272_r3 = fddst[uptr->u6] + WP; // i8272_msr |= (RQM + DIO + CB); /* enter result phase */ -// printf("\nWrite Protected fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); +// sim_printf("\nWrite Protected fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); // if (isbc208_dev.dctrl & DEBUG_flow) -// printf("isbc208_svc: FDC write: Write Protected\n"); +// sim_printf("isbc208_svc: FDC write: Write Protected\n"); } else { // get image addr for this d, h, c, s imgadr = (cyl * bpc) + (h * bpt) + ((sec - 1) * ssize); sim_debug (DEBUG_flow, &isbc208_dev, @@ -796,7 +796,7 @@ t_stat isbc208_svc (UNIT *uptr) } rsp = wsp = 0; /* reset indexes */ set_irq(SBC208_INT); /* set interrupt */ -// printf("WRITE-x: fddst=%02X\n", fddst[uptr->u6]); +// sim_printf("WRITE-x: fddst=%02X\n", fddst[uptr->u6]); break; case FMTTRK: /* 0x0D */ if ((fddst[uptr->u6] & RDY) == 0) { @@ -834,7 +834,7 @@ t_stat isbc208_svc (UNIT *uptr) rsp = wsp = 0; /* reset indexes */ break; case HOME: /* 0x07 */ -// printf("HOME-e: fddst=%02X\n", fddst[uptr->u6]); +// sim_printf("HOME-e: fddst=%02X\n", fddst[uptr->u6]); sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC home: disk=%d fddst=%02X\n", drv, fddst[uptr->u6]); if ((fddst[uptr->u6] & RDY) == 0) { @@ -852,14 +852,14 @@ t_stat isbc208_svc (UNIT *uptr) i8272_msr |= RQM; /* enter COMMAND phase */ rsp = wsp = 0; /* reset indexes */ set_irq(SBC208_INT); /* set interrupt */ -// printf("HOME-x: fddst=%02X\n", fddst[uptr->u6]); +// sim_printf("HOME-x: fddst=%02X\n", fddst[uptr->u6]); break; case SPEC: /* 0x03 */ fddst[0] |= TS; //*** bad, bad, bad! fddst[1] |= TS; fddst[2] |= TS; fddst[3] |= TS; -// printf("SPEC-e: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); +// sim_printf("SPEC-e: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC specify SRT=%d ms HUT=%d ms HLT=%d ms \n", 16 - (drv >> 4), 16 * (drv & 0x0f), i8272_w2 & 0xfe); @@ -870,7 +870,7 @@ t_stat isbc208_svc (UNIT *uptr) i8272_msr = 0; // force 0 for now, where does 0x07 come from? i8272_msr |= RQM; /* enter command phase */ rsp = wsp = 0; /* reset indexes */ -// printf("SPEC-x: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); +// sim_printf("SPEC-x: fddst[%d]=%02X\n", uptr->u6, fddst[uptr->u6]); break; case READID: /* 0x0A */ if ((fddst[uptr->u6] & RDY) == 0) { @@ -891,7 +891,7 @@ t_stat isbc208_svc (UNIT *uptr) rsp = wsp = 0; /* reset indexes */ break; case SEEK: /* 0x0F */ -// printf("SEEK-e: fddst=%02X\n", fddst[uptr->u6]); +// sim_printf("SEEK-e: fddst=%02X\n", fddst[uptr->u6]); sim_debug (DEBUG_flow, &isbc208_dev, "isbc208_svc: FDC seek: disk=%d cyl=%d fddst=%02X\n", drv, i8272_w2, fddst[uptr->u6]); if ((fddst[uptr->u6] & RDY) == 0) { /* Not ready? */ @@ -918,7 +918,7 @@ t_stat isbc208_svc (UNIT *uptr) i8272_msr |= RQM; /* enter command phase */ rsp = wsp = 0; /* reset indexes */ // set_irq(SBC208_INT); /* set interrupt */ -// printf("SEEK-x: fddst=%02X\n", fddst[uptr->u6]); +// sim_printf("SEEK-x: fddst=%02X\n", fddst[uptr->u6]); break; default: i8272_msr &= ~(RQM + DIO + CB); /* execution phase done*/ @@ -1096,14 +1096,14 @@ void isbc208_reset1 (void) UNIT *uptr; static int flag = 1; - if (flag) printf("iSBC 208: Initializing\n"); + if (flag) sim_printf("iSBC 208: Initializing\n"); for (i = 0; i < FDD_NUM; i++) { /* handle all units */ uptr = isbc208_dev.units + i; if (uptr->capac == 0) { /* if not configured */ -// printf(" SBC208%d: Not configured\n", i); +// sim_printf(" SBC208%d: Not configured\n", i); // if (flag) { -// printf(" ALL: \"set isbc208 en\"\n"); -// printf(" EPROM: \"att isbc2080 \"\n"); +// sim_printf(" ALL: \"set isbc208 en\"\n"); +// sim_printf(" EPROM: \"att isbc2080 \"\n"); // flag = 0; // } uptr->capac = 0; /* initialize unit */ @@ -1116,7 +1116,7 @@ void isbc208_reset1 (void) sim_activate (&isbc208_unit[uptr->u6], isbc208_unit[uptr->u6].wait); } else { fddst[i] = RDY + WP + T0 + i; /* initial attach drive status */ -// printf(" SBC208%d: Configured, Attached to %s\n", i, uptr->filename); +// sim_printf(" SBC208%d: Configured, Attached to %s\n", i, uptr->filename); } } i8237_r8 = 0; /* status */ @@ -1128,8 +1128,8 @@ void isbc208_reset1 (void) rsp = wsp = 0; /* reset indexes */ cmd = 0; /* clear command */ if (flag) { - printf(" 8237 Reset\n"); - printf(" 8272 Reset\n"); + sim_printf(" 8237 Reset\n"); + sim_printf(" 8272 Reset\n"); } flag = 0; } @@ -1145,22 +1145,22 @@ t_stat isbc208_attach (UNIT *uptr, char *cptr) sim_debug (DEBUG_flow, &isbc208_dev, " isbc208_attach: Entered with cptr=%s\n", cptr); if ((r = attach_unit (uptr, cptr)) != SCPE_OK) { - printf(" isbc208_attach: Attach error\n"); + sim_printf(" isbc208_attach: Attach error\n"); return r; } fp = fopen(uptr->filename, "rb"); if (fp == NULL) { - printf(" Unable to open disk img file %s\n", uptr->filename); - printf(" No disk image loaded!!!\n"); + sim_printf(" Unable to open disk img file %s\n", uptr->filename); + sim_printf(" No disk image loaded!!!\n"); } else { - printf("iSBC 208: Attach\n"); + sim_printf("iSBC 208: Attach\n"); fseek(fp, 0, SEEK_END); /* size disk image */ flen = ftell(fp); fseek(fp, 0, SEEK_SET); if (isbc208_buf[uptr->u6] == NULL) { /* no buffer allocated */ isbc208_buf[uptr->u6] = malloc(flen); if (isbc208_buf[uptr->u6] == NULL) { - printf(" iSBC208_attach: Malloc error\n"); + sim_printf(" iSBC208_attach: Malloc error\n"); return SCPE_MEM; } } @@ -1189,7 +1189,7 @@ t_stat isbc208_attach (UNIT *uptr, char *cptr) maxcyl[uptr->u6] = 80; fddst[uptr->u6] |= TS; // two sided } - printf(" Drive-%d: %d bytes of disk image %s loaded, fddst=%02X\n", + sim_printf(" Drive-%d: %d bytes of disk image %s loaded, fddst=%02X\n", uptr->u6, i, uptr->filename, fddst[uptr->u6]); } sim_debug (DEBUG_flow, &isbc208_dev, " iSBC208_attach: Done\n"); @@ -1211,7 +1211,7 @@ t_stat isbc208_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc) fddst[uptr->u6] &= ~WP; uptr->flags &= ~val; } -// printf("fddst[%d]=%02XH uptr->flags=%08X\n", uptr->u6, fddst[uptr->u6], uptr->flags); +// sim_printf("fddst[%d]=%02XH uptr->flags=%08X\n", uptr->u6, fddst[uptr->u6], uptr->flags); sim_debug (DEBUG_flow, &isbc208_dev, " isbc208_set_mode: Done\n"); return SCPE_OK; } diff --git a/Intel-Systems/common/mds-800.c b/Intel-Systems/common/mds-800.c index 0d9b94b3..d5e35a12 100644 --- a/Intel-Systems/common/mds-800.c +++ b/Intel-Systems/common/mds-800.c @@ -79,7 +79,7 @@ extern t_stat RAM_reset (DEVICE *dptr, int32 base, int32 size); t_stat SBC_reset (DEVICE *dptr) { - printf("Initializing iSBC-80/10:\n"); + sim_printf("Initializing iSBC-80/10:\n"); i8080_reset (NULL); i8255_reset (NULL, I8255_BASE_0); i8255_reset (NULL, I8255_BASE_1); @@ -122,7 +122,7 @@ void put_mbyte(int32 addr, int32 val) { /* if local EPROM handle it */ if ((i8255_unit.u5 & 0x01) && (addr >= EPROM_unit.u3) && (addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { - printf("Write to R/O memory address %04X - ignored\n", addr); + sim_printf("Write to R/O memory address %04X - ignored\n", addr); return; } /* if local RAM handle it */ if ((i8255_unit.u5 & 0x02) && (addr >= RAM_unit.u3) && (addr <= (RAM_unit.u3 + RAM_unit.capac))) { diff --git a/Intel-Systems/common/multibus.c b/Intel-Systems/common/multibus.c index 28428564..e1942576 100644 --- a/Intel-Systems/common/multibus.c +++ b/Intel-Systems/common/multibus.c @@ -127,10 +127,10 @@ t_stat multibus_svc(UNIT *uptr) case INT_1: set_cpuint(INT_R); clr_irq(SBC208_INT); /***** bad, bad, bad! */ -// printf("multibus_svc: mbirq=%04X int_req=%04X\n", mbirq, int_req); +// sim_printf("multibus_svc: mbirq=%04X int_req=%04X\n", mbirq, int_req); break; default: -// printf("multibus_svc: default mbirq=%04X\n", mbirq); +// sim_printf("multibus_svc: default mbirq=%04X\n", mbirq); break; } sim_activate (&multibus_unit, multibus_unit.wait); /* continue poll */ @@ -143,7 +143,7 @@ t_stat multibus_reset(DEVICE *dptr) SBC_reset(NULL); isbc064_reset(NULL); isbc208_reset(NULL); - printf(" Multibus: Reset\n"); + sim_printf(" Multibus: Reset\n"); sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */ return SCPE_OK; } @@ -151,13 +151,13 @@ t_stat multibus_reset(DEVICE *dptr) void set_irq(int32 int_num) { mbirq |= int_num; -// printf("set_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq); +// sim_printf("set_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq); } void clr_irq(int32 int_num) { mbirq &= ~int_num; -// printf("clr_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq); +// sim_printf("clr_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq); } /* This is the I/O configuration table. There are 256 possible @@ -246,9 +246,9 @@ int32 nulldev(int32 flag, int32 data) int32 reg_dev(int32 (*routine)(), int32 port) { if (dev_table[port].routine != &nulldev) { /* port already assigned */ -// printf("Multibus: I/O Port %02X is already assigned\n", port); +// sim_printf("Multibus: I/O Port %02X is already assigned\n", port); } else { -// printf("Port %02X is assigned\n", port); +// sim_printf("Port %02X is assigned\n", port); dev_table[port].routine = routine; } } @@ -258,7 +258,7 @@ int32 reg_dev(int32 (*routine)(), int32 port) int32 multibus_get_mbyte(int32 addr) { SET_XACK(0); /* set no XACK */ -// printf("multibus_get_mbyte: Cleared XACK for %04X\n", addr); +// sim_printf("multibus_get_mbyte: Cleared XACK for %04X\n", addr); return isbc064_get_mbyte(addr); } @@ -278,9 +278,9 @@ int32 multibus_get_mword(int32 addr) void multibus_put_mbyte(int32 addr, int32 val) { SET_XACK(0); /* set no XACK */ -// printf("multibus_put_mbyte: Cleared XACK for %04X\n", addr); +// sim_printf("multibus_put_mbyte: Cleared XACK for %04X\n", addr); isbc064_put_mbyte(addr, val); -// printf("multibus_put_mbyte: Done XACK=%dX\n", XACK); +// sim_printf("multibus_put_mbyte: Done XACK=%dX\n", XACK); } /* put a word to memory */ diff --git a/Intel-Systems/common/pata.c b/Intel-Systems/common/pata.c index 5648bf5c..230af10c 100644 --- a/Intel-Systems/common/pata.c +++ b/Intel-Systems/common/pata.c @@ -127,9 +127,9 @@ int32 patas(int32 io, int32 data) } else { /* write status port */ if (data & 0x80) { /* mode instruction */ pata_unit[0].u3 = data; - printf("PATA: 8255 Mode Instruction=%02X\n", data); + sim_printf("PATA: 8255 Mode Instruction=%02X\n", data); if (data & 0x64) - printf(" Mode 1 and 2 not yet implemented\n"); + sim_printf(" Mode 1 and 2 not yet implemented\n"); } else { /* bit set */ bit = (data & 0x0E) >> 1; /* get bit number */ if (data & 0x01) { /* set bit */ @@ -148,7 +148,7 @@ int32 pataa(int32 io, int32 data) return (pata_unit[0].u4); } else { /* write data port */ pata_unit[0].u4 = data; - printf("PATA: 8255 Port A = %02X\n", data); + sim_printf("PATA: 8255 Port A = %02X\n", data); } return 0; } @@ -159,7 +159,7 @@ int32 patab(int32 io, int32 data) return (pata_unit[0].u5); } else { /* write data port */ pata_unit[0].u5 = data; - printf("PATA: 8255 Port B = %02X\n", data); + sim_printf("PATA: 8255 Port B = %02X\n", data); } return 0; } @@ -170,7 +170,7 @@ int32 patac(int32 io, int32 data) return (pata_unit[0].u6); } else { /* write data port */ pata_unit[0].u6 = data; - printf("PATA: 8255 Port C = %02X\n", data); + sim_printf("PATA: 8255 Port C = %02X\n", data); } return 0; } @@ -187,7 +187,7 @@ t_stat pata_reset (DEVICE *dptr, int32 base) reg_dev(patab, base + 1); reg_dev(patac, base + 2); reg_dev(patas, base + 3); - printf(" PATA: Reset\n"); + sim_printf(" PATA: Reset\n"); return SCPE_OK; }