From a7216dbbd12a4a4cc6db5cdfb4b2f3730cf1e47d Mon Sep 17 00:00:00 2001 From: Bob Supnik Date: Thu, 18 May 2017 12:45:21 -0700 Subject: [PATCH] All VAX: Added model-specific AST validation test From page 6-6 of DEC STD 032 (the VAX architecture spec): "Execution of MTPR src, #PR$_ASTLVL with src<31:0> GEQU 5 results in UNDEFINED behavior. The preferred implementation is to cause a reserved operand fault." MicroVAX II, CVAX, and Rigel all conform to the preferred behavior, as does the current simulator, which was written from the CVAX microcode. NVAX masks to 3b and does not take an exception on a value GEQU 5. The 1982 Architecture Handbook describes ASTLVL as a 3b register, with src<31:3> ignored/read as zero, and exceptions taken on values GEQU 5. The780 microcode masks the input value to 3b before doing the GEQU 5 test. The ASTLVL test needs to be model specific. I suspect the behavior became undefined when MicroVAX II simplified the original test to save a microword. I do not see how the code fragment Matt references could work on a MicroVAX II, which was supported under 4.5. Perhaps the device Matt mentions couldn't exist on a MicroVAX II? For those who wants the gory details... uVAX, CVAX, and Rigel do an unsigned compare on the unmasked src and the constant 5. Carry out means reserved operand. Overflow is ignored. So an input of 0x80000002 - 0x00000005 (done in the data path as 0x80000002 + 0xFFFFFFFB) generates overflow (ignored) and carry out. # Conflicts: # VAX/vaxmod_defs.h --- VAX/vax610_defs.h | 4 +++- VAX/vax630_defs.h | 4 +++- VAX/vax730_defs.h | 3 +++ VAX/vax750_defs.h | 3 +++ VAX/vax780_defs.h | 4 ++++ VAX/vax860_defs.h | 3 +++ VAX/vax_cpu1.c | 3 +-- VAX/vaxmod_defs.h | 8 ++++++-- 8 files changed, 26 insertions(+), 6 deletions(-) diff --git a/VAX/vax610_defs.h b/VAX/vax610_defs.h index b0930001..e5a7da17 100644 --- a/VAX/vax610_defs.h +++ b/VAX/vax610_defs.h @@ -132,7 +132,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define ADDR_IS_ROM(x) (0) #define ADDR_IS_NVR(x) (0) -/* Machine specific reserved operand tests (all NOPs) */ +/* Machine specific reserved operand tests (mostly NOPs) */ #define ML_PA_TEST(r) #define ML_LR_TEST(r) @@ -142,6 +142,8 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + /* Qbus I/O modes */ #define READ 0 /* PDP-11 compatibility */ diff --git a/VAX/vax630_defs.h b/VAX/vax630_defs.h index 39ea5770..59d5f5f3 100644 --- a/VAX/vax630_defs.h +++ b/VAX/vax630_defs.h @@ -182,7 +182,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define ADDR_IS_CDG(x) (0) -/* Machine specific reserved operand tests (all NOPs) */ +/* Machine specific reserved operand tests (mostly NOPs) */ #define ML_PA_TEST(r) #define ML_LR_TEST(r) @@ -192,6 +192,8 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + /* Qbus I/O modes */ #define READ 0 /* PDP-11 compatibility */ diff --git a/VAX/vax730_defs.h b/VAX/vax730_defs.h index 3946f4c3..c863ede4 100644 --- a/VAX/vax730_defs.h +++ b/VAX/vax730_defs.h @@ -116,6 +116,9 @@ #define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT #define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define MT_AST_TEST(r) r = (r) & 07; \ + if ((r) > AST_MAX) RSVD_OPND_FAULT + /* Memory */ #define MAXMEMWIDTH 21 /* max mem, 16k chips */ diff --git a/VAX/vax750_defs.h b/VAX/vax750_defs.h index 6bce6e23..a534410e 100644 --- a/VAX/vax750_defs.h +++ b/VAX/vax750_defs.h @@ -137,6 +137,9 @@ #define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT #define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define MT_AST_TEST(r) r = (r) & 07; \ + if ((r) > AST_MAX) RSVD_OPND_FAULT + /* Memory */ #define MAXMEMWIDTH 21 /* max mem, 16k chips */ diff --git a/VAX/vax780_defs.h b/VAX/vax780_defs.h index 42b0aaef..bbbbf452 100644 --- a/VAX/vax780_defs.h +++ b/VAX/vax780_defs.h @@ -23,6 +23,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 18-May-17 RMS Added model-specific AST validation test 19-Jan-17 RMS Moved CR to BR6 (Mark Pizzolato) 29-Mar-15 RMS Added model specific IPR max 16-Dec-14 RMS Removed TQ boot code (780 VMB doesn't support tape boot) @@ -154,6 +155,9 @@ #define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT #define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define MT_AST_TEST(r) r = (r) & 07; \ + if ((r) > AST_MAX) RSVD_OPND_FAULT + /* Memory */ #define MAXMEMWIDTH 23 /* max mem, MS780C */ diff --git a/VAX/vax860_defs.h b/VAX/vax860_defs.h index 5a7d312b..c281f38b 100644 --- a/VAX/vax860_defs.h +++ b/VAX/vax860_defs.h @@ -174,6 +174,9 @@ #define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT #define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT +#define MT_AST_TEST(r) r = (r) & 07; \ + if ((r) > AST_MAX) RSVD_OPND_FAULT + /* Memory */ #define MAXMEMWIDTH 25 /* max mem, 4MB boards */ diff --git a/VAX/vax_cpu1.c b/VAX/vax_cpu1.c index c7c0372b..144ee826 100644 --- a/VAX/vax_cpu1.c +++ b/VAX/vax_cpu1.c @@ -1506,8 +1506,7 @@ switch (prn) { /* case on reg # */ break; case MT_ASTLVL: /* ASTLVL */ - if (val > AST_MAX) /* > 4? fault */ - RSVD_OPND_FAULT; + MT_AST_TEST (val); /* trim, test val */ ASTLVL = val; break; diff --git a/VAX/vaxmod_defs.h b/VAX/vaxmod_defs.h index 46544a46..5bd7ec9c 100644 --- a/VAX/vaxmod_defs.h +++ b/VAX/vaxmod_defs.h @@ -1,6 +1,6 @@ /* vaxmod_defs.h: VAX model-specific definitions file - Copyright (c) 1998-2013, Robert M Supnik + Copyright (c) 1998-2017, Robert M Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -23,6 +23,7 @@ used in advertising or otherwise to promote the sale, use or other dealings in this Software without prior written authorization from Robert M Supnik. + 18-May-17 RMS Added model-specific AST validation test 20-Dec-13 RMS Added prototypes for unaligned IO and register handling 11-Dec-11 RMS Moved all Qbus devices to BR4; deleted RP definitions 25-Nov-11 RMS Added VEC_QBUS definition @@ -232,7 +233,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define ADDR_IS_QVM(x) ((((uint32) (x)) >= QVMBASE) && \ (((uint32) (x)) < (QVMBASE + QVMSIZE))) -/* Machine specific reserved operand tests (all NOPs) */ +/* Machine specific reserved operand tests (mostly NOPs) */ #define ML_PA_TEST(r) #define ML_LR_TEST(r) @@ -242,6 +243,9 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc #define LP_MBZ84_TEST(r) #define LP_MBZ92_TEST(r) +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + + /* Qbus I/O modes */ #define READ 0 /* PDP-11 compatibility */