isys8010, isys8020, isys8024, isys8030, imds-225: Coverity identified problems
Corrected disk controller behaviors.
This commit is contained in:
Bill Beech
parent
f10f8bc9c5
commit
a943737ab4
11 changed files with 6408 additions and 6332 deletions
File diff suppressed because it is too large
Load diff
|
|
@ -1,233 +1,233 @@
|
||||||
/* ioc-cont.c: Intel IPC DBB adapter
|
/* ioc-cont.c: Intel IPC DBB adapter
|
||||||
|
|
||||||
Copyright (c) 2010, William A. Beech
|
Copyright (c) 2010, William A. Beech
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
to deal in the Software without restriction, including without limitation
|
to deal in the Software without restriction, including without limitation
|
||||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
and/or sell copies of the Software, and to permit persons to whom the
|
and/or sell copies of the Software, and to permit persons to whom the
|
||||||
Software is furnished to do so, subject to the following conditions:
|
Software is furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
The above copyright notice and this permission notice shall be included in
|
The above copyright notice and this permission notice shall be included in
|
||||||
all copies or substantial portions of the Software.
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
|
||||||
Except as contained in this notice, the name of William A. Beech shall not be
|
Except as contained in this notice, the name of William A. Beech shall not be
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from William A. Beech.
|
in this Software without prior written authorization from William A. Beech.
|
||||||
|
|
||||||
MODIFICATIONS:
|
MODIFICATIONS:
|
||||||
|
|
||||||
27 Jun 16 - Original file.
|
27 Jun 16 - Original file.
|
||||||
|
|
||||||
NOTES:
|
NOTES:
|
||||||
|
|
||||||
|
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "system_defs.h" /* system header in system dir */
|
#include "system_defs.h" /* system header in system dir */
|
||||||
|
|
||||||
#define DEBUG 0
|
#define DEBUG 0
|
||||||
|
|
||||||
//dbb status flag bits
|
//dbb status flag bits
|
||||||
#define OBF 1
|
#define OBF 1
|
||||||
#define IBF 2
|
#define IBF 2
|
||||||
#define F0 4
|
#define F0 4
|
||||||
#define CD 8
|
#define CD 8
|
||||||
|
|
||||||
//dbb command codes
|
//dbb command codes
|
||||||
#define PACIFY 0x00 //Resets IOC and its devices
|
#define PACIFY 0x00 //Resets IOC and its devices
|
||||||
#define ERESET 0x01 //Resets device-generated error (not used by standard devices)
|
#define ERESET 0x01 //Resets device-generated error (not used by standard devices)
|
||||||
#define SYSTAT 0x02 //Returns subsystem status byte to master
|
#define SYSTAT 0x02 //Returns subsystem status byte to master
|
||||||
#define DSTAT 0x03 //Returns device status byte to master
|
#define DSTAT 0x03 //Returns device status byte to master
|
||||||
#define SRQDAK 0x04 //Enables input of device interrupt acknowledge mask from master
|
#define SRQDAK 0x04 //Enables input of device interrupt acknowledge mask from master
|
||||||
#define SRQACK 0x05 //Clears IOC subsystem interrupt request
|
#define SRQACK 0x05 //Clears IOC subsystem interrupt request
|
||||||
#define SRQ 0x06 //Tests ability of IOC to forward an interrupt request to the master
|
#define SRQ 0x06 //Tests ability of IOC to forward an interrupt request to the master
|
||||||
#define DECHO 0x07 //Tests ability of IOC to echo data byte sent by master
|
#define DECHO 0x07 //Tests ability of IOC to echo data byte sent by master
|
||||||
#define CSMEM 0x08 //Requests IOC to checksum on-board ROM. Returns pass/fail
|
#define CSMEM 0x08 //Requests IOC to checksum on-board ROM. Returns pass/fail
|
||||||
#define TRAM 0x09 //Requests IOC to test on-board RAM. Returns pass/fail
|
#define TRAM 0x09 //Requests IOC to test on-board RAM. Returns pass/fail
|
||||||
#define SINT 0x0A //Enables specified device interrupt from IOC
|
#define SINT 0x0A //Enables specified device interrupt from IOC
|
||||||
#define CRTC 0x10 //Requests data byte output to the CRT monitor
|
#define CRTC 0x10 //Requests data byte output to the CRT monitor
|
||||||
#define CRTS 0x11 //Returns CRT status byte to master
|
#define CRTS 0x11 //Returns CRT status byte to master
|
||||||
#define KEYC 0x12 //Requests data byte input from the keyboard
|
#define KEYC 0x12 //Requests data byte input from the keyboard
|
||||||
#define KSTC 0x13 //Returns keyboard status byte to master
|
#define KSTC 0x13 //Returns keyboard status byte to master
|
||||||
#define WPBC 0x15 //Enables input of first of five bytes that define current diskette operation
|
#define WPBC 0x15 //Enables input of first of five bytes that define current diskette operation
|
||||||
#define WPBCC 0x16 //Enables input of each of four bytes that follow WPBC
|
#define WPBCC 0x16 //Enables input of each of four bytes that follow WPBC
|
||||||
#define WDBC 0x17 //Enables input of diskette write bytes from master
|
#define WDBC 0x17 //Enables input of diskette write bytes from master
|
||||||
#define RDBC 0x19 //Enables output of diskette read bytes to master
|
#define RDBC 0x19 //Enables output of diskette read bytes to master
|
||||||
#define RRSTS 0x1B //Returns diskette result byte to master
|
#define RRSTS 0x1B //Returns diskette result byte to master
|
||||||
#define RDSTS 0x1C //Returns diskette device status byte to master
|
#define RDSTS 0x1C //Returns diskette device status byte to master
|
||||||
|
|
||||||
/* external globals */
|
/* external globals */
|
||||||
|
|
||||||
extern uint16 port; //port called in dev_table[port]
|
extern uint16 port; //port called in dev_table[port]
|
||||||
extern int32 PCX;
|
extern int32 PCX;
|
||||||
|
|
||||||
/* function prototypes */
|
/* function prototypes */
|
||||||
|
|
||||||
uint8 ioc_cont0(t_bool io, uint8 data); /* ioc_cont*/
|
uint8 ioc_cont0(t_bool io, uint8 data); /* ioc_cont*/
|
||||||
uint8 ioc_cont1(t_bool io, uint8 data); /* ioc_cont*/
|
uint8 ioc_cont1(t_bool io, uint8 data); /* ioc_cont*/
|
||||||
t_stat ioc_cont_reset (DEVICE *dptr, uint16 baseport);
|
t_stat ioc_cont_reset (DEVICE *dptr, uint16 baseport);
|
||||||
|
|
||||||
/* external function prototypes */
|
/* external function prototypes */
|
||||||
|
|
||||||
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16, uint8);
|
extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16, uint8);
|
||||||
extern uint32 saved_PC; /* program counter */
|
extern uint32 saved_PC; /* program counter */
|
||||||
|
|
||||||
/* globals */
|
/* globals */
|
||||||
|
|
||||||
uint8 dbb_stat;
|
uint8 dbb_stat;
|
||||||
uint8 dbb_cmd;
|
uint8 dbb_cmd;
|
||||||
uint8 dbb_in;
|
uint8 dbb_in;
|
||||||
uint8 dbb_out;
|
uint8 dbb_out;
|
||||||
|
|
||||||
UNIT ioc_cont_unit[] = {
|
UNIT ioc_cont_unit[] = {
|
||||||
{ UDATA (0, 0, 0) }, /* ioc_cont*/
|
{ UDATA (0, 0, 0) }, /* ioc_cont*/
|
||||||
};
|
};
|
||||||
|
|
||||||
REG ioc_cont_reg[] = {
|
REG ioc_cont_reg[] = {
|
||||||
{ HRDATA (CONTROL0, ioc_cont_unit[0].u3, 8) }, /* ioc_cont */
|
{ HRDATA (CONTROL0, ioc_cont_unit[0].u3, 8) }, /* ioc_cont */
|
||||||
{ NULL }
|
{ NULL }
|
||||||
};
|
};
|
||||||
|
|
||||||
DEBTAB ioc_cont_debug[] = {
|
DEBTAB ioc_cont_debug[] = {
|
||||||
{ "ALL", DEBUG_all },
|
{ "ALL", DEBUG_all },
|
||||||
{ "FLOW", DEBUG_flow },
|
{ "FLOW", DEBUG_flow },
|
||||||
{ "READ", DEBUG_read },
|
{ "READ", DEBUG_read },
|
||||||
{ "WRITE", DEBUG_write },
|
{ "WRITE", DEBUG_write },
|
||||||
{ "XACK", DEBUG_xack },
|
{ "XACK", DEBUG_xack },
|
||||||
{ "LEV1", DEBUG_level1 },
|
{ "LEV1", DEBUG_level1 },
|
||||||
{ "LEV2", DEBUG_level2 },
|
{ "LEV2", DEBUG_level2 },
|
||||||
{ NULL }
|
{ NULL }
|
||||||
};
|
};
|
||||||
|
|
||||||
/* address width is set to 16 bits to use devices in 8086/8088 implementations */
|
/* address width is set to 16 bits to use devices in 8086/8088 implementations */
|
||||||
|
|
||||||
DEVICE ioc_cont_dev = {
|
DEVICE ioc_cont_dev = {
|
||||||
"IOC-CONT", //name
|
"IOC-CONT", //name
|
||||||
ioc_cont_unit, //units
|
ioc_cont_unit, //units
|
||||||
ioc_cont_reg, //registers
|
ioc_cont_reg, //registers
|
||||||
NULL, //modifiers
|
NULL, //modifiers
|
||||||
1, //numunits
|
1, //numunits
|
||||||
16, //aradix
|
16, //aradix
|
||||||
16, //awidth
|
16, //awidth
|
||||||
1, //aincr
|
1, //aincr
|
||||||
16, //dradix
|
16, //dradix
|
||||||
8, //dwidth
|
8, //dwidth
|
||||||
NULL, //examine
|
NULL, //examine
|
||||||
NULL, //deposit
|
NULL, //deposit
|
||||||
// &ioc_cont_reset, //reset
|
// &ioc_cont_reset, //reset
|
||||||
NULL, //reset
|
NULL, //reset
|
||||||
NULL, //boot
|
NULL, //boot
|
||||||
NULL, //attach
|
NULL, //attach
|
||||||
NULL, //detach
|
NULL, //detach
|
||||||
NULL, //ctxt
|
NULL, //ctxt
|
||||||
0, //flags
|
0, //flags
|
||||||
0, //dctrl
|
0, //dctrl
|
||||||
ioc_cont_debug, //debflags
|
ioc_cont_debug, //debflags
|
||||||
NULL, //msize
|
NULL, //msize
|
||||||
NULL //lname
|
NULL //lname
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Reset routine */
|
/* Reset routine */
|
||||||
|
|
||||||
t_stat ioc_cont_reset(DEVICE *dptr, uint16 baseport)
|
t_stat ioc_cont_reset(DEVICE *dptr, uint16 baseport)
|
||||||
{
|
{
|
||||||
sim_printf(" ioc_cont[%d]: Reset\n", 0);
|
sim_printf(" ioc_cont[%d]: Reset\n", 0);
|
||||||
sim_printf(" ioc_cont[%d]: Registered at %04X\n", 0, baseport);
|
sim_printf(" ioc_cont[%d]: Registered at %04X\n", 0, baseport);
|
||||||
reg_dev(ioc_cont0, baseport, 0);
|
reg_dev(ioc_cont0, baseport, 0);
|
||||||
reg_dev(ioc_cont1, baseport + 1, 0);
|
reg_dev(ioc_cont1, baseport + 1, 0);
|
||||||
dbb_stat = 0x00; /* clear DBB status */
|
dbb_stat = 0x00; /* clear DBB status */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* I/O instruction handlers, called from the CPU module when an
|
/* I/O instruction handlers, called from the CPU module when an
|
||||||
IN or OUT instruction is issued.
|
IN or OUT instruction is issued.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/* IOC control port functions */
|
/* IOC control port functions */
|
||||||
|
|
||||||
uint8 ioc_cont0(t_bool io, uint8 data)
|
uint8 ioc_cont0(t_bool io, uint8 data)
|
||||||
{
|
{
|
||||||
if (io == 0) { /* read data port */
|
if (io == 0) { /* read data port */
|
||||||
if (DEBUG)
|
if (DEBUG)
|
||||||
sim_printf(" ioc_cont0: read data returned %02X PCX=%04X\n", dbb_out, PCX);
|
sim_printf("\n ioc_cont0: read data returned %02X PCX=%04X", dbb_out, PCX);
|
||||||
return dbb_out;
|
return dbb_out;
|
||||||
} else { /* write data port */
|
} else { /* write data port */
|
||||||
dbb_in = data;
|
dbb_in = data;
|
||||||
dbb_stat |= IBF;
|
dbb_stat |= IBF;
|
||||||
if (DEBUG)
|
if (DEBUG)
|
||||||
sim_printf(" ioc_cont0: write data=%02X port=%02X PCX=%04X\n", dbb_in, port, PCX);
|
sim_printf("\n ioc_cont0: write data=%02X port=%02X PCX=%04X", dbb_in, port, PCX);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
uint8 ioc_cont1(t_bool io, uint8 data)
|
uint8 ioc_cont1(t_bool io, uint8 data)
|
||||||
{
|
{
|
||||||
int temp;
|
int temp;
|
||||||
|
|
||||||
if (io == 0) { /* read status port */
|
if (io == 0) { /* read status port */
|
||||||
if ((dbb_stat & F0) && (dbb_stat & IBF)) {
|
if ((dbb_stat & F0) && (dbb_stat & IBF)) {
|
||||||
temp = dbb_stat;
|
temp = dbb_stat;
|
||||||
if (DEBUG)
|
if (DEBUG)
|
||||||
sim_printf(" ioc_cont1: DBB status read 1 data=%02X PCX=%04X\n", dbb_stat, PCX);
|
sim_printf("\n ioc_cont1: DBB status read 1 data=%02X PCX=%04X", dbb_stat, PCX);
|
||||||
dbb_stat &= ~IBF; //reset IBF flag
|
dbb_stat &= ~IBF; //reset IBF flag
|
||||||
return temp;
|
return temp;
|
||||||
}
|
}
|
||||||
if ((dbb_stat & F0) && (dbb_stat & OBF)) {
|
if ((dbb_stat & F0) && (dbb_stat & OBF)) {
|
||||||
temp = dbb_stat;
|
temp = dbb_stat;
|
||||||
if (DEBUG)
|
if (DEBUG)
|
||||||
sim_printf(" ioc_cont1: DBB status read 2 data=%02X PCX=%04X\n", dbb_stat, PCX);
|
sim_printf("\n ioc_cont1: DBB status read 2 data=%02X PCX=%04X", dbb_stat, PCX);
|
||||||
dbb_stat &= ~OBF; //reset OBF flag
|
dbb_stat &= ~OBF; //reset OBF flag
|
||||||
return temp;
|
return temp;
|
||||||
}
|
}
|
||||||
if (dbb_stat & F0) {
|
if (dbb_stat & F0) {
|
||||||
temp = dbb_stat;
|
temp = dbb_stat;
|
||||||
if (DEBUG)
|
if (DEBUG)
|
||||||
sim_printf(" ioc_cont1: DBB status read 3 data=%02X PCX=%04X\n", dbb_stat, PCX);
|
sim_printf("\n ioc_cont1: DBB status read 3 data=%02X PCX=%04X", dbb_stat, PCX);
|
||||||
dbb_stat &= ~F0; //reset F0 flag
|
dbb_stat &= ~F0; //reset F0 flag
|
||||||
return temp;
|
return temp;
|
||||||
}
|
}
|
||||||
// if (DEBUG)
|
// if (DEBUG)
|
||||||
// sim_printf(" ioc_cont1: DBB status read 4 data=%02X PCX=%04X\n", dbb_stat, PCX);
|
// sim_printf(" ioc_cont1: DBB status read 4 data=%02X PCX=%04X\n", dbb_stat, PCX);
|
||||||
return dbb_stat;
|
return dbb_stat;
|
||||||
} else { /* write command port */
|
} else { /* write command port */
|
||||||
dbb_cmd = data;
|
dbb_cmd = data;
|
||||||
switch(dbb_cmd){
|
switch(dbb_cmd){
|
||||||
case PACIFY: //should delay 100 ms
|
case PACIFY: //should delay 100 ms
|
||||||
dbb_stat = 0;
|
dbb_stat = 0;
|
||||||
break;
|
break;
|
||||||
case SYSTAT:
|
case SYSTAT:
|
||||||
dbb_out = 0;
|
dbb_out = 0;
|
||||||
dbb_stat |= OBF;
|
dbb_stat |= OBF;
|
||||||
dbb_stat &= ~CD;
|
dbb_stat &= ~CD;
|
||||||
break;
|
break;
|
||||||
case CRTS:
|
case CRTS:
|
||||||
dbb_out = 0;
|
dbb_out = 0;
|
||||||
dbb_stat |= F0;
|
dbb_stat |= F0;
|
||||||
break;
|
break;
|
||||||
case KSTC:
|
case KSTC:
|
||||||
dbb_out = 0;
|
dbb_out = 0;
|
||||||
dbb_stat |= F0;
|
dbb_stat |= F0;
|
||||||
break;
|
break;
|
||||||
case RDSTS:
|
case RDSTS:
|
||||||
dbb_out = 0x80; //not ready
|
dbb_out = 0x80; //not ready
|
||||||
dbb_stat |= (F0 | IBF);
|
dbb_stat |= (F0 | IBF);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
sim_printf(" ioc_cont1: Unknown command %02X PCX=%04X\n", dbb_cmd, PCX);
|
sim_printf("\n ioc_cont1: Unknown command %02X PCX=%04X", dbb_cmd, PCX);
|
||||||
}
|
}
|
||||||
if (DEBUG)
|
if (DEBUG)
|
||||||
sim_printf(" ioc_cont1: DBB command write data=%02X PCX=%04X\n", dbb_cmd, PCX);
|
sim_printf("\n ioc_cont1: DBB command write data=%02X PCX=%04X", dbb_cmd, PCX);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/* end of ioc-cont.c */
|
/* end of ioc-cont.c */
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,308 +1,307 @@
|
||||||
/* multibus.c: Multibus I simulator
|
/* multibus.c: Multibus I simulator
|
||||||
|
|
||||||
Copyright (c) 2010, William A. Beech
|
Copyright (c) 2010, William A. Beech
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
to deal in the Software without restriction, including without limitation
|
to deal in the Software without restriction, including without limitation
|
||||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
and/or sell copies of the Software, and to permit persons to whom the
|
and/or sell copies of the Software, and to permit persons to whom the
|
||||||
Software is furnished to do so, subject to the following conditions:
|
Software is furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
The above copyright notice and this permission notice shall be included in
|
The above copyright notice and this permission notice shall be included in
|
||||||
all copies or substantial portions of the Software.
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
WILLIAM A. BEECH BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
|
||||||
Except as contained in this notice, the name of William A. Beech shall not be
|
Except as contained in this notice, the name of William A. Beech shall not be
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from William A. Beech.
|
in this Software without prior written authorization from William A. Beech.
|
||||||
|
|
||||||
MODIFICATIONS:
|
MODIFICATIONS:
|
||||||
|
|
||||||
?? ??? 10 - Original file.
|
?? ??? 10 - Original file.
|
||||||
16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
|
16 Dec 12 - Modified to use isbc_80_10.cfg file to set base and size.
|
||||||
24 Apr 15 -- Modified to use simh_debug
|
24 Apr 15 -- Modified to use simh_debug
|
||||||
|
|
||||||
NOTES:
|
NOTES:
|
||||||
|
|
||||||
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
|
This software was written by Bill Beech, Dec 2010, to allow emulation of Multibus
|
||||||
Computer Systems.
|
Computer Systems.
|
||||||
|
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "system_defs.h"
|
#include "system_defs.h"
|
||||||
|
|
||||||
int32 mbirq = 0; /* set no multibus interrupts */
|
int32 mbirq = 0; /* set no multibus interrupts */
|
||||||
|
|
||||||
/* function prototypes */
|
/* function prototypes */
|
||||||
|
|
||||||
t_stat multibus_svc(UNIT *uptr);
|
t_stat multibus_svc(UNIT *uptr);
|
||||||
t_stat multibus_reset(DEVICE *dptr);
|
t_stat multibus_reset(DEVICE *dptr);
|
||||||
void set_irq(int32 int_num);
|
void set_irq(int32 int_num);
|
||||||
void clr_irq(int32 int_num);
|
void clr_irq(int32 int_num);
|
||||||
uint8 nulldev(t_bool io, uint8 data);
|
uint8 nulldev(t_bool io, uint8 data);
|
||||||
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data), uint16 port, uint8 devnum);
|
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data), uint16 port, uint8 devnum);
|
||||||
t_stat multibus_reset (DEVICE *dptr);
|
t_stat multibus_reset (DEVICE *dptr);
|
||||||
uint8 multibus_get_mbyte(uint16 addr);
|
uint8 multibus_get_mbyte(uint16 addr);
|
||||||
void multibus_put_mbyte(uint16 addr, uint8 val);
|
void multibus_put_mbyte(uint16 addr, uint8 val);
|
||||||
|
|
||||||
/* external function prototypes */
|
/* external function prototypes */
|
||||||
|
|
||||||
extern t_stat SBC_reset(DEVICE *dptr); /* reset the iSBC80/10 emulator */
|
extern t_stat SBC_reset(DEVICE *dptr); /* reset the iSBC80/10 emulator */
|
||||||
extern uint8 isbc064_get_mbyte(uint16 addr);
|
extern uint8 isbc064_get_mbyte(uint16 addr);
|
||||||
extern void isbc064_put_mbyte(uint16 addr, uint8 val);
|
extern void isbc064_put_mbyte(uint16 addr, uint8 val);
|
||||||
extern void set_cpuint(int32 int_num);
|
extern void set_cpuint(int32 int_num);
|
||||||
extern t_stat SBC_reset (DEVICE *dptr);
|
extern t_stat SBC_reset (DEVICE *dptr);
|
||||||
extern t_stat isbc064_reset (DEVICE *dptr);
|
extern t_stat isbc064_reset (DEVICE *dptr);
|
||||||
extern t_stat isbc201_reset (DEVICE *dptr, uint16);
|
extern t_stat isbc201_reset (DEVICE *dptr, uint16);
|
||||||
extern t_stat isbc202_reset (DEVICE *dptr, uint16);
|
extern t_stat isbc202_reset (DEVICE *dptr, uint16);
|
||||||
extern t_stat zx200a_reset(DEVICE *dptr, uint16 base);
|
extern t_stat zx200a_reset(DEVICE *dptr, uint16 base);
|
||||||
|
|
||||||
/* external globals */
|
/* external globals */
|
||||||
|
|
||||||
extern uint8 xack; /* XACK signal */
|
extern uint8 xack; /* XACK signal */
|
||||||
extern int32 int_req; /* i8080 INT signal */
|
extern int32 int_req; /* i8080 INT signal */
|
||||||
extern int32 isbc201_fdcnum;
|
extern int32 isbc201_fdcnum;
|
||||||
extern int32 isbc202_fdcnum;
|
extern int32 isbc202_fdcnum;
|
||||||
extern int32 zx200a_fdcnum;
|
extern int32 zx200a_fdcnum;
|
||||||
|
|
||||||
/* multibus Standard SIMH Device Data Structures */
|
/* multibus Standard SIMH Device Data Structures */
|
||||||
|
|
||||||
UNIT multibus_unit = {
|
UNIT multibus_unit = {
|
||||||
UDATA (&multibus_svc, 0, 0), 20
|
UDATA (&multibus_svc, 0, 0), 20
|
||||||
};
|
};
|
||||||
|
|
||||||
REG multibus_reg[] = {
|
REG multibus_reg[] = {
|
||||||
{ HRDATA (MBIRQ, mbirq, 32) },
|
{ HRDATA (MBIRQ, mbirq, 32) },
|
||||||
{ HRDATA (XACK, xack, 8) }
|
{ HRDATA (XACK, xack, 8) }
|
||||||
};
|
};
|
||||||
|
|
||||||
DEBTAB multibus_debug[] = {
|
DEBTAB multibus_debug[] = {
|
||||||
{ "ALL", DEBUG_all },
|
{ "ALL", DEBUG_all },
|
||||||
{ "FLOW", DEBUG_flow },
|
{ "FLOW", DEBUG_flow },
|
||||||
{ "READ", DEBUG_read },
|
{ "READ", DEBUG_read },
|
||||||
{ "WRITE", DEBUG_write },
|
{ "WRITE", DEBUG_write },
|
||||||
{ "LEV1", DEBUG_level1 },
|
{ "LEV1", DEBUG_level1 },
|
||||||
{ "LEV2", DEBUG_level2 },
|
{ "LEV2", DEBUG_level2 },
|
||||||
{ NULL }
|
{ NULL }
|
||||||
};
|
};
|
||||||
|
|
||||||
DEVICE multibus_dev = {
|
DEVICE multibus_dev = {
|
||||||
"MBIRQ", //name
|
"MBIRQ", //name
|
||||||
&multibus_unit, //units
|
&multibus_unit, //units
|
||||||
multibus_reg, //registers
|
multibus_reg, //registers
|
||||||
NULL, //modifiers
|
NULL, //modifiers
|
||||||
1, //numunits
|
1, //numunits
|
||||||
16, //aradix
|
16, //aradix
|
||||||
16, //awidth
|
16, //awidth
|
||||||
1, //aincr
|
1, //aincr
|
||||||
16, //dradix
|
16, //dradix
|
||||||
8, //dwidth
|
8, //dwidth
|
||||||
NULL, //examine
|
NULL, //examine
|
||||||
NULL, //deposit
|
NULL, //deposit
|
||||||
&multibus_reset, //reset
|
&multibus_reset, //reset
|
||||||
NULL, //boot
|
NULL, //boot
|
||||||
NULL, //attach
|
NULL, //attach
|
||||||
NULL, //detach
|
NULL, //detach
|
||||||
NULL, //ctxt
|
NULL, //ctxt
|
||||||
DEV_DEBUG, //flags
|
DEV_DEBUG, //flags
|
||||||
0, //dctrl
|
0, //dctrl
|
||||||
multibus_debug, //debflags
|
multibus_debug, //debflags
|
||||||
NULL, //msize
|
NULL, //msize
|
||||||
NULL //lname
|
NULL //lname
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Service routines to handle simulator functions */
|
/* Service routines to handle simulator functions */
|
||||||
|
|
||||||
/* service routine - actually does the simulated interrupts */
|
/* service routine - actually does the simulated interrupts */
|
||||||
|
|
||||||
t_stat multibus_svc(UNIT *uptr)
|
t_stat multibus_svc(UNIT *uptr)
|
||||||
{
|
{
|
||||||
switch (mbirq) {
|
switch (mbirq) {
|
||||||
case INT_1:
|
case INT_1:
|
||||||
set_cpuint(INT_R);
|
set_cpuint(INT_R);
|
||||||
clr_irq(SBC202_INT); /***** bad, bad, bad! */
|
clr_irq(SBC202_INT); /***** bad, bad, bad! */
|
||||||
// sim_printf("multibus_svc: mbirq=%04X int_req=%04X\n", mbirq, int_req);
|
// sim_printf("multibus_svc: mbirq=%04X int_req=%04X\n", mbirq, int_req);
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
// sim_printf("multibus_svc: default mbirq=%04X\n", mbirq);
|
// sim_printf("multibus_svc: default mbirq=%04X\n", mbirq);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
sim_activate (&multibus_unit, multibus_unit.wait); /* continue poll */
|
sim_activate (&multibus_unit, multibus_unit.wait); /* continue poll */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Reset routine */
|
/* Reset routine */
|
||||||
|
|
||||||
t_stat multibus_reset(DEVICE *dptr)
|
t_stat multibus_reset(DEVICE *dptr)
|
||||||
{
|
{
|
||||||
SBC_reset(NULL);
|
SBC_reset(NULL);
|
||||||
sim_printf("Initializing The Multibus\n Multibus Boards:\n");
|
sim_printf("Initializing The Multibus\n Multibus Boards:\n");
|
||||||
isbc064_reset(NULL);
|
isbc064_reset(NULL);
|
||||||
isbc201_fdcnum = 0;
|
isbc201_fdcnum = 0;
|
||||||
isbc201_reset(NULL, SBC201_BASE);
|
isbc201_reset(NULL, SBC201_BASE);
|
||||||
isbc202_fdcnum = 0;
|
isbc202_fdcnum = 0;
|
||||||
isbc202_reset(NULL, SBC202_BASE);
|
isbc202_reset(NULL, SBC202_BASE);
|
||||||
zx200a_fdcnum = 0;
|
zx200a_fdcnum = 0;
|
||||||
zx200a_reset(NULL, ZX200A_BASE_DD);
|
zx200a_reset(NULL, ZX200A_BASE);
|
||||||
zx200a_reset(NULL, ZX200A_BASE_SD);
|
sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */
|
||||||
sim_activate (&multibus_unit, multibus_unit.wait); /* activate unit */
|
return SCPE_OK;
|
||||||
return SCPE_OK;
|
}
|
||||||
}
|
|
||||||
|
void set_irq(int32 int_num)
|
||||||
void set_irq(int32 int_num)
|
{
|
||||||
{
|
mbirq |= int_num;
|
||||||
mbirq |= int_num;
|
// sim_printf("set_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
|
||||||
// sim_printf("set_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
|
}
|
||||||
}
|
|
||||||
|
void clr_irq(int32 int_num)
|
||||||
void clr_irq(int32 int_num)
|
{
|
||||||
{
|
mbirq &= ~int_num;
|
||||||
mbirq &= ~int_num;
|
// sim_printf("clr_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
|
||||||
// sim_printf("clr_irq: int_num=%04X mbirq=%04X\n", int_num, mbirq);
|
}
|
||||||
}
|
|
||||||
|
/* This is the I/O configuration table. There are 256 possible
|
||||||
/* This is the I/O configuration table. There are 256 possible
|
device addresses, if a device is plugged to a port it's routine
|
||||||
device addresses, if a device is plugged to a port it's routine
|
address is here, 'nulldev' means no device has been registered.
|
||||||
address is here, 'nulldev' means no device has been registered.
|
*/
|
||||||
*/
|
struct idev {
|
||||||
struct idev {
|
uint8 (*routine)(t_bool io, uint8 data);
|
||||||
uint8 (*routine)(t_bool io, uint8 data);
|
uint16 port;
|
||||||
uint16 port;
|
uint8 devnum;
|
||||||
uint8 devnum;
|
};
|
||||||
};
|
|
||||||
|
struct idev dev_table[256] = {
|
||||||
struct idev dev_table[256] = {
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 000H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 000H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 004H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 004H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 008H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 008H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 00CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 00CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 010H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 010H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 014H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 014H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 018H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 018H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 01CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 01CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 020H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 020H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 024H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 024H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 028H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 028H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 02CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 02CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 030H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 030H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 034H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 034H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 038H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 038H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 03CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 03CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 040H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 040H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 044H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 044H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 048H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 048H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 050H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 050H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 054H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 054H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 058H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 058H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 05CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 05CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 060H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 060H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 064H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 064H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 068H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 068H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 06CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 06CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 070H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 070H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 074H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 074H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 078H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 078H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 07CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 07CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 080H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 080H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 084H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 084H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 088H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 088H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 08CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 08CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 090H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 090H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 094H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 094H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 098H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 098H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 09CH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 09CH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A4H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A4H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A8H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A8H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0A0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B4H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B4H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B8H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B8H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0B0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C4H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C4H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C8H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C8H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0CCH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0CCH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D4H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D4H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D8H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0D8H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0DCH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0DCH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E4H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E4H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E8H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0E8H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0ECH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0ECH */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F0H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F0H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F4H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F4H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F8H */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0F8H */
|
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev} /* 0FCH */
|
||||||
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev} /* 0FCH */
|
};
|
||||||
};
|
|
||||||
|
//uint8 nulldev(t_bool flag, uint8 data, uint8 devnum)
|
||||||
//uint8 nulldev(t_bool flag, uint8 data, uint8 devnum)
|
uint8 nulldev(t_bool flag, uint8 data)
|
||||||
uint8 nulldev(t_bool flag, uint8 data)
|
{
|
||||||
{
|
SET_XACK(0); /* set no XACK */
|
||||||
SET_XACK(0); /* set no XACK */
|
return 0xFF;
|
||||||
return 0xFF;
|
}
|
||||||
}
|
|
||||||
|
//uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint16 port, uint8 devnum)
|
||||||
//uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data, uint8 devnum), uint16 port, uint8 devnum)
|
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data), uint16 port, uint8 devnum)
|
||||||
uint8 reg_dev(uint8 (*routine)(t_bool io, uint8 data), uint16 port, uint8 devnum)
|
{
|
||||||
{
|
if (dev_table[port].routine != &nulldev) { /* port already assigned */
|
||||||
if (dev_table[port].routine != &nulldev) { /* port already assigned */
|
if (dev_table[port].routine != routine)
|
||||||
if (dev_table[port].routine != routine)
|
sim_printf(" I/O Port %04X is already assigned\n", port);
|
||||||
sim_printf(" I/O Port %04X is already assigned\n", port);
|
} else {
|
||||||
} else {
|
sim_printf(" Port %04X is assigned to dev %04X\n", port, devnum);
|
||||||
sim_printf(" Port %04X is assigned to dev %04X\n", port, devnum);
|
dev_table[port].routine = routine;
|
||||||
dev_table[port].routine = routine;
|
dev_table[port].devnum = devnum;
|
||||||
dev_table[port].devnum = devnum;
|
}
|
||||||
}
|
return 0;
|
||||||
return 0;
|
}
|
||||||
}
|
|
||||||
|
/* get a byte from memory */
|
||||||
/* get a byte from memory */
|
|
||||||
|
uint8 multibus_get_mbyte(uint16 addr)
|
||||||
uint8 multibus_get_mbyte(uint16 addr)
|
{
|
||||||
{
|
SET_XACK(0); /* set no XACK */
|
||||||
SET_XACK(0); /* set no XACK */
|
// sim_printf("multibus_get_mbyte: Cleared XACK for %04X\n", addr);
|
||||||
// sim_printf("multibus_get_mbyte: Cleared XACK for %04X\n", addr);
|
return isbc064_get_mbyte(addr);
|
||||||
return isbc064_get_mbyte(addr);
|
}
|
||||||
}
|
|
||||||
|
/* get a word from memory */
|
||||||
/* get a word from memory */
|
|
||||||
|
uint16 multibus_get_mword(uint16 addr)
|
||||||
uint16 multibus_get_mword(uint16 addr)
|
{
|
||||||
{
|
uint16 val;
|
||||||
uint16 val;
|
|
||||||
|
val = multibus_get_mbyte(addr);
|
||||||
val = multibus_get_mbyte(addr);
|
val |= (multibus_get_mbyte(addr+1) << 8);
|
||||||
val |= (multibus_get_mbyte(addr+1) << 8);
|
return val;
|
||||||
return val;
|
}
|
||||||
}
|
|
||||||
|
/* put a byte to memory */
|
||||||
/* put a byte to memory */
|
|
||||||
|
void multibus_put_mbyte(uint16 addr, uint8 val)
|
||||||
void multibus_put_mbyte(uint16 addr, uint8 val)
|
{
|
||||||
{
|
SET_XACK(0); /* set no XACK */
|
||||||
SET_XACK(0); /* set no XACK */
|
// sim_printf("multibus_put_mbyte: Cleared XACK for %04X\n", addr);
|
||||||
// sim_printf("multibus_put_mbyte: Cleared XACK for %04X\n", addr);
|
isbc064_put_mbyte(addr, val);
|
||||||
isbc064_put_mbyte(addr, val);
|
// sim_printf("multibus_put_mbyte: Done XACK=%dX\n", XACK);
|
||||||
// sim_printf("multibus_put_mbyte: Done XACK=%dX\n", XACK);
|
}
|
||||||
}
|
|
||||||
|
/* put a word to memory */
|
||||||
/* put a word to memory */
|
|
||||||
|
void multibus_put_mword(uint16 addr, uint16 val)
|
||||||
void multibus_put_mword(uint16 addr, uint16 val)
|
{
|
||||||
{
|
multibus_put_mbyte(addr, val & 0xff);
|
||||||
multibus_put_mbyte(addr, val & 0xff);
|
multibus_put_mbyte(addr+1, val >> 8);
|
||||||
multibus_put_mbyte(addr+1, val >> 8);
|
}
|
||||||
}
|
|
||||||
|
/* end of multibus.c */
|
||||||
/* end of multibus.c */
|
|
||||||
|
|
||||||
|
|
|
||||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,130 +1,130 @@
|
||||||
/* system_defs.h: Intel iSBC simulator definitions
|
/* system_defs.h: Intel iSBC simulator definitions
|
||||||
|
|
||||||
Copyright (c) 2010, William A. Beech
|
Copyright (c) 2010, William A. Beech
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
to deal in the Software without restriction, including without limitation
|
to deal in the Software without restriction, including without limitation
|
||||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
and/or sell copies of the Software, and to permit persons to whom the
|
and/or sell copies of the Software, and to permit persons to whom the
|
||||||
Software is furnished to do so, subject to the following conditions:
|
Software is furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
The above copyright notice and this permission notice shall be included in
|
The above copyright notice and this permission notice shall be included in
|
||||||
all copies or substantial portions of the Software.
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
|
||||||
Except as contained in this notice, the name of William A. Beech shall not be
|
Except as contained in this notice, the name of William A. Beech shall not be
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from William A. Beech.
|
in this Software without prior written authorization from William A. Beech.
|
||||||
|
|
||||||
?? ??? 10 - Original file.
|
?? ??? 10 - Original file.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <ctype.h>
|
#include <ctype.h>
|
||||||
#include "sim_defs.h" /* simulator defns */
|
#include "sim_defs.h" /* simulator defns */
|
||||||
|
|
||||||
#define SET_XACK(VAL) (xack = VAL)
|
#define SET_XACK(VAL) (xack = VAL)
|
||||||
|
|
||||||
//chip definitions for the iSBC-80/10
|
//chip definitions for the iSBC-80/10
|
||||||
/* set the base I/O address and device count for the 8251s */
|
/* set the base I/O address and device count for the 8251s */
|
||||||
#define I8251_BASE 0xEC
|
#define I8251_BASE 0xEC
|
||||||
#define I8251_NUM 1
|
#define I8251_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address and device count for the 8255s */
|
/* set the base I/O address and device count for the 8255s */
|
||||||
#define I8255_BASE_0 0xE4
|
#define I8255_BASE_0 0xE4
|
||||||
#define I8255_BASE_1 0xE8
|
#define I8255_BASE_1 0xE8
|
||||||
#define I8255_NUM 2
|
#define I8255_NUM 2
|
||||||
|
|
||||||
/* set the base and size for the EPROM on the iSBC 80/10 */
|
/* set the base and size for the EPROM on the iSBC 80/10 */
|
||||||
#define ROM_BASE 0x0000
|
#define ROM_BASE 0x0000
|
||||||
#define ROM_SIZE 0x1000
|
#define ROM_SIZE 0x1000
|
||||||
#define ROM_DISABLE 1
|
#define ROM_DISABLE 1
|
||||||
|
|
||||||
/* set the base and size for the RAM on the iSBC 80/10 */
|
/* set the base and size for the RAM on the iSBC 80/10 */
|
||||||
#define RAM_BASE 0x3C00
|
#define RAM_BASE 0x3C00
|
||||||
#define RAM_SIZE 0x0400
|
#define RAM_SIZE 0x0400
|
||||||
#define RAM_DISABLE 1
|
#define RAM_DISABLE 1
|
||||||
|
|
||||||
/* set INTR for CPU on the iSBC 80/10 */
|
/* set INTR for CPU on the iSBC 80/10 */
|
||||||
#define INTR INT_1
|
#define INTR INT_1
|
||||||
|
|
||||||
//board definitions for the multibus
|
//board definitions for the multibus
|
||||||
/* set the base I/O address for the iSBC 201 */
|
/* set the base I/O address for the iSBC 201 */
|
||||||
#define SBC201_BASE 0x78
|
#define SBC201_BASE 0x88
|
||||||
#define SBC201_INT INT_1
|
#define SBC201_INT INT_1
|
||||||
#define SBC201_NUM 0
|
#define SBC201_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 202 */
|
/* set the base I/O address for the iSBC 202 */
|
||||||
#define SBC202_BASE 0x78
|
#define SBC202_BASE 0x78
|
||||||
#define SBC202_INT INT_1
|
#define SBC202_INT INT_1
|
||||||
#define SBC202_NUM 1
|
#define SBC202_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 208 */
|
/* set the base I/O address for the iSBC 208 */
|
||||||
#define SBC208_BASE 0x40
|
#define SBC208_BASE 0x40
|
||||||
#define SBC208_INT INT_1
|
#define SBC208_INT INT_1
|
||||||
#define SBC208_NUM 0
|
#define SBC208_NUM 0
|
||||||
|
|
||||||
/* set the base for the zx-200a disk controller */
|
/* set the base for the zx-200a disk controller */
|
||||||
#define ZX200A_BASE_DD 0x78
|
#define ZX200A_BASE 0x78
|
||||||
#define ZX200A_BASE_SD 0x88
|
#define ZX200A_INT INT_1
|
||||||
#define ZX200A_NUM 0
|
#define ZX200A_NUM 0
|
||||||
|
|
||||||
/* set the base and size for the iSBC 064 */
|
/* set the base and size for the iSBC 064 */
|
||||||
#define SBC064_BASE 0x0000
|
#define SBC064_BASE 0x0000
|
||||||
#define SBC064_SIZE 0x10000
|
#define SBC064_SIZE 0x10000
|
||||||
#define SBC064_NUM 1
|
#define SBC064_NUM 1
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
||||||
#define INT_0 0x01
|
#define INT_0 0x01
|
||||||
#define INT_1 0x02
|
#define INT_1 0x02
|
||||||
#define INT_2 0x04
|
#define INT_2 0x04
|
||||||
#define INT_3 0x08
|
#define INT_3 0x08
|
||||||
#define INT_4 0x10
|
#define INT_4 0x10
|
||||||
#define INT_5 0x20
|
#define INT_5 0x20
|
||||||
#define INT_6 0x40
|
#define INT_6 0x40
|
||||||
#define INT_7 0x80
|
#define INT_7 0x80
|
||||||
|
|
||||||
/* CPU interrupts definitions */
|
/* CPU interrupts definitions */
|
||||||
|
|
||||||
#define INT_R 0x200
|
#define INT_R 0x200
|
||||||
#define I75 0x40
|
#define I75 0x40
|
||||||
#define I65 0x20
|
#define I65 0x20
|
||||||
#define I55 0x10
|
#define I55 0x10
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
#define DEBUG_flow 0x0001
|
#define DEBUG_flow 0x0001
|
||||||
#define DEBUG_read 0x0002
|
#define DEBUG_read 0x0002
|
||||||
#define DEBUG_write 0x0004
|
#define DEBUG_write 0x0004
|
||||||
#define DEBUG_level1 0x0008
|
#define DEBUG_level1 0x0008
|
||||||
#define DEBUG_level2 0x0010
|
#define DEBUG_level2 0x0010
|
||||||
#define DEBUG_reg 0x0020
|
#define DEBUG_reg 0x0020
|
||||||
#define DEBUG_asm 0x0040
|
#define DEBUG_asm 0x0040
|
||||||
#define DEBUG_xack 0x0080
|
#define DEBUG_xack 0x0080
|
||||||
#define DEBUG_all 0xFFFF
|
#define DEBUG_all 0xFFFF
|
||||||
|
|
||||||
/* Simulator stop codes */
|
/* Simulator stop codes */
|
||||||
|
|
||||||
#define STOP_RSRV 1 /* must be 1 */
|
#define STOP_RSRV 1 /* must be 1 */
|
||||||
#define STOP_HALT 2 /* HALT */
|
#define STOP_HALT 2 /* HALT */
|
||||||
#define STOP_IBKPT 3 /* breakpoint */
|
#define STOP_IBKPT 3 /* breakpoint */
|
||||||
#define STOP_OPCODE 4 /* Invalid Opcode */
|
#define STOP_OPCODE 4 /* Invalid Opcode */
|
||||||
#define STOP_IO 5 /* I/O error */
|
#define STOP_IO 5 /* I/O error */
|
||||||
#define STOP_MEM 6 /* Memory error */
|
#define STOP_MEM 6 /* Memory error */
|
||||||
#define STOP_XACK 7 /* XACK error */
|
#define STOP_XACK 7 /* XACK error */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,134 +1,134 @@
|
||||||
/* system_defs.h: Intel iSBC simulator definitions
|
/* system_defs.h: Intel iSBC simulator definitions
|
||||||
|
|
||||||
Copyright (c) 2010, William A. Beech
|
Copyright (c) 2010, William A. Beech
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
to deal in the Software without restriction, including without limitation
|
to deal in the Software without restriction, including without limitation
|
||||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
and/or sell copies of the Software, and to permit persons to whom the
|
and/or sell copies of the Software, and to permit persons to whom the
|
||||||
Software is furnished to do so, subject to the following conditions:
|
Software is furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
The above copyright notice and this permission notice shall be included in
|
The above copyright notice and this permission notice shall be included in
|
||||||
all copies or substantial portions of the Software.
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
|
||||||
Except as contained in this notice, the name of William A. Beech shall not be
|
Except as contained in this notice, the name of William A. Beech shall not be
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from William A. Beech.
|
in this Software without prior written authorization from William A. Beech.
|
||||||
|
|
||||||
?? ??? 10 - Original file.
|
?? ??? 10 - Original file.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <ctype.h>
|
#include <ctype.h>
|
||||||
#include "sim_defs.h" /* simulator defns */
|
#include "sim_defs.h" /* simulator defns */
|
||||||
|
|
||||||
#define SET_XACK(VAL) (xack = VAL)
|
#define SET_XACK(VAL) (xack = VAL)
|
||||||
|
|
||||||
//chip definitions for the iSBC-80/20
|
//chip definitions for the iSBC-80/20
|
||||||
/* set the base I/O address for the 8251 */
|
/* set the base I/O address for the 8251 */
|
||||||
#define I8251_BASE 0xEC
|
#define I8251_BASE 0xEC
|
||||||
#define I8251_NUM 1
|
#define I8251_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address for the 8255 */
|
/* set the base I/O address for the 8255 */
|
||||||
#define I8255_BASE_0 0xE4
|
#define I8255_BASE_0 0xE4
|
||||||
#define I8255_BASE_1 0xE8
|
#define I8255_BASE_1 0xE8
|
||||||
#define I8255_NUM 2
|
#define I8255_NUM 2
|
||||||
|
|
||||||
/* set the base I/O address for the 8259 */
|
/* set the base I/O address for the 8259 */
|
||||||
#define I8259_BASE 0xD8
|
#define I8259_BASE 0xD8
|
||||||
#define I8259_NUM 1
|
#define I8259_NUM 1
|
||||||
|
|
||||||
/* set the base and size for the EPROM on the iSBC 80/20 */
|
/* set the base and size for the EPROM on the iSBC 80/20 */
|
||||||
#define ROM_BASE 0x0000
|
#define ROM_BASE 0x0000
|
||||||
#define ROM_SIZE 0x1000
|
#define ROM_SIZE 0x1000
|
||||||
#define ROM_DISABLE 1
|
#define ROM_DISABLE 1
|
||||||
|
|
||||||
/* set the base and size for the RAM on the iSBC 80/20 */
|
/* set the base and size for the RAM on the iSBC 80/20 */
|
||||||
#define RAM_BASE 0x3C00
|
#define RAM_BASE 0x3C00
|
||||||
#define RAM_SIZE 0x0400
|
#define RAM_SIZE 0x0400
|
||||||
#define RAM_DISABLE 1
|
#define RAM_DISABLE 1
|
||||||
|
|
||||||
/* set INTR for CPU */
|
/* set INTR for CPU */
|
||||||
#define INTR INT_1
|
#define INTR INT_1
|
||||||
|
|
||||||
//board definitions for the multibus
|
//board definitions for the multibus
|
||||||
/* set the base I/O address for the iSBC 201 */
|
/* set the base I/O address for the iSBC 201 */
|
||||||
#define SBC201_BASE 0x78
|
#define SBC201_BASE 0x78
|
||||||
#define SBC201_INT INT_1
|
#define SBC201_INT INT_1
|
||||||
#define SBC201_NUM 0
|
#define SBC201_NUM 0
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 202 */
|
/* set the base I/O address for the iSBC 202 */
|
||||||
#define SBC202_BASE 0x78
|
#define SBC202_BASE 0x78
|
||||||
#define SBC202_INT INT_1
|
#define SBC202_INT INT_1
|
||||||
#define SBC202_NUM 1
|
#define SBC202_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 208 */
|
/* set the base I/O address for the iSBC 208 */
|
||||||
#define SBC208_BASE 0x40
|
#define SBC208_BASE 0x40
|
||||||
#define SBC208_INT INT_1
|
#define SBC208_INT INT_1
|
||||||
#define SBC208_NUM 0
|
#define SBC208_NUM 0
|
||||||
|
|
||||||
/* set the base for the zx-200a disk controller */
|
/* set the base for the zx-200a disk controller */
|
||||||
#define ZX200A_BASE_DD 0x78
|
#define ZX200A_BASE 0x78
|
||||||
#define ZX200A_BASE_SD 0x88
|
#define ZX200A_INT INT_1
|
||||||
#define ZX200A_NUM 0
|
#define ZX200A_NUM 0
|
||||||
|
|
||||||
/* set the base and size for the iSBC 064 */
|
/* set the base and size for the iSBC 064 */
|
||||||
#define SBC064_BASE 0x0000
|
#define SBC064_BASE 0x0000
|
||||||
#define SBC064_SIZE 0x10000
|
#define SBC064_SIZE 0x10000
|
||||||
#define SBC064_NUM 1
|
#define SBC064_NUM 1
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
||||||
#define INT_0 0x01
|
#define INT_0 0x01
|
||||||
#define INT_1 0x02
|
#define INT_1 0x02
|
||||||
#define INT_2 0x04
|
#define INT_2 0x04
|
||||||
#define INT_3 0x08
|
#define INT_3 0x08
|
||||||
#define INT_4 0x10
|
#define INT_4 0x10
|
||||||
#define INT_5 0x20
|
#define INT_5 0x20
|
||||||
#define INT_6 0x40
|
#define INT_6 0x40
|
||||||
#define INT_7 0x80
|
#define INT_7 0x80
|
||||||
|
|
||||||
/* CPU interrupts definitions */
|
/* CPU interrupts definitions */
|
||||||
|
|
||||||
#define INT_R 0x200
|
#define INT_R 0x200
|
||||||
#define I75 0x40
|
#define I75 0x40
|
||||||
#define I65 0x20
|
#define I65 0x20
|
||||||
#define I55 0x10
|
#define I55 0x10
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
#define DEBUG_flow 0x0001
|
#define DEBUG_flow 0x0001
|
||||||
#define DEBUG_read 0x0002
|
#define DEBUG_read 0x0002
|
||||||
#define DEBUG_write 0x0004
|
#define DEBUG_write 0x0004
|
||||||
#define DEBUG_level1 0x0008
|
#define DEBUG_level1 0x0008
|
||||||
#define DEBUG_level2 0x0010
|
#define DEBUG_level2 0x0010
|
||||||
#define DEBUG_reg 0x0020
|
#define DEBUG_reg 0x0020
|
||||||
#define DEBUG_asm 0x0040
|
#define DEBUG_asm 0x0040
|
||||||
#define DEBUG_xack 0x0080
|
#define DEBUG_xack 0x0080
|
||||||
#define DEBUG_all 0xFFFF
|
#define DEBUG_all 0xFFFF
|
||||||
|
|
||||||
/* Simulator stop codes */
|
/* Simulator stop codes */
|
||||||
|
|
||||||
#define STOP_RSRV 1 /* must be 1 */
|
#define STOP_RSRV 1 /* must be 1 */
|
||||||
#define STOP_HALT 2 /* HALT */
|
#define STOP_HALT 2 /* HALT */
|
||||||
#define STOP_IBKPT 3 /* breakpoint */
|
#define STOP_IBKPT 3 /* breakpoint */
|
||||||
#define STOP_OPCODE 4 /* Invalid Opcode */
|
#define STOP_OPCODE 4 /* Invalid Opcode */
|
||||||
#define STOP_IO 5 /* I/O error */
|
#define STOP_IO 5 /* I/O error */
|
||||||
#define STOP_MEM 6 /* Memory error */
|
#define STOP_MEM 6 /* Memory error */
|
||||||
#define STOP_XACK 7 /* XACK error */
|
#define STOP_XACK 7 /* XACK error */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,138 +1,138 @@
|
||||||
/* system_defs.h: Intel iSBC simulator definitions
|
/* system_defs.h: Intel iSBC simulator definitions
|
||||||
|
|
||||||
Copyright (c) 2010, William A. Beech
|
Copyright (c) 2010, William A. Beech
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
to deal in the Software without restriction, including without limitation
|
to deal in the Software without restriction, including without limitation
|
||||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
and/or sell copies of the Software, and to permit persons to whom the
|
and/or sell copies of the Software, and to permit persons to whom the
|
||||||
Software is furnished to do so, subject to the following conditions:
|
Software is furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
The above copyright notice and this permission notice shall be included in
|
The above copyright notice and this permission notice shall be included in
|
||||||
all copies or substantial portions of the Software.
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
|
||||||
Except as contained in this notice, the name of William A. Beech shall not be
|
Except as contained in this notice, the name of William A. Beech shall not be
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from William A. Beech.
|
in this Software without prior written authorization from William A. Beech.
|
||||||
|
|
||||||
?? ??? 10 - Original file.
|
?? ??? 10 - Original file.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <ctype.h>
|
#include <ctype.h>
|
||||||
#include "sim_defs.h" /* simulator defns */
|
#include "sim_defs.h" /* simulator defns */
|
||||||
|
|
||||||
#define SET_XACK(VAL) (xack = VAL)
|
#define SET_XACK(VAL) (xack = VAL)
|
||||||
|
|
||||||
//chip definitions for the iSBC-80/10
|
//chip definitions for the iSBC-80/10
|
||||||
/* set the base I/O address and device count for the 8251s */
|
/* set the base I/O address and device count for the 8251s */
|
||||||
#define I8251_BASE 0xEC
|
#define I8251_BASE 0xEC
|
||||||
#define I8251_NUM 1
|
#define I8251_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address for the 8253/8254 */
|
/* set the base I/O address for the 8253/8254 */
|
||||||
#define I8253_BASE 0xDC
|
#define I8253_BASE 0xDC
|
||||||
#define I8253_NUM 1
|
#define I8253_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address and device count for the 8255s */
|
/* set the base I/O address and device count for the 8255s */
|
||||||
#define I8255_BASE_0 0xE4
|
#define I8255_BASE_0 0xE4
|
||||||
#define I8255_BASE_1 0xE8
|
#define I8255_BASE_1 0xE8
|
||||||
#define I8255_NUM 2
|
#define I8255_NUM 2
|
||||||
|
|
||||||
/* set the base I/O address for the 8259 */
|
/* set the base I/O address for the 8259 */
|
||||||
#define I8259_BASE 0xDA
|
#define I8259_BASE 0xDA
|
||||||
#define I8259_NUM 1
|
#define I8259_NUM 1
|
||||||
|
|
||||||
/* set the base and size for the EPROM on the iSBC 80/10 */
|
/* set the base and size for the EPROM on the iSBC 80/10 */
|
||||||
#define ROM_BASE 0x0000
|
#define ROM_BASE 0x0000
|
||||||
#define ROM_SIZE 0x1000
|
#define ROM_SIZE 0x1000
|
||||||
#define ROM_DISABLE 1
|
#define ROM_DISABLE 1
|
||||||
|
|
||||||
/* set the base and size for the RAM on the iSBC 80/10 */
|
/* set the base and size for the RAM on the iSBC 80/10 */
|
||||||
#define RAM_BASE 0xF000
|
#define RAM_BASE 0xF000
|
||||||
#define RAM_SIZE 0x1000
|
#define RAM_SIZE 0x1000
|
||||||
#define RAM_DISABLE 0
|
#define RAM_DISABLE 0
|
||||||
|
|
||||||
/* set INTR for CPU on the iSBC 80/10 */
|
/* set INTR for CPU on the iSBC 80/10 */
|
||||||
#define INTR INT_1
|
#define INTR INT_1
|
||||||
|
|
||||||
//board definitions for the multibus
|
//board definitions for the multibus
|
||||||
/* set the base I/O address for the iSBC 201 */
|
/* set the base I/O address for the iSBC 201 */
|
||||||
#define SBC201_BASE 0x78
|
#define SBC201_BASE 0x78
|
||||||
#define SBC201_INT INT_1
|
#define SBC201_INT INT_1
|
||||||
#define SBC201_NUM 0
|
#define SBC201_NUM 0
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 202 */
|
/* set the base I/O address for the iSBC 202 */
|
||||||
#define SBC202_BASE 0x78
|
#define SBC202_BASE 0x78
|
||||||
#define SBC202_INT INT_1
|
#define SBC202_INT INT_1
|
||||||
#define SBC202_NUM 1
|
#define SBC202_NUM 1
|
||||||
|
|
||||||
/* set the base for the zx-200a disk controller */
|
/* set the base for the zx-200a disk controller */
|
||||||
#define ZX200A_BASE_DD 0x78
|
#define ZX200A_BASE 0x78
|
||||||
#define ZX200A_BASE_SD 0x88
|
#define ZX200A_INT INT_1
|
||||||
#define ZX200A_NUM 0
|
#define ZX200A_NUM 0
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 208 */
|
/* set the base I/O address for the iSBC 208 */
|
||||||
#define SBC208_BASE 0x40
|
#define SBC208_BASE 0x40
|
||||||
#define SBC208_INT INT_1
|
#define SBC208_INT INT_1
|
||||||
#define SBC208_NUM 0
|
#define SBC208_NUM 0
|
||||||
|
|
||||||
/* set the base and size for the iSBC 064 */
|
/* set the base and size for the iSBC 064 */
|
||||||
#define SBC064_BASE 0x0000
|
#define SBC064_BASE 0x0000
|
||||||
#define SBC064_SIZE 0x10000
|
#define SBC064_SIZE 0x10000
|
||||||
#define SBC064_NUM 1
|
#define SBC064_NUM 1
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
||||||
#define INT_0 0x01
|
#define INT_0 0x01
|
||||||
#define INT_1 0x02
|
#define INT_1 0x02
|
||||||
#define INT_2 0x04
|
#define INT_2 0x04
|
||||||
#define INT_3 0x08
|
#define INT_3 0x08
|
||||||
#define INT_4 0x10
|
#define INT_4 0x10
|
||||||
#define INT_5 0x20
|
#define INT_5 0x20
|
||||||
#define INT_6 0x40
|
#define INT_6 0x40
|
||||||
#define INT_7 0x80
|
#define INT_7 0x80
|
||||||
|
|
||||||
/* CPU interrupts definitions */
|
/* CPU interrupts definitions */
|
||||||
|
|
||||||
#define INT_R 0x200
|
#define INT_R 0x200
|
||||||
#define I75 0x40
|
#define I75 0x40
|
||||||
#define I65 0x20
|
#define I65 0x20
|
||||||
#define I55 0x10
|
#define I55 0x10
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
#define DEBUG_flow 0x0001
|
#define DEBUG_flow 0x0001
|
||||||
#define DEBUG_read 0x0002
|
#define DEBUG_read 0x0002
|
||||||
#define DEBUG_write 0x0004
|
#define DEBUG_write 0x0004
|
||||||
#define DEBUG_level1 0x0008
|
#define DEBUG_level1 0x0008
|
||||||
#define DEBUG_level2 0x0010
|
#define DEBUG_level2 0x0010
|
||||||
#define DEBUG_reg 0x0020
|
#define DEBUG_reg 0x0020
|
||||||
#define DEBUG_asm 0x0040
|
#define DEBUG_asm 0x0040
|
||||||
#define DEBUG_xack 0x0080
|
#define DEBUG_xack 0x0080
|
||||||
#define DEBUG_all 0xFFFF
|
#define DEBUG_all 0xFFFF
|
||||||
|
|
||||||
/* Simulator stop codes */
|
/* Simulator stop codes */
|
||||||
|
|
||||||
#define STOP_RSRV 1 /* must be 1 */
|
#define STOP_RSRV 1 /* must be 1 */
|
||||||
#define STOP_HALT 2 /* HALT */
|
#define STOP_HALT 2 /* HALT */
|
||||||
#define STOP_IBKPT 3 /* breakpoint */
|
#define STOP_IBKPT 3 /* breakpoint */
|
||||||
#define STOP_OPCODE 4 /* Invalid Opcode */
|
#define STOP_OPCODE 4 /* Invalid Opcode */
|
||||||
#define STOP_IO 5 /* I/O error */
|
#define STOP_IO 5 /* I/O error */
|
||||||
#define STOP_MEM 6 /* Memory error */
|
#define STOP_MEM 6 /* Memory error */
|
||||||
#define STOP_XACK 7 /* XACK error */
|
#define STOP_XACK 7 /* XACK error */
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,141 +1,141 @@
|
||||||
/* system_defs.h: Intel iSBC simulator definitions
|
/* system_defs.h: Intel iSBC simulator definitions
|
||||||
|
|
||||||
Copyright (c) 2010, William A. Beech
|
Copyright (c) 2010, William A. Beech
|
||||||
|
|
||||||
Permission is hereby granted, free of charge, to any person obtaining a
|
Permission is hereby granted, free of charge, to any person obtaining a
|
||||||
copy of this software and associated documentation files (the "Software"),
|
copy of this software and associated documentation files (the "Software"),
|
||||||
to deal in the Software without restriction, including without limitation
|
to deal in the Software without restriction, including without limitation
|
||||||
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||||
and/or sell copies of the Software, and to permit persons to whom the
|
and/or sell copies of the Software, and to permit persons to whom the
|
||||||
Software is furnished to do so, subject to the following conditions:
|
Software is furnished to do so, subject to the following conditions:
|
||||||
|
|
||||||
The above copyright notice and this permission notice shall be included in
|
The above copyright notice and this permission notice shall be included in
|
||||||
all copies or substantial portions of the Software.
|
all copies or substantial portions of the Software.
|
||||||
|
|
||||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
William A. Beech BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
|
||||||
Except as contained in this notice, the name of William A. Beech shall not be
|
Except as contained in this notice, the name of William A. Beech shall not be
|
||||||
used in advertising or otherwise to promote the sale, use or other dealings
|
used in advertising or otherwise to promote the sale, use or other dealings
|
||||||
in this Software without prior written authorization from William A. Beech.
|
in this Software without prior written authorization from William A. Beech.
|
||||||
|
|
||||||
?? ??? 10 - Original file.
|
?? ??? 10 - Original file.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <stdio.h>
|
#include <stdio.h>
|
||||||
#include <ctype.h>
|
#include <ctype.h>
|
||||||
#include "sim_defs.h" /* simulator defns */
|
#include "sim_defs.h" /* simulator defns */
|
||||||
|
|
||||||
#define SET_XACK(VAL) (xack = VAL)
|
#define SET_XACK(VAL) (xack = VAL)
|
||||||
|
|
||||||
//chip definitions for the iSBC-80/30
|
//chip definitions for the iSBC-80/30
|
||||||
/* set the base I/O address for the 8253/8254 */
|
/* set the base I/O address for the 8253/8254 */
|
||||||
#define I8041_BASE 0xDC
|
#define I8041_BASE 0xDC
|
||||||
#define I8041_NUM 1
|
#define I8041_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address and device count for the 8251s */
|
/* set the base I/O address and device count for the 8251s */
|
||||||
#define I8251_BASE 0xEC
|
#define I8251_BASE 0xEC
|
||||||
#define I8251_NUM 1
|
#define I8251_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address for the 8253/8254 */
|
/* set the base I/O address for the 8253/8254 */
|
||||||
#define I8253_BASE 0xDC
|
#define I8253_BASE 0xDC
|
||||||
#define I8253_NUM 1
|
#define I8253_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address and device count for the 8255s */
|
/* set the base I/O address and device count for the 8255s */
|
||||||
#define I8255_BASE 0xE8
|
#define I8255_BASE 0xE8
|
||||||
#define I8255_NUM 1
|
#define I8255_NUM 1
|
||||||
|
|
||||||
/* set the base I/O address for the 8259 */
|
/* set the base I/O address for the 8259 */
|
||||||
#define I8259_BASE 0xDA
|
#define I8259_BASE 0xDA
|
||||||
#define I8259_NUM 1
|
#define I8259_NUM 1
|
||||||
|
|
||||||
/* set the base and size for the EPROM on the iSBC 80/30 */
|
/* set the base and size for the EPROM on the iSBC 80/30 */
|
||||||
#define ROM_BASE 0x0000
|
#define ROM_BASE 0x0000
|
||||||
#define ROM_SIZE 0x1000
|
#define ROM_SIZE 0x1000
|
||||||
#define ROM_DISABLE 1
|
#define ROM_DISABLE 1
|
||||||
|
|
||||||
/* set the base and size for the RAM on the iSBC 80/30 */
|
/* set the base and size for the RAM on the iSBC 80/30 */
|
||||||
#define RAM_BASE 0xF000
|
#define RAM_BASE 0xF000
|
||||||
#define RAM_SIZE 0x1000
|
#define RAM_SIZE 0x1000
|
||||||
#define RAM_DISABLE 0
|
#define RAM_DISABLE 0
|
||||||
|
|
||||||
/* set INTR for CPU on the iSBC 80/30 */
|
/* set INTR for CPU on the iSBC 80/30 */
|
||||||
#define INTR INT_1
|
#define INTR INT_1
|
||||||
|
|
||||||
//board definitions for the multibus
|
//board definitions for the multibus
|
||||||
/* set the base I/O address for the iSBC 201 */
|
/* set the base I/O address for the iSBC 201 */
|
||||||
#define SBC201_BASE 0x78
|
#define SBC201_BASE 0x78
|
||||||
#define SBC201_INT INT_1
|
#define SBC201_INT INT_1
|
||||||
#define SBC201_NUM 0
|
#define SBC201_NUM 0
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 202 */
|
/* set the base I/O address for the iSBC 202 */
|
||||||
#define SBC202_BASE 0x78
|
#define SBC202_BASE 0x78
|
||||||
#define SBC202_INT INT_1
|
#define SBC202_INT INT_1
|
||||||
#define SBC202_NUM 1
|
#define SBC202_NUM 1
|
||||||
|
|
||||||
/* set the base for the zx-200a disk controller */
|
/* set the base for the zx-200a disk controller */
|
||||||
#define ZX200A_BASE_DD 0x78
|
#define ZX200A_BASE 0x78
|
||||||
#define ZX200A_BASE_SD 0x88
|
#define ZX200A_INT INT_1
|
||||||
#define ZX200A_NUM 0
|
#define ZX200A_NUM 0
|
||||||
|
|
||||||
/* set the base I/O address for the iSBC 208 */
|
/* set the base I/O address for the iSBC 208 */
|
||||||
#define SBC208_BASE 0x40
|
#define SBC208_BASE 0x40
|
||||||
#define SBC208_INT INT_1
|
#define SBC208_INT INT_1
|
||||||
#define SBC208_NUM 0
|
#define SBC208_NUM 0
|
||||||
|
|
||||||
/* set the base and size for the iSBC 064 */
|
/* set the base and size for the iSBC 064 */
|
||||||
#define SBC064_BASE 0x0000
|
#define SBC064_BASE 0x0000
|
||||||
#define SBC064_SIZE 0x10000
|
#define SBC064_SIZE 0x10000
|
||||||
#define SBC064_NUM 1
|
#define SBC064_NUM 1
|
||||||
|
|
||||||
/* multibus interrupt definitions */
|
/* multibus interrupt definitions */
|
||||||
|
|
||||||
#define INT_0 0x01
|
#define INT_0 0x01
|
||||||
#define INT_1 0x02
|
#define INT_1 0x02
|
||||||
#define INT_2 0x04
|
#define INT_2 0x04
|
||||||
#define INT_3 0x08
|
#define INT_3 0x08
|
||||||
#define INT_4 0x10
|
#define INT_4 0x10
|
||||||
#define INT_5 0x20
|
#define INT_5 0x20
|
||||||
#define INT_6 0x40
|
#define INT_6 0x40
|
||||||
#define INT_7 0x80
|
#define INT_7 0x80
|
||||||
|
|
||||||
/* CPU interrupts definitions */
|
/* CPU interrupts definitions */
|
||||||
|
|
||||||
#define INT_R 0x200
|
#define INT_R 0x200
|
||||||
#define I75 0x40
|
#define I75 0x40
|
||||||
#define I65 0x20
|
#define I65 0x20
|
||||||
#define I55 0x10
|
#define I55 0x10
|
||||||
|
|
||||||
/* Memory */
|
/* Memory */
|
||||||
|
|
||||||
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
#define MAXMEMSIZE 0x10000 /* 8080 max memory size */
|
||||||
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
#define MEMSIZE (i8080_unit.capac) /* 8080 actual memory size */
|
||||||
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
#define ADDRMASK (MAXMEMSIZE - 1) /* 8080 address mask */
|
||||||
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)
|
||||||
|
|
||||||
/* debug definitions */
|
/* debug definitions */
|
||||||
|
|
||||||
#define DEBUG_flow 0x0001
|
#define DEBUG_flow 0x0001
|
||||||
#define DEBUG_read 0x0002
|
#define DEBUG_read 0x0002
|
||||||
#define DEBUG_write 0x0004
|
#define DEBUG_write 0x0004
|
||||||
#define DEBUG_level1 0x0008
|
#define DEBUG_level1 0x0008
|
||||||
#define DEBUG_level2 0x0010
|
#define DEBUG_level2 0x0010
|
||||||
#define DEBUG_reg 0x0020
|
#define DEBUG_reg 0x0020
|
||||||
#define DEBUG_asm 0x0040
|
#define DEBUG_asm 0x0040
|
||||||
#define DEBUG_xack 0x0080
|
#define DEBUG_xack 0x0080
|
||||||
#define DEBUG_all 0xFFFF
|
#define DEBUG_all 0xFFFF
|
||||||
|
|
||||||
/* Simulator stop codes */
|
/* Simulator stop codes */
|
||||||
|
|
||||||
#define STOP_RSRV 1 /* must be 1 */
|
#define STOP_RSRV 1 /* must be 1 */
|
||||||
#define STOP_HALT 2 /* HALT */
|
#define STOP_HALT 2 /* HALT */
|
||||||
#define STOP_IBKPT 3 /* breakpoint */
|
#define STOP_IBKPT 3 /* breakpoint */
|
||||||
#define STOP_OPCODE 4 /* Invalid Opcode */
|
#define STOP_OPCODE 4 /* Invalid Opcode */
|
||||||
#define STOP_IO 5 /* I/O error */
|
#define STOP_IO 5 /* I/O error */
|
||||||
#define STOP_MEM 6 /* Memory error */
|
#define STOP_MEM 6 /* Memory error */
|
||||||
#define STOP_XACK 7 /* XACK error */
|
#define STOP_XACK 7 /* XACK error */
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue