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Fix off-by-one in reading cache address from memory

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Commit a9ac7c153 properly avoided writing past the end of cache_line,
but in doing so introduced an error as to the first memory address that
should be written. This fix avoids writing past the cache_line by simply
reading the previous memory location.

Fixes the CP/M 68K simulation example and issue #181
This commit is contained in:
Eric Scharff 2015-01-22 21:58:56 -05:00
parent f0f3176c78
commit af713b78e1
1 changed files with 1 additions and 1 deletions
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2
SAGE/m68k_cpu.c
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@ -269,7 +269,7 @@ static t_stat ReadICache(t_addr tpc)
t_stat rc;
uint8* mem;
ASSERT_OKRET(Mem((tpc+CACHE_SIZE)&addrmask,&mem));
ASSERT_OKRET(Mem((tpc+CACHE_SIZE-1)&addrmask,&mem));
/* 68000/08/10 do not like unaligned access */
if (cputype < 3 && (tpc & 1)) return STOP_ERRADR;