From afffe300ee64df6a1a5c88c6e0eb50fc8f442c31 Mon Sep 17 00:00:00 2001
From: Seth Morabito <web@loomcom.com>
Date: Fri, 13 Apr 2018 13:42:30 -0700
Subject: [PATCH] 3b2: Fix minor MMU paging bug

On a full cache miss, the MMU should only bring a page
descriptor into cache if the segment descriptor does NOT
have the 'contiguous' bit set.
---
 3B2/3b2_mmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/3B2/3b2_mmu.c b/3B2/3b2_mmu.c
index 3f330d97..5669dd97 100644
--- a/3B2/3b2_mmu.c
+++ b/3B2/3b2_mmu.c
@@ -664,7 +664,7 @@ t_stat mmu_decode_va(uint32 va, uint8 r_acc, t_bool fc, uint32 *pa)
             return SCPE_NXM;
         }
 
-        if (mmu_get_pd(va, r_acc, fc, sd0, sd1, &pd, &pd_acc) != SCPE_OK) {
+        if (SD_PAGED(sd0) && mmu_get_pd(va, r_acc, fc, sd0, sd1, &pd, &pd_acc) != SCPE_OK) {
             sim_debug(EXECUTE_MSG, &mmu_dev,
                       "[%08x] Could not get PD (full miss). r_acc=%d, fc=%d, va=%08x\n",
                       R[NUM_PC], r_acc, fc, va);