folkert/simh-testsetgenerator
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Merge branch 'master' into AutoConfigure

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This commit is contained in:
Mark Pizzolato 2012-12-28 08:42:01 -08:00
commit b25ca80dc6
3 changed files with 53 additions and 5 deletions
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14
VAX/vax780_defs.h
View file

@ -56,6 +56,8 @@
/* Microcode constructs */ /* Microcode constructs */
#define VAX780_SID (1 << 24) /* system ID */ #define VAX780_SID (1 << 24) /* system ID */
#define VAX780_TYP (0 << 23) /* sys type: 780 */
#define VAX785_TYP (1 << 23) /* sys type: 785 */
#define VAX780_ECO (7 << 19) /* ucode revision */ #define VAX780_ECO (7 << 19) /* ucode revision */
#define VAX780_PLANT (0 << 12) /* plant (Salem NH) */ #define VAX780_PLANT (0 << 12) /* plant (Salem NH) */
#define VAX780_SN (1234) #define VAX780_SN (1234)
@ -68,6 +70,10 @@
#define VER_WCSP (VER_FPLA) /* WCS primary version */ #define VER_WCSP (VER_FPLA) /* WCS primary version */
#define VER_WCSS 0x12 /* WCS secondary version */ #define VER_WCSS 0x12 /* WCS secondary version */
#define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */ #define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */
#define VER_WCSP_785 0x01 /* 785 WCS primary version */
#define VER_WCSS_785 0x00 /* 785 WCS secondary version */
#define VER_PCS_785 0x04 /* 785 PCS version */
#define VER_MTCH_785 0x04 /* 785 PCS/WCS primary version */
/* Interrupts */ /* Interrupts */
@ -142,6 +148,11 @@
#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT #define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT #define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
/* CPU */
#define CPU_MODEL_MODIFIERS \
{ MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={785|780}", \
&cpu_set_model, &cpu_show_model },
/* Memory */ /* Memory */
#define MAXMEMWIDTH 23 /* max mem, MS780C */ #define MAXMEMWIDTH 23 /* max mem, MS780C */
@ -415,6 +426,9 @@ t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);
void sbi_set_errcnf (void); void sbi_set_errcnf (void);
int32 clk_cosched (int32 wait); int32 clk_cosched (int32 wait);
t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc);
#include "pdp11_io_lib.h" #include "pdp11_io_lib.h"
#endif #endif

24
VAX/vax780_sbi.c
View file

@ -108,6 +108,7 @@ uint32 sbi_sc = 0; /* SBI silo comparator *
uint32 sbi_mt = 0; /* SBI maintenance */ uint32 sbi_mt = 0; /* SBI maintenance */
uint32 sbi_er = 0; /* SBI error status */ uint32 sbi_er = 0; /* SBI error status */
uint32 sbi_tmo = 0; /* SBI timeout addr */ uint32 sbi_tmo = 0; /* SBI timeout addr */
int32 sys_model = 0; /* 780 or 785 */
static char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */ static char cpu_boot_cmd[CBUFSIZE] = { 0 }; /* boot command */
static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md); static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
@ -389,7 +390,10 @@ switch (rg) {
break; break;
case MT_SID: /* SID */ case MT_SID: /* SID */
val = VAX780_SID | VAX780_ECO | VAX780_PLANT | VAX780_SN; if (sys_model)
val = VAX780_SID | VAX785_TYP | VAX780_ECO | VAX780_PLANT | VAX780_SN;
else
val = VAX780_SID | VAX780_TYP | VAX780_ECO | VAX780_PLANT | VAX780_SN;
break; break;
default: default:
@ -814,3 +818,21 @@ for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* loop thru dev */
} /* end for */ } /* end for */
return SCPE_OK; return SCPE_OK;
} }
t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc)
{
if (cptr == NULL) return SCPE_ARG;
if (strcmp(cptr, "780") == 0)
sys_model = 0;
else if (strcmp(cptr, "785") == 0)
sys_model = 1;
else
return SCPE_ARG;
return SCPE_OK;
}
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
{
fprintf (st, "model=%s", (sys_model ? "785" : "780"));
return SCPE_OK;
}

20
VAX/vax780_stddev.c
View file

@ -110,6 +110,9 @@
#define COMM_WCSV 0153 /* WCS version */ #define COMM_WCSV 0153 /* WCS version */
#define COMM_WCSS 0154 /* WCS secondary */ #define COMM_WCSS 0154 /* WCS secondary */
#define COMM_FPLV 0155 /* FPLA version */ #define COMM_FPLV 0155 /* FPLA version */
#define COMM_MTCH_785 0153 /* 785 PCS/WCS version */
#define COMM_WCSP_785 0154 /* 785 WCS version */
#define COMM_WCSS_785 0155 /* 785 WCS secondary */
#define COMM_DATA 0x300 /* comm data return */ #define COMM_DATA 0x300 /* comm data return */
#define MISC_MASK 0xFF /* console data mask */ #define MISC_MASK 0xFF /* console data mask */
#define MISC_SWDN 0x1 /* software done */ #define MISC_SWDN 0x1 /* software done */
@ -1054,6 +1057,7 @@ return;
t_stat fl_reset (DEVICE *dptr) t_stat fl_reset (DEVICE *dptr)
{ {
uint32 i; uint32 i;
extern int32 sys_model;
fl_esr = FL_STAINC; fl_esr = FL_STAINC;
fl_ecode = 0; /* clear error */ fl_ecode = 0; /* clear error */
@ -1065,10 +1069,18 @@ sim_cancel (&fl_unit); /* cancel drive */
fl_unit.TRACK = 0; fl_unit.TRACK = 0;
for (i = 0; i < COMM_LNT; i++) for (i = 0; i < COMM_LNT; i++)
comm_region[i] = 0; comm_region[i] = 0;
comm_region[COMM_FPLV] = VER_FPLA; if (sys_model) { /* 785 */
comm_region[COMM_PCSV] = VER_PCS; comm_region[COMM_WCSS_785] = VER_WCSS_785;
comm_region[COMM_WCSV] = VER_WCSP; comm_region[COMM_WCSP_785] = VER_WCSP_785;
comm_region[COMM_WCSS] = VER_WCSS; comm_region[COMM_MTCH_785] = VER_MTCH_785;
comm_region[COMM_PCSV] = VER_PCS_785;
}
else { /* 780 */
comm_region[COMM_FPLV] = VER_FPLA;
comm_region[COMM_PCSV] = VER_PCS;
comm_region[COMM_WCSV] = VER_WCSP;
comm_region[COMM_WCSS] = VER_WCSS;
}
comm_region[COMM_GH] = 1; comm_region[COMM_GH] = 1;
return SCPE_OK; return SCPE_OK;
} }