Removed IOBA_FLOAT and replaced with IOBA_AUTO
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0a0b8dbe31
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b2ed63f31a
12 changed files with 10 additions and 18 deletions
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@ -518,7 +518,6 @@ typedef struct pdp_dib DIB;
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* Processor registers which have I/O page addresses
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/* Processor registers which have I/O page addresses
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*/
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*/
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@ -353,14 +353,14 @@ MTAB dmc_mod[] = {
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};
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};
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#define IOLN_DMC 010
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#define IOLN_DMC 010
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DIB dmc0_dib = { IOBA_FLOAT, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_FLOAT, {&dmc_rxint, &dmc_txint} };
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DIB dmc0_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} };
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DIB dmc1_dib = { IOBA_FLOAT, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_FLOAT, {&dmc_rxint, &dmc_txint} };
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DIB dmc1_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} };
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DIB dmc2_dib = { IOBA_FLOAT, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_FLOAT, {&dmc_rxint, &dmc_txint} };
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DIB dmc2_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} };
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DIB dmc3_dib = { IOBA_FLOAT, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_FLOAT, {&dmc_rxint, &dmc_txint} };
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DIB dmc3_dib = { IOBA_AUTO, IOLN_DMC, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint} };
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#define IOLN_DMP 010
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#define IOLN_DMP 010
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DIB dmp_dib = { IOBA_FLOAT, IOLN_DMP, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_FLOAT, {&dmc_rxint, &dmc_txint }};
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DIB dmp_dib = { IOBA_AUTO, IOLN_DMP, &dmc_rd, &dmc_wr, 2, IVCL (DMCRX), VEC_AUTO, {&dmc_rxint, &dmc_txint }};
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DEVICE dmc_dev[] =
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DEVICE dmc_dev[] =
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{
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{
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@ -1023,7 +1023,7 @@ DEVICE rq_dev = {
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MSC rqb_ctx = { 1 };
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MSC rqb_ctx = { 1 };
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DIB rqb_dib = {
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DIB rqb_dib = {
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IOBA_FLOAT, IOLN_RQ, &rq_rd, &rq_wr,
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IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr,
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1, IVCL (RQ), 0, { &rq_inta }
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1, IVCL (RQ), 0, { &rq_inta }
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};
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};
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@ -1095,7 +1095,7 @@ DEVICE rqb_dev = {
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MSC rqc_ctx = { 2 };
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MSC rqc_ctx = { 2 };
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DIB rqc_dib = {
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DIB rqc_dib = {
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IOBA_FLOAT, IOLN_RQ, &rq_rd, &rq_wr,
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IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr,
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1, IVCL (RQ), 0, { &rq_inta }
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1, IVCL (RQ), 0, { &rq_inta }
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};
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};
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@ -1167,7 +1167,7 @@ DEVICE rqc_dev = {
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MSC rqd_ctx = { 3 };
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MSC rqd_ctx = { 3 };
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DIB rqd_dib = {
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DIB rqd_dib = {
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IOBA_FLOAT, IOLN_RQ, &rq_rd, &rq_wr,
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IOBA_AUTO, IOLN_RQ, &rq_rd, &rq_wr,
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1, IVCL (RQ), 0, { &rq_inta }
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1, IVCL (RQ), 0, { &rq_inta }
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};
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};
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@ -345,7 +345,7 @@ static t_stat vh_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
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#define IOLN_VH 020
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#define IOLN_VH 020
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static DIB vh_dib = {
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static DIB vh_dib = {
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IOBA_FLOAT,
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IOBA_AUTO,
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IOLN_VH * VH_MUXES,
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IOLN_VH * VH_MUXES,
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&vh_rd, /* read */
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&vh_rd, /* read */
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&vh_wr, /* write */
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&vh_wr, /* write */
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@ -198,7 +198,7 @@ DEVICE xu_dev = {
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#define IOLN_XU 010
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#define IOLN_XU 010
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DIB xub_dib = { IOBA_FLOAT, IOLN_XU, &xu_rd, &xu_wr,
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DIB xub_dib = { IOBA_AUTO, IOLN_XU, &xu_rd, &xu_wr,
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1, IVCL (XU), 0, { &xu_int } };
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1, IVCL (XU), 0, { &xu_int } };
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UNIT xub_unit[] = {
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UNIT xub_unit[] = {
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@ -190,7 +190,6 @@ typedef struct {
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/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
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/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* The KA610 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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/* The KA610 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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@ -235,7 +235,6 @@ typedef struct {
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/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
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/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* The KA620/KA630 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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/* The KA620/KA630 maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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@ -234,7 +234,6 @@ typedef struct {
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/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details */
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/* Unibus I/O page layout - see pdp11_ui_lib.c for address layout details */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* Interrupt assignments; within each level, priority is right to left */
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/* Interrupt assignments; within each level, priority is right to left */
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@ -270,7 +270,6 @@ typedef struct {
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* Interrupt assignments; within each level, priority is right to left */
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/* Interrupt assignments; within each level, priority is right to left */
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@ -288,7 +288,6 @@ typedef struct {
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* Interrupt assignments; within each level, priority is right to left */
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/* Interrupt assignments; within each level, priority is right to left */
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@ -322,7 +322,6 @@ typedef struct {
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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Massbus devices (RP, TU) do not appear in the Unibus IO page */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* Interrupt assignments; within each level, priority is right to left */
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/* Interrupt assignments; within each level, priority is right to left */
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@ -285,7 +285,6 @@ typedef struct {
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/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
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/* Qbus I/O page layout - see pdp11_ui_lib.c for address layout details */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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#define IOBA_FLOAT (0) /* Assigned by Auto Configure */
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/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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