ND100: Initial support for Nord-100, implements the base instruction set.
Passes the test program INSTRUCTION-B.
This commit is contained in:
Anders Magnusson
Paul Koning
parent
b0f69eea95
commit
b40f7efde8
9 changed files with 3563 additions and 1 deletions
1748
ND100/nd100_cpu.c
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1748
ND100/nd100_cpu.c
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File diff suppressed because it is too large
Load diff
263
ND100/nd100_defs.h
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263
ND100/nd100_defs.h
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/*
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* Copyright (c) 2023 Anders Magnusson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* masks for instruction matching.
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*/
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#define ND_MEMMSK 0174000
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#define ND_MEMSH 11
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#define ND_CJPMSK 0003400
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#define ND_CJPSH 8
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#define ND_IOXMSK 0003777
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#define ND_BOPSH 7
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#define ND_BOPMSK 0003600
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#define ND_ROPMSK 0177700
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/* mem instructions args */
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#define NDMEM_B 00400
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#define NDMEM_I 01000
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#define NDMEM_X 02000
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#define NDMEM_OMSK 0377
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/*
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* Major group of instructions (ND10 + ND100)
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* All up to CJP (+JPL) uses the memory address syntax.
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*/
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#define ND_STZ 0000000
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#define ND_STA 0004000
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#define ND_STT 0010000
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#define ND_STX 0014000
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#define ND_STD 0020000
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#define ND_LDD 0024000
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#define ND_STF 0030000
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#define ND_LDF 0034000
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#define ND_MIN 0040000
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#define ND_LDA 0044000
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#define ND_LDT 0050000
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#define ND_LDX 0054000
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#define ND_ADD 0060000
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#define ND_SUB 0064000
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#define ND_AND 0070000
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#define ND_ORA 0074000
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#define ND_FAD 0100000
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#define ND_FSB 0104000
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#define ND_FMU 0110000
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#define ND_FDV 0114000
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#define ND_MPY 0120000
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#define ND_JMP 0124000
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#define ND_CJP 0130000
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#define ND_JPL 0134000
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#define ND_SKP 0140000
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#define ND_ROP 0144000
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#define ND_MIS 0150000
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#define ND_SHT 0154000
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#define ND_NA 0160000
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#define ND_IOX 0164000
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#define ND_ARG 0170000
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#define ND_BOP 0174000
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#define ND_SKP_CLEPT 0140301
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#define ND_SKP_EXR 0140600
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#define ND_SKP_BFILL 0140130
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#define ND_SKP_MOVB 0140131
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#define ND_SKP_MOVBF 0140132
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#define ND_SKP_RMPY 0141200
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#define ND_SKP_RDIV 0141600
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#define ND_SKP_LBYT 0142200
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#define ND_SKP_SBYT 0142600
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#define ND_SKP_MIX3 0143200
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#define ND_SKP_IDENT10 0143604
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#define ND_SKP_IDENT11 0143611
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#define ND_SKP_IDENT12 0143622
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#define ND_SKP_IDENT13 0143643
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#define ISEXR(x) (((x) & 0177707) == ND_SKP_EXR)
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#define ND_MIS_TRA 0150000
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#define ND_MIS_TRR 0150100
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#define ND_MIS_MCL 0150200
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#define ND_MIS_MST 0150300
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#define ND_MIS_TRMSK 0177700
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#define ND_MIS_NLZ 0151400
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#define ND_MIS_DNZ 0152000
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#define ND_MIS_LRB 0152600
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#define ND_MIS_SRB 0152402
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#define ND_MIS_RBMSK 0177607
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#define ND_MIS_IRW 0153400
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#define ND_MIS_IRR 0153600
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#define ND_MIS_IRRMSK 0177600
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#define ND_MON 0153000
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#define ND_WAIT 0151000
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#define ND_MONMSK 0177400
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#define ND_MIS_IOF 0150401
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#define ND_MIS_ION 0150402
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#define ND_MIS_POF 0150404
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#define ND_MIS_PIOF 0150405
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#define ND_MIS_SEX 0150406
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#define ND_MIS_REX 0150407
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#define ND_MIS_PON 0150410
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#define ND_MIS_PION 0150412
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#define ND_MIS_IOXT 0150415
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#define ND_MIS_EXAM 0150416
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#define ND_MIS_DEPO 0150417
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/* Internal registers */
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#define IR_STS 001 /* Status reg (as in register stack) */
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#define IR_OPR 002 /* Operator reg */
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#define IR_LMP 002 /* Display reg */
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#define IR_PGS 003 /* paging status reg */
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#define IR_PCR 003 /* paging control reg */
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#define IR_PVL 004 /* Previous level */
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#define IR_IIC 005 /* Internal interrupt code */
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#define IR_IIE 005 /* Internal interrupt enable */
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#define IR_PID 006 /* Priority interrupt detect */
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#define IR_PIE 007 /* Priority interrupt enable */
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#define IR_CSR 010 /* Cache status reg */
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#define IR_PCR14 014 /* paging control reg */
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#define IR_ECCR 015 /* Error Correction Control Register */
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/* internal interrupt enable register */
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#define IIE_MC 0000002 /* Monitor call */
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#define IIE_PV 0000004 /* Protect Violation */
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#define IIE_PF 0000010 /* Page fault */
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#define IIE_II 0000020 /* Illegal instruction */
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#define IIE_V 0000040 /* Error indicator */
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#define IIE_PI 0000100 /* Privileged instruction */
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#define IIE_IOX 0000200 /* IOX error */
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#define IIE_PTY 0000400 /* Memory parity error */
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#define IIE_MOR 0001000 /* Memory out of range */
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#define IIE_POW 0002000 /* Power fail interrupt */
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/* Status register bits */
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#define STS_PTM 0000001 /* page table mode */
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#define STS_TG 0000002 /* floating point rounding mode */
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#define STS_K 0000004
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#define STS_Z 0000010
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#define STS_Q 0000020
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#define STS_O 0000040
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#define STS_C 0000100
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#define STS_M 0000200
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#define STS_N100 0010000 /* Nord-100 */
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#define STS_SEXI 0020000 /* Extended addressing enabled */
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#define STS_PONI 0040000 /* Paging turned on */
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#define STS_IONI 0100000 /* interrupts turned on */
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#define ISION() BIT15(regSTH)
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#define ISPON() BIT14(regSTH)
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#define ISSEX() BIT13(regSTH)
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/* paging bits */
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#define PT_WIP 0010000
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#define PT_PGU 0004000
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/* Simulator-specific stuff */
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#define rnSTS 0
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#define rnD 1
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#define rnP 2
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#define rnB 3
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#define rnL 4
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#define rnA 5
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#define rnT 6
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#define rnX 7
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#define regSTL R[0] /* Only low 8 bits valid */
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#define regD R[1]
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#define regP R[2]
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#define regB R[3]
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#define regL R[4]
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#define regA R[5]
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#define regT R[6]
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#define regX R[7]
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extern uint16 PM[];
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extern uint16 R[8];
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extern uint16 regSTH; /* common for all levels */
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extern int ald; /* Automatic load descriptor - set by boot */
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extern int curlvl;
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/*
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* interrupt link per device.
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*/
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struct intr {
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struct intr *next;
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short ident;
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short inuse;
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};
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extern DEVICE cpu_dev;
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extern DEVICE mm_dev;
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extern DEVICE tti_dev;
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extern DEVICE tto_dev;
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extern DEVICE floppy_dev;
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extern DEVICE clk_dev;
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int iox_floppy(int addr);
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int iox_tty(int addr);
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int iox_clk(int addr);
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#define M_PHYS 0
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#define M_PT 1
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#define M_APT 2
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#define M_FETCH 3
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uint16 rdmem(int addr/* , int how*/);
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uint8 rdbyte(int vaddr, int lr/* , int how*/);
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void wrmem(int addr, int val/* , int how*/);
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void wrbyte(int vaddr, int val, int lr/* , int how*/);
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void mm_wrpcr(void);
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void mm_rdpcr(void);
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void extint(int lvl, struct intr *intr);
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#define STOP_UNHIOX 1
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#define STOP_UNHINS 2
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#define STOP_CKSUM 3
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#define STOP_BP 4
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#define STOP_WAIT 5
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/* Useful bit extraction macros */
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#define BIT0(x) ((x) & 1)
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#define BIT1(x) (((x) >> 1) & 1)
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#define BIT2(x) (((x) >> 2) & 1)
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#define BIT3(x) (((x) >> 3) & 1)
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#define BIT4(x) (((x) >> 4) & 1)
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#define BIT5(x) (((x) >> 5) & 1)
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#define BIT6(x) (((x) >> 6) & 1)
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#define BIT7(x) (((x) >> 7) & 1)
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#define BIT8(x) (((x) >> 8) & 1)
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#define BIT9(x) (((x) >> 9) & 1)
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#define BIT10(x) (((x) >> 10) & 1)
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#define BIT11(x) (((x) >> 11) & 1)
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#define BIT12(x) (((x) >> 12) & 1)
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#define BIT13(x) (((x) >> 13) & 1)
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#define BIT14(x) (((x) >> 14) & 1)
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#define BIT15(x) (((x) >> 15) & 1)
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#define BIT30(x) (((x) >> 30) & 1)
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#define BIT31(x) (((x) >> 31) & 1)
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#define SEXT8(x) ((x & 0377) > 127 ? (int)(x & 0377) - 256 : (x & 0377))
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358
ND100/nd100_floppy.c
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358
ND100/nd100_floppy.c
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/*
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* Copyright (c) 2023 Anders Magnusson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include "sim_defs.h"
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#include "nd100_defs.h"
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/*
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* Floppy and Streamer Controller (3112).
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* ND documentation ND-11.021.1
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*
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* Currently only 5 1/4" DS/DD floppies implemented (no streamer).
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*
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* The device uses eight IOX addresses, but the transfer commands
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* are given in a command block of 12 words in memory.
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*/
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t_stat floppy_svc(UNIT *uptr);
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t_stat floppy_reset (DEVICE *dptr);
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t_stat floppy_boot (int32 unitno, DEVICE *dptr);
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t_stat floppy_attach (UNIT *uptr, CONST char *cptr);
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static int floppy_excmd(void);
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#define FL_NTR 80 /* # tracks/side */
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#define FL_NSC 8 /* # sectors/track */
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#define FL_NSD 2 /* # sides */
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#define FL_NBY 1024 /* # bytes/sector */
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#define FL_SZ (FL_NTR*FL_NTR*FL_NSD*FL_NBY)
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/* hardware status reg flags */
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#define FL_ST_IE 0000002 /* interrupt enable (RFT) */
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#define FL_ST_ACT 0000004 /* device active */
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#define FL_ST_RDY 0000010 /* device ready for transfer (RFT) */
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#define FL_ST_ERR 0000020 /* OR of errors */
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#define FL_ST_HE 0000100 /* Hard error (DMA) */
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#define FL_ST_DENS 0100000 /* Dual density ctlr */
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/* hardware control word */
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#define FL_CW_IE 0000002 /* interrupt enable (RFT) */
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#define FL_CW_AUTO 0000004 /* Activate autoload */
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#define FL_CW_TEST 0000010 /* Test mode */
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#define FL_CW_CLR 0000020 /* Device clear */
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#define FL_CW_ENSTR 0000040 /* Enable streamer */
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#define FL_CW_FCE 0000400 /* Fetch Command and Execute */
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static int fl_rdata; /* devno + 0, read data */
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static int fl_rstatus; /* devno + 2 (+4) read status */
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static int fl_lcw; /* devno + 3 load control word */
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static int fl_lph; /* devno + 5 load pointer high */
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static int fl_lpl; /* devno + 7 load pointer low */
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/*
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* The command block (CB) is DMAed from ND100 memory.
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* Word 0-5 are the command part, 06-13 are the status part.
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*
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* 15 8 7 0
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* +---------------------------------------------+
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* 0 | Command word |
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* +---------------------------------------------+
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* 1 | Device address bit 15-0 |
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* +----------------------+----------------------+
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* 2 | Device addr bit 23-16| Memory addr bit 23-16|
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* +----------------------+----------------------+
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* 3 | Memory addr bit 15-0 |
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* +----------------------+----------------------+
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* 4 | Options | Word count bit 23-16 |
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* +----------------------+----------------------+
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* 5 | Word count (or record count) bit 15-0 |
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* +---------------------------------------------+
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* 6 | Status 1 |
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* +---------------------------------------------+
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* 7 | Status 2 |
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* +---------------------------------------------+
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* 10 | Empty | Last addr 23-16 |
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* +---------------------------------------------+
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* 11 | last memory address 15-0 |
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* +---------------------------------------------+
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* 12 | Empty | Rem. words 23-16 |
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* +---------------------------------------------+
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* 13 | Remaining words 15-0 |
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* +---------------------------------------------+
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*
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*/
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/* CB offsets */
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#define CB_CW 000
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#define CB_DAL 001
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#define CB_DAHMAH 002
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#define CB_MAL 003
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#define CB_OPTWCH 004
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#define CB_WCL 005
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#define CB_ST1 006
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#define CB_ST2 007
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#define CB_LAH 010
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#define CB_LAL 011
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#define CB_REMWH 012
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#define CB_REMWL 013
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/* Options word (004) */
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#define CB_OPT_WC 0100000 /* set if word count in 4/5, else record */
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/* Command word (000) */
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#define CW_FL_RD 0000000 /* Read data */
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#define CW_FL_WR 0000001 /* Write data */
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#define CW_FL_RDFMT 0000042 /* Read format */
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#define CW_FL_CMDMSK 077 /* mask for command */
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#define CW_FL_SELSH 6 /* shift for unit */
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#define CW_FL_1K 0001400 /* 1K sectors */
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#define CW_FL_DS 0002000 /* Double sided */
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#define CW_FL_DD 0004000 /* Double density */
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/* Status 2 */
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#define ST2_FL_BS1K 0000003 /* 1k sectors */
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#define ST2_FL_DS 0000004 /* Double sided */
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#define ST2_FL_DD 0000010 /* Double density */
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#define ST2_FL_514 0000020 /* 5 1/4" floppy */
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/* soft data structures (for simh) */
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#define state u3 /* current unit state */
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#define U_RDY 00 /* unit idling */
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#define U_READ 01 /* unit reading */
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#define U_WRITE 02 /* unit writing */
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#define U_RDFMT 03 /* Read format */
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#define devaddr u4 /* unit offset (in words) */
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#define wcnt u5 /* word count */
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#define memaddr u6 /* place in memory */
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UNIT floppy_unit[] = {
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{ UDATA (&floppy_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, FL_SZ) },
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{ UDATA (&floppy_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, FL_SZ) },
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{ UDATA (&floppy_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, FL_SZ) },
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{ UDATA (&floppy_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+
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UNIT_ROABLE, FL_SZ) },
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{ 0 }
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};
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REG floppy_reg[] = {
|
||||
{ ORDATA (RDATA, fl_rdata, 16) },
|
||||
{ ORDATA (RSTATUS, fl_rstatus, 16) },
|
||||
{ ORDATA (LCW, fl_lcw, 16) },
|
||||
{ ORDATA (LPH, fl_lph, 16) },
|
||||
{ ORDATA (LPL, fl_lpl, 16) },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
MTAB floppy_mod[] = {
|
||||
{ MTAB_XTD|MTAB_VUN, 0, "write enabled", "WRITEENABLED",
|
||||
&set_writelock, &show_writelock, NULL,
|
||||
"Write enable floppy drive" },
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
DEVICE floppy_dev = {
|
||||
"FLOPPY", floppy_unit, floppy_reg, floppy_mod,
|
||||
1, 8, 12, 1, 8, 16,
|
||||
NULL, NULL, &floppy_reset,
|
||||
&floppy_boot, NULL, NULL,
|
||||
NULL, DEV_DISABLE
|
||||
};
|
||||
|
||||
struct intr floppy0_int = { 0, 021 };
|
||||
|
||||
/*
|
||||
* Floppy called via iox instruction.
|
||||
*/
|
||||
int
|
||||
iox_floppy(int addr)
|
||||
{
|
||||
int n;
|
||||
int rv = 0;
|
||||
|
||||
|
||||
switch (addr & 07) {
|
||||
case 0: /* read data */
|
||||
regA = 0;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
break;
|
||||
|
||||
case 2:
|
||||
regA = fl_rstatus;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
n = regA;
|
||||
if (n & FL_CW_FCE) {
|
||||
rv = floppy_excmd();
|
||||
break;
|
||||
}
|
||||
if (n & FL_CW_IE) { /* Interrupt enable */
|
||||
if ((fl_rstatus & (FL_CW_IE|FL_ST_RDY)) == FL_ST_RDY)
|
||||
extint(11, &floppy0_int);
|
||||
fl_rstatus |= FL_ST_IE;
|
||||
break;
|
||||
}
|
||||
if (n & FL_CW_CLR) { /* reset */
|
||||
break;
|
||||
}
|
||||
return STOP_UNHIOX;
|
||||
break;
|
||||
|
||||
case 5:
|
||||
fl_lph = regA;
|
||||
break;
|
||||
|
||||
case 7:
|
||||
fl_lpl = regA;
|
||||
break;
|
||||
|
||||
default:
|
||||
rv = STOP_UNHIOX;
|
||||
break;
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
t_stat
|
||||
floppy_reset(DEVICE *dptr)
|
||||
{
|
||||
fl_rstatus = FL_ST_DENS | FL_ST_RDY;
|
||||
return 0;
|
||||
}
|
||||
|
||||
t_stat
|
||||
floppy_svc(UNIT *uptr)
|
||||
{
|
||||
unsigned char *wp;
|
||||
int i, j;
|
||||
int cbaddr = fl_lpl + ((fl_lph & 0377) << 8);
|
||||
int lah = 0, lal = 0;
|
||||
|
||||
if ((fl_rstatus & FL_ST_ACT) == 0)
|
||||
return STOP_UNHIOX;
|
||||
|
||||
switch (uptr->state) {
|
||||
case U_READ:
|
||||
wp = malloc(uptr->wcnt * 2);
|
||||
if (fseek(uptr->fileref, uptr->devaddr * 2, SEEK_SET) < 0)
|
||||
goto err;
|
||||
if (sim_fread(wp, uptr->wcnt, 2, uptr->fileref) < 0)
|
||||
goto err;
|
||||
for (i = 0, j = 0; i < uptr->wcnt; i++, j += 2)
|
||||
wrmem(uptr->memaddr+i, (wp[j] << 8) | wp[j+1]);
|
||||
lah = (uptr->memaddr + uptr->wcnt) >> 16;
|
||||
lal = (uptr->memaddr + uptr->wcnt) & 0177777;
|
||||
free(wp);
|
||||
break;
|
||||
|
||||
case U_RDFMT:
|
||||
break;
|
||||
|
||||
case U_WRITE:
|
||||
default:
|
||||
return STOP_UNHIOX;
|
||||
}
|
||||
|
||||
wrmem(cbaddr+CB_ST1, FL_ST_RDY);
|
||||
wrmem(cbaddr+CB_ST2,
|
||||
ST2_FL_BS1K|ST2_FL_DS|ST2_FL_DD|ST2_FL_514);
|
||||
wrmem(cbaddr+CB_LAH, lah);
|
||||
wrmem(cbaddr+CB_LAL, lal);
|
||||
wrmem(cbaddr+CB_REMWH, 0);
|
||||
wrmem(cbaddr+CB_REMWL, 0);
|
||||
|
||||
fl_rstatus &= ~FL_ST_ACT;
|
||||
fl_rstatus |= FL_ST_RDY;
|
||||
if (fl_rstatus & FL_ST_IE)
|
||||
extint(11, &floppy0_int);
|
||||
|
||||
return SCPE_OK;
|
||||
|
||||
err:
|
||||
return STOP_UNHIOX;
|
||||
}
|
||||
|
||||
t_stat
|
||||
floppy_boot(int32 unitno, DEVICE *dptr)
|
||||
{
|
||||
printf("floppy_boot \n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int
|
||||
floppy_excmd(void)
|
||||
{
|
||||
UNIT *unit;
|
||||
int cw, u, cmd;
|
||||
int cbaddr = fl_lpl + ((fl_lph & 0377) << 8);
|
||||
|
||||
cw = rdmem(cbaddr+CB_CW);
|
||||
u = (cw >> CW_FL_SELSH) & 03;
|
||||
cmd = cw & CW_FL_CMDMSK;
|
||||
|
||||
unit = &floppy_unit[u];
|
||||
if ((unit->flags & UNIT_ATT) == 0)
|
||||
goto err; /* floppy not inserted */
|
||||
|
||||
/* XXX check disk size, word count etc... */
|
||||
unit->memaddr = ((rdmem(cbaddr+CB_DAHMAH) & 0377) << 16) | rdmem(cbaddr+CB_MAL);
|
||||
unit->wcnt = ((rdmem(cbaddr+CB_OPTWCH) & 0377) << 16) | rdmem(cbaddr+CB_WCL);
|
||||
unit->devaddr = ((rdmem(cbaddr+CB_DAHMAH) & 0177400) << 8) |
|
||||
rdmem(cbaddr+CB_DAL);
|
||||
|
||||
if (cmd == CW_FL_RDFMT) {
|
||||
unit->state = U_RDFMT;
|
||||
} else if (cmd == CW_FL_RD || cmd == CW_FL_WR) {
|
||||
if (cmd == CW_FL_WR)
|
||||
goto err; /* floppy write protected */
|
||||
|
||||
if ((cw & CW_FL_1K) != CW_FL_1K)
|
||||
goto err; /* Require 1K sectors */
|
||||
if ((cw & (CW_FL_DS|CW_FL_DD)) != (CW_FL_DS|CW_FL_DD))
|
||||
goto err; /* Must be double sided/double density */
|
||||
|
||||
unit->state = U_READ;
|
||||
} else
|
||||
goto err;
|
||||
|
||||
sim_activate(&floppy_unit[u], 10);
|
||||
fl_rstatus &= ~FL_ST_RDY;
|
||||
fl_rstatus |= FL_ST_ACT;
|
||||
return SCPE_OK;
|
||||
|
||||
err:
|
||||
return STOP_UNHIOX;
|
||||
}
|
||||
195
ND100/nd100_mm.c
Normal file
195
ND100/nd100_mm.c
Normal file
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Anders Magnusson.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#include "sim_defs.h"
|
||||
|
||||
#include "nd100_defs.h"
|
||||
|
||||
#define MAXMEMSIZE 512*1024
|
||||
|
||||
t_stat mm_reset(DEVICE *dptr);
|
||||
|
||||
uint16 PM[MAXMEMSIZE];
|
||||
uint16 PCR[16]; /* Paging control register */
|
||||
uint16 ptmap[4][64]; /* protection */
|
||||
uint16 pmmap[4][64]; /* memory mapping */
|
||||
|
||||
#define ISDIS() (mm_dev.flags & DEV_DIS)
|
||||
|
||||
UNIT mm_unit = { UDATA(NULL, UNIT_FIX+UNIT_DISABLE+UNIT_BINK, 0) };
|
||||
|
||||
REG mm_reg[] = {
|
||||
{ BRDATA(PCR, PCR, 8, 16, 16) },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
|
||||
DEVICE mm_dev = {
|
||||
"MM", &mm_unit, mm_reg, 0,
|
||||
1, 8, 16, 1, 8, 16,
|
||||
0, 0, &mm_reset,
|
||||
NULL, NULL, NULL,
|
||||
NULL, DEV_DISABLE+DEV_DIS
|
||||
};
|
||||
|
||||
/*
|
||||
* Read a byte. 0 in lr is left byte, 1 is right byte.
|
||||
*/
|
||||
uint8
|
||||
rdbyte(int vaddr, int lr/* , int how*/)
|
||||
{
|
||||
uint16 val = rdmem(vaddr);
|
||||
|
||||
return lr ? val & 0377 : val >> 8;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a byte. 0 in lr is left byte, 1 is right byte.
|
||||
*/
|
||||
void
|
||||
wrbyte(int vaddr, int val, int lr/* , int how*/)
|
||||
{
|
||||
uint16 ov = rdmem(vaddr);
|
||||
|
||||
val &= 0377; /* sanity */
|
||||
ov = lr ? (ov & 0177400) | val : (ov & 0377) | (val << 8);
|
||||
wrmem(vaddr, ov);
|
||||
}
|
||||
|
||||
/*
|
||||
* Access shadow memory. if:
|
||||
* sexi == 0 && v >= 0177400 && (myring == 3 || pon == 0)
|
||||
* or
|
||||
* sexi == 1 && v >= 0177000 && (myring == 3 || pon == 0)
|
||||
*/
|
||||
static int
|
||||
is_shadow(int vaddr)
|
||||
{
|
||||
if ((PCR[curlvl] & 03) < 3 && ISPON())
|
||||
return 0; /* not valid */
|
||||
if (ISSEX())
|
||||
return 1;
|
||||
return (vaddr >= 0177400);
|
||||
}
|
||||
|
||||
/*
|
||||
* Fetch a word from the shadow mem.
|
||||
*/
|
||||
static int
|
||||
shadowrd(int v)
|
||||
{
|
||||
int pt;
|
||||
int x = 0;
|
||||
|
||||
if (ISSEX())
|
||||
x = v & 1, v >>= 1;
|
||||
pt = (v >> 6) & 03;
|
||||
v &= 077;
|
||||
|
||||
if (ISSEX())
|
||||
return x ? pmmap[pt][v] : ptmap[pt][v];
|
||||
return ptmap[pt][v]|pmmap[pt][v];
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a word to the shadow mem.
|
||||
*/
|
||||
static void
|
||||
shadowwr(int v, int dat)
|
||||
{
|
||||
int pt;
|
||||
int x = 0;
|
||||
|
||||
if (ISSEX())
|
||||
x = v & 1, v >>= 1;
|
||||
pt = (v >> 6) & 03;
|
||||
v &= 077;
|
||||
|
||||
if (ISSEX()) {
|
||||
if (x)
|
||||
pmmap[pt][v] = dat;
|
||||
else
|
||||
ptmap[pt][v] = dat;
|
||||
} else {
|
||||
pmmap[pt][v] = dat & 0777;
|
||||
ptmap[pt][v] = dat & 0177000;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint16
|
||||
rdmem(int vaddr/* , int how*/)
|
||||
{
|
||||
int pt;
|
||||
|
||||
vaddr &= 0177777;
|
||||
|
||||
if ((vaddr >= 0177000) && is_shadow(vaddr))
|
||||
return shadowrd(vaddr);
|
||||
/* Mark page as read */
|
||||
if (ISPON()) {
|
||||
pt = (PCR[curlvl] >> 8) & 03;
|
||||
ptmap[pt][vaddr >> 10] |= PT_PGU;
|
||||
}
|
||||
|
||||
// if (ISPON() == 0)
|
||||
return PM[vaddr];
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
wrmem(int vaddr, int val/* , int how*/)
|
||||
{
|
||||
vaddr &= 0177777;
|
||||
if ((vaddr >= 0177000) && is_shadow(vaddr)) {
|
||||
shadowwr(vaddr, val);
|
||||
return;
|
||||
}
|
||||
PM[vaddr] = val;
|
||||
}
|
||||
|
||||
void
|
||||
mm_wrpcr()
|
||||
{
|
||||
if (ISDIS())
|
||||
return;
|
||||
PCR[(regA >> 3) & 017] = regA & 03603;
|
||||
}
|
||||
|
||||
void
|
||||
mm_rdpcr()
|
||||
{
|
||||
if (ISDIS())
|
||||
return;
|
||||
regA = PCR[(regA >> 3) & 017];
|
||||
}
|
||||
|
||||
|
||||
t_stat
|
||||
mm_reset(DEVICE *dptr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
292
ND100/nd100_stddev.c
Normal file
292
ND100/nd100_stddev.c
Normal file
|
|
@ -0,0 +1,292 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Anders Magnusson.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "sim_defs.h"
|
||||
#include "sim_tmxr.h"
|
||||
|
||||
#include "nd100_defs.h"
|
||||
|
||||
struct intr tti_int = { 0, 1 };
|
||||
struct intr tto_int = { 0, 1 };
|
||||
|
||||
MTAB ttx_mod[];
|
||||
|
||||
int tti_status, tti_ctrl;
|
||||
int tto_status, tto_ctrl;
|
||||
|
||||
t_stat tti_svc(UNIT *uptr);
|
||||
t_stat tto_svc(UNIT *uptr);
|
||||
t_stat tti_reset(DEVICE *dptr);
|
||||
t_stat tto_reset(DEVICE *dptr);
|
||||
t_stat tty_setpar(UNIT *uptr);
|
||||
|
||||
#define TT_ICTRL_EIRDY 0000001 /* enable int on dev ready */
|
||||
#define TT_ICTRL_EIERR 0000002 /* enable int on error */
|
||||
#define TT_ICTRL_ACT 0000004 /* set device active */
|
||||
|
||||
#define TT_ISTAT_IRDY 0000001 /* device ready gives interrupt */
|
||||
#define TT_ISTAT_RDY 0000010 /* device ready for transfer */
|
||||
|
||||
#define TT_OCTRL_EIRDY 0000001 /* enable int on dev ready */
|
||||
#define TT_OCTRL_EIERR 0000002 /* enable int on error */
|
||||
#define TT_OCTRL_ACT 0000004 /* set device active */
|
||||
|
||||
#define TT_OSTAT_IRDY 0000001 /* device ready gives interrupt */
|
||||
#define TT_OSTAT_RDY 0000010 /* device ready for transfer */
|
||||
|
||||
UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
|
||||
|
||||
REG tti_reg[] = {
|
||||
{ ORDATA(BUF, tti_unit.buf, 8) },
|
||||
{ ORDATA(ISTATUS, tti_status, 16) },
|
||||
{ ORDATA(ICTRL, tti_ctrl, 16) },
|
||||
{ DRDATA (TIME, tti_unit.wait, 24), },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
DEVICE tti_dev = {
|
||||
"TTI", &tti_unit, tti_reg, ttx_mod,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &tti_reset,
|
||||
NULL, NULL, NULL,
|
||||
NULL, 0
|
||||
};
|
||||
|
||||
UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT };
|
||||
|
||||
REG tto_reg[] = {
|
||||
{ ORDATA(OSTATUS, tto_status, 16) },
|
||||
{ ORDATA(OCTRL, tto_ctrl, 16) },
|
||||
{ DRDATA(POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
|
||||
{ DRDATA(TIME, tto_unit.wait, 24), REG_NZ + PV_LEFT },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
MTAB ttx_mod[] = {
|
||||
#if 0
|
||||
{ TT_PAR, TT_PAR_EVEN, "even parity", "EVEN", &tty_setpar },
|
||||
{ TT_PAR, TT_PAR_ODD, "odd parity", "ODD", &tty_setpar },
|
||||
{ TT_PAR, TT_PAR_MARK, "mark parity", "MARK", &tty_setpar },
|
||||
{ TT_PAR, TT_PAR_SPACE, "no parity", "NONE", &tty_setpar },
|
||||
#endif
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
DEVICE tto_dev = {
|
||||
"TTO", &tto_unit, tto_reg, ttx_mod,
|
||||
1, 10, 31, 1, 8, 8,
|
||||
NULL, NULL, &tto_reset,
|
||||
NULL, NULL, NULL,
|
||||
NULL, 0
|
||||
};
|
||||
|
||||
t_stat
|
||||
tti_reset(DEVICE *dptr)
|
||||
{
|
||||
sim_cancel(&tti_unit);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_stat
|
||||
tto_reset(DEVICE *dptr)
|
||||
{
|
||||
sim_cancel(&tto_unit);
|
||||
tto_status |= TT_OSTAT_RDY;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_stat
|
||||
tti_svc(UNIT *uptr)
|
||||
{
|
||||
int temp;
|
||||
|
||||
sim_activate (&tti_unit, tti_unit.wait);
|
||||
if ((temp = sim_poll_kbd()) < SCPE_KFLAG)
|
||||
return temp;
|
||||
|
||||
tti_unit.buf = temp & 0177;
|
||||
if (tti_ctrl & TT_ICTRL_ACT) {
|
||||
tti_status |= TT_ISTAT_RDY;
|
||||
if (tti_ctrl & TT_ICTRL_EIRDY)
|
||||
extint(12, &tti_int);
|
||||
}
|
||||
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_stat
|
||||
tto_svc(UNIT *uptr)
|
||||
{
|
||||
int32 c;
|
||||
t_stat r;
|
||||
|
||||
c = tto_unit.buf & 0177;
|
||||
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
|
||||
sim_activate (uptr, uptr->wait); /* try again */
|
||||
return ((r == SCPE_STALL)? SCPE_OK : r);/* !stall? report */
|
||||
}
|
||||
tto_status |= TT_OSTAT_RDY;
|
||||
if (tto_ctrl & TT_OCTRL_EIRDY)
|
||||
extint(10, &tto_int);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
iox_tty(int addr)
|
||||
{
|
||||
int rv = 0;
|
||||
|
||||
/*
|
||||
* First four addresses are input, following four are output.
|
||||
*/
|
||||
switch (addr & 07) {
|
||||
case 0: /* read data */
|
||||
regA = tti_unit.buf;
|
||||
tti_status &= ~TT_ISTAT_RDY;
|
||||
break;
|
||||
|
||||
case 1: /* Ignored */
|
||||
break;
|
||||
|
||||
case 2: /* read input status reg */
|
||||
regA = tti_status;
|
||||
break;
|
||||
|
||||
case 3: /* Write control reg */
|
||||
if ((tti_ctrl & TT_ICTRL_ACT) == 0 && (regA & TT_ICTRL_ACT))
|
||||
sim_activate (&tti_unit, tti_unit.wait);
|
||||
if ((regA & TT_ICTRL_ACT) == 0)
|
||||
sim_cancel(&tti_unit);
|
||||
tti_ctrl = regA;
|
||||
if (tti_ctrl & TT_ICTRL_EIRDY)
|
||||
tti_status |= TT_ISTAT_IRDY;
|
||||
else
|
||||
tti_status &= ~TT_ISTAT_IRDY;
|
||||
break;
|
||||
|
||||
case 4: /* Ignored */
|
||||
break;
|
||||
|
||||
case 5: /* Write data */
|
||||
tto_unit.buf = regA & 0177;
|
||||
tto_status &= ~TT_OSTAT_RDY;
|
||||
sim_activate (&tto_unit, tto_unit.wait);
|
||||
break;
|
||||
|
||||
case 6: /* Read output status */
|
||||
regA = tto_status;
|
||||
break;
|
||||
|
||||
case 7: /* Write output control reg */
|
||||
tto_ctrl = regA;
|
||||
if (tto_ctrl & TT_OCTRL_ACT)
|
||||
tto_status |= TT_OSTAT_RDY;
|
||||
else
|
||||
tto_status &= ~TT_OSTAT_RDY;
|
||||
if (tto_ctrl & TT_OCTRL_EIRDY)
|
||||
tto_status |= TT_OSTAT_IRDY;
|
||||
else
|
||||
tto_status &= ~TT_OSTAT_IRDY;
|
||||
break;
|
||||
}
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
||||
/*
|
||||
* Real-time clock.
|
||||
*/
|
||||
#define US_PER_CLK 20000
|
||||
#define CLK_PER_SEC 50
|
||||
|
||||
int int_enabled, dev_ready;
|
||||
|
||||
struct intr rtc_int = { 0, 1 };
|
||||
|
||||
t_stat clk_svc(UNIT *uptr);
|
||||
|
||||
UNIT clk_unit = { UDATA (&clk_svc, 0, 0) };
|
||||
|
||||
REG clk_reg[] = {
|
||||
{ FLDATA (INTENB, int_enabled, 0) },
|
||||
{ FLDATA (DEVRDY, dev_ready, 0) },
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
MTAB clk_mod[] = {
|
||||
{ 0 }
|
||||
};
|
||||
|
||||
DEVICE clk_dev = {
|
||||
"RTC", &clk_unit, clk_reg, clk_mod,
|
||||
1, 0, 0, 0, 0, 0,
|
||||
NULL, NULL, NULL,
|
||||
NULL, NULL, NULL,
|
||||
0, 0
|
||||
};
|
||||
|
||||
int
|
||||
iox_clk(int addr)
|
||||
{
|
||||
int rv = 0;
|
||||
|
||||
switch (addr & 3) {
|
||||
case 0: /* return 0 in A */
|
||||
regA = 0;
|
||||
break;
|
||||
case 1: /* Reset counter */
|
||||
sim_cancel(&clk_unit);
|
||||
if (!sim_is_active(&clk_unit))
|
||||
sim_activate(&clk_unit, sim_rtc_init(US_PER_CLK));
|
||||
break;
|
||||
case 2: /* read status */
|
||||
regA = (dev_ready << 3) | int_enabled;
|
||||
break;
|
||||
|
||||
case 3: /* set status */
|
||||
sim_cancel(&clk_unit);
|
||||
if (!sim_is_active(&clk_unit))
|
||||
sim_activate(&clk_unit, sim_rtc_init(US_PER_CLK));
|
||||
int_enabled = regA & 1;
|
||||
if (BIT13(regA))
|
||||
dev_ready = 0;
|
||||
break;
|
||||
|
||||
default:
|
||||
rv = STOP_UNHIOX;
|
||||
}
|
||||
return rv;
|
||||
}
|
||||
|
||||
t_stat
|
||||
clk_svc(UNIT *uptr)
|
||||
{
|
||||
sim_activate(&clk_unit, sim_rtc_calb(US_PER_CLK));
|
||||
dev_ready = 1;
|
||||
if (int_enabled)
|
||||
extint(13, &rtc_int);
|
||||
return SCPE_OK;
|
||||
}
|
||||
351
ND100/nd100_sys.c
Normal file
351
ND100/nd100_sys.c
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
/*
|
||||
* Copyright (c) 2023 Anders Magnusson.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "sim_defs.h"
|
||||
|
||||
#include "nd100_defs.h"
|
||||
|
||||
char sim_name[] = "ND100";
|
||||
|
||||
extern REG cpu_reg[];
|
||||
REG *sim_PC = &cpu_reg[2];
|
||||
int32 sim_emax = 1;
|
||||
|
||||
DEVICE *sim_devices[] = {
|
||||
&cpu_dev,
|
||||
&mm_dev,
|
||||
&tti_dev,
|
||||
&tto_dev,
|
||||
&floppy_dev,
|
||||
&clk_dev,
|
||||
NULL
|
||||
};
|
||||
|
||||
const char *sim_stop_messages[SCPE_BASE] = {
|
||||
"Unknown error",
|
||||
"Unhandled IOX address",
|
||||
"Unknown instruction",
|
||||
"Checksum error",
|
||||
"Simulator breakpoint",
|
||||
"Wait at level 0",
|
||||
};
|
||||
|
||||
static int mlp;
|
||||
|
||||
static int
|
||||
gb(FILE *f)
|
||||
{
|
||||
int w;
|
||||
|
||||
if (f == NULL)
|
||||
return rdmem(mlp++);
|
||||
w = getc(f) & 0377;
|
||||
return w;
|
||||
}
|
||||
|
||||
static int
|
||||
gw(FILE *f)
|
||||
{
|
||||
int c = gb(f);
|
||||
return (c << 8) | gb(f);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Bootable (BPUN) tape format.
|
||||
* Disks can use it as well with a max of 64 words data. In this case
|
||||
* the bytes are stored in the LSB of the words from beginning of disk.
|
||||
* 1kw block should be read at address 0 in memory.
|
||||
*
|
||||
* A bootable tape consists of nine segments, named A-I.
|
||||
*
|
||||
* A - Any chars not including '!'
|
||||
* B - (optional) octal number terminated by CR (LF ignored).
|
||||
* C - (optional) octal number terminated by '!'.
|
||||
* D - A '!' delimeter
|
||||
* E - Block start address (in memory), two byte, MSB first.
|
||||
* F - Word count in G section, two byte, MSB first.
|
||||
* G - Words as counted in F section.
|
||||
* H - Checksum of G section, one word.
|
||||
* I - Action code. If non-zero, start at address in B, otherwise nothing.
|
||||
*/
|
||||
|
||||
t_stat
|
||||
sim_load(FILE *f, CONST char *buf, CONST char *fnam, t_bool flag)
|
||||
{
|
||||
int B, C, E, F, H, I;
|
||||
int w, i, rv;
|
||||
uint16 s;
|
||||
|
||||
rv = SCPE_OK;
|
||||
if (sim_switches & SWMASK('D')) { /* read file from disk */
|
||||
mlp = 0;
|
||||
for (i = 0; i < 1024; i++) {
|
||||
/* images have MSB first */
|
||||
s = (getc(f) & 0377) << 8;
|
||||
s |= getc(f) & 0377;
|
||||
wrmem(i, s);
|
||||
}
|
||||
f = NULL;
|
||||
}
|
||||
|
||||
/* read B/C section */
|
||||
for (B = C = 0;(w = gb(f) & 0177) != '!'; ) {
|
||||
switch (w) {
|
||||
case '\n':
|
||||
continue;
|
||||
case '\r':
|
||||
B = C, C = 0;
|
||||
break;
|
||||
case '0': case '1': case '2': case '3':
|
||||
case '4': case '5': case '6': case '7':
|
||||
C = (C << 3) | (w - '0');
|
||||
break;
|
||||
default:
|
||||
B = C = 0;
|
||||
}
|
||||
}
|
||||
printf("B address %06o\n", B);
|
||||
printf("C address %06o\n", C);
|
||||
regP = B;
|
||||
printf("Load address %06o\n", E = gw(f));
|
||||
printf("Word count %06o\n", F = gw(f));
|
||||
for (i = s = 0; i < F; i++) {
|
||||
wrmem(E+i, gw(f));
|
||||
s += rdmem(E+i);
|
||||
}
|
||||
printf("Checksum %06o\n", H = gw(f));
|
||||
if (H != s)
|
||||
rv = STOP_CKSUM;
|
||||
printf("Execute %06o\n", I = gw(f));
|
||||
printf("Words read %06o\n", i);
|
||||
ald = 0300; /* from tape reader */
|
||||
return rv;
|
||||
}
|
||||
|
||||
static char *nd_mem[] = {
|
||||
"stz", "sta", "stt", "stx", "std", "ldd", "stf", "ldf",
|
||||
"min", "lda", "ldt", "ldx", "add", "sub", "and", "ora",
|
||||
"fad", "fsb", "fmu", "fdv", "mpy", "jmp", "cjp", "jpl",
|
||||
"skp", "rop", "mis", "sht", "N/A", "iox", "arg", "bop"
|
||||
};
|
||||
|
||||
static char *jptab[] =
|
||||
{ "jap", "jan", "jaz", "jaf", "jpc", "jnc", "jxz", "jxn" };
|
||||
|
||||
static char *argtab[] =
|
||||
{ "sab", "saa", "sat", "sax", "aab", "aaa", "aat", "aax" };
|
||||
|
||||
static char *boptab[] = {
|
||||
"bset zro", "bset one", "bset bcm", "bset bac",
|
||||
"bskp zro", "bskp one", "bskp bcm", "bskp bac",
|
||||
"bstc", "bsta", "bldc", "blda", "banc", "band", "borc", "bora",
|
||||
};
|
||||
|
||||
static char *dactab[] = { "", "d", "p", "b", "l", "a", "t", "x" };
|
||||
|
||||
static char *skptab[] = {
|
||||
"eql", "geq", "gre", "mgre", "ueq", "lss", "lst", "mlst"
|
||||
};
|
||||
|
||||
static char *tratab[] = {
|
||||
"pans", "sts", "opr", "pgs", "pvl", "iic", "pid", "pie",
|
||||
"csr", "actl", "ald", "pes", "pcs14", "pea", "err16", "err17"
|
||||
};
|
||||
|
||||
static char *trrtab[] = {
|
||||
"panc", "sts", "lmp", "pcr", "err04", "iie", "pid", "pie",
|
||||
"cclr", "lcil", "ucil", "err13", "err14", "eccr", "err16", "err17"
|
||||
};
|
||||
|
||||
t_stat
|
||||
fprint_sym(FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw)
|
||||
{
|
||||
int ins, op, off;
|
||||
|
||||
if (!(sw & SWMASK ('M')))
|
||||
return SCPE_ARG;
|
||||
|
||||
op = val[0];
|
||||
ins = op & ND_MEMMSK;
|
||||
off = SEXT8(op);
|
||||
|
||||
#define R(x) ((x) & 0177777)
|
||||
fprintf(of, "%06o\t", op);
|
||||
if (ins < ND_CJP || ins == ND_JPL) {
|
||||
/* MEMORY REFERENCE INSTRUCTIONS */
|
||||
fprintf(of, "%s ", nd_mem[ins >> ND_MEMSH]);
|
||||
switch ((op >> 8) & 07) {
|
||||
case 0:
|
||||
fprintf(of, "0%o", R(off + addr));
|
||||
break;
|
||||
case 1:
|
||||
fprintf(of, "B+0%o", R(off));
|
||||
break;
|
||||
case 2:
|
||||
fprintf(of, "(0%o)", R(off + addr));
|
||||
break;
|
||||
case 3:
|
||||
fprintf(of, "(B+0%o)", R(off));
|
||||
break;
|
||||
case 4:
|
||||
fprintf(of, "0%o+X", R(off));
|
||||
break;
|
||||
case 5:
|
||||
fprintf(of, "B+0%o+X", R(off));
|
||||
break;
|
||||
case 6:
|
||||
fprintf(of, "(0%o)+X", R(off + addr));
|
||||
break;
|
||||
case 7:
|
||||
fprintf(of, "(B+0%o)+X", R(off));
|
||||
break;
|
||||
}
|
||||
#undef R
|
||||
} else if (ins == ND_CJP) {
|
||||
fprintf(of, "%s 0%o", jptab[(op & ND_CJPMSK) >> ND_CJPSH],
|
||||
off + addr);
|
||||
} else if (ins == ND_IOX) {
|
||||
fprintf(of, "iox 0%04o", op & ND_IOXMSK);
|
||||
} else if (ins == ND_ARG) {
|
||||
fprintf(of, "%s 0%o", argtab[(op & ND_CJPMSK) >> ND_CJPSH],
|
||||
off & 0177777);
|
||||
} else if (ins == ND_SHT) {
|
||||
fprintf(of, "s%c%c ", (op & 0600) == 0600 ? 'a' : 'h',
|
||||
(op & 0200) ? 'd' : (op & 0400) ? 'a' : 't');
|
||||
if (op & 03000)
|
||||
fprintf(of, "%s ", (op & 01000) == 01000 ? "rot " :
|
||||
(op & 02000) == 02000 ? "zin" : "lin");
|
||||
fprintf(of, "%d", op & 040 ? 32 - (op & 037) : (op & 037));
|
||||
} else if (ins == ND_BOP) {
|
||||
fprintf(of, "%s ", boptab[(op & ND_BOPMSK) >> ND_BOPSH]);
|
||||
fprintf(of, "%d d%s", (op & 0170) >> 3, dactab[op & 7]);
|
||||
} else if (ins == ND_MIS) {
|
||||
if ((op & 0177400) == 0151000)
|
||||
fprintf(of, "wait 0%o", op & 0377);
|
||||
else if (op == ND_MIS_SEX)
|
||||
fprintf(of, "sex");
|
||||
else if (op == ND_MIS_REX)
|
||||
fprintf(of, "rex");
|
||||
else if (op == ND_MIS_IOF)
|
||||
fprintf(of, "iof");
|
||||
else if (op == ND_MIS_ION)
|
||||
fprintf(of, "ion");
|
||||
else if (op == ND_MIS_POF)
|
||||
fprintf(of, "pof");
|
||||
else if (op == ND_MIS_PON)
|
||||
fprintf(of, "pon");
|
||||
else if (op == ND_MIS_PIOF)
|
||||
fprintf(of, "piof");
|
||||
else if (op == ND_MIS_PION)
|
||||
fprintf(of, "pion");
|
||||
else if (op == ND_MIS_IOXT)
|
||||
fprintf(of, "ioxt");
|
||||
else if ((op & ND_MIS_TRMSK) == ND_MIS_TRA)
|
||||
fprintf(of, "tra %s", tratab[op & 017]);
|
||||
else if ((op & ND_MIS_TRMSK) == ND_MIS_TRR)
|
||||
fprintf(of, "trr %s", trrtab[op & 017]);
|
||||
else if ((op & ND_MIS_TRMSK) == ND_MIS_MCL)
|
||||
fprintf(of, "mcl 0%o", op & 077);
|
||||
else if ((op & ND_MIS_TRMSK) == ND_MIS_MST)
|
||||
fprintf(of, "mst 0%o", op & 077);
|
||||
else if ((op & 0177600) == 0153600)
|
||||
fprintf(of, "irr 0%02o d%s",
|
||||
(op >> 3) & 017, dactab[op & 07]);
|
||||
else if ((op & 0177600) == 0153400)
|
||||
fprintf(of, "irw 0%02o d%s",
|
||||
(op >> 3) & 017, dactab[op & 07]);
|
||||
else if ((op & ND_MONMSK) == ND_MON)
|
||||
fprintf(of, "mon 0%o", op & 0377);
|
||||
else if ((op & ND_MONMSK) == ND_MIS_NLZ)
|
||||
fprintf(of, "nlz 0%o", op & 0377);
|
||||
else if ((op & ND_MIS_RBMSK) == ND_MIS_LRB)
|
||||
fprintf(of, "lrb");
|
||||
else if ((op & ND_MIS_RBMSK) == ND_MIS_SRB)
|
||||
fprintf(of, "srb");
|
||||
else
|
||||
fprintf(of, "MISSING2: 0%06o", op);
|
||||
} else if (ins == ND_ROP) {
|
||||
switch (op & ND_ROPMSK) {
|
||||
case 0146000: fprintf(of, "radd"); break;
|
||||
case 0146600: fprintf(of, "rsub"); break;
|
||||
case 0144400: fprintf(of, "rand"); break;
|
||||
case 0145400: fprintf(of, "rora"); break;
|
||||
case 0145000: fprintf(of, "rexo"); break;
|
||||
case 0144000: fprintf(of, "swap"); break;
|
||||
case 0146100: fprintf(of, "copy"); break;
|
||||
case 0146500: fprintf(of, "rinc"); break;
|
||||
default:
|
||||
if ((op & 0177770) == 0146400) {
|
||||
fprintf(of, "rinc %s", dactab[op & 07]);
|
||||
op = 0;
|
||||
} else
|
||||
fprintf(of, "%07o", op & ND_ROPMSK);
|
||||
break;
|
||||
}
|
||||
if (op)
|
||||
fprintf(of, " s%s to d%s",
|
||||
dactab[(op & 070) >> 3], dactab[op & 07]);
|
||||
} else if (ins == ND_SKP) {
|
||||
if (op & 0300) {
|
||||
if (op == ND_SKP_BFILL)
|
||||
fprintf(of, "bfill");
|
||||
else if (op == ND_SKP_MOVB)
|
||||
fprintf(of, "movb");
|
||||
else if (op == ND_SKP_MOVBF)
|
||||
fprintf(of, "movbf");
|
||||
else if (op == ND_SKP_IDENT10)
|
||||
fprintf(of, "ident 10");
|
||||
else if (op == ND_SKP_IDENT11)
|
||||
fprintf(of, "ident 11");
|
||||
else if (op == ND_SKP_IDENT12)
|
||||
fprintf(of, "ident 12");
|
||||
else if (op == ND_SKP_IDENT13)
|
||||
fprintf(of, "ident 13");
|
||||
else if (op == ND_SKP_LBYT)
|
||||
fprintf(of, "lbyt");
|
||||
else if (op == ND_SKP_SBYT)
|
||||
fprintf(of, "sbyt");
|
||||
else if ((op & 0177707) == ND_SKP_EXR)
|
||||
fprintf(of, "exr %s", dactab[(op & 070) >> 3]);
|
||||
else if ((op & 0177700) == ND_SKP_RMPY)
|
||||
fprintf(of, "rmpy %s %s",
|
||||
dactab[(op & 070) >> 3], dactab[op & 07]);
|
||||
else
|
||||
fprintf(of, "MISSING4: 0%06o", op);
|
||||
} else
|
||||
fprintf(of, "skp d%s %s s%s", dactab[op & 07],
|
||||
skptab[(op >> 8) & 07], dactab[(op & 070) >> 3]);
|
||||
} else
|
||||
fprintf(of, "MISSING: 0%06o", op);
|
||||
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_stat
|
||||
parse_sym(CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
|
||||
{
|
||||
return SCPE_ARG;
|
||||
}
|
||||
|
|
@ -388,6 +388,11 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "SEL32", "SEL32.vcproj", "{9
|
|||
{D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8}
|
||||
EndProjectSection
|
||||
EndProject
|
||||
Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ND100", "nd100.vcproj", "{F3623A45-3B4C-4880-83D8-1CD49D36A67C}"
|
||||
ProjectSection(ProjectDependencies) = postProject
|
||||
{D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8}
|
||||
EndProjectSection
|
||||
EndProject
|
||||
Global
|
||||
GlobalSection(SolutionConfigurationPlatforms) = preSolution
|
||||
Debug|Win32 = Debug|Win32
|
||||
|
|
@ -706,6 +711,10 @@ Global
|
|||
{9B214A06-3727-44D4-99B7-2C3E44B86B32}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{9B214A06-3727-44D4-99B7-2C3E44B86B32}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{9B214A06-3727-44D4-99B7-2C3E44B86B32}.Release|Win32.Build.0 = Release|Win32
|
||||
{F3623A45-3B4C-4880-83D8-1CD49D36A67C}.Debug|Win32.ActiveCfg = Debug|Win32
|
||||
{F3623A45-3B4C-4880-83D8-1CD49D36A67C}.Debug|Win32.Build.0 = Debug|Win32
|
||||
{F3623A45-3B4C-4880-83D8-1CD49D36A67C}.Release|Win32.ActiveCfg = Release|Win32
|
||||
{F3623A45-3B4C-4880-83D8-1CD49D36A67C}.Release|Win32.Build.0 = Release|Win32
|
||||
EndGlobalSection
|
||||
GlobalSection(SolutionProperties) = preSolution
|
||||
HideSolutionNode = FALSE
|
||||
|
|
|
|||
332
Visual Studio Projects/nd100.vcproj
Normal file
332
Visual Studio Projects/nd100.vcproj
Normal file
|
|
@ -0,0 +1,332 @@
|
|||
<?xml version="1.0" encoding="Windows-1252"?>
|
||||
<VisualStudioProject
|
||||
ProjectType="Visual C++"
|
||||
Version="9.00"
|
||||
Name="ND100"
|
||||
ProjectGUID="{F3623A45-3B4C-4880-83D8-1CD49D36A67C}"
|
||||
RootNamespace="ND100"
|
||||
Keyword="Win32Proj"
|
||||
TargetFrameworkVersion="131072"
|
||||
>
|
||||
<Platforms>
|
||||
<Platform
|
||||
Name="Win32"
|
||||
/>
|
||||
</Platforms>
|
||||
<ToolFiles>
|
||||
</ToolFiles>
|
||||
<Configurations>
|
||||
<Configuration
|
||||
Name="Debug|Win32"
|
||||
OutputDirectory="..\BIN\NT\$(PlatformName)-$(ConfigurationName)"
|
||||
IntermediateDirectory="..\BIN\NT\Project\simh\$(ProjectName)\$(PlatformName)-$(ConfigurationName)"
|
||||
ConfigurationType="1"
|
||||
CharacterSet="0"
|
||||
>
|
||||
<Tool
|
||||
Name="VCPreBuildEventTool"
|
||||
Description="Check for required build dependencies & git commit id"
|
||||
CommandLine="Pre-Build-Event.cmd "$(TargetDir)$(TargetName).exe" LIBPCRE"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCustomBuildTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXMLDataGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCMIDLTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCLCompilerTool"
|
||||
Optimization="0"
|
||||
AdditionalIncludeDirectories="./;../;../slirp;../slirp_glue;../slirp_glue/qemu;../slirp_glue/qemu/win32/include;../../windows-build/include;;../../windows-build/include/SDL2"
|
||||
PreprocessorDefinitions="_CRT_NONSTDC_NO_WARNINGS;SIM_BUILD_TOOL=simh-Visual-Studio-Project;_CRT_NONSTDC_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;SIM_NEED_GIT_COMMIT_ID;HAVE_PCRE_H;PCRE_STATIC"
|
||||
KeepComments="false"
|
||||
BasicRuntimeChecks="0"
|
||||
RuntimeLibrary="1"
|
||||
UsePrecompiledHeader="0"
|
||||
WarningLevel="3"
|
||||
WarnAsError="true"
|
||||
DebugInformationFormat="3"
|
||||
CompileAs="1"
|
||||
ShowIncludes="false"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManagedResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPreLinkEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCLinkerTool"
|
||||
AdditionalDependencies="libcmtd.lib wsock32.lib winmm.lib Iphlpapi.lib pcrestaticd.lib SDL2-StaticD.lib SDL2_ttf-StaticD.lib freetype2412MT_D.lib libpng16.lib zlib.lib dxguid.lib Imm32.lib Version.lib Setupapi.lib"
|
||||
LinkIncremental="1"
|
||||
AdditionalLibraryDirectories="../../windows-build/lib/Debug/"
|
||||
GenerateDebugInformation="true"
|
||||
SubSystem="1"
|
||||
StackReserveSize="10485760"
|
||||
StackCommitSize="10485760"
|
||||
RandomizedBaseAddress="1"
|
||||
DataExecutionPrevention="0"
|
||||
TargetMachine="1"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCALinkTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManifestTool"
|
||||
UseUnicodeResponseFiles="false"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXDCMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCBscMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCFxCopTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCAppVerifierTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPostBuildEventTool"
|
||||
Description="Running Available Tests"
|
||||
CommandLine="Post-Build-Event.cmd LGP "$(TargetDir)$(TargetName).exe""
|
||||
/>
|
||||
</Configuration>
|
||||
<Configuration
|
||||
Name="Release|Win32"
|
||||
OutputDirectory="..\BIN\NT\$(PlatformName)-$(ConfigurationName)"
|
||||
IntermediateDirectory="..\BIN\NT\Project\simh\$(ProjectName)\$(PlatformName)-$(ConfigurationName)"
|
||||
ConfigurationType="1"
|
||||
CharacterSet="0"
|
||||
>
|
||||
<Tool
|
||||
Name="VCPreBuildEventTool"
|
||||
Description="Check for required build dependencies & git commit id"
|
||||
CommandLine="Pre-Build-Event.cmd "$(TargetDir)$(TargetName).exe" LIBPCRE"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCustomBuildTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXMLDataGeneratorTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCMIDLTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCCLCompilerTool"
|
||||
Optimization="2"
|
||||
InlineFunctionExpansion="1"
|
||||
OmitFramePointers="true"
|
||||
WholeProgramOptimization="true"
|
||||
AdditionalIncludeDirectories="./;../;../slirp;../slirp_glue;../slirp_glue/qemu;../slirp_glue/qemu/win32/include;../../windows-build/include;;../../windows-build/include/SDL2"
|
||||
PreprocessorDefinitions="_CRT_NONSTDC_NO_WARNINGS;SIM_BUILD_TOOL=simh-Visual-Studio-Project;_CRT_NONSTDC_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;_WINSOCK_DEPRECATED_NO_WARNINGS;SIM_NEED_GIT_COMMIT_ID;HAVE_PCRE_H;PCRE_STATIC"
|
||||
StringPooling="true"
|
||||
RuntimeLibrary="0"
|
||||
EnableFunctionLevelLinking="true"
|
||||
UsePrecompiledHeader="0"
|
||||
WarningLevel="3"
|
||||
WarnAsError="true"
|
||||
DebugInformationFormat="3"
|
||||
CompileAs="1"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManagedResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCResourceCompilerTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPreLinkEventTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCLinkerTool"
|
||||
AdditionalDependencies="libcmt.lib wsock32.lib winmm.lib Iphlpapi.lib pcrestatic.lib SDL2-Static.lib SDL2_ttf-Static.lib freetype2412MT.lib libpng16.lib zlib.lib dxguid.lib Imm32.lib Version.lib Setupapi.lib"
|
||||
LinkIncremental="1"
|
||||
AdditionalLibraryDirectories="../../windows-build/lib/Release/"
|
||||
GenerateDebugInformation="false"
|
||||
SubSystem="1"
|
||||
StackReserveSize="10485760"
|
||||
StackCommitSize="10485760"
|
||||
OptimizeReferences="2"
|
||||
EnableCOMDATFolding="2"
|
||||
LinkTimeCodeGeneration="1"
|
||||
RandomizedBaseAddress="1"
|
||||
DataExecutionPrevention="0"
|
||||
TargetMachine="1"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCALinkTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCManifestTool"
|
||||
UseUnicodeResponseFiles="false"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCXDCMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCBscMakeTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCFxCopTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCAppVerifierTool"
|
||||
/>
|
||||
<Tool
|
||||
Name="VCPostBuildEventTool"
|
||||
Description="Running Available Tests"
|
||||
CommandLine="Post-Build-Event.cmd LGP "$(TargetDir)$(TargetName).exe""
|
||||
/>
|
||||
</Configuration>
|
||||
</Configurations>
|
||||
<References>
|
||||
</References>
|
||||
<Files>
|
||||
<Filter
|
||||
Name="Source Files"
|
||||
Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm"
|
||||
>
|
||||
<File
|
||||
RelativePath="..\ND100\nd100_cpu.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\ND100\nd100_floppy.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\ND100\nd100_mm.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\ND100\nd100_stddev.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\ND100\nd100_sys.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\scp.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_console.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_disk.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_ether.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_fio.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_serial.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_sock.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_tape.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_timer.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_tmxr.c"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_video.c"
|
||||
>
|
||||
</File>
|
||||
</Filter>
|
||||
<Filter
|
||||
Name="Header Files"
|
||||
Filter="h;hpp;hxx;hm;inl;inc"
|
||||
>
|
||||
<File
|
||||
RelativePath="..\ND100\nd100_defs.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\scp.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_console.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_defs.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_disk.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_ether.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_fio.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_rev.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_serial.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_sock.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_tape.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_timer.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_tmxr.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath="..\sim_video.h"
|
||||
>
|
||||
</File>
|
||||
</Filter>
|
||||
<Filter
|
||||
Name="Resource Files"
|
||||
Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe"
|
||||
>
|
||||
</Filter>
|
||||
</Files>
|
||||
<Globals>
|
||||
</Globals>
|
||||
</VisualStudioProject>
|
||||
16
makefile
16
makefile
|
|
@ -1439,6 +1439,11 @@ PDP1 = ${PDP1D}/pdp1_lp.c ${PDP1D}/pdp1_cpu.c ${PDP1D}/pdp1_stddev.c \
|
|||
PDP1_OPT = -I ${PDP1D} ${DISPLAY_OPT} $(PDP1_DISPLAY_OPT)
|
||||
|
||||
|
||||
ND100D = ${SIMHD}/ND100
|
||||
ND100 = ${ND100D}/nd100_sys.c ${ND100D}/nd100_cpu.c ${ND100D}/nd100_floppy.c \
|
||||
${ND100D}/nd100_stddev.c ${ND100D}/nd100_mm.c
|
||||
ND100_OPT = -I ${ND100D}
|
||||
|
||||
NOVAD = ${SIMHD}/NOVA
|
||||
NOVA = ${NOVAD}/nova_sys.c ${NOVAD}/nova_cpu.c ${NOVAD}/nova_dkp.c \
|
||||
${NOVAD}/nova_dsk.c ${NOVAD}/nova_lp.c ${NOVAD}/nova_mta.c \
|
||||
|
|
@ -2187,7 +2192,7 @@ ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 \
|
|||
microvax2000 infoserver100 infoserver150vxt microvax3100 microvax3100e \
|
||||
vaxstation3100m30 vaxstation3100m38 vaxstation3100m76 vaxstation4000m60 \
|
||||
microvax3100m80 vaxstation4000vlc infoserver1000 \
|
||||
nova eclipse hp2100 hp3000 i1401 i1620 s3 altair altairz80 gri \
|
||||
nd100 nova eclipse hp2100 hp3000 i1401 i1620 s3 altair altairz80 gri \
|
||||
i7094 ibm1130 id16 id32 sds lgp h316 cdc1700 \
|
||||
swtp6800mp-a swtp6800mp-a2 tx-0 ssem b5500 intel-mds \
|
||||
scelbi 3b2 3b2-700 i701 i704 i7010 i7070 i7080 i7090 \
|
||||
|
|
@ -2520,6 +2525,15 @@ ifneq (,$(call find_test,${VAXD},vax-diag))
|
|||
$@ $(call find_test,${VAXD},vax-diag) ${TEST_ARG}
|
||||
endif
|
||||
|
||||
nd100 : ${BIN}nd100${EXE}
|
||||
|
||||
${BIN}nd100${EXE} : ${ND100} ${SIM}
|
||||
${MKDIRBIN}
|
||||
${CC} ${ND100} ${SIM} ${ND100_OPT} ${CC_OUTSPEC} ${LDFLAGS}
|
||||
ifneq (,$(call find_test,${ND100D},nd100))
|
||||
$@ $(call find_test,${ND100D},nd100) ${TEST_ARG}
|
||||
endif
|
||||
|
||||
nova : ${BIN}nova${EXE}
|
||||
|
||||
${BIN}nova${EXE} : ${NOVA} ${SIM}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue