parent
611b7632c9
commit
b80fa0ae50
2 changed files with 12 additions and 68 deletions
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@ -197,7 +197,6 @@ jmp_buf save_env;
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int32 hst_p = 0; /* history pointer */
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int32 hst_p = 0; /* history pointer */
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int32 hst_lnt = 0; /* history length */
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int32 hst_lnt = 0; /* history length */
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InstHistory *hst = NULL; /* instruction history */
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InstHistory *hst = NULL; /* instruction history */
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int32 apr_serial = -1; /* CPU Serial number */
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/* Forward and external declarations */
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/* Forward and external declarations */
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@ -206,9 +205,6 @@ t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat cpu_set_serial (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_show_serial (FILE *st, UNIT *uptr, int32 val, void *desc);
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d10 adjsp (d10 val, a10 ea);
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d10 adjsp (d10 val, a10 ea);
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void ibp (a10 ea, int32 pflgs);
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void ibp (a10 ea, int32 pflgs);
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d10 ldb (a10 ea, int32 pflgs);
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d10 ldb (a10 ea, int32 pflgs);
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@ -404,7 +400,6 @@ MTAB cpu_mod[] = {
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NULL, &show_iospace },
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NULL, &show_iospace },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
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&cpu_set_hist, &cpu_show_hist },
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&cpu_set_hist, &cpu_show_hist },
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{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "SERIAL", "SERIAL", &cpu_set_serial, &cpu_show_serial },
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{ 0 }
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{ 0 }
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};
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};
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@ -2109,14 +2104,8 @@ return;
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t_bool aprid (a10 ea, int32 prv)
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t_bool aprid (a10 ea, int32 prv)
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{
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{
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d10 value = (Q_ITS)? UC_AIDITS: UC_AIDDEC;
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Write (ea, (Q_ITS)? UC_AIDITS: UC_AIDDEC, prv);
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if( (apr_serial == -1) || (!Q_ITS && apr_serial < 4096) )
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return FALSE;
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value |= (Q_ITS)? UC_SERITS: UC_SERDEC;
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else
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value |= apr_serial;
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Write (ea, value, prv);
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return FALSE;
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}
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}
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/* Checked against KS10 ucode */
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/* Checked against KS10 ucode */
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@ -2430,34 +2419,3 @@ for (k = 0; k < lnt; k++) { /* print specified */
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} /* end for */
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} /* end for */
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return SCPE_OK;
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return SCPE_OK;
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}
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}
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/* Set serial */
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t_stat cpu_set_serial (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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int32 lnt;
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t_stat r;
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if (cptr == NULL) {
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apr_serial = -1;
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return SCPE_OK;
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}
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lnt = (int32) get_uint (cptr, 10, 077777, &r);
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if ((r != SCPE_OK) || (lnt <= 0) || (!Q_ITS && lnt < 4096))
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return SCPE_ARG;
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apr_serial = lnt & 077777;
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return SCPE_OK;
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}
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/* Show serial */
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t_stat cpu_show_serial (FILE *st, UNIT *uptr, int32 val, void *desc)
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{
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fprintf (st, "Serial: " );
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if( (apr_serial == -1) || (!Q_ITS && apr_serial < 4096) ) {
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fprintf (st, "%d (default)", (Q_ITS)? UC_SERITS: UC_SERDEC);
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return SCPE_OK;
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}
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fprintf (st, "%d", apr_serial);
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return SCPE_OK;
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}
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@ -476,8 +476,8 @@ typedef t_int64 d10; /* PDP-10 data (36b) */
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#define UC_SERDEC 4097 /* serial number */
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#define UC_SERDEC 4097 /* serial number */
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#define UC_SERITS 1729
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#define UC_SERITS 1729
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#define UC_AIDDEC (UC_INHCST | UC_UBABLT | UC_KIPAGE | UC_KLPAGE | \
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#define UC_AIDDEC (UC_INHCST | UC_UBABLT | UC_KIPAGE | UC_KLPAGE | \
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UC_VERDEC)
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UC_VERDEC | UC_SERDEC)
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#define UC_AIDITS (UC_KIPAGE | UC_VERITS)
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#define UC_AIDITS (UC_KIPAGE | UC_VERITS | UC_SERITS)
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#define UC_HSBDEC 0376000 /* DEC initial HSB */
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#define UC_HSBDEC 0376000 /* DEC initial HSB */
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#define UC_HSBITS 0000500 /* ITS initial HSB */
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#define UC_HSBITS 0000500 /* ITS initial HSB */
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@ -619,6 +619,7 @@ typedef struct pdp_dib DIB;
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#define DZ_MUXES 4 /* max # of muxes */
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#define DZ_MUXES 4 /* max # of muxes */
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#define DZ_LINES 8 /* lines per mux */
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#define DZ_LINES 8 /* lines per mux */
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#define DUP_LINES 4 /* max # of DUP11's */
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#define DIB_MAX 100 /* max DIBs */
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#define DIB_MAX 100 /* max DIBs */
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#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
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#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
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@ -658,12 +659,6 @@ typedef struct pdp_dib DIB;
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#define IOLN_UBMNT3 001
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#define IOLN_UBMNT3 001
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#define IOBA_XU (IO_UBA3 + 0774510) /* DEUNA/DELUA */
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#define IOBA_XU (IO_UBA3 + 0774510) /* DEUNA/DELUA */
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#define IOLN_XU 010
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#define IOLN_XU 010
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#define IOBA_DMR (IO_UBA3 + 0764000) /* DMR11 */
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#define IOLN_DMR 010
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#define IOBA_DUP (IO_UBA3 + 0760300) /* DUP11 */
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#define IOLN_DUP 010
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#define IOBA_KMC (IO_UBA3 + 0760540) /* KMC11 */
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#define IOLN_KMC 010
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#define IOBA_CR (IO_UBA3 + 0777160) /* CD/CR/CM */
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#define IOBA_CR (IO_UBA3 + 0777160) /* CD/CR/CM */
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#define IOLN_CR 010
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#define IOLN_CR 010
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#define IOBA_RY (IO_UBA3 + 0777170) /* RX211 */
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#define IOBA_RY (IO_UBA3 + 0777170) /* RX211 */
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@ -702,10 +697,6 @@ typedef struct pdp_dib DIB;
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#define INT_V_RP 6 /* RH11/RP,RM drives */
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#define INT_V_RP 6 /* RH11/RP,RM drives */
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#define INT_V_TU 7 /* RH11/TM03/TU45 */
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#define INT_V_TU 7 /* RH11/TM03/TU45 */
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#define INT_V_KMCA 8 /* KMC11 */
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#define INT_V_KMCB 9
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#define INT_V_DMRA 10 /* DMR11 */
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#define INT_V_DMRB 11
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#define INT_V_DMCRX 13
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#define INT_V_DMCRX 13
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#define INT_V_DMCTX 14
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#define INT_V_DMCTX 14
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#define INT_V_XU 15 /* DEUNA/DELUA */
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#define INT_V_XU 15 /* DEUNA/DELUA */
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@ -716,13 +707,12 @@ typedef struct pdp_dib DIB;
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#define INT_V_PTP 25
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#define INT_V_PTP 25
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#define INT_V_LP20 26 /* LPT20 */
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#define INT_V_LP20 26 /* LPT20 */
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#define INT_V_CR 27 /* CD20 (CD11) */
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#define INT_V_CR 27 /* CD20 (CD11) */
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#define INT_V_CR 27 /* CD20 (CD11) */
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#define INT_V_DUPRX 28 /* DUP11 */
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#define INT_V_DUPTX 29
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#define INT_RP (1u << INT_V_RP)
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#define INT_RP (1u << INT_V_RP)
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#define INT_TU (1u << INT_V_TU)
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#define INT_TU (1u << INT_V_TU)
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#define INT_KMCA (1u << INT_V_KMCA)
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#define INT_KMCB (1u << INT_V_KMCB)
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#define INT_DMRA (1u << INT_V_DMRA)
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#define INT_DMRB (1u << INT_V_DMRB)
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#define INT_DMCRX (1u << INT_V_DMCRX)
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#define INT_DMCRX (1u << INT_V_DMCRX)
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#define INT_DMCTX (1u << INT_V_DMCTX)
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#define INT_DMCTX (1u << INT_V_DMCTX)
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#define INT_XU (1u << INT_V_XU)
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#define INT_XU (1u << INT_V_XU)
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@ -733,19 +723,19 @@ typedef struct pdp_dib DIB;
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_LP20 (1u << INT_V_LP20)
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#define INT_LP20 (1u << INT_V_LP20)
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#define INT_CR (1u << INT_V_CR)
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#define INT_CR (1u << INT_V_CR)
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#define INT_DUPRX (1u << INT_V_DUPRX)
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#define INT_DUPTX (1u << INT_V_DUPTX)
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#define IPL_RP 6 /* int levels */
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#define IPL_RP 6 /* int levels */
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#define IPL_TU 6
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#define IPL_TU 6
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#define IPL_KMCA 5
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#define IPL_KMCB 5
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#define IPL_DMRA 5
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#define IPL_DMRB 5
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#define IPL_DMCRX 5
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#define IPL_DMCRX 5
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#define IPL_DMCTX 5
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#define IPL_DMCTX 5
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#define IPL_XU 5
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#define IPL_XU 5
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#define IPL_DZRX 5
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#define IPL_DZRX 5
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#define IPL_DZTX 5
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#define IPL_DZTX 5
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#define IPL_RY 5
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#define IPL_RY 5
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#define IPL_DUPRX 5
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#define IPL_DUPTX 5
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#define IPL_PTR 4
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#define IPL_PTR 4
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#define IPL_PTP 4
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#define IPL_PTP 4
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#define IPL_LP20 4
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#define IPL_LP20 4
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@ -769,10 +759,6 @@ typedef struct pdp_dib DIB;
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#define VEC_RY 0264
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#define VEC_RY 0264
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#define VEC_DZRX 0340
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#define VEC_DZRX 0340
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#define VEC_DZTX 0344
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#define VEC_DZTX 0344
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#define VEC_KMCA 0540
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#define VEC_KMCB 0544
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#define VEC_DMRA 0610
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#define VEC_DMRB 0614
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#define VEC_LP20 0754
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#define VEC_LP20 0754
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#define VEC_AUTO 0 /* Set by Auto Configure */
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#define VEC_AUTO 0 /* Set by Auto Configure */
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