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B5500: Normalized end of lines to DOS/Unix.

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This commit is contained in:
Richard Cornwell 2022-02-18 22:06:05 -05:00
parent 9f5e40e240
commit ba01a5793c
4 changed files with 20 additions and 20 deletions
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8
B5500/b5500_cpu.c
View file

@ -3073,7 +3073,7 @@ control:
} }
break; break;
} }
sim_debug(DEBUG_DETAIL, &cpu_dev, "IAR=%05o Q=%03o\n\r", sim_debug(DEBUG_DETAIL, &cpu_dev, "IAR=%05o Q=%03o\n",
IAR,Q); IAR,Q);
L = 0; L = 0;
S = 0100; S = 0100;
@ -3149,7 +3149,7 @@ control:
if (P2_run == 0 || (cpu_unit[1].flags & UNIT_DIS)) { if (P2_run == 0 || (cpu_unit[1].flags & UNIT_DIS)) {
break; break;
} }
sim_debug(DEBUG_DETAIL, &cpu_dev, "HALT P2\n\r"); sim_debug(DEBUG_DETAIL, &cpu_dev, "HALT P2\n");
/* Flag P2 to stop */ /* Flag P2 to stop */
hltf[1] = 1; hltf[1] = 1;
TROF = 1; /* Reissue until CPU2 stopped */ TROF = 1; /* Reissue until CPU2 stopped */
@ -3159,7 +3159,7 @@ control:
if (NCSF) if (NCSF)
break; break;
A_valid(); /* Load ICW */ A_valid(); /* Load ICW */
sim_debug(DEBUG_DETAIL, &cpu_dev, "INIT P1\n\r"); sim_debug(DEBUG_DETAIL, &cpu_dev, "INIT P1\n");
initiate(); initiate();
break; break;
@ -3180,7 +3180,7 @@ control:
cpu_index = 1; /* To CPU 2 */ cpu_index = 1; /* To CPU 2 */
Ma = 010; Ma = 010;
memory_cycle(4); memory_cycle(4);
sim_debug(DEBUG_DETAIL, &cpu_dev, "INIT P2\n\r"); sim_debug(DEBUG_DETAIL, &cpu_dev, "INIT P2\n");
initiate(); initiate();
break; break;

20
B5500/b5500_dk.c
View file

@ -233,7 +233,7 @@ t_stat dsk_srv(UNIT * uptr)
/* Map to ESU */ /* Map to ESU */
if (u && (dsk_unit[u].flags & DFX) == 0) if (u && (dsk_unit[u].flags & DFX) == 0)
esu += 10; esu += 10;
sim_debug(DEBUG_DETAIL, dptr, "Disk access %d %s %02o %d,%d\n\r", u, sim_debug(DEBUG_DETAIL, dptr, "Disk access %d %s %02o %d,%d\n", u,
(uptr->CMD & DK_RDCK) ? "rcheck" : (uptr->CMD & DK_RDCK) ? "rcheck" :
(uptr->CMD & DK_RD) ? "read" : (uptr->CMD & DK_RD) ? "read" :
(uptr->CMD & DK_WR)? "write" : "nop", (uptr->CMD >> 9) & 077, (uptr->CMD & DK_WR)? "write" : "nop", (uptr->CMD >> 9) & 077,
@ -255,11 +255,11 @@ t_stat dsk_srv(UNIT * uptr)
chan_set_eof(chan); chan_set_eof(chan);
if (uptr->CMD & DK_WR) { if (uptr->CMD & DK_WR) {
sim_debug(DEBUG_DETAIL, dptr, "Disk write int %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk write int %d %d %o\n",
uptr->ESU, uptr->ADDR, uptr->CMD); uptr->ESU, uptr->ADDR, uptr->CMD);
} }
if (uptr->CMD & DK_RD) { if (uptr->CMD & DK_RD) {
sim_debug(DEBUG_DETAIL, dptr, "Disk read int %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk read int %d %d %o\n",
uptr->ESU, uptr->ADDR, uptr->CMD); uptr->ESU, uptr->ADDR, uptr->CMD);
if (eptr->flags & MODIB) if (eptr->flags & MODIB)
chan_set_error(chan); chan_set_error(chan);
@ -302,7 +302,7 @@ void esu_set_end(UNIT *uptr, int err) {
int dsk = ((uptr->CMD & DK_CTRL) != 0); int dsk = ((uptr->CMD & DK_CTRL) != 0);
DEVICE *dptr = find_dev_from_unit(uptr); DEVICE *dptr = find_dev_from_unit(uptr);
sim_debug(DEBUG_DETAIL, dptr, "Disk done %d %d %o\n\r", uptr->POS, sim_debug(DEBUG_DETAIL, dptr, "Disk done %d %d %o\n", uptr->POS,
uptr->ADDR, uptr->CMD); uptr->ADDR, uptr->CMD);
if (err) if (err)
chan_set_error(chan); chan_set_error(chan);
@ -335,13 +335,13 @@ t_stat esu_srv(UNIT * uptr)
/* Check if over end of disk */ /* Check if over end of disk */
if (uptr->ADDR >= uptr->wait) { if (uptr->ADDR >= uptr->wait) {
sim_debug(DEBUG_DETAIL, dptr, "Disk read over %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk read over %d %d %o\n",
uptr->POS, uptr->ADDR, uptr->CMD); uptr->POS, uptr->ADDR, uptr->CMD);
chan_set_eof(chan); chan_set_eof(chan);
esu_set_end(uptr, 0); esu_set_end(uptr, 0);
return SCPE_OK; return SCPE_OK;
} }
sim_debug(DEBUG_DETAIL, dptr, "Disk read %d %d %d %o %d\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk read %d %d %d %o %d\n",
u,uptr->POS, uptr->ADDR, uptr->CMD, da); u,uptr->POS, uptr->ADDR, uptr->CMD, da);
if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) { if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) {
@ -369,13 +369,13 @@ t_stat esu_srv(UNIT * uptr)
/* Check if over end of disk */ /* Check if over end of disk */
if (uptr->ADDR >= uptr->wait) { if (uptr->ADDR >= uptr->wait) {
sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk over %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk over %d %d %o\n",
uptr->POS, uptr->ADDR, uptr->CMD); uptr->POS, uptr->ADDR, uptr->CMD);
uptr->CMD = 0; uptr->CMD = 0;
IAR |= IRQ_14 << dsk; IAR |= IRQ_14 << dsk;
return SCPE_OK; return SCPE_OK;
} }
sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk %d %d %d %o\n\r", u, sim_debug(DEBUG_DETAIL, dptr, "Disk rdchk %d %d %d %o\n", u,
uptr->POS, uptr->ADDR, uptr->CMD); uptr->POS, uptr->ADDR, uptr->CMD);
uptr->ADDR++; /* Advance disk address */ uptr->ADDR++; /* Advance disk address */
@ -416,14 +416,14 @@ t_stat esu_srv(UNIT * uptr)
/* Check if over end of disk */ /* Check if over end of disk */
if (uptr->ADDR >= uptr->wait) { if (uptr->ADDR >= uptr->wait) {
sim_debug(DEBUG_DETAIL, dptr, "Disk write over %d %d %o\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk write over %d %d %o\n",
uptr->POS, uptr->ADDR, uptr->CMD); uptr->POS, uptr->ADDR, uptr->CMD);
chan_set_eof(chan); chan_set_eof(chan);
esu_set_end(uptr, 0); esu_set_end(uptr, 0);
return SCPE_OK; return SCPE_OK;
} }
sim_debug(DEBUG_DETAIL, dptr, "Disk write %d %d %d %o %d\n\r", sim_debug(DEBUG_DETAIL, dptr, "Disk write %d %d %d %o %d\n",
u, uptr->POS, uptr->ADDR, uptr->CMD, da); u, uptr->POS, uptr->ADDR, uptr->CMD, da);
if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) { if (sim_fseek(uptr->fileref, da, SEEK_SET) < 0) {
esu_set_end(uptr, 1); esu_set_end(uptr, 1);

8
B5500/b5500_dr.c
View file

@ -91,7 +91,7 @@ t_stat drm_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc, uint8 rd_flg)
} }
if ((uptr->flags & (UNIT_BUF)) == 0) { if ((uptr->flags & (UNIT_BUF)) == 0) {
sim_debug(DEBUG_CMD, &drm_dev, "Drum not buffered\n\r"); sim_debug(DEBUG_CMD, &drm_dev, "Drum not buffered\n");
return SCPE_UNATT; return SCPE_UNATT;
} }
@ -105,7 +105,7 @@ t_stat drm_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc, uint8 rd_flg)
else else
uptr->CMD |= DR_WR; uptr->CMD |= DR_WR;
uptr->ADDR = cmd << 3; uptr->ADDR = cmd << 3;
sim_debug(DEBUG_CMD, &drm_dev, "Drum access %s %06o\n\r", sim_debug(DEBUG_CMD, &drm_dev, "Drum access %s %06o\n",
(uptr->CMD & DR_RD) ? "read" : "write", uptr->ADDR); (uptr->CMD & DR_RD) ? "read" : "write", uptr->ADDR);
sim_activate(uptr, 100); sim_activate(uptr, 100);
return SCPE_OK; return SCPE_OK;
@ -129,7 +129,7 @@ t_stat drm_srv(UNIT * uptr)
} }
uptr->ADDR++; uptr->ADDR++;
if (uptr->ADDR > ((int32)uptr->capac << 3)) { if (uptr->ADDR > ((int32)uptr->capac << 3)) {
sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n\r"); sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n");
uptr->CMD = DR_RDY; uptr->CMD = DR_RDY;
chan_set_error(chan); chan_set_error(chan);
chan_set_end(chan); chan_set_end(chan);
@ -148,7 +148,7 @@ t_stat drm_srv(UNIT * uptr)
} }
uptr->ADDR++; uptr->ADDR++;
if (uptr->ADDR > ((int32)uptr->capac << 3)) { if (uptr->ADDR > ((int32)uptr->capac << 3)) {
sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n\r"); sim_debug(DEBUG_CMD, &drm_dev, "Drum overrun\n");
uptr->CMD = DR_RDY; uptr->CMD = DR_RDY;
chan_set_error(chan); chan_set_error(chan);
chan_set_end(chan); chan_set_end(chan);

4
B5500/b5500_urec.c
View file

@ -1024,7 +1024,7 @@ con_srv(UNIT *uptr) {
if(chan_read_char(chan, &ch, 0)) { if(chan_read_char(chan, &ch, 0)) {
sim_putchar('\r'); sim_putchar('\r');
sim_putchar('\n'); sim_putchar('\n');
sim_debug(DEBUG_EXP, &con_dev, "\n\r"); sim_debug(DEBUG_EXP, &con_dev, "\n");
uptr->CMD &= ~URCSTA_FILL; uptr->CMD &= ~URCSTA_FILL;
chan_set_end(chan); chan_set_end(chan);
} else { } else {
@ -1041,7 +1041,7 @@ con_srv(UNIT *uptr) {
(con_data[0].inptr == con_data[0].outptr))) { (con_data[0].inptr == con_data[0].outptr))) {
sim_putchar('\r'); sim_putchar('\r');
sim_putchar('\n'); sim_putchar('\n');
sim_debug(DEBUG_EXP, &con_dev, "\n\r"); sim_debug(DEBUG_EXP, &con_dev, "\n");
uptr->CMD &= ~URCSTA_READ; uptr->CMD &= ~URCSTA_READ;
chan_set_end(chan); chan_set_end(chan);
} }