folkert/simh-testsetgenerator
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Fix to properly manage modem DCD and RNG state.

Browse source
This commit is contained in:
Mark Pizzolato 2013-04-17 09:32:48 -07:00
parent 0f078e9168
commit ba87329baa
2 changed files with 14 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
PDP11/pdp11_dz.c
View file

@ -430,12 +430,13 @@ char lineconfig[16];
TMLN *lp; TMLN *lp;
sim_debug(DBG_REG, &dz_dev, "dz_wr(PA=0x%08X [%s], access=%d, data=0x%X) ", PA, dz_wr_regs[(PA >> 1) & 03], access, data); sim_debug(DBG_REG, &dz_dev, "dz_wr(PA=0x%08X [%s], access=%d, data=0x%X) ", PA, dz_wr_regs[(PA >> 1) & 03], access, data);
sim_debug_bits(DBG_REG, &dz_dev, bitdefs[(PA >> 1) & 03], (uint32)data, (uint32)data, TRUE); sim_debug_bits(DBG_REG, &dz_dev, bitdefs[(PA >> 1) & 03], (uint32)((PA & 1) ? data<<8 : data), (uint32)((PA & 1) ? data<<8 : data), TRUE);
switch ((PA >> 1) & 03) { /* case on PA<2:1> */ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
case 00: /* CSR */ case 00: /* CSR */
if (access == WRITEB) data = (PA & 1)? /* byte? merge */ if (access == WRITEB)
data = (PA & 1)? /* byte? merge */
(dz_csr[dz] & 0377) | (data << 8): (dz_csr[dz] & 0377) | (data << 8):
(dz_csr[dz] & ~0377) | data; (dz_csr[dz] & ~0377) | data;
if (data & CSR_CLR) /* clr? reset */ if (data & CSR_CLR) /* clr? reset */
@ -473,10 +474,12 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
break; break;
case 02: /* TCR */ case 02: /* TCR */
if (access == WRITEB) data = (PA & 1)? /* byte? merge */ if (access == WRITEB)
data = (PA & 1)? /* byte? merge */
(dz_tcr[dz] & 0377) | (data << 8): (dz_tcr[dz] & 0377) | (data << 8):
(dz_tcr[dz] & ~0377) | data; (dz_tcr[dz] & ~0377) | data;
if (dz_mctl) { /* modem ctl? */ if (dz_mctl &&
((access != WRITEB) || (PA & 1))) { /* modem ctl (DTR)? */
int32 changed = data ^ dz_tcr[dz]; int32 changed = data ^ dz_tcr[dz];
for (i = 0; i < DZ_LINES; i++) { for (i = 0; i < DZ_LINES; i++) {
@ -484,10 +487,10 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
continue; /* line unchanged skip */ continue; /* line unchanged skip */
line = (dz * DZ_LINES) + i; /* get line num */ line = (dz * DZ_LINES) + i; /* get line num */
lp = &dz_ldsc[line]; /* get line desc */ lp = &dz_ldsc[line]; /* get line desc */
if (data & (1 << (TCR_V_DTR + i))) { if (data & (1 << (TCR_V_DTR + i))) { /* just asserted, so turn on */
tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL); tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL);
} }
else else /* just deasserted, so turn off */
if (dz_auto) if (dz_auto)
tmxr_set_get_modem_bits (lp, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL); tmxr_set_get_modem_bits (lp, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);
} }

2
sim_tmxr.c
View file

@ -1074,7 +1074,7 @@ if ((bits_to_set & ~(TMXR_MDM_OUTGOING)) || /* Assure only settable bits
return SCPE_ARG; return SCPE_ARG;
before_modem_bits = lp->modembits; before_modem_bits = lp->modembits;
lp->modembits |= bits_to_set; lp->modembits |= bits_to_set;
lp->modembits &= ~(bits_to_clear & TMXR_MDM_INCOMING); lp->modembits &= ~(bits_to_clear | TMXR_MDM_INCOMING);
if ((lp->sock) || (lp->serport)) { if ((lp->sock) || (lp->serport)) {
if (lp->modembits & TMXR_MDM_DTR) if (lp->modembits & TMXR_MDM_DTR)
incoming_state = TMXR_MDM_DCD | TMXR_MDM_CTS | TMXR_MDM_DSR; incoming_state = TMXR_MDM_DCD | TMXR_MDM_CTS | TMXR_MDM_DSR;