VAX: Change interval timers to pass boot ROM diagnostics.
Various boot ROM activities, including testing the Interval Timers, presume that ROM based code execute instructions at 1 instruction per usec. To accommodate this, we not only throttle memory accesses to ROM space, but we also use instruction based delays when the interval timers are programmed from the ROM for short duration delays.
This commit is contained in:
Mark Pizzolato
parent
77312ec8ca
commit
bcac7d0973
1 changed files with 65 additions and 37 deletions
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@ -248,6 +248,7 @@ int32 tmr_csr[2] = { 0 }; /* SSC timers */
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uint32 tmr_tir[2] = { 0 }; /* curr interval */
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uint32 tmr_tnir[2] = { 0 }; /* next interval */
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int32 tmr_tivr[2] = { 0 }; /* vector */
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t_bool tmr_inst[2] = { 0 }; /* wait instructions vs usecs */
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int32 ssc_adsm[2] = { 0 }; /* addr strobes */
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int32 ssc_adsk[2] = { 0 };
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int32 cdg_dat[CDASIZE >> 2]; /* cache data */
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@ -480,10 +481,12 @@ REG sysd_reg[] = {
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{ HRDATAD (TIR0, tmr_tir[0], 32, "SSC timer 0 interval register") },
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{ HRDATAD (TNIR0, tmr_tnir[0], 32, "SSC timer 0 next interval register") },
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{ HRDATAD (TIVEC0, tmr_tivr[0], 9, "SSC timer 0 interrupt vector register") },
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{ HRDATAD (TCSR1, tmr_csr[1], 32, "SSC timer 1 control/status register") },
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{ HRDATAD (TIVEC0, tmr_tivr[0], 9, "SSC timer 0 interrupt vector register") },
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{ FLDATAD (TINST0, tmr_inst[0], 0, "SSC timer 0 last wait instructions") },
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{ HRDATAD (TIR1, tmr_tir[1], 32, "SSC timer 1 interval register") },
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{ HRDATAD (TNIR1, tmr_tnir[1], 32, "SSC timer 1 next interval register") },
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{ HRDATAD (TIVEC1, tmr_tivr[1], 9, "SSC timer 1 interrupt vector register") },
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{ FLDATAD (TINST1, tmr_inst[1], 0, "SSC timer 1 last wait instructions") },
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{ HRDATAD (ADSM0, ssc_adsm[0], 32, "SSC address match 0 address") },
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{ HRDATAD (ADSK0, ssc_adsk[0], 32, "SSC address match 0 mask") },
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{ HRDATAD (ADSM1, ssc_adsm[1], 32, "SSC address match 1 address") },
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@ -551,37 +554,6 @@ uint32 i, l = rom_delay;
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if (rom_unit.flags & UNIT_NODELAY)
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return val;
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/* Calibrate the loop delay factor when first used.
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Do this 4 times and use the largest value computed. */
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if (rom_delay == 0) {
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uint32 ts, te, c = 10000, samples = 0;
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while (1) {
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c = c * 2;
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te = sim_os_msec();
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while (te == (ts = sim_os_msec ())); /* align on ms tick */
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/* This is merely a busy wait with some "work" that won't get optimized
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away by a good compiler. loopval always is zero. To avoid smart compilers,
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the loopval variable is referenced in the function arguments so that the
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function expression is not loop invariant. It also must be referenced
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by subsequent code to avoid the whole computation being eliminated. */
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for (i = 0; i < c; i++)
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rom_loopval |= (rom_loopval + ts) ^ rom_swapb (rom_swapb (rom_loopval + ts));
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te = sim_os_msec ();
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if ((te - ts) < 50) /* sample big enough? */
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continue;
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if (rom_delay < (rom_loopval + (c / (te - ts) / 1000) + 1))
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rom_delay = rom_loopval + (c / (te - ts) / 1000) + 1;
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if (++samples >= 4)
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break;
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c = c / 2;
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}
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if (rom_delay < 5)
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rom_delay = 5;
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}
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for (i = 0; i < l; i++)
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rom_loopval |= (rom_loopval + val) ^ rom_swapb (rom_swapb (rom_loopval + val));
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return val + rom_loopval;
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@ -636,6 +608,40 @@ t_stat rom_reset (DEVICE *dptr)
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{
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if (rom == NULL)
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rom = (uint32 *) calloc (ROMSIZE >> 2, sizeof (uint32));
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/* Calibrate the loop delay factor at startup.
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Do this 4 times and use the largest value computed.
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The goal here is to come up with a delay factor which will throttle
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a 6 byte delay loop running from ROM address space to execute
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1 instruction per usec */
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if (rom_delay == 0) {
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uint32 i, ts, te, c = 10000, samples = 0;
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while (1) {
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c = c * 2;
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te = sim_os_msec();
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while (te == (ts = sim_os_msec ())); /* align on ms tick */
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/* This is merely a busy wait with some "work" that won't get optimized
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away by a good compiler. loopval always is zero. To avoid smart compilers,
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the loopval variable is referenced in the function arguments so that the
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function expression is not loop invariant. It also must be referenced
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by subsequent code to avoid the whole computation being eliminated. */
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for (i = 0; i < c; i++)
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rom_loopval |= (rom_loopval + ts) ^ rom_swapb (rom_swapb (rom_loopval + ts));
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te = sim_os_msec ();
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if ((te - ts) < 50) /* sample big enough? */
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continue;
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if (rom_delay < (rom_loopval + (c / (te - ts) / 1000) + 1))
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rom_delay = rom_loopval + (c / (te - ts) / 1000) + 1;
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if (++samples >= 4)
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break;
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c = c / 2;
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}
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if (rom_delay < 5)
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rom_delay = 5;
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}
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if (rom == NULL)
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return SCPE_MEM;
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return SCPE_OK;
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@ -1509,7 +1515,7 @@ switch (rg) {
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with ticks due to the overhead that would be required for 1M
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clock events per second.
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The powerup TOY Test sometimes fails its tolerance test. This was
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The powerup TOY Test sometimes failed its tolerance test. This was
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due to varying system load causing varying calibration values to be
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used at different times while referencing the TIR. While timing long
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intervals, we now synchronize the stepping (and calibration) of the
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@ -1518,14 +1524,25 @@ switch (rg) {
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to measure the system clock), regardless of other load issues on the
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host system which might cause varying values of the system clock's
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calibration factor.
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Various ROM activities, including testing the Interval Timers, presume
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that ROM based code execute instructions at 1 instruction per usec.
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To accommodate this, we not only throttle memory accesses to ROM space,
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but we also use instruction based delays when the interval timers are
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programmed from the ROM for short duration delays.
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*/
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int32 tmr_tir_rd (int32 tmr)
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{
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if (tmr_csr[tmr] & TMR_CSR_RUN) { /* running? then interpolate */
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uint32 usecs_remaining = (uint32)sim_activate_time_usecs (&sysd_dev.units[tmr]);
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uint32 cur_tir = ~usecs_remaining + 1;
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uint32 usecs_remaining, cur_tir;
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if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */
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(tmr_inst[tmr])) /* waiting instructions? */
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usecs_remaining = sim_activate_time (&sysd_dev.units[tmr]) - 1;
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else
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usecs_remaining = (uint32)sim_activate_time_usecs (&sysd_dev.units[tmr]);
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cur_tir = ~usecs_remaining + 1;
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sim_debug (DBG_REGR, &sysd_dev, "tmr_tir_rd(tmr=%d) - 0x%X, Interpolated while running\n", tmr, cur_tir);
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return cur_tir;
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}
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@ -1628,9 +1645,19 @@ else {
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void tmr_sched (int32 tmr)
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{
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uint32 usecs_sched = tmr_tir[tmr] ? (~tmr_tir[tmr] + 1) : 0xFFFFFFFF;
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if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */
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(usecs_sched < TMR_INC)) { /* short delay? */
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tmr_inst[tmr] = TRUE; /* wait for instructions */
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sim_debug (DBG_SCHD, &sysd_dev, "tmr_sched(tmr=%d) - after %u instructions\n", tmr, usecs_sched);
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sim_activate (&sysd_unit[tmr], usecs_sched);
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}
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else {
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tmr_inst[tmr] = FALSE;
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sim_debug (DBG_SCHD, &sysd_dev, "tmr_sched(tmr=%d) - after %u usecs\n", tmr, usecs_sched);
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sim_activate_after (&sysd_unit[tmr], usecs_sched);
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}
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}
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int32 tmr0_inta (void)
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{
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@ -1760,6 +1787,7 @@ int32 i;
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if (sim_switches & SWMASK ('P')) sysd_powerup (); /* powerup? */
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for (i = 0; i < 2; i++) {
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tmr_csr[i] = tmr_tnir[i] = tmr_tir[i] = 0;
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tmr_inst[i] = FALSE;
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sim_cancel (&sysd_unit[i]);
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}
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csi_csr = 0;
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