diff --git a/PDP11/pdp11_dc.c b/PDP11/pdp11_dc.c index 65ecc1ea..b6e630a2 100644 --- a/PDP11/pdp11_dc.c +++ b/PDP11/pdp11_dc.c @@ -158,12 +158,13 @@ DIB dci_dib = { 2, IVCL (DCI), VEC_AUTO, { &dci_iack, &dco_iack }, IOLN_DC, }; -UNIT dci_unit = { UDATA (&dci_svc, 0, 0), KBD_POLL_WAIT }; +UNIT dci_unit = { UDATA (&dci_svc, 0, 0), SERIAL_IN_WAIT }; REG dci_reg[] = { { BRDATAD (BUF, dci_buf, DEV_RDX, 8, DCX_LINES, "input control/stats register") }, { BRDATAD (CSR, dci_csr, DEV_RDX, 16, DCX_LINES, "input buffer") }, { GRDATAD (IREQ, dci_ireq, DEV_RDX, DCX_LINES, 0, "interrupt requests") }, + { DRDATAD (TIME, dci_unit.wait, 24, "input polling interval"), PV_LEFT }, { DRDATA (LINES, dcx_desc.lines, 6), REG_HRO }, { GRDATA (DEVADDR, dci_dib.ba, DEV_RDX, 32, 0), REG_HRO }, { GRDATA (DEVIOLN, dci_dib.lnt, DEV_RDX, 32, 0), REG_HRO }, @@ -289,6 +290,7 @@ switch ((PA >> 1) & 03) { /* decode PA<2:1> */ case 01: /* dci buf */ dci_clr_int (ln); *data = dci_buf[ln]; + sim_activate_abs (&dci_unit, dci_unit.wait); return SCPE_OK; case 02: /* dco csr */ diff --git a/PDP11/pdp11_dl.c b/PDP11/pdp11_dl.c index d18973e3..f05d7354 100644 --- a/PDP11/pdp11_dl.c +++ b/PDP11/pdp11_dl.c @@ -122,11 +122,12 @@ DIB dli_dib = { 2, IVCL (DLI), VEC_AUTO, { &dli_iack, &dlo_iack }, IOLN_DL, }; -UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT }; +UNIT dli_unit = { UDATA (&dli_svc, 0, 0), SERIAL_IN_WAIT }; REG dli_reg[] = { { BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) }, { BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) }, + { DRDATAD (TIME, dli_unit.wait, 24, "input polling interval"), PV_LEFT }, { GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) }, { GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) }, { DRDATA (LINES, dlx_desc.lines, 6), REG_HRO }, @@ -245,6 +246,7 @@ switch ((PA >> 1) & 03) { /* decode PA<2:1> */ *data = dli_buf[ln] & DLIBUF_RD; dli_csr[ln] &= ~CSR_DONE; /* clr rcv done */ dli_clr_int (ln, DLI_RCI); /* clr rcv int req */ + sim_activate_abs (&dli_unit, dli_unit.wait); return SCPE_OK; case 02: /* tto csr */ diff --git a/PDP11/pdp11_stddev.c b/PDP11/pdp11_stddev.c index 0be6a39b..ca2f79d1 100644 --- a/PDP11/pdp11_stddev.c +++ b/PDP11/pdp11_stddev.c @@ -113,17 +113,17 @@ DIB tti_dib = { 1, IVCL (TTI), VEC_TTI, { NULL } }; -UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { - { ORDATA (BUF, tti_unit.buf, 8) }, - { ORDATA (CSR, tti_csr, 16) }, - { FLDATA (INT, IREQ (TTI), INT_V_TTI) }, - { FLDATA (ERR, tti_csr, CSR_V_ERR) }, - { FLDATA (DONE, tti_csr, CSR_V_DONE) }, - { FLDATA (IE, tti_csr, CSR_V_IE) }, - { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT }, - { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT }, + { HRDATAD (BUF, tti_unit.buf, 8, "last data item processed") }, + { HRDATAD (CSR, tti_csr, 16, "control/status register") }, + { FLDATAD (INT, IREQ (TTI), INT_V_TTI, "interrupt pending flag") }, + { FLDATAD (DONE, tti_csr, CSR_V_DONE, "device done flag (CSR<7>)") }, + { FLDATAD (ERR, tti_csr, CSR_V_ERR, "device error flag (CSR<15>)") }, + { FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT }, { NULL } }; @@ -258,6 +258,7 @@ switch ((PA >> 1) & 01) { /* decode PA<1> */ tti_csr = tti_csr & ~CSR_DONE; CLR_INT (TTI); *data = tti_unit.buf & 0377; + sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return SCPE_OK; } /* end switch PA */ diff --git a/PDP8/pdp8_tt.c b/PDP8/pdp8_tt.c index bd918d87..729f81f6 100644 --- a/PDP8/pdp8_tt.c +++ b/PDP8/pdp8_tt.c @@ -66,7 +66,7 @@ t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc); DIB tti_dib = { DEV_TTI, 1, { &tti } }; -UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_KSR, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { ORDATA (BUF, tti_unit.buf, 8) }, @@ -164,6 +164,7 @@ switch (IR & 07) { /* decode IR<9:11> */ case 6: /* KRB */ dev_done = dev_done & ~INT_TTI; /* clear flag */ int_req = int_req & ~INT_TTI; + sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return (tti_unit.buf); /* return buffer */ default: diff --git a/PDP8/pdp8_ttx.c b/PDP8/pdp8_ttx.c index e03655c2..198c28ff 100644 --- a/PDP8/pdp8_ttx.c +++ b/PDP8/pdp8_ttx.c @@ -92,7 +92,7 @@ void ttx_enbdis (int32 dis); DIB ttix_dib = { DEV_KJ8, 8, { &ttix, &ttox, &ttix, &ttox, &ttix, &ttox, &ttix, &ttox } }; -UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), KBD_POLL_WAIT }; +UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), SERIAL_IN_WAIT }; REG ttix_reg[] = { { BRDATA (BUF, ttix_buf, 8, 8, TTX_LINES) }, @@ -119,30 +119,12 @@ MTAB ttix_mod[] = { { 0 } }; -#define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */ -#define DBG_RCV TMXR_DBG_RCV /* display Received Data */ -#define DBG_MDM TMXR_DBG_MDM /* display Modem Signals */ -#define DBG_CON TMXR_DBG_CON /* display connection activities */ -#define DBG_TRC TMXR_DBG_TRC /* display trace routine calls */ -#define DBG_ASY TMXR_DBG_ASY /* display Asynchronous Activities */ - -DEBTAB ttx_debug[] = { - {"XMT", DBG_XMT}, - {"RCV", DBG_RCV}, - {"MDM", DBG_MDM}, - {"CON", DBG_CON}, - {"TRC", DBG_TRC}, - {"ASY", DBG_ASY}, - {0} -}; - DEVICE ttix_dev = { "TTIX", &ttix_unit, ttix_reg, ttix_mod, 1, 10, 31, 1, 8, 8, &tmxr_ex, &tmxr_dep, &ttix_reset, NULL, &ttx_attach, &ttx_detach, - &ttix_dib, DEV_DEBUG | DEV_MUX | DEV_DISABLE, - 0, ttx_debug + &ttix_dib, DEV_MUX | DEV_DISABLE, }; /* TTOx data structures @@ -188,8 +170,7 @@ DEVICE ttox_dev = { 4, 10, 31, 1, 8, 8, NULL, NULL, &ttox_reset, NULL, NULL, NULL, - NULL, DEV_DISABLE | DEV_DEBUG, - 0, ttx_debug + NULL, DEV_DISABLE }; /* Terminal input: IOT routine */ @@ -200,7 +181,6 @@ int32 pulse = inst & 07; /* IOT pulse */ int32 ln = TTX_GETLN (inst); /* line # */ int32 itti = (INT_TTI1 << ln); /* rx intr */ int32 itto = (INT_TTO1 << ln); /* tx intr */ -int32 itti_data; switch (pulse) { /* case IR<9:11> */ @@ -219,7 +199,7 @@ switch (pulse) { /* case IR<9:11> */ return 0; /* clear AC */ case 4: /* KRS */ - return ttix_buf[ln]; /* return buf */ + return (AC | ttix_buf[ln]); /* return buf */ case 5: /* KIE */ if (AC & 1) @@ -231,9 +211,8 @@ switch (pulse) { /* case IR<9:11> */ case 6: /* KRB */ dev_done = dev_done & ~itti; /* clear flag */ int_req = int_req & ~itti; - itti_data = ttix_buf[ln]; /* return buf */ sim_activate_abs (&ttix_unit, ttix_unit.wait); /* check soon for more input */ - return itti_data; + return ttix_buf[ln]; /* return buf */ default: return (stop_inst << IOT_V_REASON) + AC; diff --git a/VAX/vax610_stddev.c b/VAX/vax610_stddev.c index afb2e80e..8a55229c 100644 --- a/VAX/vax610_stddev.c +++ b/VAX/vax610_stddev.c @@ -107,7 +107,7 @@ extern int32 con_halt (int32 code, int32 cc); DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; -UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, @@ -238,6 +238,7 @@ int32 t = tti_unit.buf; /* char + error */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ CLR_INT (TTI); +sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return t; } diff --git a/VAX/vax630_stddev.c b/VAX/vax630_stddev.c index 6cda6973..d66cb362 100644 --- a/VAX/vax630_stddev.c +++ b/VAX/vax630_stddev.c @@ -82,7 +82,7 @@ extern int32 sysd_hlt_enb (void); DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; -UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, @@ -214,6 +214,7 @@ int32 t = tti_unit.buf; /* char + error */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ CLR_INT (TTI); +sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return t; } diff --git a/VAX/vax730_stddev.c b/VAX/vax730_stddev.c index 088ba6e1..71ddafe2 100644 --- a/VAX/vax730_stddev.c +++ b/VAX/vax730_stddev.c @@ -243,7 +243,7 @@ t_bool td_test_xfr (UNIT *uptr, int32 state); tti_reg TTI register list */ -UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, @@ -629,6 +629,7 @@ int32 t = tti_buf; /* char + error */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_buf = tti_buf & BMASK; /* clr errors */ tti_int = 0; +sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return t; } diff --git a/VAX/vax750_stddev.c b/VAX/vax750_stddev.c index d93f1447..9e68913f 100644 --- a/VAX/vax750_stddev.c +++ b/VAX/vax750_stddev.c @@ -243,7 +243,7 @@ extern int32 con_halt (int32 code, int32 cc); tti_reg TTI register list */ -UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, @@ -622,6 +622,7 @@ int32 t = tti_buf; /* char + error */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_buf = tti_buf & BMASK; /* clr errors */ tti_int = 0; +sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return t; } diff --git a/VAX/vax780_stddev.c b/VAX/vax780_stddev.c index 4e1d809a..63983255 100644 --- a/VAX/vax780_stddev.c +++ b/VAX/vax780_stddev.c @@ -259,7 +259,7 @@ extern int32 con_halt (int32 code, int32 cc); tti_reg TTI register list */ -UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (RXDB, tti_buf, 16, "last data item processed") }, @@ -443,6 +443,7 @@ int32 t = tti_buf; /* char + error */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_buf = tti_buf & BMASK; /* clr errors */ tti_int = 0; +sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return t; } diff --git a/VAX/vax860_stddev.c b/VAX/vax860_stddev.c index 387dceb8..c32efd9f 100644 --- a/VAX/vax860_stddev.c +++ b/VAX/vax860_stddev.c @@ -274,10 +274,10 @@ extern int32 con_halt (int32 code, int32 cc); */ UNIT tti_unit[] = { - { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, - { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, - { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, - { UDATA (&tti_svc, TT_MODE_8B, 0), 0 }, + { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }, + { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }, + { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }, + { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }, }; REG tti_reg[] = { diff --git a/VAX/vax_stddev.c b/VAX/vax_stddev.c index 501ee52a..8a5dc862 100644 --- a/VAX/vax_stddev.c +++ b/VAX/vax_stddev.c @@ -139,7 +139,7 @@ extern int32 fault_PC; DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } }; -UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), 0 }; +UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), SERIAL_IN_WAIT }; REG tti_reg[] = { { HRDATAD (BUF, tti_unit.buf, 16, "last data item processed") }, @@ -277,6 +277,7 @@ int32 t = tti_unit.buf; /* char + error */ tti_csr = tti_csr & ~CSR_DONE; /* clr done */ tti_unit.buf = tti_unit.buf & 0377; /* clr errors */ CLR_INT (TTI); +sim_activate_abs (&tti_unit, tti_unit.wait); /* check soon for more input */ return t; }