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All VAX: extend REI debugging support

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Identify reserved operand fault reason details.
This commit is contained in:
Mark Pizzolato 2018-09-27 06:41:40 -07:00
parent 0ca011cd46
commit be52190067
11 changed files with 41 additions and 63 deletions
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6
VAX/vax610_defs.h
View file

@ -330,12 +330,6 @@ typedef struct {
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */ extern int32 int_req[IPL_HLVL]; /* intr, IPL 14-17 */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* System model */ /* System model */
extern int32 sys_model; extern int32 sys_model;

6
VAX/vax630_defs.h
View file

@ -385,12 +385,6 @@ typedef struct {
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* Function prototypes for I/O */ /* Function prototypes for I/O */
int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);

6
VAX/vax730_defs.h
View file

@ -354,12 +354,6 @@ typedef struct {
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* Boot definitions */ /* Boot definitions */
#define BOOT_HK 1 /* device codes */ #define BOOT_HK 1 /* device codes */

6
VAX/vax750_defs.h
View file

@ -394,12 +394,6 @@ typedef struct {
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* Massbus definitions */ /* Massbus definitions */
#define MBA_RMASK 0x1F /* max 32 reg */ #define MBA_RMASK 0x1F /* max 32 reg */

6
VAX/vax780_defs.h
View file

@ -410,12 +410,6 @@ typedef struct {
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* Massbus definitions */ /* Massbus definitions */
#define MBA_RMASK 0x1F /* max 32 reg */ #define MBA_RMASK 0x1F /* max 32 reg */

6
VAX/vax860_defs.h
View file

@ -437,12 +437,6 @@ typedef struct {
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* Massbus definitions */ /* Massbus definitions */
#define MBA_RMASK 0x1F /* max 32 reg */ #define MBA_RMASK 0x1F /* max 32 reg */

6
VAX/vax_cpu.c
View file

@ -433,6 +433,10 @@ DEBTAB cpu_deb[] = {
{ "INTEXC", LOG_CPU_I, "interrupt and exception activities" }, { "INTEXC", LOG_CPU_I, "interrupt and exception activities" },
{ "REI", LOG_CPU_R, "REI activities" }, { "REI", LOG_CPU_R, "REI activities" },
{ "CONTEXT", LOG_CPU_P, "context switching activities" }, { "CONTEXT", LOG_CPU_P, "context switching activities" },
{ "RSVDFAULT", LOG_CPU_FAULT_RSVD, "reserved fault activities" },
{ "FLTFAULT", LOG_CPU_FAULT_FLT, "floating fault activities" },
{ "CMODFAULT", LOG_CPU_FAULT_CMODE, "cmode fault activities" },
{ "MCHKFAULT", LOG_CPU_FAULT_MCHK, "machine check fault activities" },
{ "EVENT", SIM_DBG_EVENT, "event dispatch activities" }, { "EVENT", SIM_DBG_EVENT, "event dispatch activities" },
{ "ACTIVATE", SIM_DBG_ACTIVATE, "queue insertion activities" }, { "ACTIVATE", SIM_DBG_ACTIVATE, "queue insertion activities" },
{ "ASYNCH", SIM_DBG_AIO_QUEUE, "asynch queue activities" }, { "ASYNCH", SIM_DBG_AIO_QUEUE, "asynch queue activities" },
@ -3654,7 +3658,7 @@ char args[CBUFSIZE];
t_stat r; t_stat r;
int32 saved_sim_switches = sim_switches; int32 saved_sim_switches = sim_switches;
sim_printf ("Loading boot code from %s%s\n", builtin_code ? "internal " : "", filename); sim_messagef (SCPE_OK, "Loading boot code from %s%s\n", builtin_code ? "internal " : "", filename);
if (builtin_code) if (builtin_code)
sim_set_memory_load_file (builtin_code, size); sim_set_memory_load_file (builtin_code, size);
if (rom) if (rom)

18
VAX/vax_cpu1.c
View file

@ -1201,6 +1201,11 @@ Rule SRM formulation Comment
9 tmp<31> = 1 => tmp<cur_mode> = 3, tmp<prv_mode> = 3>, tmp<fpd,is,ipl,dv,fu,iv> = 0 9 tmp<31> = 1 => tmp<cur_mode> = 3, tmp<prv_mode> = 3>, tmp<fpd,is,ipl,dv,fu,iv> = 0
*/ */
#define REI_RSVD_FAULT(desc) do { \
sim_debug (LOG_CPU_FAULT_RSVD, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x - %s\n",\
PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur]), desc); \
RSVD_OPND_FAULT; } while (0)
int32 op_rei (int32 acc) int32 op_rei (int32 acc)
{ {
int32 newpc = Read (SP, L_LONG, RA); int32 newpc = Read (SP, L_LONG, RA);
@ -1211,23 +1216,23 @@ int32 newipl, i;
if ((newpsl & PSL_MBZ) || /* rule 8 */ if ((newpsl & PSL_MBZ) || /* rule 8 */
(newcur < oldcur)) /* rule 1 */ (newcur < oldcur)) /* rule 1 */
RSVD_OPND_FAULT; REI_RSVD_FAULT("rule 8 or rule 1");
if (newcur) { /* to esu, skip 2,4,7 */ if (newcur) { /* to esu, skip 2,4,7 */
if ((newpsl & (PSL_IS | PSL_IPL)) || /* rules 3,5 */ if ((newpsl & (PSL_IS | PSL_IPL)) || /* rules 3,5 */
(newcur > PSL_GETPRV (newpsl))) /* rule 6 */ (newcur > PSL_GETPRV (newpsl))) /* rule 6 */
RSVD_OPND_FAULT; /* end rei to esu */ REI_RSVD_FAULT("rule 3,5 or rule 6"); /* end rei to esu */
} }
else { /* to k, skip 3,5,6 */ else { /* to k, skip 3,5,6 */
newipl = PSL_GETIPL (newpsl); /* get new ipl */ newipl = PSL_GETIPL (newpsl); /* get new ipl */
if ((newpsl & PSL_IS) && /* setting IS? */ if ((newpsl & PSL_IS) && /* setting IS? */
(((PSL & PSL_IS) == 0) || (newipl == 0))) /* test rules 2,4 */ (((PSL & PSL_IS) == 0) || (newipl == 0))) /* test rules 2,4 */
RSVD_OPND_FAULT; /* else skip 2,4 */ REI_RSVD_FAULT("rule 2 or rule 4"); /* else skip 2,4 */
if (newipl > PSL_GETIPL (PSL)) /* test rule 7 */ if (newipl > PSL_GETIPL (PSL)) /* test rule 7 */
RSVD_OPND_FAULT; REI_RSVD_FAULT("rule 7");
} /* end if kernel */ } /* end if kernel */
if (newpsl & PSL_CM) { /* setting cmode? */ if (newpsl & PSL_CM) { /* setting cmode? */
if (BadCmPSL (newpsl)) /* validate PSL */ if (BadCmPSL (newpsl)) /* validate PSL */
RSVD_OPND_FAULT; REI_RSVD_FAULT("cmode invalid PSL");
for (i = 0; i < 7; i++) /* mask R0-R6, PC */ for (i = 0; i < 7; i++) /* mask R0-R6, PC */
R[i] = R[i] & WMASK; R[i] = R[i] & WMASK;
newpc = newpc & WMASK; newpc = newpc & WMASK;
@ -1235,7 +1240,8 @@ if (newpsl & PSL_CM) { /* setting cmode? */
SP = SP + 8; /* pop stack */ SP = SP + 8; /* pop stack */
if (PSL & PSL_IS) /* save stack */ if (PSL & PSL_IS) /* save stack */
IS = SP; IS = SP;
else STK[oldcur] = SP; else
STK[oldcur] = SP;
sim_debug (LOG_CPU_R, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x\n", sim_debug (LOG_CPU_R, &cpu_dev, "PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x\n",
PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur])); PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur]));
PSL = (PSL & PSL_TP) | (newpsl & ~CC_MASK); /* set PSL */ PSL = (PSL & PSL_TP) | (newpsl & ~CC_MASK); /* set PSL */

10
VAX/vax_defs.h
View file

@ -87,6 +87,16 @@ extern jmp_buf save_env;
#define CMODE_FAULT(cd) p1 = (cd), ABORT (ABORT_CMODE) #define CMODE_FAULT(cd) p1 = (cd), ABORT (ABORT_CMODE)
#define MACH_CHECK(cd) p1 = (cd), ABORT (ABORT_MCHK) #define MACH_CHECK(cd) p1 = (cd), ABORT (ABORT_MCHK)
/* Logging */
#define LOG_CPU_I 0x001 /* intexc */
#define LOG_CPU_R 0x002 /* REI */
#define LOG_CPU_P 0x004 /* process context */
#define LOG_CPU_FAULT_RSVD 0x008 /* reserved faults */
#define LOG_CPU_FAULT_FLT 0x010 /* floating faults*/
#define LOG_CPU_FAULT_CMODE 0x020 /* cmode faults */
#define LOG_CPU_FAULT_MCHK 0x040 /* machine check faults */
/* Recovery queue */ /* Recovery queue */
#define RQ_RN 0xF /* register */ #define RQ_RN 0xF /* register */

6
VAX/vaxmod_defs.h
View file

@ -437,12 +437,6 @@ typedef struct {
#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
/* Logging */
#define LOG_CPU_I 0x1 /* intexc */
#define LOG_CPU_R 0x2 /* REI */
#define LOG_CPU_P 0x4 /* context */
/* Function prototypes for I/O */ /* Function prototypes for I/O */
int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);

14
sim_defs.h
View file

@ -855,13 +855,13 @@ struct DEBTAB {
#define DEBUG_PRI(d,m) (sim_deb && (d.dctrl & (m))) #define DEBUG_PRI(d,m) (sim_deb && (d.dctrl & (m)))
#define DEBUG_PRJ(d,m) (sim_deb && ((d)->dctrl & (m))) #define DEBUG_PRJ(d,m) (sim_deb && ((d)->dctrl & (m)))
#define SIM_DBG_EVENT 0x010000 /* event dispatch activities */ #define SIM_DBG_EVENT 0x01000000 /* event dispatch activities */
#define SIM_DBG_ACTIVATE 0x020000 /* queue insertion activities */ #define SIM_DBG_ACTIVATE 0x02000000 /* queue insertion activities */
#define SIM_DBG_AIO_QUEUE 0x040000 /* asynch event queue activities */ #define SIM_DBG_AIO_QUEUE 0x04000000 /* asynch event queue activities */
#define SIM_DBG_EXP_STACK 0x080000 /* expression stack activities */ #define SIM_DBG_EXP_STACK 0x08000000 /* expression stack activities */
#define SIM_DBG_EXP_EVAL 0x100000 /* expression evaluation activities */ #define SIM_DBG_EXP_EVAL 0x10000000 /* expression evaluation activities */
#define SIM_DBG_BRK_ACTION 0x200000 /* action activities */ #define SIM_DBG_BRK_ACTION 0x20000000 /* action activities */
#define SIM_DBG_DO 0x400000 /* do activities */ #define SIM_DBG_DO 0x40000000 /* do activities */
/* Open File Reference */ /* Open File Reference */
struct FILEREF { struct FILEREF {