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B5500: Added macros to detect buffer empty to remove compiler warnings.

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b5500_mt.c: Changed checking of hwmark from -1 to 0xfffffff.
This commit is contained in:
Richard Cornwell 2016-02-08 17:08:06 -05:00
parent 02aa4539cd
commit c45878feb3
1 changed files with 44 additions and 41 deletions
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63
B5500/b5500_mt.c
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@ -76,6 +76,9 @@
#define MT_LOADED 0040000 /* Tape loaded, return ready */ #define MT_LOADED 0040000 /* Tape loaded, return ready */
#define BUF_EMPTY(u) (u->hwmark == 0xFFFFFFFF)
#define CLR_BUF(u) u->hwmark = 0xFFFFFFFF
t_stat mt_srv(UNIT *); t_stat mt_srv(UNIT *);
t_stat mt_attach(UNIT *, char *); t_stat mt_attach(UNIT *, char *);
t_stat mt_detach(UNIT *); t_stat mt_detach(UNIT *);
@ -200,8 +203,8 @@ mt_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
if (cmd & URCSTA_DIRECT) if (cmd & URCSTA_DIRECT)
uptr->u5 |= MT_BACK; uptr->u5 |= MT_BACK;
uptr->u6 = 0; uptr->u6 = 0;
uptr->hwmark = -1; CLR_BUF(uptr);
sim_debug(DEBUG_CMD, &mt_dev, "Command %d %o %o\n\r", unit, uptr->u5, cmd); sim_debug(DEBUG_CMD, &mt_dev, "Command %d %o %o\n", unit, uptr->u5, cmd);
if ((uptr->u5 & MT_IDLE) == 0) { if ((uptr->u5 & MT_IDLE) == 0) {
sim_activate(uptr,50000); sim_activate(uptr,50000);
} }
@ -281,14 +284,14 @@ t_stat mt_srv(UNIT * uptr)
if (uptr->u5 & MT_LOADED) { if (uptr->u5 & MT_LOADED) {
uptr->u5 &= ~MT_LOADED; uptr->u5 &= ~MT_LOADED;
uptr->u5 |= MT_BSY|MT_RDY; uptr->u5 |= MT_BSY|MT_RDY;
sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Loaded\n\r", unit); sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Loaded\n", unit);
sim_activate(uptr, 50000); sim_activate(uptr, 50000);
return SCPE_OK; return SCPE_OK;
} }
if (uptr->u5 & MT_BSY) { if (uptr->u5 & MT_BSY) {
uptr->u5 &= ~MT_BSY; uptr->u5 &= ~MT_BSY;
sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Online\n\r", unit); sim_debug(DEBUG_DETAIL, dptr, "Unit=%d Online\n", unit);
iostatus |= 1 << (uptr - mt_unit); iostatus |= 1 << (uptr - mt_unit);
if (uptr->u5 & MT_IDLE) if (uptr->u5 & MT_IDLE)
sim_activate(uptr, 50000); sim_activate(uptr, 50000);
@ -298,10 +301,10 @@ t_stat mt_srv(UNIT * uptr)
if (uptr->u5 & MT_IDLE) { if (uptr->u5 & MT_IDLE) {
uptr->u5 &= ~MT_IDLE; uptr->u5 &= ~MT_IDLE;
if (uptr->u5 & MT_RDY) { if (uptr->u5 & MT_RDY) {
sim_debug(DEBUG_DETAIL, dptr, "Unit=%d idling\n\r", unit); sim_debug(DEBUG_DETAIL, dptr, "Unit=%d idling\n", unit);
return SCPE_OK; return SCPE_OK;
} }
sim_debug(DEBUG_DETAIL, dptr, "Unit=%d start %02o\n\r", unit, cmd); sim_debug(DEBUG_DETAIL, dptr, "Unit=%d start %02o\n", unit, cmd);
} }
switch (cmd) { switch (cmd) {
@ -312,12 +315,12 @@ t_stat mt_srv(UNIT * uptr)
uptr->u5 &= ~(MT_CMD|MT_BIN); uptr->u5 &= ~(MT_CMD|MT_BIN);
uptr->u5 |= MT_RDY; uptr->u5 |= MT_RDY;
chan_set_end(chan); chan_set_end(chan);
sim_debug(DEBUG_DETAIL, dptr, "Status\n\r"); sim_debug(DEBUG_DETAIL, dptr, "Status\n");
return SCPE_OK; return SCPE_OK;
case MT_RD: /* Read */ case MT_RD: /* Read */
/* If at end of record, fill buffer */ /* If at end of record, fill buffer */
if (uptr->hwmark == -1) { if (BUF_EMPTY(uptr)) {
sim_debug(DEBUG_DETAIL, dptr, "Read unit=%d %s ", unit, sim_debug(DEBUG_DETAIL, dptr, "Read unit=%d %s ", unit,
(uptr->u5 & MT_BIN)? "bin": "bcd"); (uptr->u5 & MT_BIN)? "bin": "bcd");
if (sim_tape_eot(uptr)) { if (sim_tape_eot(uptr)) {
@ -327,12 +330,12 @@ t_stat mt_srv(UNIT * uptr)
r = sim_tape_rdrecf(uptr, &mt_buffer[chan][0], &reclen, BUFFSIZE); r = sim_tape_rdrecf(uptr, &mt_buffer[chan][0], &reclen, BUFFSIZE);
if (r != MTSE_OK) { if (r != MTSE_OK) {
if (r == MTSE_TMK) { if (r == MTSE_TMK) {
sim_debug(DEBUG_DETAIL, dptr, "TM\n\r"); sim_debug(DEBUG_DETAIL, dptr, "TM\n");
ch = 017; ch = 017;
(void)chan_write_char(chan, &ch, 1); (void)chan_write_char(chan, &ch, 1);
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
} else { } else {
sim_debug(DEBUG_DETAIL, dptr, "r=%d\n\r", r); sim_debug(DEBUG_DETAIL, dptr, "r=%d\n", r);
sim_activate(uptr, 5000); sim_activate(uptr, 5000);
} }
return mt_error(uptr, chan, r, dptr); return mt_error(uptr, chan, r, dptr);
@ -340,7 +343,7 @@ t_stat mt_srv(UNIT * uptr)
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->u5 &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
} }
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n\r", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
uptr->u6 = 0; uptr->u6 = 0;
if ((uptr->u5 & MT_BIN) == 0) if ((uptr->u5 & MT_BIN) == 0)
mode = 0100; mode = 0100;
@ -368,12 +371,12 @@ t_stat mt_srv(UNIT * uptr)
if (chan_write_char(chan, &ch, if (chan_write_char(chan, &ch,
(((uint32)uptr->u6) >= uptr->hwmark) ? 1 : 0)) { (((uint32)uptr->u6) >= uptr->hwmark) ? 1 : 0)) {
sim_debug(DEBUG_DATA, dptr, "Read unit=%d %d EOR\n\r", unit, sim_debug(DEBUG_DATA, dptr, "Read unit=%d %d EOR\n", unit,
uptr->hwmark-uptr->u6); uptr->hwmark-uptr->u6);
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
} else { } else {
sim_debug(DEBUG_DATA, dptr, "Read data unit=%d %d %03o\n\r", sim_debug(DEBUG_DATA, dptr, "Read data unit=%d %d %03o\n",
unit, uptr->u6, ch); unit, uptr->u6, ch);
sim_activate(uptr, HT); sim_activate(uptr, HT);
} }
@ -381,7 +384,7 @@ t_stat mt_srv(UNIT * uptr)
case MT_RDBK: /* Read Backword */ case MT_RDBK: /* Read Backword */
/* If at end of record, fill buffer */ /* If at end of record, fill buffer */
if (uptr->hwmark == -1) { if (BUF_EMPTY(uptr)) {
sim_debug(DEBUG_DETAIL, dptr, "Read back unit=%d %s ", unit, sim_debug(DEBUG_DETAIL, dptr, "Read back unit=%d %s ", unit,
(uptr->u5 & MT_BIN)? "bin": "bcd"); (uptr->u5 & MT_BIN)? "bin": "bcd");
if (sim_tape_bot(uptr)) { if (sim_tape_bot(uptr)) {
@ -391,13 +394,13 @@ t_stat mt_srv(UNIT * uptr)
r = sim_tape_rdrecr(uptr, &mt_buffer[chan][0], &reclen, BUFFSIZE); r = sim_tape_rdrecr(uptr, &mt_buffer[chan][0], &reclen, BUFFSIZE);
if (r != MTSE_OK) { if (r != MTSE_OK) {
if (r == MTSE_TMK) { if (r == MTSE_TMK) {
sim_debug(DEBUG_DETAIL, dptr, "TM\n\r"); sim_debug(DEBUG_DETAIL, dptr, "TM\n");
ch = 017; ch = 017;
(void)chan_write_char(chan, &ch, 1); (void)chan_write_char(chan, &ch, 1);
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
} else { } else {
uptr->u5 |= MT_BSY; uptr->u5 |= MT_BSY;
sim_debug(DEBUG_DETAIL, dptr, "r=%d\n\r", r); sim_debug(DEBUG_DETAIL, dptr, "r=%d\n", r);
sim_activate(uptr, 100); sim_activate(uptr, 100);
} }
return mt_error(uptr, chan, r, dptr); return mt_error(uptr, chan, r, dptr);
@ -405,7 +408,7 @@ t_stat mt_srv(UNIT * uptr)
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->u5 &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
} }
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n\r", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
uptr->u6 = uptr->hwmark; uptr->u6 = uptr->hwmark;
if ((uptr->u5 & MT_BIN) == 0) if ((uptr->u5 & MT_BIN) == 0)
mode = 0100; mode = 0100;
@ -432,12 +435,12 @@ t_stat mt_srv(UNIT * uptr)
} }
if (chan_write_char(chan, &ch, (uptr->u6 > 0) ? 0 : 1)) { if (chan_write_char(chan, &ch, (uptr->u6 > 0) ? 0 : 1)) {
sim_debug(DEBUG_DATA, dptr, "Read back unit=%d %d EOR\n\r", sim_debug(DEBUG_DATA, dptr, "Read back unit=%d %d EOR\n",
unit, uptr->hwmark-uptr->u6); unit, uptr->hwmark-uptr->u6);
sim_activate(uptr, 100); sim_activate(uptr, 100);
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
} else { } else {
sim_debug(DEBUG_DATA, dptr, "Read back data unit=%d %d %03o\n\r", sim_debug(DEBUG_DATA, dptr, "Read back data unit=%d %d %03o\n",
unit, uptr->u6, ch); unit, uptr->u6, ch);
sim_activate(uptr, HT); sim_activate(uptr, HT);
} }
@ -454,16 +457,16 @@ t_stat mt_srv(UNIT * uptr)
reclen = uptr->u6; reclen = uptr->u6;
/* If no transfer, then either erase */ /* If no transfer, then either erase */
if (reclen == 0) { if (reclen == 0) {
sim_debug(DEBUG_DETAIL, dptr, "Erase\n\r"); sim_debug(DEBUG_DETAIL, dptr, "Erase\n");
r = MTSE_OK; r = MTSE_OK;
} else if ((reclen == 1) && (cmd & MT_BIN) == 0 && } else if ((reclen == 1) && (cmd & MT_BIN) == 0 &&
(mt_buffer[chan][0] == 017)) { (mt_buffer[chan][0] == 017)) {
/* Check if write rtape mark */ /* Check if write rtape mark */
sim_debug(DEBUG_DETAIL, dptr, "Write Mark unit=%d\n\r", unit); sim_debug(DEBUG_DETAIL, dptr, "Write Mark unit=%d\n", unit);
r = sim_tape_wrtmk(uptr); r = sim_tape_wrtmk(uptr);
} else { } else {
sim_debug(DEBUG_DETAIL, dptr, sim_debug(DEBUG_DETAIL, dptr,
"Write unit=%d Block %d %s chars\n\r", unit, reclen, "Write unit=%d Block %d %s chars\n", unit, reclen,
(uptr->u5 & MT_BIN)? "bin": "bcd"); (uptr->u5 & MT_BIN)? "bin": "bcd");
r = sim_tape_wrrecf(uptr, &mt_buffer[chan][0], reclen); r = sim_tape_wrrecf(uptr, &mt_buffer[chan][0], reclen);
} }
@ -479,7 +482,7 @@ t_stat mt_srv(UNIT * uptr)
/* Don't write out even parity zeros */ /* Don't write out even parity zeros */
if (ch != 0) if (ch != 0)
mt_buffer[chan][uptr->u6++] = ch; mt_buffer[chan][uptr->u6++] = ch;
sim_debug(DEBUG_DATA, dptr, "Write data unit=%d %d %03o\n\r", sim_debug(DEBUG_DATA, dptr, "Write data unit=%d %d %03o\n",
unit, uptr->u6, ch); unit, uptr->u6, ch);
uptr->hwmark = uptr->u6; uptr->hwmark = uptr->u6;
} }
@ -487,12 +490,12 @@ t_stat mt_srv(UNIT * uptr)
return SCPE_OK; return SCPE_OK;
case MT_FSR: /* Space forward one record */ case MT_FSR: /* Space forward one record */
if (uptr->hwmark == -1) { if (BUF_EMPTY(uptr)) {
/* If at end of record, fill buffer */ /* If at end of record, fill buffer */
sim_debug(DEBUG_DETAIL, dptr, "Space unit=%d ", unit); sim_debug(DEBUG_DETAIL, dptr, "Space unit=%d ", unit);
if (sim_tape_eot(uptr)) { if (sim_tape_eot(uptr)) {
uptr->u5 &= ~MT_BOT; uptr->u5 &= ~MT_BOT;
sim_debug(DEBUG_DETAIL, dptr, "EOT\r\n"); sim_debug(DEBUG_DETAIL, dptr, "EOT\n");
sim_activate(uptr, 4000); sim_activate(uptr, 4000);
return mt_error(uptr, chan, MTSE_EOM, dptr); return mt_error(uptr, chan, MTSE_EOM, dptr);
} }
@ -509,7 +512,7 @@ t_stat mt_srv(UNIT * uptr)
} }
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->u5 &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n\r", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
sim_activate(uptr, uptr->hwmark * HT); sim_activate(uptr, uptr->hwmark * HT);
return SCPE_OK; return SCPE_OK;
} }
@ -517,11 +520,11 @@ t_stat mt_srv(UNIT * uptr)
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
case MT_BSR: /* Backspace record */ case MT_BSR: /* Backspace record */
if (uptr->hwmark == -1) { if (BUF_EMPTY(uptr)) {
/* If at end of record, fill buffer */ /* If at end of record, fill buffer */
sim_debug(DEBUG_DETAIL, dptr, "backspace unit=%d ", unit); sim_debug(DEBUG_DETAIL, dptr, "backspace unit=%d ", unit);
if (sim_tape_bot(uptr)) { if (sim_tape_bot(uptr)) {
sim_debug(DEBUG_DETAIL, dptr, "BOT\n\r"); sim_debug(DEBUG_DETAIL, dptr, "BOT\n");
sim_activate(uptr, 100); sim_activate(uptr, 100);
return mt_error(uptr, chan, MTSE_BOT, dptr); return mt_error(uptr, chan, MTSE_BOT, dptr);
} }
@ -538,7 +541,7 @@ t_stat mt_srv(UNIT * uptr)
} }
uptr->u5 &= ~(MT_BOT|MT_EOT); uptr->u5 &= ~(MT_BOT|MT_EOT);
uptr->hwmark = reclen; uptr->hwmark = reclen;
sim_debug(DEBUG_DETAIL, dptr, "%d chars\n\r", uptr->hwmark); sim_debug(DEBUG_DETAIL, dptr, "%d chars\n", uptr->hwmark);
sim_activate(uptr, uptr->hwmark * HT); sim_activate(uptr, uptr->hwmark * HT);
return SCPE_OK; return SCPE_OK;
} }
@ -546,7 +549,7 @@ t_stat mt_srv(UNIT * uptr)
return mt_error(uptr, chan, MTSE_OK, dptr); return mt_error(uptr, chan, MTSE_OK, dptr);
case MT_REW: /* Rewind */ case MT_REW: /* Rewind */
sim_debug(DEBUG_DETAIL, dptr, "Rewind unit=%d pos=%d\n\r", unit, sim_debug(DEBUG_DETAIL, dptr, "Rewind unit=%d pos=%d\n", unit,
uptr->pos); uptr->pos);
uptr->u5 &= ~(MT_CMD | MT_BIN | MT_IDLE | MT_RDY); uptr->u5 &= ~(MT_CMD | MT_BIN | MT_IDLE | MT_RDY);
uptr->u5 |= MT_BSY|MT_RDY; uptr->u5 |= MT_BSY|MT_RDY;