VAX780: Fix Interval Timer logic
- Previous changes made to support 32V's 60HZ clock tick introduced changes which didn't properly handle increments and interrupt generation while single stepping the timer. - The icr_rd routine returned an incorrect value when interpolation was necessary due to a missing cast when converting from double to uint32. - Properly start the timer from the current state of the interval count register when the timer was previously stopped.
This commit is contained in:
Mark Pizzolato
parent
b935a2dafc
commit
c5d5a9dfbf
3 changed files with 123 additions and 31 deletions
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@ -134,6 +134,18 @@ static BITFIELD tx_buf_bits[] = {
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#define CLK_DELAY 5000 /* 100 Hz */
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#define TMXR_MULT 1 /* 100 Hz */
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static BITFIELD tmr_iccs_bits [] = {
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BIT(RUN), /* Run */
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BITNCF(3), /* unused */
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BIT(XFR), /* Transfer */
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BIT(SGL), /* Single */
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BIT(IE), /* Interrupt Enable */
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BIT(DON), /* Done */
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BITNCF(23), /* unused */
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BIT(ERR), /* Error */
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ENDBITS
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};
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/* TU58 definitions */
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#define UNIT_V_WLK (UNIT_V_UF) /* write locked */
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@ -301,22 +313,36 @@ DEVICE clk_dev = {
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UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
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REG tmr_reg[] = {
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{ HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") },
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{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
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{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
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{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
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{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
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{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
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{ FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN },
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{ HRDATADF (ICCS, tmr_iccs, 32, "interval timer control and status", tmr_iccs_bits) },
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{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
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{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
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{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
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{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
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{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
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{ FLDATA (USE100HZ, tmr_use_100hz, 0), REG_HIDDEN },
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{ NULL }
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};
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#define TMR_DB_REG 0x01 /* Register Access */
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#define TMR_DB_TICK 0x02 /* Ticks */
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#define TMR_DB_SCHED 0x04 /* Scheduling */
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#define TMR_DB_INT 0x08 /* Interrupts */
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DEBTAB tmr_deb[] = {
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{ "REG", TMR_DB_REG, "Register Access"},
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{ "TICK", TMR_DB_TICK, "Ticks"},
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{ "SCHED", TMR_DB_SCHED, "Ticks"},
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{ "INT", TMR_DB_INT, "Interrupts"},
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{ NULL, 0 }
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};
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DEVICE tmr_dev = {
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"TMR", &tmr_unit, tmr_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &tmr_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, DEV_DEBUG, 0,
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tmr_deb, NULL, NULL, NULL, NULL, NULL,
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&tmr_description
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};
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@ -627,11 +653,13 @@ return "console terminal output";
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int32 iccs_rd (void)
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{
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sim_debug (TMR_DB_REG, &tmr_dev, "iccs_rd() = 0x%08X\n", tmr_iccs & TMR_CSR_RD);
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return tmr_iccs & TMR_CSR_RD;
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}
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void iccs_wr (int32 val)
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{
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, val, val, TRUE);
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if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
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sim_cancel (&tmr_unit); /* cancel timer */
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tmr_use_100hz = 0;
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@ -654,8 +682,12 @@ else if (val & TMR_CSR_SGL) { /* single step? */
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tmr_icr = tmr_nicr; /* reload tir */
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}
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if ((tmr_iccs & (TMR_CSR_DON | TMR_CSR_IE)) != /* update int */
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(TMR_CSR_DON | TMR_CSR_IE))
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tmr_int = 0;
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(TMR_CSR_DON | TMR_CSR_IE)) {
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if (tmr_int) {
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tmr_int = 0;
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sim_debug (TMR_DB_INT, &tmr_dev, "iccs_wr() - INT=0\n");
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}
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}
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return;
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}
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@ -669,18 +701,22 @@ if (interp || (tmr_iccs & TMR_CSR_RUN)) { /* interp, running? */
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delta = (uint32) ((((double) delta) * TMR_INC) / tmr_poll);
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if (delta >= tmr_inc)
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delta = tmr_inc - 1;
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sim_debug (TMR_DB_REG, &tmr_dev, "icr_rd() = 0x%08X\n", tmr_icr + delta);
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return tmr_icr + delta;
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}
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sim_debug (TMR_DB_REG, &tmr_dev, "icr_rd() = 0x%08X\n", tmr_icr);
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return tmr_icr;
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}
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int32 nicr_rd (void)
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{
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sim_debug (TMR_DB_REG, &tmr_dev, "nicr_rd() = 0x%08X\n", tmr_nicr);
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return tmr_nicr;
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}
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void nicr_wr (int32 val)
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{
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sim_debug (TMR_DB_REG, &tmr_dev, "nicr_wr(0x%08X)\n", val);
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tmr_nicr = val;
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}
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@ -688,6 +724,7 @@ tmr_nicr = val;
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t_stat clk_svc (UNIT *uptr)
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{
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sim_debug (TMR_DB_TICK, &tmr_dev, "clk_svc()\n");
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tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
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sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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@ -701,6 +738,7 @@ return SCPE_OK;
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t_stat tmr_svc (UNIT *uptr)
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{
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sim_debug (TMR_DB_TICK, &tmr_dev, "tmr_svc()\n");
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tmr_incr (tmr_inc); /* incr timer */
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return SCPE_OK;
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}
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@ -720,8 +758,10 @@ if (new_icr < tmr_icr) { /* ovflo? */
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tmr_icr = tmr_nicr; /* reload */
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tmr_sched (); /* reactivate */
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}
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if (tmr_iccs & TMR_CSR_IE) /* ie? set int req */
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if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */
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tmr_int = 1;
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sim_debug (TMR_DB_INT, &tmr_dev, "tmr_incr() - INT=1\n");
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}
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else tmr_int = 0;
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}
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else {
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@ -739,6 +779,7 @@ void tmr_sched (void)
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tmr_sav = sim_grtime (); /* save intvl base */
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tmr_inc = (~tmr_icr + 1); /* inc = interval */
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if (tmr_inc == 0) tmr_inc = 1;
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sim_debug (TMR_DB_SCHED, &tmr_dev, "tmr_sched(0x%08X)\n", tmr_inc);
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if (tmr_inc < TMR_INC) { /* 100Hz multiple? */
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sim_activate (&tmr_unit, tmr_inc); /* schedule timer */
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tmr_use_100hz = 0;
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@ -137,6 +137,18 @@
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#define CLK_DELAY 5000 /* 100 Hz */
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#define TMXR_MULT 1 /* 100 Hz */
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static BITFIELD tmr_iccs_bits [] = {
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BIT(RUN), /* Run */
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BITNCF(3), /* unused */
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BIT(XFR), /* Transfer */
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BIT(SGL), /* Single */
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BIT(IE), /* Interrupt Enable */
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BIT(DON), /* Done */
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BITNCF(23), /* unused */
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BIT(ERR), /* Error */
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ENDBITS
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};
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/* Floppy definitions */
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#define FL_NUMTR 77 /* tracks/disk */
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@ -347,21 +359,35 @@ DEVICE clk_dev = {
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UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
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REG tmr_reg[] = {
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{ HRDATAD (ICCS, tmr_iccs, 32, "interval timer control and status") },
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{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
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{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
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{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
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{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
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{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
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{ HRDATADF (ICCS, tmr_iccs, 32, "interval timer control and status", tmr_iccs_bits) },
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{ HRDATAD (ICR, tmr_icr, 32, "interval count register") },
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{ HRDATAD (NICR, tmr_nicr, 32, "next interval count register") },
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{ FLDATAD (INT, tmr_int, 0, "interrupt request") },
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{ HRDATA (INCR, tmr_inc, 32), REG_HIDDEN },
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{ HRDATA (SAVE, tmr_sav, 32), REG_HIDDEN },
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{ NULL }
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};
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#define TMR_DB_REG 0x01 /* Register Access */
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#define TMR_DB_TICK 0x02 /* Ticks */
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#define TMR_DB_SCHED 0x04 /* Scheduling */
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#define TMR_DB_INT 0x08 /* Interrupts */
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DEBTAB tmr_deb[] = {
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{ "REG", TMR_DB_REG, "Register Access"},
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{ "TICK", TMR_DB_TICK, "Ticks"},
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{ "SCHED", TMR_DB_SCHED, "Ticks"},
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{ "INT", TMR_DB_INT, "Interrupts"},
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{ NULL, 0 }
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};
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DEVICE tmr_dev = {
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"TMR", &tmr_unit, tmr_reg, NULL,
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1, 0, 0, 0, 0, 0,
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NULL, NULL, &tmr_reset,
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NULL, NULL, NULL,
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NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, DEV_DEBUG, 0,
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tmr_deb, NULL, NULL, NULL, NULL, NULL,
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&tmr_description
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};
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@ -585,11 +611,13 @@ return "console terminal output";
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int32 iccs_rd (void)
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{
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_rd()", tmr_iccs_bits, tmr_iccs, tmr_iccs, TRUE);
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return tmr_iccs & TMR_CSR_RD;
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}
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void iccs_wr (int32 val)
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{
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sim_debug_bits_hdr (TMR_DB_REG, &tmr_dev, "iccs_wr()", tmr_iccs_bits, tmr_iccs, val, TRUE);
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if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
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sim_cancel (&tmr_unit); /* cancel timer */
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if (tmr_iccs & TMR_CSR_RUN) /* run 1 -> 0? */
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@ -604,42 +632,59 @@ if (val & TMR_CSR_RUN) { /* run? */
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if (val & TMR_CSR_XFR) /* new tir? */
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sim_cancel (&tmr_unit); /* stop prev */
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if (!sim_is_active (&tmr_unit)) /* not running? */
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tmr_sched (tmr_nicr); /* activate */
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tmr_sched (tmr_icr); /* activate */
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}
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else {
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if (val & TMR_CSR_XFR) /* xfr set? */
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tmr_icr = tmr_nicr;
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if (val & TMR_CSR_SGL) { /* single step? */
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tmr_icr = tmr_inc + 1; /* incr tmr */
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tmr_icr = tmr_icr + 1; /* incr tmr */
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if (tmr_icr == 0) { /* if ovflo, */
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if (tmr_iccs & TMR_CSR_IE) /* ie? */
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if (tmr_iccs & TMR_CSR_DON) /* done? set err */
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tmr_iccs = tmr_iccs | TMR_CSR_ERR;
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else
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tmr_iccs = tmr_iccs | TMR_CSR_DON; /* set done */
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if (tmr_iccs & TMR_CSR_IE) { /* ie? */
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tmr_int = 1; /* set int req */
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sim_debug (TMR_DB_INT, &tmr_dev, "tmr_incr() - INT=1\n");
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}
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tmr_icr = tmr_nicr; /* reload tir */
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}
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}
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}
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if ((tmr_iccs & (TMR_CSR_DON | TMR_CSR_IE)) != /* update int */
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(TMR_CSR_DON | TMR_CSR_IE))
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tmr_int = 0;
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(TMR_CSR_DON | TMR_CSR_IE)) {
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if (tmr_int) {
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tmr_int = 0;
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sim_debug (TMR_DB_INT, &tmr_dev, "iccs_wr() - INT=0\n");
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}
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}
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return;
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}
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int32 icr_rd ()
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{
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uint32 delta = sim_grtime() - tmr_sav;
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int32 result;
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if (tmr_iccs & TMR_CSR_RUN) /* running? */
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return (int32)(tmr_nicr + ((1000000.0 * delta) / sim_timer_inst_per_sec ()));
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return (int32)tmr_icr;
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if (tmr_iccs & TMR_CSR_RUN) { /* running? */
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uint32 delta = sim_grtime() - tmr_sav;
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result = (int32)(tmr_nicr + (uint32)((1000000.0 * delta) / sim_timer_inst_per_sec ()));
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}
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else
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result = (int32)tmr_icr;
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sim_debug (TMR_DB_REG, &tmr_dev, "icr_rd() = 0x%08X%s\n", result, (tmr_iccs & TMR_CSR_RUN) ? " - interpolated" : "");
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return result;
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}
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int32 nicr_rd (void)
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{
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sim_debug (TMR_DB_REG, &tmr_dev, "nicr_rd() = 0x%08X\n", tmr_nicr);
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return tmr_nicr;
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}
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void nicr_wr (int32 val)
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{
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sim_debug (TMR_DB_REG, &tmr_dev, "nicr_wr(0x%08X)\n", val);
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tmr_nicr = val;
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}
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@ -658,14 +703,17 @@ return SCPE_OK;
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t_stat tmr_svc (UNIT *uptr)
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{
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sim_debug (TMR_DB_TICK, &tmr_dev, "tmr_svc()\n");
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if (tmr_iccs & TMR_CSR_DON) /* done? set err */
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tmr_iccs = tmr_iccs | TMR_CSR_ERR;
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else
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tmr_iccs = tmr_iccs | TMR_CSR_DON; /* set done */
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if (tmr_iccs & TMR_CSR_RUN) /* run? */
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tmr_sched (tmr_nicr); /* reactivate */
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if (tmr_iccs & TMR_CSR_IE) /* ie? set int req */
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if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */
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tmr_int = 1;
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sim_debug (TMR_DB_INT, &tmr_dev, "tmr_svc() - INT=1\n");
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}
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else
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tmr_int = 0;
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return SCPE_OK;
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@ -675,8 +723,11 @@ return SCPE_OK;
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void tmr_sched (uint32 nicr)
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{
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sim_activate_after (&tmr_unit, (nicr) ? (~nicr + 1) : 0xFFFFFFFF);
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tmr_sav = sim_grtime();
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uint32 usecs = (nicr) ? (~nicr + 1) : 0xFFFFFFFF;
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sim_debug (TMR_DB_SCHED, &tmr_dev, "tmr_sched(0x%08X-0x%08X)\n", nicr, usecs);
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if (SCPE_OK == sim_activate_after (&tmr_unit, usecs))
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tmr_sav = sim_grtime(); /* Save interval base time */
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}
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/* 100Hz clock reset */
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2
scp.c
2
scp.c
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@ -1986,7 +1986,7 @@ if (*argv[0]) { /* sim name arg? */
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if (np == NULL)
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np = strrchr (nbuf, ']'); /* VMS path separator */
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if (np != NULL)
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setenv ("SIM_BIN_NAME", np, 1); /* Publish simulator binary name */
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setenv ("SIM_BIN_NAME", np+1, 1); /* Publish simulator binary name */
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}
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sim_argv = argv;
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cptr = getenv("HOME");
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