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SWTP6800: General cleanup and boot fixup

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DC-4: fixed flags
M6800: simplified code in big instr decode loop, Removed sim-debug
M6810: added examine and deposit (from Thomas Pfau), Removed sim-debug
MP-A: added examine and deposit (from Thomas Pfau)
This commit is contained in:
Bill Beech 2022-03-09 15:37:29 -07:00
parent 2cede2fb99
commit c9c9fa641b
12 changed files with 469 additions and 446 deletions
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10
swtp6800/common/bootrom.c
View file

@ -92,12 +92,10 @@ MTAB BOOTROM_mod[] = {
};
DEBTAB BOOTROM_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};

76
swtp6800/common/dc-4.c
View file

@ -223,8 +223,6 @@
#include <stdio.h>
#include "swtp_defs.h"
#define DEBUG 0
#define UNIT_V_ENABLE (UNIT_V_UF + 0) /* Write Enable */
#define UNIT_ENABLE (1 << UNIT_V_ENABLE)
@ -242,12 +240,27 @@
#define MAXCYL 0x26 /* last cylinder # */
#define MAXSEC 0x27 /* last sector # */
/* 1797 status bits */
/* 1797 status bits type I commands*/
#define BUSY 0x01
#define DRQ 0x02
#define WRPROT 0x40
#define NOTRDY 0x80
#define WRPROT 0x40
#define HEDLOD 0x20
#define SEEKERR 0x10
#define CRCERR 0x08
#define LOST 0x04
#define DRQ 0x02
#define BUSY 0x01
/* 1797 status bits type II/III commands*/
#define NOTRDY 0x80
#define WRPROT 0x40
#define WRTFALT 0x20
#define RECNF 0x10
#define CRCERR 0x08
#define LOST 0x04
#define DRQ 0x02
#define BUSY 0x01
/* function prototypes */
@ -276,10 +289,10 @@ int32 dsksiz; /* dsk size (bytes) */
/* Floppy Disk Controller data structures
dsk_dev Mother Board device descriptor
dsk_unit Mother Board unit descriptor
dsk_reg Mother Board register list
dsk_mod Mother Board modifiers list
dsk_dev Disk Controller device descriptor
dsk_unit Disk Controller unit descriptor
dsk_reg Disk Controller register list
dsk_mod Disk Controller modifiers list
*/
UNIT dsk_unit[] = {
@ -301,12 +314,10 @@ MTAB dsk_mod[] = {
};
DEBTAB dsk_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};
@ -330,7 +341,7 @@ DEVICE dsk_dev = {
NULL, //ctxt
DEV_DEBUG, //flags
0, //dctrl
dsk_debug, /* debflags */
dsk_debug, //debflags
NULL, //msize
NULL //lname
};
@ -381,6 +392,7 @@ int32 fdcdrv(int32 io, int32 data)
return 0; /* already selected */
cur_dsk = data & 0x03; /* only 2 drive select bits */
sim_debug (DEBUG_flow, &dsk_dev, "\nfdcdrv: Drive set to %d", cur_dsk);
dsk_unit[cur_dsk].flags &= ~LOST;
if ((dsk_unit[cur_dsk].flags & UNIT_ENABLE) == 0) {
dsk_unit[cur_dsk].u3 |= WRPROT; /* set 1797 WPROT */
sim_debug (DEBUG_flow, &dsk_dev, "\nfdcdrv: Drive write protected");
@ -430,14 +442,15 @@ int32 fdccmd(int32 io, int32 data)
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Drive %d is not attached", cur_dsk);
return 0;
} else {
dsk_unit[cur_dsk].u3 &= ~NOTRDY; /* clear not ready flag */
dsk_unit[cur_dsk].u3 &= ~(NOTRDY); /* clear not ready flag */
}
if (io) { /* write command to fdc */
switch(data) {
case 0x8C: /* read command */
case 0x9C:
case 0x8C: //read sector command type II
case 0x9C: //read multiple sectors command type II
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Read of disk %d, track %d, sector %d",
cur_dsk, dsk_unit[cur_dsk].u4, dsk_unit[cur_dsk].u5);
dsk_unit[cur_dsk].u3 |= BUSY; /* set BUSY */
pos = trksiz * dsk_unit[cur_dsk].u4; /* calculate file offset */
pos += SECT_SIZE * (dsk_unit[cur_dsk].u5 - 1);
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Read pos = %ld ($%08X)",
@ -452,15 +465,17 @@ int32 fdccmd(int32 io, int32 data)
sim_printf("\nfdccmd: File error in read command\n");
return SCPE_IOERR;
}
dsk_unit[cur_dsk].u3 |= BUSY | DRQ; /* set DRQ & BUSY */
dsk_unit[cur_dsk].u3 |= DRQ; /* set DRQ */
dsk_unit[cur_dsk].pos = 0; /* clear counter */
break;
case 0xAC: /* write command */
case 0xAC: //write command type II
case 0xBC: //write multiple sectors command type II
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Write of disk %d, track %d, sector %d",
cur_dsk, dsk_unit[cur_dsk].u4, dsk_unit[cur_dsk].u5);
if (dsk_unit[cur_dsk].u3 & WRPROT) {
printf("\nfdccmd: Drive %d is write-protected", cur_dsk);
} else {
dsk_unit[cur_dsk].u3 |= BUSY;/* set BUSY */
pos = trksiz * dsk_unit[cur_dsk].u4; /* calculate file offset */
pos += SECT_SIZE * (dsk_unit[cur_dsk].u5 - 1);
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Write pos = %ld ($%08X)",
@ -470,24 +485,25 @@ int32 fdccmd(int32 io, int32 data)
sim_printf("\nfdccmd: Seek error in write command\n");
return SCPE_IOERR;
}
dsk_unit[cur_dsk].u3 |= DRQ;/* set DRQ */
wrt_flag = 1; /* set write flag */
dsk_unit[cur_dsk].u3 |= BUSY | DRQ;/* set DRQ & BUSY */
dsk_unit[cur_dsk].pos = 0; /* clear counter */
}
break;
case 0x18: /* seek command */
case 0x1B:
case 0x18: //seek command type I
case 0x1B: //seek command type I
dsk_unit[cur_dsk].u4 = fdcbyte; /* set track */
dsk_unit[cur_dsk].u3 &= ~(BUSY | DRQ); /* clear flags */
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Seek of disk %d, track %d",
cur_dsk, fdcbyte);
break;
case 0x0B: /* restore command */
case 0x0B: //restore command type I
dsk_unit[cur_dsk].u4 = 0; /* home the drive */
dsk_unit[cur_dsk].u3 &= ~(BUSY | DRQ); /* clear flags */
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Drive %d homed", cur_dsk);
break;
case 0xF0: /* write track command */
case 0xF0: //write track command type III
case 0xF4: //write track command type III
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Write track command for drive %d",
cur_dsk);
break;
@ -499,12 +515,6 @@ int32 fdccmd(int32 io, int32 data)
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Exit Drive %d status=%02X",
cur_dsk, val);
sim_debug (DEBUG_flow, &dsk_dev, "\n%02X", val); //even this short fails it!
if (val1 == 0 && ((val & (BUSY + DRQ)) == (BUSY + DRQ))) /* delay BUSY going high */
val &= ~BUSY;
if (val != val1) /* now allow BUSY after one read */
val1 = val;
sim_debug (DEBUG_flow, &dsk_dev, "\nfdccmd: Exit Drive %d status=%02X",
cur_dsk, val);
}
return val;
}

10
swtp6800/common/i2716.c
View file

@ -71,12 +71,10 @@ MTAB i2716_mod[] = {
};
DEBTAB i2716_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};

531
swtp6800/common/m6800.c
View file

File diff suppressed because it is too large Load diff

31
swtp6800/common/m6810.c
View file

@ -43,6 +43,8 @@
t_stat m6810_reset (DEVICE *dptr);
int32 m6810_get_mbyte(int32 offset);
void m6810_put_mbyte(int32 offset, int32 val);
t_stat m6810_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches);
t_stat m6810_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches);
/* SIMH RAM Standard I/O Data Structures */
@ -54,12 +56,10 @@ MTAB m6810_mod[] = {
};
DEBTAB m6810_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};
@ -74,8 +74,8 @@ DEVICE m6810_dev = {
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
&m6810_examine, //examine
&m6810_deposit, //deposit
&m6810_reset, //reset
NULL, //boot
NULL, //attach
@ -144,3 +144,18 @@ void m6810_put_mbyte(int32 offset, int32 val)
}
/* end of m6810.c */
t_stat m6810_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches)
{
int32 i;
for (i=0; i<sim_emax; ++i)
*eval_array++ = m6810_get_mbyte(addr++);
return SCPE_OK;
}
t_stat m6810_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches)
{
m6810_put_mbyte(addr,value);
return SCPE_OK;
}

24
swtp6800/common/mp-8m.c
View file

@ -66,12 +66,10 @@ MTAB mp_8m_mod[] = {
};
DEBTAB mp_8m_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};
@ -104,7 +102,7 @@ DEVICE mp_8m_dev = {
t_stat mp_8m_reset (DEVICE *dptr)
{
int32 i, j, val;
int32 i;
UNIT *uptr;
sim_debug (DEBUG_flow, &mp_8m_dev, "mp_8m_reset: \n");
@ -118,15 +116,15 @@ t_stat mp_8m_reset (DEVICE *dptr)
else
uptr->u3 = 0x2000 * (i + 1);
if (uptr->filebuf == NULL) {
uptr->filebuf = malloc(0x2000);
uptr->filebuf = calloc(0x2000, sizeof(uint8));
if (uptr->filebuf == NULL) {
printf("mp_8m_reset: Malloc error\n");
printf("mp_8m_reset: Calloc error\n");
return SCPE_MEM;
}
for (j=0; j<8192; j++) { /* fill pattern for testing */
val = (0xA0 | i);
*((uint8 *)(uptr->filebuf) + j) = val & 0xFF;
}
// for (j=0; j<8192; j++) { /* fill pattern for testing */
// val = (0xA0 | i);
// *((uint8 *)(uptr->filebuf) + j) = val & 0xFF;
// }
}
sim_debug (DEBUG_flow, &mp_8m_dev, "MP-8M %d initialized at [%04X-%04XH]\n",
i, uptr->u3, uptr->u3 + uptr->capac - 1);

31
swtp6800/common/mp-a.c
View file

@ -55,6 +55,8 @@ int32 CPU_BD_get_mbyte(int32 addr);
int32 CPU_BD_get_mword(int32 addr);
void CPU_BD_put_mbyte(int32 addr, int32 val);
void CPU_BD_put_mword(int32 addr, int32 val);
t_stat mpa_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches);
t_stat mpa_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches);
/* external routines */
@ -94,12 +96,10 @@ MTAB CPU_BD_mod[] = {
};
DEBTAB CPU_BD_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};
@ -114,8 +114,8 @@ DEVICE CPU_BD_dev = {
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
mpa_examine, //examine
mpa_deposit, //deposit
NULL, //reset
NULL, //boot
NULL, //attach
@ -202,4 +202,19 @@ void CPU_BD_put_mword(int32 addr, int32 val)
CPU_BD_put_mbyte(addr+1, val);
}
t_stat mpa_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches)
{
int32 i;
for (i=0; i<sim_emax; ++i)
*eval_array++ = CPU_BD_get_mbyte(addr++);
return SCPE_OK;
}
t_stat mpa_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches)
{
CPU_BD_put_mbyte(addr,value);
return SCPE_OK;
}
/* end of mp-a.c */

31
swtp6800/common/mp-a2.c
View file

@ -70,6 +70,8 @@ int32 CPU_BD_get_mbyte(int32 addr);
int32 CPU_BD_get_mword(int32 addr);
void CPU_BD_put_mbyte(int32 addr, int32 val);
void CPU_BD_put_mword(int32 addr, int32 val);
t_stat mpa2_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches);
t_stat mpa2_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches);
/* external routines */
@ -124,12 +126,10 @@ MTAB CPU_BD_mod[] = {
};
DEBTAB CPU_BD_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};
@ -144,8 +144,8 @@ DEVICE CPU_BD_dev = {
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
mpa2_examine, //examine
mpa2_deposit, //deposit
NULL, //reset
NULL, //boot
NULL, //attach
@ -252,4 +252,19 @@ void CPU_BD_put_mword(int32 addr, int32 val)
CPU_BD_put_mbyte(addr+1, val);
}
t_stat mpa2_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches)
{
int32 i;
for (i=0; i<sim_emax; ++i)
*eval_array++ = CPU_BD_get_mbyte(addr++);
return SCPE_OK;
}
t_stat mpa2_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches)
{
CPU_BD_put_mbyte(addr,value);
return SCPE_OK;
}
/* end of mp-a2.c */

139
swtp6800/common/mp-b2.c
View file

@ -49,6 +49,12 @@
/* function prototypes */
int32 get_base(void);
int32 CPU_BD_get_mbyte(int32 addr);
int32 CPU_BD_get_mword(int32 addr);
void CPU_BD_put_mbyte(int32 addr, int32 val);
void CPU_BD_put_mword(int32 addr, int32 val);
/* empty I/O device routine */
int32 nulldev(int32 io, int32 data);
@ -57,6 +63,8 @@ int32 MB_get_mbyte(int32 addr);
int32 MB_get_mword(int32 addr);
void MB_put_mbyte(int32 addr, int32 val);
void MB_put_mword(int32 addr, int32 val);
t_stat mpb2_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches);
t_stat mpb2_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches);
/* MP-8M bus routines */
extern int32 mp_8m_get_mbyte(int32 addr);
@ -141,12 +149,10 @@ MTAB MB_mod[] = {
};
DEBTAB MB_debug[] = {
{ "ALL", DEBUG_all },
{ "FLOW", DEBUG_flow },
{ "READ", DEBUG_read },
{ "WRITE", DEBUG_write },
{ "LEV1", DEBUG_level1 },
{ "LEV2", DEBUG_level2 },
{ "ALL", DEBUG_all, "All debug bits" },
{ "FLOW", DEBUG_flow, "Flow control" },
{ "READ", DEBUG_read, "Read Command" },
{ "WRITE", DEBUG_write, "Write Command"},
{ NULL }
};
@ -161,8 +167,8 @@ DEVICE MB_dev = {
1, //aincr
16, //dradix
8, //dwidth
NULL, //examine
NULL, //deposit
mpb2_examine, //examine
mpb2_deposit, //deposit
NULL, //reset
NULL, //boot
NULL, //attach
@ -181,45 +187,32 @@ int32 MB_get_mbyte(int32 addr)
{
int32 val;
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: addr=%04X\n", addr);
switch(addr & 0xF000) {
case 0x0000:
case 0x1000:
if (MB_unit.flags & UNIT_RAM_0000) {
switch(addr & 0xE000) {
case 0x0000: //0000-1FFFh
if (MB_unit.flags & UNIT_RAM_0000)
val = mp_8m_get_mbyte(addr) & 0xFF;
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: addr=%04X\n", addr);
if (MB_dev.dctrl & DEBUG_read)
printf("MB_get_mbyte: mp_8m val=%02X\n", val);
} else
else
val = 0xFF;
break;
case 0x2000:
case 0x3000:
if (MB_unit.flags & UNIT_RAM_2000) {
case 0x2000: //2000-3FFFh
if (MB_unit.flags & UNIT_RAM_2000)
val = mp_8m_get_mbyte(addr) & 0xFF;
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val);
} else
else
val = 0xFF;
break;
case 0x4000:
case 0x5000:
if (MB_unit.flags & UNIT_RAM_4000) {
case 0x4000: //4000-5FFFh
if (MB_unit.flags & UNIT_RAM_4000)
val = mp_8m_get_mbyte(addr) & 0xFF;
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: addr=%04X\n", addr);
if (MB_dev.dctrl & DEBUG_read)
printf("MB_get_mbyte: mp_8m val=%02X\n", val);
} else
else
val = 0xFF;
break;
case 0x6000:
case 0x7000:
if (MB_unit.flags & UNIT_RAM_6000) {
case 0x6000: //6000-7FFFh
if (MB_unit.flags & UNIT_RAM_6000)
val = mp_8m_get_mbyte(addr) & 0xFF;
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val);
} else
else
val = 0xFF;
break;
case 0x8000:
case 0x8000: //8000-9FFFh (I/O ports)
if (addr < 0x8020)
val = (dev_table[addr - 0x8000].routine(0, 0)) & 0xFF;
else
@ -227,20 +220,16 @@ int32 MB_get_mbyte(int32 addr)
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: I/O addr=%04X val=%02X\n",
addr, val);
break;
case 0xA000:
case 0xB000:
if (MB_unit.flags & UNIT_RAM_A000) {
case 0xA000: //A000-AFFFh
if (MB_unit.flags & UNIT_RAM_A000)
val = mp_8m_get_mbyte(addr) & 0xFF;
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val);
} else
else
val = 0xFF;
break;
case 0xC000:
case 0xD000:
if (MB_unit.flags & UNIT_RAM_C000) {
case 0xC000: //C000-CFFFh
if (MB_unit.flags & UNIT_RAM_C000)
val = mp_8m_get_mbyte(addr) & 0xFF;
sim_debug (DEBUG_read, &MB_dev, "MB_get_mbyte: mp_8m val=%02X\n", val);
} else
else
val = 0xFF;
break;
default:
@ -267,49 +256,34 @@ int32 MB_get_mword(int32 addr)
void MB_put_mbyte(int32 addr, int32 val)
{
sim_debug (DEBUG_write, &MB_dev, "MB_put_mbyte: addr=%04X, val=%02X\n",
addr, val);
switch(addr & 0xF000) {
case 0x0000:
case 0x1000:
if (MB_unit.flags & UNIT_RAM_0000) {
switch(addr & 0xE000) {
case 0x0000: //0000-1FFFh
if (MB_unit.flags & UNIT_RAM_0000)
mp_8m_put_mbyte(addr, val);
}
break;
case 0x2000:
case 0x3000:
if (MB_unit.flags & UNIT_RAM_2000) {
case 0x2000: //2000-3FFFh
if (MB_unit.flags & UNIT_RAM_2000)
mp_8m_put_mbyte(addr, val);
}
break;
case 0x4000:
case 0x5000:
if (MB_unit.flags & UNIT_RAM_4000) {
case 0x4000: //4000-5FFFh
if (MB_unit.flags & UNIT_RAM_4000)
mp_8m_put_mbyte(addr, val);
}
break;
case 0x6000:
case 0x7000:
if (MB_unit.flags & UNIT_RAM_6000) {
case 0x6000: //6000-7FFFh
if (MB_unit.flags & UNIT_RAM_6000)
mp_8m_put_mbyte(addr, val);
}
break;
case 0x8000:
if (addr < 0x8020) {
case 0x8000: //8000-9FFFh (I/O ports)
if (addr < 0x8020)
dev_table[addr - 0x8000].routine(1, val);
}
break;
case 0xA000:
case 0xB000:
if (MB_unit.flags & UNIT_RAM_A000) {
case 0xA000: //A000-AFFFh
if (MB_unit.flags & UNIT_RAM_A000)
mp_8m_put_mbyte(addr, val);
}
break;
case 0xC000:
case 0xD000:
if (MB_unit.flags & UNIT_RAM_C000) {
case 0xC000: //C000-CFFFh
if (MB_unit.flags & UNIT_RAM_C000)
mp_8m_put_mbyte(addr, val);
}
break;
default:
;
@ -325,5 +299,20 @@ void MB_put_mword(int32 addr, int32 val)
MB_put_mbyte(addr+1, val);
}
t_stat mpb2_examine(t_value *eval_array, t_addr addr, UNIT *uptr, int32 switches)
{
int32 i;
for (i=0; i<sim_emax; ++i)
*eval_array++ = CPU_BD_get_mbyte(addr++);
return SCPE_OK;
}
t_stat mpb2_deposit(t_value value, t_addr addr, UNIT *uptr, int32 switches)
{
CPU_BD_put_mbyte(addr,value);
return SCPE_OK;
}
/* end of mp-b2.c */

13
swtp6800/swtp6800/mp-a2_sys.c
View file

@ -1,4 +1,4 @@
/* mp-a_sys.c: SWTP 6800 system interface
/* mp-a2_sys.c: SWTP 6800 system interface
Copyright (c) 2005-2012, William Beech
@ -44,6 +44,15 @@ extern DEVICE ptp_dev;
extern DEVICE mp_8m_dev;
extern DEVICE dsk_dev;
/* external routines */
extern void CPU_BD_put_mbyte(int32 addr, int32 val);
extern void CPU_BD_put_mword(int32 addr, int32 val);
extern int32 CPU_BD_get_mbyte(int32 addr);
extern int32 CPU_BD_get_mword(int32 addr);
extern int32 saved_PC; /* Program counter */
/* SCP data structures
sim_name simulator name string
@ -84,4 +93,4 @@ const char *sim_stop_messages[SCPE_BASE] = {
"Invalid Memory"
};
/* end of mp-a_sys.c */
/* end of mp-a2_sys.c */

9
swtp6800/swtp6800/mp-a_sys.c
View file

@ -43,6 +43,15 @@ extern DEVICE ptp_dev;
extern DEVICE mp_8m_dev;
extern DEVICE dsk_dev;
/* external routines */
extern void CPU_BD_put_mbyte(int32 addr, int32 val);
extern void CPU_BD_put_mword(int32 addr, int32 val);
extern int32 CPU_BD_get_mbyte(int32 addr);
extern int32 CPU_BD_get_mword(int32 addr);
extern int32 saved_PC; /* Program counter */
/* SCP data structures
sim_name simulator name string

4
swtp6800/swtp6800/swtp_defs.h
View file

@ -43,10 +43,6 @@ Copyright (c) 2005-2012, William Beech
#define DEBUG_flow 0x0001
#define DEBUG_read 0x0002
#define DEBUG_write 0x0004
#define DEBUG_level1 0x0008
#define DEBUG_level2 0x0010
#define DEBUG_reg 0x0020
#define DEBUG_asm 0x0040
#define DEBUG_all 0xFFFF
/* Simulator stop codes */