Created a way for devices to have a description presentation routine and if it is supplied for its output to be visible with a SHOW SYSTEM command. Provided device description routines for devices used in the VAX simulators
This commit is contained in:
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bb9f9155f2
commit
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46 changed files with 695 additions and 113 deletions
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@ -333,6 +333,8 @@ t_stat cr_set_reset (UNIT *, int32, char *, void *);
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t_stat cr_set_stop (UNIT *, int32, char *, void *);
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t_stat cr_set_stop (UNIT *, int32, char *, void *);
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t_stat cr_set_trans (UNIT *, int32, char*, void *);
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t_stat cr_set_trans (UNIT *, int32, char*, void *);
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t_stat cr_show_trans (FILE *, UNIT *, int32, void *);
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t_stat cr_show_trans (FILE *, UNIT *, int32, void *);
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char *cr_description (DEVICE *dptr);
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/* CR data structures
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/* CR data structures
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@ -408,7 +410,10 @@ DEVICE cr_dev = {
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1, 10, 31, 1, DEV_RDX, 8,
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1, 10, 31, 1, DEV_RDX, 8,
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NULL, NULL, &cr_reset,
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NULL, NULL, &cr_reset,
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NULL, &cr_attach, &cr_detach,
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NULL, &cr_attach, &cr_detach,
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&cr_dib, DEV_DISABLE | DFLT_DIS | DEV_UBUS | DEV_DEBUG };
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&cr_dib, DEV_DISABLE | DFLT_DIS | DEV_UBUS | DEV_DEBUG, 0,
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NULL, NULL, NULL, NULL, NULL, NULL,
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&cr_description
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};
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/* Utility routines */
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/* Utility routines */
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@ -1282,3 +1287,8 @@ t_stat cr_show_trans ( FILE *st,
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fprintf (st, "translation %s", trans[table]);
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fprintf (st, "translation %s", trans[table]);
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return (SCPE_OK);
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return (SCPE_OK);
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}
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}
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char *cr_description (DEVICE *dptr)
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{
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return "CR11 card reader";
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}
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@ -28,6 +28,7 @@
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Modification history:
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Modification history:
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23-Jan-13 RJ Don't do anything if not attached. See https://github.com/simh/simh/issues/28
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23-Jan-13 RJ Clock co-scheduling move to generic framework (from Mark Pizzolato)
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23-Jan-13 RJ Clock co-scheduling move to generic framework (from Mark Pizzolato)
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21-Jan-13 RJ Added help.
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21-Jan-13 RJ Added help.
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15-Jan-13 RJ Contribution from Paul Koning:
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15-Jan-13 RJ Contribution from Paul Koning:
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@ -220,7 +221,6 @@ t_stat dmc_wr(int32 data, int32 PA, int32 access);
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t_stat dmc_svc(UNIT * uptr);
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t_stat dmc_svc(UNIT * uptr);
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t_stat dmc_reset (DEVICE * dptr);
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t_stat dmc_reset (DEVICE * dptr);
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t_stat dmc_attach (UNIT * uptr, char * cptr);
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t_stat dmc_attach (UNIT * uptr, char * cptr);
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int dmc_isattached(CTLR *controller);
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t_stat dmc_detach (UNIT * uptr);
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t_stat dmc_detach (UNIT * uptr);
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int32 dmc_rxint (void);
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int32 dmc_rxint (void);
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int32 dmc_txint (void);
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int32 dmc_txint (void);
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@ -238,6 +238,9 @@ t_stat dmc_setlinemode (UNIT* uptr, int32 val, char* cptr, void* desc);
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t_stat dmc_showlinemode (FILE* st, UNIT* uptr, int32 val, void* desc);
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t_stat dmc_showlinemode (FILE* st, UNIT* uptr, int32 val, void* desc);
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t_stat dmc_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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t_stat dmc_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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t_stat dmc_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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t_stat dmc_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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char *dmc_description (DEVICE *dptr);
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char *dmp_description (DEVICE *dptr);
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int dmc_is_attached(UNIT* uptr);
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int dmc_is_dmc(CTLR *controller);
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int dmc_is_dmc(CTLR *controller);
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int dmc_is_rqi_set(CTLR *controller);
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int dmc_is_rqi_set(CTLR *controller);
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int dmc_is_rdyi_set(CTLR *controller);
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int dmc_is_rdyi_set(CTLR *controller);
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@ -448,19 +451,19 @@ DEVICE dmc_dev[] =
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{ "DMC0", &dmc0_unit, dmca_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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{ "DMC0", &dmc0_unit, dmca_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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&dmc0_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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&dmc0_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL },
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL, &dmc_description },
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{ "DMC1", &dmc1_unit, dmcb_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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{ "DMC1", &dmc1_unit, dmcb_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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&dmc1_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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&dmc1_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL },
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL, &dmc_description },
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{ "DMC2", &dmc2_unit, dmcc_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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{ "DMC2", &dmc2_unit, dmcc_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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&dmc2_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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&dmc2_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL },
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL, &dmc_description },
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{ "DMC3", &dmc3_unit, dmcd_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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{ "DMC3", &dmc3_unit, dmcd_reg, dmc_mod, DMC_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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&dmc3_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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&dmc3_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL }
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL, &dmc_description }
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};
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};
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#ifdef DMP
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#ifdef DMP
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@ -469,7 +472,7 @@ DEVICE dmp_dev[] =
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{ "DMP", &dmp_unit, dmp_reg, dmc_mod, DMP_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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{ "DMP", &dmp_unit, dmp_reg, dmc_mod, DMP_UNITSPERDEVICE, DMC_RDX, 8, 1, DMC_RDX, 8,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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NULL,NULL,&dmc_reset,NULL,&dmc_attach,&dmc_detach,
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&dmp_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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&dmp_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG, 0, dmc_debug,
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL }
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NULL, NULL, &dmc_help, &dmc_help_attach, NULL, &dmp_description }
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};
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};
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#endif
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#endif
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@ -521,6 +524,11 @@ double dmc_timer_cumulative_seconds(TIMER *t)
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return (double)t->cumulative_time/CLOCKS_PER_SEC;
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return (double)t->cumulative_time/CLOCKS_PER_SEC;
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}
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}
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int dmc_is_attached(UNIT* uptr)
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{
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return uptr->flags & UNIT_ATT;
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}
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int dmc_is_dmc(CTLR *controller)
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int dmc_is_dmc(CTLR *controller)
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{
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{
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return controller->dev_type != DMP;
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return controller->dev_type != DMP;
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@ -589,7 +597,7 @@ t_stat dmc_setpeer (UNIT* uptr, int32 val, char* cptr, void* desc)
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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if (!cptr) return SCPE_IERR;
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if (!cptr) return SCPE_IERR;
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if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
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if (dmc_is_attached(uptr)) return SCPE_ALATT;
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status = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), NULL, NULL);
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status = sim_parse_addr (cptr, host, sizeof(host), NULL, port, sizeof(port), NULL, NULL);
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if (status != SCPE_OK)
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if (status != SCPE_OK)
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return status;
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return status;
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@ -621,7 +629,7 @@ t_stat dmc_setspeed (UNIT* uptr, int32 val, char* cptr, void* desc)
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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if (!cptr) return SCPE_IERR;
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if (!cptr) return SCPE_IERR;
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if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
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if (dmc_is_attached(uptr)) return SCPE_ALATT;
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if (sscanf(cptr, "%d", &controller->line->speed) != 1)
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if (sscanf(cptr, "%d", &controller->line->speed) != 1)
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{
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{
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status = SCPE_ARG;
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status = SCPE_ARG;
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@ -666,7 +674,7 @@ t_stat dmc_settype (UNIT* uptr, int32 val, char* cptr, void* desc)
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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if (!cptr) return SCPE_IERR;
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if (!cptr) return SCPE_IERR;
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if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
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if (UNIT_ATT) return SCPE_ALATT;
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if (sscanf(cptr, "%s", buf) != 1)
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if (sscanf(cptr, "%s", buf) != 1)
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{
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{
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status = SCPE_ARG;
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status = SCPE_ARG;
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@ -780,7 +788,7 @@ t_stat dmc_setlinemode (UNIT* uptr, int32 val, char* cptr, void* desc)
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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if (!cptr) return SCPE_IERR;
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if (!cptr) return SCPE_IERR;
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if (uptr->flags & UNIT_ATT) return SCPE_ALATT;
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if (dmc_is_attached(uptr)) return SCPE_ALATT;
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if (MATCH_CMD(cptr, "PRIMARY") == 0)
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if (MATCH_CMD(cptr, "PRIMARY") == 0)
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{
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{
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@ -1400,7 +1408,7 @@ t_stat dmc_svc(UNIT* uptr)
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dmc_timer_start(poll_timer);
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dmc_timer_start(poll_timer);
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}
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}
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if (dmc_isattached(controller))
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if (dmc_is_attached(controller->device->units))
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{
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{
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dmc_line_update_speed_stats(controller->line);
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dmc_line_update_speed_stats(controller->line);
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@ -2309,7 +2317,7 @@ t_stat dmc_wr(int32 data, int32 PA, int32 access)
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dmc_setreg(controller, PA, (oldValue & ~mask) | (data & mask), 1);
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dmc_setreg(controller, PA, (oldValue & ~mask) | (data & mask), 1);
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}
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}
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if (dmc_getsel(reg) == 0 || dmc_getsel(reg) == 1)
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if (dmc_is_attached(controller->device->units) && (dmc_getsel(reg) == 0 || dmc_getsel(reg) == 1))
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{
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{
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dmc_process_command(controller);
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dmc_process_command(controller);
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}
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}
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@ -2393,11 +2401,6 @@ t_stat dmc_attach (UNIT *uptr, char *cptr)
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return ans;
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return ans;
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}
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}
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int dmc_isattached(CTLR *controller)
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{
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return controller->master_socket != INVALID_SOCKET;
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}
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t_stat dmc_detach (UNIT *uptr)
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t_stat dmc_detach (UNIT *uptr)
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{
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{
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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CTLR *controller = dmc_get_controller_from_unit(uptr);
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@ -2410,3 +2413,14 @@ t_stat dmc_detach (UNIT *uptr)
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return SCPE_OK;
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return SCPE_OK;
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}
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}
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char *dmc_description (DEVICE *dptr)
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{
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return "DMC11 Synchronous network controller";
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}
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char *dmp_description (DEVICE *dptr)
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{
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return "DMP11 Synchronous network controller";
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}
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@ -277,6 +277,7 @@ t_stat dz_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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t_stat dz_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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t_stat dz_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
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char *dz_description (DEVICE *dptr);
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/* DZ data structures
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/* DZ data structures
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@ -350,7 +351,8 @@ DEVICE dz_dev = {
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&dz_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_MUX,
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&dz_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_MUX,
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0, dz_debug, NULL, NULL,
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0, dz_debug, NULL, NULL,
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&dz_help, &dz_help_attach, /* help and attach_help routines */
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&dz_help, &dz_help_attach, /* help and attach_help routines */
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(void *)&dz_desc /* help context variable */
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(void *)&dz_desc, /* help context variable */
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&dz_description /* description routine */
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};
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};
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/* Register names for Debug tracing */
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/* Register names for Debug tracing */
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@ -476,8 +478,9 @@ switch ((PA >> 1) & 03) { /* case on PA<2:1> */
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continue; /* line unchanged skip */
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continue; /* line unchanged skip */
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line = (dz * DZ_LINES) + i; /* get line num */
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line = (dz * DZ_LINES) + i; /* get line num */
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lp = &dz_ldsc[line]; /* get line desc */
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lp = &dz_ldsc[line]; /* get line desc */
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if (data & (1 << (TCR_V_DTR + i)))
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if (data & (1 << (TCR_V_DTR + i))) {
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tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL);
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tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL);
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}
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else
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else
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if (dz_auto)
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if (dz_auto)
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tmxr_set_get_modem_bits (lp, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);
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tmxr_set_get_modem_bits (lp, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL);
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@ -691,6 +694,8 @@ t_stat dz_clear (int32 dz, t_bool flag)
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{
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{
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int32 i, line;
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int32 i, line;
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sim_debug(DBG_TRC, &dz_dev, "dz_clear(dz=%d,flag=%d)\n", dz, flag);
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dz_csr[dz] = 0; /* clear CSR */
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dz_csr[dz] = 0; /* clear CSR */
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dz_rbuf[dz] = 0; /* silo empty */
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dz_rbuf[dz] = 0; /* silo empty */
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dz_lpr[dz] = 0; /* no params */
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dz_lpr[dz] = 0; /* no params */
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@ -714,6 +719,8 @@ t_stat dz_reset (DEVICE *dptr)
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{
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{
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int32 i, ndev;
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int32 i, ndev;
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sim_debug(DBG_TRC, dptr, "dz_reset()\n");
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if (dz_ldsc == NULL)
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if (dz_ldsc == NULL)
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dz_desc.ldsc = dz_ldsc = calloc (dz_desc.lines, sizeof(*dz_ldsc));
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dz_desc.ldsc = dz_ldsc = calloc (dz_desc.lines, sizeof(*dz_ldsc));
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for (i = 0; i < dz_desc.lines/DZ_LINES; i++) /* init muxes */
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for (i = 0; i < dz_desc.lines/DZ_LINES; i++) /* init muxes */
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@ -918,3 +925,7 @@ fprintf (st, "status.\n\n");
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return SCPE_OK;
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return SCPE_OK;
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}
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}
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char *dz_description (DEVICE *dptr)
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{
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return (UNIBUS) ? "DZ11 8-line terminal multiplexer" : "DZV11 4-line terminal multiplexer";
|
||||||
|
}
|
||||||
|
|
|
@ -566,6 +566,7 @@ void hk_cmderr (int32 err, int32 drv);
|
||||||
void hk_go (int32 drv);
|
void hk_go (int32 drv);
|
||||||
t_stat hk_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat hk_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat hk_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat hk_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
|
char *hk_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* HK data structures
|
/* HK data structures
|
||||||
|
|
||||||
|
@ -677,7 +678,8 @@ DEVICE hk_dev = {
|
||||||
NULL, NULL, &hk_reset,
|
NULL, NULL, &hk_reset,
|
||||||
&hk_boot, &hk_attach, &hk_detach,
|
&hk_boot, &hk_attach, &hk_detach,
|
||||||
&hk_dib, DEV_DISABLE | DEV_UBUS | DEV_Q18 | DEV_DEBUG, 0,
|
&hk_dib, DEV_DISABLE | DEV_UBUS | DEV_Q18 | DEV_DEBUG, 0,
|
||||||
hk_deb, NULL, 0
|
hk_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&hk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* I/O dispatch routines, I/O addresses 17777440 - 17777476 */
|
/* I/O dispatch routines, I/O addresses 17777440 - 17777476 */
|
||||||
|
@ -1572,3 +1574,8 @@ return SCPE_NOFNC;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
char *hk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "RK611/RK06(7) cartridge disk controller";
|
||||||
|
}
|
||||||
|
|
|
@ -63,6 +63,7 @@ t_stat lpt_svc (UNIT *uptr);
|
||||||
t_stat lpt_reset (DEVICE *dptr);
|
t_stat lpt_reset (DEVICE *dptr);
|
||||||
t_stat lpt_attach (UNIT *uptr, char *ptr);
|
t_stat lpt_attach (UNIT *uptr, char *ptr);
|
||||||
t_stat lpt_detach (UNIT *uptr);
|
t_stat lpt_detach (UNIT *uptr);
|
||||||
|
char *lpt_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* LPT data structures
|
/* LPT data structures
|
||||||
|
|
||||||
|
@ -110,7 +111,9 @@ DEVICE lpt_dev = {
|
||||||
1, 10, 31, 1, DEV_RDX, 8,
|
1, 10, 31, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &lpt_reset,
|
NULL, NULL, &lpt_reset,
|
||||||
NULL, &lpt_attach, &lpt_detach,
|
NULL, &lpt_attach, &lpt_detach,
|
||||||
&lpt_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS
|
&lpt_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS, 0,
|
||||||
|
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&lpt_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Line printer routines
|
/* Line printer routines
|
||||||
|
@ -199,3 +202,9 @@ t_stat lpt_detach (UNIT *uptr)
|
||||||
lpt_csr = lpt_csr | CSR_ERR;
|
lpt_csr = lpt_csr | CSR_ERR;
|
||||||
return detach_unit (uptr);
|
return detach_unit (uptr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *lpt_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return (UNIBUS) ? "LP11 line printer" :
|
||||||
|
"LPV11 line printer";
|
||||||
|
}
|
||||||
|
|
|
@ -260,6 +260,7 @@ t_stat rl_show_dstate (FILE *, UNIT *, int32, void *);
|
||||||
t_stat rl_set_ctrl (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat rl_set_ctrl (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
#endif
|
#endif
|
||||||
t_stat rl_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat rl_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *rl_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* RL11 data structures
|
/* RL11 data structures
|
||||||
|
|
||||||
|
@ -347,7 +348,9 @@ DEVICE rl_dev = {
|
||||||
RL_NUMDR, DEV_RDX, 24, 1, DEV_RDX, 16,
|
RL_NUMDR, DEV_RDX, 24, 1, DEV_RDX, 16,
|
||||||
NULL, NULL, &rl_reset,
|
NULL, NULL, &rl_reset,
|
||||||
&rl_boot, &rl_attach, &rl_detach,
|
&rl_boot, &rl_attach, &rl_detach,
|
||||||
&rl_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG
|
&rl_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG, 0,
|
||||||
|
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rl_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Drive states */
|
/* Drive states */
|
||||||
|
@ -1208,3 +1211,10 @@ return SCPE_NOFNC;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
char *rl_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return (UNIBUS) ? "RL11/RL01(2) cartridge disk controller" :
|
||||||
|
"RLV12/RL01(2) cartridge disk controller";
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
@ -581,6 +581,8 @@ t_stat rp_go (int32 drv);
|
||||||
t_stat rp_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat rp_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat rp_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat rp_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
int32 rp_abort (void);
|
int32 rp_abort (void);
|
||||||
|
char *rp_description (DEVICE *dptr);
|
||||||
|
|
||||||
|
|
||||||
/* RP data structures
|
/* RP data structures
|
||||||
|
|
||||||
|
@ -702,7 +704,8 @@ DEVICE rp_dev = {
|
||||||
NULL, NULL, &rp_reset,
|
NULL, NULL, &rp_reset,
|
||||||
&rp_boot, &rp_attach, &rp_detach,
|
&rp_boot, &rp_attach, &rp_detach,
|
||||||
&rp_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_MBUS | DEV_DEBUG | DEV_DISK,
|
&rp_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_MBUS | DEV_DEBUG | DEV_DISK,
|
||||||
0, rp_debug
|
0, rp_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rp_description
|
||||||
};
|
};
|
||||||
|
|
||||||
char *rp_regnam[] =
|
char *rp_regnam[] =
|
||||||
|
@ -1482,3 +1485,8 @@ return SCPE_NOFNC;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
char *rp_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "RP04/05/06/07 RM02/03/05/80 Massbus disk controller";
|
||||||
|
}
|
||||||
|
|
|
@ -798,6 +798,7 @@ t_stat rq_show_ctype (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat rq_show_wlk (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat rq_show_wlk (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat rq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat rq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat rq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat rq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *rq_description (DEVICE *dptr);
|
||||||
|
|
||||||
t_bool rq_step4 (MSC *cp);
|
t_bool rq_step4 (MSC *cp);
|
||||||
t_bool rq_mscp (MSC *cp, int32 pkt, t_bool q);
|
t_bool rq_mscp (MSC *cp, int32 pkt, t_bool q);
|
||||||
|
@ -1009,7 +1010,8 @@ DEVICE rq_dev = {
|
||||||
NULL, NULL, &rq_reset,
|
NULL, NULL, &rq_reset,
|
||||||
&rq_boot, &rq_attach, &rq_detach,
|
&rq_boot, &rq_attach, &rq_detach,
|
||||||
&rq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
&rq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
||||||
0, rq_debug
|
0, rq_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rq_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* RQB data structures
|
/* RQB data structures
|
||||||
|
@ -1083,7 +1085,8 @@ DEVICE rqb_dev = {
|
||||||
NULL, NULL, &rq_reset,
|
NULL, NULL, &rq_reset,
|
||||||
&rq_boot, &rq_attach, &rq_detach,
|
&rq_boot, &rq_attach, &rq_detach,
|
||||||
&rqb_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
&rqb_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
||||||
0, rq_debug
|
0, rq_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rq_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* RQC data structures
|
/* RQC data structures
|
||||||
|
@ -1157,7 +1160,8 @@ DEVICE rqc_dev = {
|
||||||
NULL, NULL, &rq_reset,
|
NULL, NULL, &rq_reset,
|
||||||
&rq_boot, &rq_attach, &rq_detach,
|
&rq_boot, &rq_attach, &rq_detach,
|
||||||
&rqc_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
&rqc_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
||||||
0, rq_debug
|
0, rq_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rq_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* RQD data structures
|
/* RQD data structures
|
||||||
|
@ -1231,7 +1235,8 @@ DEVICE rqd_dev = {
|
||||||
NULL, NULL, &rq_reset,
|
NULL, NULL, &rq_reset,
|
||||||
&rq_boot, &rq_attach, &rq_detach,
|
&rq_boot, &rq_attach, &rq_detach,
|
||||||
&rqd_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
&rqd_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_DISK,
|
||||||
0, rq_debug
|
0, rq_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rq_description
|
||||||
};
|
};
|
||||||
|
|
||||||
static DEVICE *rq_devmap[RQ_NUMCT] = {
|
static DEVICE *rq_devmap[RQ_NUMCT] = {
|
||||||
|
@ -3074,3 +3079,11 @@ if (val & RQ_SH_UN) {
|
||||||
}
|
}
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *rq_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
static char buf[80];
|
||||||
|
|
||||||
|
sprintf (buf, "%s MSCP disk controller", ctlr_tab[rq_ctxmap[dptr->units->cnum]->ctype].name);
|
||||||
|
return buf;
|
||||||
|
}
|
|
@ -164,6 +164,8 @@ t_stat ry_boot (int32 unitno, DEVICE *dptr);
|
||||||
void ry_done (int32 esr_flags, int32 new_ecode);
|
void ry_done (int32 esr_flags, int32 new_ecode);
|
||||||
t_stat ry_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat ry_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat ry_attach (UNIT *uptr, char *cptr);
|
t_stat ry_attach (UNIT *uptr, char *cptr);
|
||||||
|
char *ry_description (DEVICE *dptr);
|
||||||
|
|
||||||
|
|
||||||
/* RY11 data structures
|
/* RY11 data structures
|
||||||
|
|
||||||
|
@ -246,7 +248,9 @@ DEVICE ry_dev = {
|
||||||
RX_NUMDR, DEV_RDX, 20, 1, DEV_RDX, 8,
|
RX_NUMDR, DEV_RDX, 20, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &ry_reset,
|
NULL, NULL, &ry_reset,
|
||||||
&ry_boot, &ry_attach, NULL,
|
&ry_boot, &ry_attach, NULL,
|
||||||
&ry_dib, DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18
|
&ry_dib, DEV_DISABLE | DEV_DISI | DEV_UBUS | DEV_Q18, 0,
|
||||||
|
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&ry_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* I/O dispatch routine, I/O addresses 17777170 - 17777172
|
/* I/O dispatch routine, I/O addresses 17777170 - 17777172
|
||||||
|
@ -702,3 +706,9 @@ return SCPE_NOFNC;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
char *ry_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return (UNIBUS) ? "RX211 floppy disk controller" :
|
||||||
|
"RXV21 floppy disk controller";
|
||||||
|
}
|
||||||
|
|
|
@ -359,6 +359,7 @@ t_stat tq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat tq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat tq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat tq_set_type (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat tq_set_type (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat tq_show_type (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat tq_show_type (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *tq_description (DEVICE *dptr);
|
||||||
|
|
||||||
t_bool tq_step4 (void);
|
t_bool tq_step4 (void);
|
||||||
t_bool tq_mscp (int32 pkt, t_bool q);
|
t_bool tq_mscp (int32 pkt, t_bool q);
|
||||||
|
@ -539,7 +540,9 @@ DEVICE tq_dev = {
|
||||||
NULL, NULL, &tq_reset,
|
NULL, NULL, &tq_reset,
|
||||||
&tq_boot, &tq_attach, &tq_detach,
|
&tq_boot, &tq_attach, &tq_detach,
|
||||||
&tq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE,
|
&tq_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE,
|
||||||
0, tq_debug
|
0, tq_debug,
|
||||||
|
NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tq_description
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
@ -2379,3 +2382,9 @@ t_stat tq_show_type (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||||
fprintf (st, "%s (%dMB)", drv_tab[tq_typ].name, (uint32) (drv_tab[tq_typ].cap >> 20));
|
fprintf (st, "%s (%dMB)", drv_tab[tq_typ].name, (uint32) (drv_tab[tq_typ].cap >> 20));
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tq_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return (UNIBUS) ? "TUK50 TMSCP magnetic tape controller" :
|
||||||
|
"TQK50 TMSCP magnetic tape controller";
|
||||||
|
}
|
||||||
|
|
|
@ -296,6 +296,7 @@ int32 ts_updxs0 (int32 t);
|
||||||
void ts_cmpendcmd (int32 s0, int32 s1);
|
void ts_cmpendcmd (int32 s0, int32 s1);
|
||||||
void ts_endcmd (int32 ssf, int32 xs0f, int32 msg);
|
void ts_endcmd (int32 ssf, int32 xs0f, int32 msg);
|
||||||
int32 ts_map_status (t_stat st);
|
int32 ts_map_status (t_stat st);
|
||||||
|
char *ts_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* TS data structures
|
/* TS data structures
|
||||||
|
|
||||||
|
@ -365,7 +366,9 @@ DEVICE ts_dev = {
|
||||||
1, 10, T_ADDR_W, 1, DEV_RDX, 8,
|
1, 10, T_ADDR_W, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &ts_reset,
|
NULL, NULL, &ts_reset,
|
||||||
&ts_boot, &ts_attach, &ts_detach,
|
&ts_boot, &ts_attach, &ts_detach,
|
||||||
&ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE
|
&ts_dib, DEV_DISABLE | TS_DIS | DEV_UBUS | DEV_QBUS | DEV_DEBUG | DEV_TAPE, 0,
|
||||||
|
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&ts_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* I/O dispatch routines, I/O addresses 17772520 - 17772522
|
/* I/O dispatch routines, I/O addresses 17772520 - 17772522
|
||||||
|
@ -1171,3 +1174,9 @@ t_stat ts_boot (int32 unitno, DEVICE *dptr)
|
||||||
return SCPE_NOFNC;
|
return SCPE_NOFNC;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
char *ts_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return (UNIBUS) ? "TS11 magnetic tape controller" :
|
||||||
|
"TSV11/TSV05 magnetic tape controller ";
|
||||||
|
}
|
||||||
|
|
|
@ -248,6 +248,7 @@ t_stat tu_detach (UNIT *uptr);
|
||||||
t_stat tu_boot (int32 unitno, DEVICE *dptr);
|
t_stat tu_boot (int32 unitno, DEVICE *dptr);
|
||||||
t_stat tu_set_fmtr (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat tu_set_fmtr (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat tu_show_fmtr (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat tu_show_fmtr (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *tu_description (DEVICE *dptr);
|
||||||
t_stat tu_go (int32 drv);
|
t_stat tu_go (int32 drv);
|
||||||
int32 tu_abort (void);
|
int32 tu_abort (void);
|
||||||
void tu_set_er (int32 flg);
|
void tu_set_er (int32 flg);
|
||||||
|
@ -320,7 +321,9 @@ DEVICE tu_dev = {
|
||||||
TU_NUMDR, 10, T_ADDR_W, 1, DEV_RDX, 8,
|
TU_NUMDR, 10, T_ADDR_W, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &tu_reset,
|
NULL, NULL, &tu_reset,
|
||||||
&tu_boot, &tu_attach, &tu_detach,
|
&tu_boot, &tu_attach, &tu_detach,
|
||||||
&tu_dib, DEV_MBUS|DEV_UBUS|DEV_QBUS|DEV_DEBUG|DEV_DISABLE|DEV_DIS_INIT|DEV_TM03|DEV_TAPE
|
&tu_dib, DEV_MBUS|DEV_UBUS|DEV_QBUS|DEV_DEBUG|DEV_DISABLE|DEV_DIS_INIT|DEV_TM03|DEV_TAPE,
|
||||||
|
0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tu_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Massbus register read */
|
/* Massbus register read */
|
||||||
|
@ -1053,3 +1056,8 @@ return SCPE_NOFNC;
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
char *tu_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "TM03 tape formatter";
|
||||||
|
}
|
||||||
|
|
|
@ -343,6 +343,7 @@ static t_stat vh_set_nolog (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
static t_stat vh_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
|
static t_stat vh_show_log (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
static t_stat vh_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
|
static t_stat vh_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
|
||||||
static t_stat vh_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
|
static t_stat vh_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
|
||||||
|
static char *vh_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* SIMH I/O Structures */
|
/* SIMH I/O Structures */
|
||||||
|
|
||||||
|
@ -437,7 +438,8 @@ DEVICE vh_dev = {
|
||||||
NULL, /* logical name */
|
NULL, /* logical name */
|
||||||
&vh_help, /* help routine */
|
&vh_help, /* help routine */
|
||||||
&vh_help_attach,/* attach_help routines */
|
&vh_help_attach,/* attach_help routines */
|
||||||
(void *)&vh_desc/* help context variable */
|
(void *)&vh_desc,/* help context variable */
|
||||||
|
&vh_description /* description */
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Register names for Debug tracing */
|
/* Register names for Debug tracing */
|
||||||
|
@ -1587,3 +1589,8 @@ char *devtype = (UNIBUS) ? "DH11" : "DHQ11";
|
||||||
fprintf (st, "%s %s Terminal Multiplexer Attach Help\n\n", devtype, dptr->name);
|
fprintf (st, "%s %s Terminal Multiplexer Attach Help\n\n", devtype, dptr->name);
|
||||||
return tmxr_attach_help (st, dptr, uptr, 1, cptr);
|
return tmxr_attach_help (st, dptr, uptr, 1, cptr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static char *vh_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return (UNIBUS) ? "DH11 16-line Terminal Multiplexer" : "DHQ11 8-line Terminal Multiplexer";
|
||||||
|
}
|
||||||
|
|
|
@ -296,6 +296,7 @@ void xq_setint (CTLR* xq);
|
||||||
void xq_clrint (CTLR* xq);
|
void xq_clrint (CTLR* xq);
|
||||||
int32 xq_int (void);
|
int32 xq_int (void);
|
||||||
void xq_csr_set_clr(CTLR* xq, uint16 set_bits, uint16 clear_bits);
|
void xq_csr_set_clr(CTLR* xq, uint16 set_bits, uint16 clear_bits);
|
||||||
|
char *xq_description (DEVICE *dptr);
|
||||||
|
|
||||||
struct xq_device xqa = {
|
struct xq_device xqa = {
|
||||||
xqa_read_callback, /* read callback routine */
|
xqa_read_callback, /* read callback routine */
|
||||||
|
@ -484,7 +485,8 @@ DEVICE xq_dev = {
|
||||||
&xq_ex, &xq_dep, &xq_reset,
|
&xq_ex, &xq_dep, &xq_reset,
|
||||||
NULL, &xq_attach, &xq_detach,
|
NULL, &xq_attach, &xq_detach,
|
||||||
&xqa_dib, DEV_DISABLE | DEV_QBUS | DEV_DEBUG | DEV_ETHER,
|
&xqa_dib, DEV_DISABLE | DEV_QBUS | DEV_DEBUG | DEV_ETHER,
|
||||||
0, xq_debug
|
0, xq_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&xq_description
|
||||||
};
|
};
|
||||||
|
|
||||||
DEVICE xqb_dev = {
|
DEVICE xqb_dev = {
|
||||||
|
@ -493,7 +495,8 @@ DEVICE xqb_dev = {
|
||||||
&xq_ex, &xq_dep, &xq_reset,
|
&xq_ex, &xq_dep, &xq_reset,
|
||||||
NULL, &xq_attach, &xq_detach,
|
NULL, &xq_attach, &xq_detach,
|
||||||
&xqb_dib, DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_DEBUG | DEV_ETHER,
|
&xqb_dib, DEV_DISABLE | DEV_DIS | DEV_QBUS | DEV_DEBUG | DEV_ETHER,
|
||||||
0, xq_debug
|
0, xq_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&xq_description
|
||||||
};
|
};
|
||||||
|
|
||||||
CTLR xq_ctrl[] = {
|
CTLR xq_ctrl[] = {
|
||||||
|
@ -2973,3 +2976,8 @@ void xq_debug_turbo_setup(CTLR* xq)
|
||||||
sim_debug(DBG_SET, xq->dev, "%s: setup> set Transmit Ring Buffer Address: %02X%04X\n",
|
sim_debug(DBG_SET, xq->dev, "%s: setup> set Transmit Ring Buffer Address: %02X%04X\n",
|
||||||
xq->dev->name, xq->var->init.tdra_h, xq->var->init.tdra_l);
|
xq->dev->name, xq->var->init.tdra_h, xq->var->init.tdra_l);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *xq_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "DELQA/DEQNA Ethernet controller";
|
||||||
|
}
|
|
@ -127,6 +127,7 @@ void xu_process_receive(CTLR* xu);
|
||||||
void xu_dump_rxring(CTLR* xu);
|
void xu_dump_rxring(CTLR* xu);
|
||||||
void xu_dump_txring(CTLR* xu);
|
void xu_dump_txring(CTLR* xu);
|
||||||
t_stat xu_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc);
|
t_stat xu_show_filters (FILE* st, UNIT* uptr, int32 val, void* desc);
|
||||||
|
char *xu_description (DEVICE *dptr);
|
||||||
|
|
||||||
#define IOLN_XU 010
|
#define IOLN_XU 010
|
||||||
|
|
||||||
|
@ -224,7 +225,8 @@ DEVICE xu_dev = {
|
||||||
&xu_ex, &xu_dep, &xu_reset,
|
&xu_ex, &xu_dep, &xu_reset,
|
||||||
NULL, &xu_attach, &xu_detach,
|
NULL, &xu_attach, &xu_detach,
|
||||||
&xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER,
|
&xua_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER,
|
||||||
0, xu_debug
|
0, xu_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&xu_description
|
||||||
};
|
};
|
||||||
|
|
||||||
#define IOLN_XU 010
|
#define IOLN_XU 010
|
||||||
|
@ -284,7 +286,8 @@ DEVICE xub_dev = {
|
||||||
&xu_ex, &xu_dep, &xu_reset,
|
&xu_ex, &xu_dep, &xu_reset,
|
||||||
NULL, &xu_attach, &xu_detach,
|
NULL, &xu_attach, &xu_detach,
|
||||||
&xub_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER,
|
&xub_dib, DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG | DEV_ETHER,
|
||||||
0, xu_debug
|
0, xu_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&xu_description
|
||||||
};
|
};
|
||||||
|
|
||||||
#define XU_MAX_CONTROLLERS 2
|
#define XU_MAX_CONTROLLERS 2
|
||||||
|
@ -1783,3 +1786,10 @@ void xu_dump_txring (CTLR* xu)
|
||||||
printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, txhdr[0], txhdr[1], txhdr[2], txhdr[3]);
|
printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", i, own, len, addr, txhdr[0], txhdr[1], txhdr[2], txhdr[3]);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *xu_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "DEUNA/DELUA Ethernet controller";
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -40,6 +40,7 @@ extern jmp_buf save_env;
|
||||||
|
|
||||||
int32 eval_int (void);
|
int32 eval_int (void);
|
||||||
t_stat qba_reset (DEVICE *dptr);
|
t_stat qba_reset (DEVICE *dptr);
|
||||||
|
char *qba_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* Qbus adapter data structures
|
/* Qbus adapter data structures
|
||||||
|
|
||||||
|
@ -74,7 +75,8 @@ DEVICE qba_dev = {
|
||||||
1, 16, 4, 2, 16, 16,
|
1, 16, 4, 2, 16, 16,
|
||||||
NULL, NULL, &qba_reset,
|
NULL, NULL, &qba_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, DEV_QBUS
|
NULL, DEV_QBUS, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&qba_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IO page dispatches */
|
/* IO page dispatches */
|
||||||
|
@ -246,6 +248,11 @@ for (i = 0; i < IPL_HLVL; i++)
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *qba_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Qbus adapter";
|
||||||
|
}
|
||||||
|
|
||||||
/* Qbus I/O buffer routines, aligned access
|
/* Qbus I/O buffer routines, aligned access
|
||||||
|
|
||||||
Map_ReadB - fetch byte buffer from memory
|
Map_ReadB - fetch byte buffer from memory
|
||||||
|
|
|
@ -43,6 +43,7 @@ int32 mctl_count = 0;
|
||||||
t_stat mctl_rd (int32 *data, int32 PA, int32 access);
|
t_stat mctl_rd (int32 *data, int32 PA, int32 access);
|
||||||
t_stat mctl_wr (int32 data, int32 PA, int32 access);
|
t_stat mctl_wr (int32 data, int32 PA, int32 access);
|
||||||
t_stat mctl_reset (DEVICE *dptr);
|
t_stat mctl_reset (DEVICE *dptr);
|
||||||
|
char *mctl_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* MCTL data structures
|
/* MCTL data structures
|
||||||
|
|
||||||
|
@ -72,7 +73,8 @@ DEVICE mctl_dev = {
|
||||||
1, DEV_RDX, 20, 1, DEV_RDX, 8,
|
1, DEV_RDX, 20, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &mctl_reset,
|
NULL, NULL, &mctl_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&mctl_dib, DEV_Q18
|
&mctl_dib, DEV_Q18, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&mctl_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* I/O dispatch routines */
|
/* I/O dispatch routines */
|
||||||
|
@ -105,6 +107,11 @@ mctl_count = (int32)(MEMSIZE >> 18); /* memory controllers en
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *mctl_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "memory controller";
|
||||||
|
}
|
||||||
|
|
||||||
/* Used by CPU */
|
/* Used by CPU */
|
||||||
|
|
||||||
void rom_wr_B (int32 pa, int32 val)
|
void rom_wr_B (int32 pa, int32 val)
|
||||||
|
|
|
@ -87,6 +87,9 @@ t_stat clk_svc (UNIT *uptr);
|
||||||
t_stat tti_reset (DEVICE *dptr);
|
t_stat tti_reset (DEVICE *dptr);
|
||||||
t_stat tto_reset (DEVICE *dptr);
|
t_stat tto_reset (DEVICE *dptr);
|
||||||
t_stat clk_reset (DEVICE *dptr);
|
t_stat clk_reset (DEVICE *dptr);
|
||||||
|
char *tti_description (DEVICE *dptr);
|
||||||
|
char *tto_description (DEVICE *dptr);
|
||||||
|
char *clk_description (DEVICE *dptr);
|
||||||
void txdb_func (int32 data);
|
void txdb_func (int32 data);
|
||||||
|
|
||||||
extern int32 sysd_hlt_enb (void);
|
extern int32 sysd_hlt_enb (void);
|
||||||
|
@ -128,7 +131,8 @@ DEVICE tti_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tti_reset,
|
NULL, NULL, &tti_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&tti_dib, 0
|
&tti_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tti_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TTO data structures
|
/* TTO data structures
|
||||||
|
@ -167,7 +171,8 @@ DEVICE tto_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tto_reset,
|
NULL, NULL, &tto_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&tto_dib, 0
|
&tto_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tto_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* CLK data structures
|
/* CLK data structures
|
||||||
|
@ -201,7 +206,8 @@ DEVICE clk_dev = {
|
||||||
1, 0, 0, 0, 0, 0,
|
1, 0, 0, 0, 0, 0,
|
||||||
NULL, NULL, &clk_reset,
|
NULL, NULL, &clk_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&clk_dib, 0
|
&clk_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&clk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Clock and terminal MxPR routines
|
/* Clock and terminal MxPR routines
|
||||||
|
@ -352,6 +358,11 @@ sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tti_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal input";
|
||||||
|
}
|
||||||
|
|
||||||
/* Terminal output routines
|
/* Terminal output routines
|
||||||
|
|
||||||
tto_svc process event (character typed)
|
tto_svc process event (character typed)
|
||||||
|
@ -386,6 +397,11 @@ sim_cancel (&tto_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tto_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal output";
|
||||||
|
}
|
||||||
|
|
||||||
/* Clock routines
|
/* Clock routines
|
||||||
|
|
||||||
clk_svc process event (clock tick)
|
clk_svc process event (clock tick)
|
||||||
|
@ -422,3 +438,8 @@ tmxr_poll = t * TMXR_MULT; /* set mux poll */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *clk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "100hz clock tick";
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
@ -68,6 +68,7 @@ static struct boot_dev boot_tab[] = {
|
||||||
};
|
};
|
||||||
|
|
||||||
t_stat sysd_reset (DEVICE *dptr);
|
t_stat sysd_reset (DEVICE *dptr);
|
||||||
|
char *sysd_description (DEVICE *dptr);
|
||||||
t_stat vax610_boot (int32 flag, char *ptr);
|
t_stat vax610_boot (int32 flag, char *ptr);
|
||||||
t_stat vax610_boot_parse (int32 flag, char *ptr);
|
t_stat vax610_boot_parse (int32 flag, char *ptr);
|
||||||
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
|
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
|
||||||
|
@ -108,7 +109,8 @@ DEVICE sysd_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &sysd_reset,
|
NULL, NULL, &sysd_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&sysd_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Special boot command, overrides regular boot */
|
/* Special boot command, overrides regular boot */
|
||||||
|
@ -482,6 +484,11 @@ sim_vm_cmd = vax610_cmd;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *sysd_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "system devices";
|
||||||
|
}
|
||||||
|
|
||||||
t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc)
|
t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||||
{
|
{
|
||||||
return SCPE_NOFNC;
|
return SCPE_NOFNC;
|
||||||
|
|
|
@ -64,6 +64,9 @@ t_stat clk_svc (UNIT *uptr);
|
||||||
t_stat tti_reset (DEVICE *dptr);
|
t_stat tti_reset (DEVICE *dptr);
|
||||||
t_stat tto_reset (DEVICE *dptr);
|
t_stat tto_reset (DEVICE *dptr);
|
||||||
t_stat clk_reset (DEVICE *dptr);
|
t_stat clk_reset (DEVICE *dptr);
|
||||||
|
char *tti_description (DEVICE *dptr);
|
||||||
|
char *tto_description (DEVICE *dptr);
|
||||||
|
char *clk_description (DEVICE *dptr);
|
||||||
|
|
||||||
extern int32 sysd_hlt_enb (void);
|
extern int32 sysd_hlt_enb (void);
|
||||||
|
|
||||||
|
@ -103,7 +106,8 @@ DEVICE tti_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tti_reset,
|
NULL, NULL, &tti_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&tti_dib, 0
|
&tti_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tti_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TTO data structures
|
/* TTO data structures
|
||||||
|
@ -142,7 +146,8 @@ DEVICE tto_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tto_reset,
|
NULL, NULL, &tto_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&tto_dib, 0
|
&tto_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tto_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* CLK data structures
|
/* CLK data structures
|
||||||
|
@ -176,7 +181,8 @@ DEVICE clk_dev = {
|
||||||
1, 0, 0, 0, 0, 0,
|
1, 0, 0, 0, 0, 0,
|
||||||
NULL, NULL, &clk_reset,
|
NULL, NULL, &clk_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&clk_dib, 0
|
&clk_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&clk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Clock and terminal MxPR routines
|
/* Clock and terminal MxPR routines
|
||||||
|
@ -287,6 +293,11 @@ sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tti_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal input";
|
||||||
|
}
|
||||||
|
|
||||||
/* Terminal output routines
|
/* Terminal output routines
|
||||||
|
|
||||||
tto_svc process event (character typed)
|
tto_svc process event (character typed)
|
||||||
|
@ -321,6 +332,11 @@ sim_cancel (&tto_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tto_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal output";
|
||||||
|
}
|
||||||
|
|
||||||
/* Clock routines
|
/* Clock routines
|
||||||
|
|
||||||
clk_svc process event (clock tick)
|
clk_svc process event (clock tick)
|
||||||
|
@ -358,3 +374,7 @@ tmxr_poll = t * TMXR_MULT; /* set mux poll */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *clk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "100hz clock tick";
|
||||||
|
}
|
||||||
|
|
|
@ -155,12 +155,15 @@ t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat rom_reset (DEVICE *dptr);
|
t_stat rom_reset (DEVICE *dptr);
|
||||||
t_stat rom_set_diag (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat rom_set_diag (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat rom_show_diag (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat rom_show_diag (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *rom_description (DEVICE *dptr);
|
||||||
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat nvr_reset (DEVICE *dptr);
|
t_stat nvr_reset (DEVICE *dptr);
|
||||||
t_stat nvr_attach (UNIT *uptr, char *cptr);
|
t_stat nvr_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat nvr_detach (UNIT *uptr);
|
t_stat nvr_detach (UNIT *uptr);
|
||||||
|
char *nvr_description (DEVICE *dptr);
|
||||||
t_stat sysd_reset (DEVICE *dptr);
|
t_stat sysd_reset (DEVICE *dptr);
|
||||||
|
char *sysd_description (DEVICE *dptr);
|
||||||
|
|
||||||
int32 rom_rd (int32 pa);
|
int32 rom_rd (int32 pa);
|
||||||
int32 nvr_rd (int32 pa);
|
int32 nvr_rd (int32 pa);
|
||||||
|
@ -216,7 +219,8 @@ DEVICE rom_dev = {
|
||||||
1, 16, ROMAWIDTH, 4, 16, 32,
|
1, 16, ROMAWIDTH, 4, 16, 32,
|
||||||
&rom_ex, &rom_dep, &rom_reset,
|
&rom_ex, &rom_dep, &rom_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rom_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* NVR data structures
|
/* NVR data structures
|
||||||
|
@ -238,7 +242,8 @@ DEVICE nvr_dev = {
|
||||||
1, 16, NVRAWIDTH, 4, 16, 32,
|
1, 16, NVRAWIDTH, 4, 16, 32,
|
||||||
&nvr_ex, &nvr_dep, &nvr_reset,
|
&nvr_ex, &nvr_dep, &nvr_reset,
|
||||||
NULL, &nvr_attach, &nvr_detach,
|
NULL, &nvr_attach, &nvr_detach,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&nvr_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* SYSD data structures
|
/* SYSD data structures
|
||||||
|
@ -266,7 +271,8 @@ DEVICE sysd_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &sysd_reset,
|
NULL, NULL, &sysd_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&sysd_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* ROM: read only memory - stored in a buffered file
|
/* ROM: read only memory - stored in a buffered file
|
||||||
|
@ -391,6 +397,11 @@ if (rom == NULL)
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *rom_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "read-only memory";
|
||||||
|
}
|
||||||
|
|
||||||
/* NVR: non-volatile RAM - stored in a buffered file */
|
/* NVR: non-volatile RAM - stored in a buffered file */
|
||||||
|
|
||||||
int32 nvr_rd (int32 pa)
|
int32 nvr_rd (int32 pa)
|
||||||
|
@ -488,6 +499,11 @@ if ((uptr->flags & UNIT_ATT) == 0) {
|
||||||
return r;
|
return r;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *nvr_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "non-volatile memory";
|
||||||
|
}
|
||||||
|
|
||||||
/* Read KA630 specific IPR's */
|
/* Read KA630 specific IPR's */
|
||||||
|
|
||||||
int32 ReadIPR (int32 rg)
|
int32 ReadIPR (int32 rg)
|
||||||
|
@ -875,6 +891,11 @@ sim_vm_cmd = vax630_cmd;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *sysd_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "system devices";
|
||||||
|
}
|
||||||
|
|
||||||
/* SYSD powerup */
|
/* SYSD powerup */
|
||||||
|
|
||||||
t_stat sysd_powerup (void)
|
t_stat sysd_powerup (void)
|
||||||
|
|
|
@ -74,6 +74,7 @@ uint32 mcsr2 = 0;
|
||||||
t_stat mctl_reset (DEVICE *dptr);
|
t_stat mctl_reset (DEVICE *dptr);
|
||||||
t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
|
t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
|
||||||
t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
|
t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
|
||||||
|
char *mctl_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* MCTLx data structures
|
/* MCTLx data structures
|
||||||
|
|
||||||
|
@ -111,7 +112,8 @@ DEVICE mctl_dev = {
|
||||||
NULL, NULL, &mctl_reset,
|
NULL, NULL, &mctl_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&mctl_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
&mctl_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
||||||
mctl_deb, 0, 0
|
mctl_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&mctl_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Memory controller register read */
|
/* Memory controller register read */
|
||||||
|
@ -193,3 +195,8 @@ else
|
||||||
mcsr2 = mcsr2 | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */
|
mcsr2 = mcsr2 | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *mctl_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "memory controller";
|
||||||
|
}
|
||||||
|
|
|
@ -215,6 +215,7 @@ t_stat rb_rd32 (int32 *data, int32 PA, int32 access);
|
||||||
t_stat rb_wr32 (int32 data, int32 PA, int32 access);
|
t_stat rb_wr32 (int32 data, int32 PA, int32 access);
|
||||||
t_stat rb_svc (UNIT *uptr);
|
t_stat rb_svc (UNIT *uptr);
|
||||||
t_stat rb_reset (DEVICE *dptr);
|
t_stat rb_reset (DEVICE *dptr);
|
||||||
|
char *rb_description (DEVICE *dptr);
|
||||||
void rb_set_done (int32 error);
|
void rb_set_done (int32 error);
|
||||||
t_stat rb_attach (UNIT *uptr, char *cptr);
|
t_stat rb_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat rb_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat rb_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
|
@ -280,7 +281,8 @@ DEVICE rb_dev = {
|
||||||
NULL, NULL, &rb_reset,
|
NULL, NULL, &rb_reset,
|
||||||
NULL, &rb_attach, NULL,
|
NULL, &rb_attach, NULL,
|
||||||
&rb_dib, DEV_DISABLE | DEV_UBUS | DEV_DEBUG, 0,
|
&rb_dib, DEV_DISABLE | DEV_UBUS | DEV_DEBUG, 0,
|
||||||
rb_debug, 0, 0
|
rb_debug, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rb_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* I/O dispatch routines
|
/* I/O dispatch routines
|
||||||
|
@ -632,6 +634,11 @@ if (rbxb == NULL)
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *rb_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "RB730 disk controller";
|
||||||
|
}
|
||||||
|
|
||||||
/* Attach routine */
|
/* Attach routine */
|
||||||
|
|
||||||
t_stat rb_attach (UNIT *uptr, char *cptr)
|
t_stat rb_attach (UNIT *uptr, char *cptr)
|
||||||
|
|
|
@ -214,6 +214,11 @@ t_stat tmr_svc (UNIT *uptr);
|
||||||
t_stat tti_reset (DEVICE *dptr);
|
t_stat tti_reset (DEVICE *dptr);
|
||||||
t_stat tto_reset (DEVICE *dptr);
|
t_stat tto_reset (DEVICE *dptr);
|
||||||
t_stat clk_reset (DEVICE *dptr);
|
t_stat clk_reset (DEVICE *dptr);
|
||||||
|
char *tti_description (DEVICE *dptr);
|
||||||
|
char *tto_description (DEVICE *dptr);
|
||||||
|
char *clk_description (DEVICE *dptr);
|
||||||
|
char *tmr_description (DEVICE *dptr);
|
||||||
|
char *td_description (DEVICE *dptr);
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr);
|
t_stat clk_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat clk_detach (UNIT *uptr);
|
t_stat clk_detach (UNIT *uptr);
|
||||||
t_stat tmr_reset (DEVICE *dptr);
|
t_stat tmr_reset (DEVICE *dptr);
|
||||||
|
@ -258,7 +263,8 @@ DEVICE tti_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tti_reset,
|
NULL, NULL, &tti_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tti_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TTO data structures
|
/* TTO data structures
|
||||||
|
@ -293,7 +299,8 @@ DEVICE tto_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tto_reset,
|
NULL, NULL, &tto_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tto_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TODR and TMR data structures */
|
/* TODR and TMR data structures */
|
||||||
|
@ -317,7 +324,8 @@ DEVICE clk_dev = {
|
||||||
1, 0, 8, 4, 0, 32,
|
1, 0, 8, 4, 0, 32,
|
||||||
NULL, NULL, &clk_reset,
|
NULL, NULL, &clk_reset,
|
||||||
NULL, &clk_attach, &clk_detach,
|
NULL, &clk_attach, &clk_detach,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&clk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
||||||
|
@ -338,7 +346,8 @@ DEVICE tmr_dev = {
|
||||||
1, 0, 0, 0, 0, 0,
|
1, 0, 0, 0, 0, 0,
|
||||||
NULL, NULL, &tmr_reset,
|
NULL, NULL, &tmr_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tmr_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TU58 data structures
|
/* TU58 data structures
|
||||||
|
@ -376,7 +385,8 @@ DEVICE td_dev = {
|
||||||
2, DEV_RDX, 20, 1, DEV_RDX, 8,
|
2, DEV_RDX, 20, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &td_reset,
|
NULL, NULL, &td_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&td_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Console storage MxPR routines
|
/* Console storage MxPR routines
|
||||||
|
@ -675,6 +685,10 @@ sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tti_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal input";
|
||||||
|
}
|
||||||
/* Terminal output service (output character) */
|
/* Terminal output service (output character) */
|
||||||
|
|
||||||
t_stat tto_svc (UNIT *uptr)
|
t_stat tto_svc (UNIT *uptr)
|
||||||
|
@ -709,6 +723,11 @@ sim_cancel (&tto_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tto_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal output";
|
||||||
|
}
|
||||||
|
|
||||||
/* Programmable timer
|
/* Programmable timer
|
||||||
|
|
||||||
The architected VAX timer, which increments at 1Mhz, cannot be
|
The architected VAX timer, which increments at 1Mhz, cannot be
|
||||||
|
@ -871,6 +890,11 @@ if (clk_unit.filebuf == NULL) { /* make sure the TODR is
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *clk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "time of year clock";
|
||||||
|
}
|
||||||
|
|
||||||
/* CLK attach */
|
/* CLK attach */
|
||||||
|
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr)
|
t_stat clk_attach (UNIT *uptr, char *cptr)
|
||||||
|
@ -899,7 +923,6 @@ if ((uptr->flags & UNIT_ATT) == 0)
|
||||||
return r;
|
return r;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/* Interval timer reset */
|
/* Interval timer reset */
|
||||||
|
|
||||||
t_stat tmr_reset (DEVICE *dptr)
|
t_stat tmr_reset (DEVICE *dptr)
|
||||||
|
@ -914,6 +937,11 @@ todr_resync (); /* resync TODR */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tmr_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "interval timer";
|
||||||
|
}
|
||||||
|
|
||||||
/* TODR routines */
|
/* TODR routines */
|
||||||
|
|
||||||
int32 todr_rd (void)
|
int32 todr_rd (void)
|
||||||
|
@ -1192,3 +1220,8 @@ sim_cancel (&td_dev.units[0]);
|
||||||
sim_cancel (&td_dev.units[1]);
|
sim_cancel (&td_dev.units[1]);
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *td_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Console TU58 cartridge";
|
||||||
|
}
|
||||||
|
|
|
@ -81,6 +81,7 @@ extern jmp_buf save_env;
|
||||||
extern int32 p1;
|
extern int32 p1;
|
||||||
|
|
||||||
t_stat sysb_reset (DEVICE *dptr);
|
t_stat sysb_reset (DEVICE *dptr);
|
||||||
|
char *sysb_description (DEVICE *dptr);
|
||||||
t_stat vax730_boot (int32 flag, char *ptr);
|
t_stat vax730_boot (int32 flag, char *ptr);
|
||||||
t_stat vax730_boot_parse (int32 flag, char *ptr);
|
t_stat vax730_boot_parse (int32 flag, char *ptr);
|
||||||
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
|
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
|
||||||
|
@ -131,7 +132,8 @@ DEVICE sysb_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &sysb_reset,
|
NULL, NULL, &sysb_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&sysb_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Special boot command, overrides regular boot */
|
/* Special boot command, overrides regular boot */
|
||||||
|
@ -572,6 +574,11 @@ sim_vm_cmd = vax730_cmd;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *sysb_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "system bus controller";
|
||||||
|
}
|
||||||
|
|
||||||
/* Show nexus */
|
/* Show nexus */
|
||||||
|
|
||||||
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||||
|
|
|
@ -97,6 +97,7 @@ extern UNIT cpu_unit;
|
||||||
extern int32 p1;
|
extern int32 p1;
|
||||||
|
|
||||||
t_stat uba_reset (DEVICE *dptr);
|
t_stat uba_reset (DEVICE *dptr);
|
||||||
|
char *uba_description (DEVICE *dptr);
|
||||||
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
|
t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
|
||||||
|
@ -180,7 +181,8 @@ DEVICE uba_dev = {
|
||||||
&uba_ex, &uba_dep, &uba_reset,
|
&uba_ex, &uba_dep, &uba_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
&uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
||||||
uba_deb, 0, 0
|
uba_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&uba_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Read Unibus adapter register - aligned lw only */
|
/* Read Unibus adapter register - aligned lw only */
|
||||||
|
@ -662,3 +664,8 @@ if (cptr) {
|
||||||
fprintf (of, "Invalid argument\n");
|
fprintf (of, "Invalid argument\n");
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *uba_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Unibus adapter";
|
||||||
|
}
|
||||||
|
|
|
@ -101,6 +101,7 @@ extern jmp_buf save_env;
|
||||||
extern int32 p1;
|
extern int32 p1;
|
||||||
|
|
||||||
t_stat cmi_reset (DEVICE *dptr);
|
t_stat cmi_reset (DEVICE *dptr);
|
||||||
|
char *cmi_description (DEVICE *dptr);
|
||||||
void cmi_set_tmo (void);
|
void cmi_set_tmo (void);
|
||||||
t_stat vax750_boot (int32 flag, char *ptr);
|
t_stat vax750_boot (int32 flag, char *ptr);
|
||||||
t_stat vax750_boot_parse (int32 flag, char *ptr);
|
t_stat vax750_boot_parse (int32 flag, char *ptr);
|
||||||
|
@ -158,7 +159,8 @@ DEVICE cmi_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &cmi_reset,
|
NULL, NULL, &cmi_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&cmi_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Special boot command, overrides regular boot */
|
/* Special boot command, overrides regular boot */
|
||||||
|
@ -659,6 +661,11 @@ cmi_cadr = 0;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *cmi_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "CPU/Memory interconnect";
|
||||||
|
}
|
||||||
|
|
||||||
/* Show nexus */
|
/* Show nexus */
|
||||||
|
|
||||||
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||||
|
|
|
@ -84,6 +84,7 @@ uint32 mcsr1 = 0;
|
||||||
uint32 mcsr2 = 0;
|
uint32 mcsr2 = 0;
|
||||||
|
|
||||||
t_stat mctl_reset (DEVICE *dptr);
|
t_stat mctl_reset (DEVICE *dptr);
|
||||||
|
char *mctl_description (DEVICE *dptr);
|
||||||
t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
|
t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
|
||||||
t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
|
t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
|
||||||
|
|
||||||
|
@ -120,7 +121,8 @@ DEVICE mctl_dev = {
|
||||||
NULL, NULL, &mctl_reset,
|
NULL, NULL, &mctl_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&mctl_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
&mctl_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
||||||
mctl_deb, 0, 0
|
mctl_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&mctl_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Memory controller register read */
|
/* Memory controller register read */
|
||||||
|
@ -204,3 +206,8 @@ else
|
||||||
mcsr2 = MCSR2_INIT | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */
|
mcsr2 = MCSR2_INIT | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K); /* Use 16k chips */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *mctl_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Memory controller";
|
||||||
|
}
|
||||||
|
|
|
@ -212,11 +212,16 @@ t_stat tmr_svc (UNIT *uptr);
|
||||||
t_stat tti_reset (DEVICE *dptr);
|
t_stat tti_reset (DEVICE *dptr);
|
||||||
t_stat tto_reset (DEVICE *dptr);
|
t_stat tto_reset (DEVICE *dptr);
|
||||||
t_stat clk_reset (DEVICE *dptr);
|
t_stat clk_reset (DEVICE *dptr);
|
||||||
|
char *tti_description (DEVICE *dptr);
|
||||||
|
char *tto_description (DEVICE *dptr);
|
||||||
|
char *clk_description (DEVICE *dptr);
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr);
|
t_stat clk_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat clk_detach (UNIT *uptr);
|
t_stat clk_detach (UNIT *uptr);
|
||||||
t_stat tmr_reset (DEVICE *dptr);
|
t_stat tmr_reset (DEVICE *dptr);
|
||||||
|
char *tmr_description (DEVICE *dptr);
|
||||||
t_stat td_svc (UNIT *uptr);
|
t_stat td_svc (UNIT *uptr);
|
||||||
t_stat td_reset (DEVICE *dptr);
|
t_stat td_reset (DEVICE *dptr);
|
||||||
|
char *td_description (DEVICE *dptr);
|
||||||
int32 icr_rd (t_bool interp);
|
int32 icr_rd (t_bool interp);
|
||||||
void tmr_incr (uint32 inc);
|
void tmr_incr (uint32 inc);
|
||||||
void tmr_sched (void);
|
void tmr_sched (void);
|
||||||
|
@ -258,7 +263,8 @@ DEVICE tti_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tti_reset,
|
NULL, NULL, &tti_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tti_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TTO data structures
|
/* TTO data structures
|
||||||
|
@ -293,7 +299,8 @@ DEVICE tto_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tto_reset,
|
NULL, NULL, &tto_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tto_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TODR and TMR data structures */
|
/* TODR and TMR data structures */
|
||||||
|
@ -317,7 +324,8 @@ DEVICE clk_dev = {
|
||||||
1, 0, 8, 4, 0, 32,
|
1, 0, 8, 4, 0, 32,
|
||||||
NULL, NULL, &clk_reset,
|
NULL, NULL, &clk_reset,
|
||||||
NULL, &clk_attach, &clk_detach,
|
NULL, &clk_attach, &clk_detach,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&clk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
||||||
|
@ -338,7 +346,8 @@ DEVICE tmr_dev = {
|
||||||
1, 0, 0, 0, 0, 0,
|
1, 0, 0, 0, 0, 0,
|
||||||
NULL, NULL, &tmr_reset,
|
NULL, NULL, &tmr_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tmr_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TU58 data structures
|
/* TU58 data structures
|
||||||
|
@ -374,7 +383,8 @@ DEVICE td_dev = {
|
||||||
1, DEV_RDX, 20, 1, DEV_RDX, 8,
|
1, DEV_RDX, 20, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &td_reset,
|
NULL, NULL, &td_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&td_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Console storage MxPR routines
|
/* Console storage MxPR routines
|
||||||
|
@ -671,6 +681,11 @@ csi_int = 0;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tti_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal input";
|
||||||
|
}
|
||||||
|
|
||||||
/* Terminal output service (output character) */
|
/* Terminal output service (output character) */
|
||||||
|
|
||||||
t_stat tto_svc (UNIT *uptr)
|
t_stat tto_svc (UNIT *uptr)
|
||||||
|
@ -705,6 +720,11 @@ sim_cancel (&tto_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tto_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal output";
|
||||||
|
}
|
||||||
|
|
||||||
/* Programmable timer
|
/* Programmable timer
|
||||||
|
|
||||||
The architected VAX timer, which increments at 1Mhz, cannot be
|
The architected VAX timer, which increments at 1Mhz, cannot be
|
||||||
|
@ -867,6 +887,11 @@ if (clk_unit.filebuf == NULL) { /* make sure the TODR is
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *clk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "time of year clock";
|
||||||
|
}
|
||||||
|
|
||||||
/* CLK attach */
|
/* CLK attach */
|
||||||
|
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr)
|
t_stat clk_attach (UNIT *uptr, char *cptr)
|
||||||
|
@ -910,6 +935,11 @@ todr_resync (); /* resync TODR */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tmr_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "interval timer";
|
||||||
|
}
|
||||||
|
|
||||||
/* TODR routines */
|
/* TODR routines */
|
||||||
|
|
||||||
int32 todr_rd (void)
|
int32 todr_rd (void)
|
||||||
|
@ -1185,3 +1215,8 @@ td_txsize = 0;
|
||||||
sim_cancel (&td_unit);
|
sim_cancel (&td_unit);
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *td_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Console TU58 cartridge";
|
||||||
|
}
|
||||||
|
|
|
@ -95,6 +95,7 @@ extern int32 fault_PC; /* fault PC */
|
||||||
extern int32 mem_err;
|
extern int32 mem_err;
|
||||||
|
|
||||||
t_stat uba_reset (DEVICE *dptr);
|
t_stat uba_reset (DEVICE *dptr);
|
||||||
|
char *uba_description (DEVICE *dptr);
|
||||||
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
|
t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
|
||||||
|
@ -181,7 +182,8 @@ DEVICE uba_dev = {
|
||||||
&uba_ex, &uba_dep, &uba_reset,
|
&uba_ex, &uba_dep, &uba_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
&uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
||||||
uba_deb, 0, 0
|
uba_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&uba_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Read Unibus adapter register - aligned lw only */
|
/* Read Unibus adapter register - aligned lw only */
|
||||||
|
@ -632,6 +634,11 @@ uba_csr3 = 0;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *uba_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Unibus adapter";
|
||||||
|
}
|
||||||
|
|
||||||
/* Memory examine via map (word only) */
|
/* Memory examine via map (word only) */
|
||||||
|
|
||||||
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
|
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
|
||||||
|
|
|
@ -88,6 +88,7 @@ uint32 rom_lw[MCTL_NUM][ROMSIZE >> 2];
|
||||||
extern UNIT cpu_unit;
|
extern UNIT cpu_unit;
|
||||||
|
|
||||||
t_stat mctl_reset (DEVICE *dptr);
|
t_stat mctl_reset (DEVICE *dptr);
|
||||||
|
char *mctl_description (DEVICE *dptr);
|
||||||
t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
|
t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
|
||||||
t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
|
t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
|
||||||
|
|
||||||
|
@ -141,14 +142,18 @@ DEVICE mctl_dev[] = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &mctl_reset,
|
NULL, NULL, &mctl_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&mctl0_dib, DEV_NEXUS
|
&mctl0_dib, DEV_NEXUS, 0,
|
||||||
|
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&mctl_description
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"MCTL1", &mctl1_unit, mctl1_reg, mctl1_mod,
|
"MCTL1", &mctl1_unit, mctl1_reg, mctl1_mod,
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &mctl_reset,
|
NULL, NULL, &mctl_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&mctl1_dib, DEV_NEXUS
|
&mctl1_dib, DEV_NEXUS, 0,
|
||||||
|
NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&mctl_description
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -276,3 +281,11 @@ for (i = 0; i < MCTL_NUM; i++) { /* init for MS780C */
|
||||||
}
|
}
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *mctl_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
static char buf[64];
|
||||||
|
|
||||||
|
sprintf (buf, "Memory controller %d", (int)(dptr-mctl_dev));
|
||||||
|
return buf;
|
||||||
|
}
|
||||||
|
|
|
@ -138,6 +138,7 @@ extern jmp_buf save_env;
|
||||||
extern int32 p1;
|
extern int32 p1;
|
||||||
|
|
||||||
t_stat sbi_reset (DEVICE *dptr);
|
t_stat sbi_reset (DEVICE *dptr);
|
||||||
|
char *sbi_description (DEVICE *dptr);
|
||||||
void sbi_set_tmo (int32 pa);
|
void sbi_set_tmo (int32 pa);
|
||||||
void uba_eval_int (void);
|
void uba_eval_int (void);
|
||||||
t_stat vax780_boot (int32 flag, char *ptr);
|
t_stat vax780_boot (int32 flag, char *ptr);
|
||||||
|
@ -195,7 +196,8 @@ DEVICE sbi_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &sbi_reset,
|
NULL, NULL, &sbi_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&sbi_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Special boot command, overrides regular boot */
|
/* Special boot command, overrides regular boot */
|
||||||
|
@ -727,6 +729,11 @@ sim_vm_cmd = vax780_cmd;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *sbi_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Synchronous Backplane Interconnect";
|
||||||
|
}
|
||||||
|
|
||||||
/* Show nexus */
|
/* Show nexus */
|
||||||
|
|
||||||
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||||
|
|
|
@ -228,6 +228,11 @@ t_stat tmr_svc (UNIT *uptr);
|
||||||
t_stat tti_reset (DEVICE *dptr);
|
t_stat tti_reset (DEVICE *dptr);
|
||||||
t_stat tto_reset (DEVICE *dptr);
|
t_stat tto_reset (DEVICE *dptr);
|
||||||
t_stat clk_reset (DEVICE *dptr);
|
t_stat clk_reset (DEVICE *dptr);
|
||||||
|
char *tti_description (DEVICE *dptr);
|
||||||
|
char *tto_description (DEVICE *dptr);
|
||||||
|
char *clk_description (DEVICE *dptr);
|
||||||
|
char *tmr_description (DEVICE *dptr);
|
||||||
|
char *fl_description (DEVICE *dptr);
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr);
|
t_stat clk_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat clk_detach (UNIT *uptr);
|
t_stat clk_detach (UNIT *uptr);
|
||||||
t_stat tmr_reset (DEVICE *dptr);
|
t_stat tmr_reset (DEVICE *dptr);
|
||||||
|
@ -274,7 +279,8 @@ DEVICE tti_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tti_reset,
|
NULL, NULL, &tti_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tti_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TTO data structures
|
/* TTO data structures
|
||||||
|
@ -309,7 +315,8 @@ DEVICE tto_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tto_reset,
|
NULL, NULL, &tto_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tto_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TODR and TMR data structures */
|
/* TODR and TMR data structures */
|
||||||
|
@ -333,7 +340,8 @@ DEVICE clk_dev = {
|
||||||
1, 0, 8, 4, 0, 32,
|
1, 0, 8, 4, 0, 32,
|
||||||
NULL, NULL, &clk_reset,
|
NULL, NULL, &clk_reset,
|
||||||
NULL, &clk_attach, &clk_detach,
|
NULL, &clk_attach, &clk_detach,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&clk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
||||||
|
@ -354,7 +362,8 @@ DEVICE tmr_dev = {
|
||||||
1, 0, 0, 0, 0, 0,
|
1, 0, 0, 0, 0, 0,
|
||||||
NULL, NULL, &tmr_reset,
|
NULL, NULL, &tmr_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tmr_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* RX01 data structures
|
/* RX01 data structures
|
||||||
|
@ -396,7 +405,8 @@ DEVICE fl_dev = {
|
||||||
1, DEV_RDX, 20, 1, DEV_RDX, 8,
|
1, DEV_RDX, 20, 1, DEV_RDX, 8,
|
||||||
NULL, NULL, &fl_reset,
|
NULL, NULL, &fl_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&fl_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Terminal MxPR routines
|
/* Terminal MxPR routines
|
||||||
|
@ -465,6 +475,8 @@ t_stat tti_svc (UNIT *uptr)
|
||||||
int32 c;
|
int32 c;
|
||||||
|
|
||||||
sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
|
sim_clock_coschedule (uptr, tmxr_poll); /* continue poll */
|
||||||
|
if (tti_csr & CSR_DONE) /* is last input processed yet? */
|
||||||
|
return SCPE_OK; /* wait */
|
||||||
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
|
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
|
||||||
return c;
|
return c;
|
||||||
if (c & SCPE_BREAK) /* break? */
|
if (c & SCPE_BREAK) /* break? */
|
||||||
|
@ -489,6 +501,11 @@ sim_activate (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tti_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal input";
|
||||||
|
}
|
||||||
|
|
||||||
/* Terminal output service (output character) */
|
/* Terminal output service (output character) */
|
||||||
|
|
||||||
t_stat tto_svc (UNIT *uptr)
|
t_stat tto_svc (UNIT *uptr)
|
||||||
|
@ -523,6 +540,11 @@ sim_cancel (&tto_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tto_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal output";
|
||||||
|
}
|
||||||
|
|
||||||
/* Programmable timer
|
/* Programmable timer
|
||||||
|
|
||||||
The architected VAX timer, which increments at 1Mhz, cannot be
|
The architected VAX timer, which increments at 1Mhz, cannot be
|
||||||
|
@ -685,6 +707,11 @@ if (clk_unit.filebuf == NULL) { /* make sure the TODR is
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *clk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "time of year clock";
|
||||||
|
}
|
||||||
|
|
||||||
/* CLK attach */
|
/* CLK attach */
|
||||||
|
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr)
|
t_stat clk_attach (UNIT *uptr, char *cptr)
|
||||||
|
@ -728,6 +755,11 @@ todr_resync (); /* resync TODR */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tmr_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "interval timer";
|
||||||
|
}
|
||||||
|
|
||||||
/* TODR routines */
|
/* TODR routines */
|
||||||
|
|
||||||
int32 todr_rd (void)
|
int32 todr_rd (void)
|
||||||
|
@ -1074,3 +1106,8 @@ else { /* 780 */
|
||||||
comm_region[COMM_GH] = 1;
|
comm_region[COMM_GH] = 1;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *fl_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console floppy";
|
||||||
|
}
|
||||||
|
|
|
@ -184,6 +184,7 @@ extern uint32 nexus_req[NEXUS_HLVL];
|
||||||
|
|
||||||
t_stat uba_svc (UNIT *uptr);
|
t_stat uba_svc (UNIT *uptr);
|
||||||
t_stat uba_reset (DEVICE *dptr);
|
t_stat uba_reset (DEVICE *dptr);
|
||||||
|
char *uba_description (DEVICE *dptr);
|
||||||
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
|
t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
|
||||||
|
@ -290,7 +291,8 @@ DEVICE uba_dev = {
|
||||||
&uba_ex, &uba_dep, &uba_reset,
|
&uba_ex, &uba_dep, &uba_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
&uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
||||||
uba_deb, 0, 0
|
uba_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&uba_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Read Unibus adapter register - aligned lw only */
|
/* Read Unibus adapter register - aligned lw only */
|
||||||
|
@ -931,6 +933,11 @@ uba_cnf = UBACNF_UBIC;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *uba_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Unibus adapter";
|
||||||
|
}
|
||||||
|
|
||||||
/* Memory examine via map (word only) */
|
/* Memory examine via map (word only) */
|
||||||
|
|
||||||
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
|
t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
|
||||||
|
|
|
@ -255,6 +255,7 @@ extern uint32 nexus_req[NEXUS_HLVL];
|
||||||
extern UNIT cpu_unit;
|
extern UNIT cpu_unit;
|
||||||
|
|
||||||
t_stat mba_reset (DEVICE *dptr);
|
t_stat mba_reset (DEVICE *dptr);
|
||||||
|
char *mba_description (DEVICE *dptr);
|
||||||
t_stat mba_rdreg (int32 *val, int32 pa, int32 mode);
|
t_stat mba_rdreg (int32 *val, int32 pa, int32 mode);
|
||||||
t_stat mba_wrreg (int32 val, int32 pa, int32 lnt);
|
t_stat mba_wrreg (int32 val, int32 pa, int32 lnt);
|
||||||
t_bool mba_map_addr (uint32 va, uint32 *ma, uint32 mb);
|
t_bool mba_map_addr (uint32 va, uint32 *ma, uint32 mb);
|
||||||
|
@ -340,7 +341,8 @@ DEVICE mba_dev[] = {
|
||||||
NULL, NULL, &mba_reset,
|
NULL, NULL, &mba_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&mba0_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
&mba0_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
||||||
mba_deb, 0, 0
|
mba_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&mba_description
|
||||||
},
|
},
|
||||||
{
|
{
|
||||||
"MBA1", &mba1_unit, mba1_reg, mba1_mod,
|
"MBA1", &mba1_unit, mba1_reg, mba1_mod,
|
||||||
|
@ -348,7 +350,8 @@ DEVICE mba_dev[] = {
|
||||||
NULL, NULL, &mba_reset,
|
NULL, NULL, &mba_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&mba1_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
&mba1_dib, DEV_NEXUS | DEV_DEBUG, 0,
|
||||||
mba_deb, 0, 0
|
mba_deb, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&mba_description
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -853,6 +856,14 @@ if (mbabort[mb]) /* reset device */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *mba_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
static char buf[64];
|
||||||
|
|
||||||
|
sprintf (buf, "Massbus adapter %d", (int)(dptr-mba_dev));
|
||||||
|
return buf;
|
||||||
|
}
|
||||||
|
|
||||||
/* Show Massbus adapter number */
|
/* Show Massbus adapter number */
|
||||||
|
|
||||||
t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc)
|
t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||||
|
|
|
@ -123,6 +123,7 @@ extern UNIT cpu_unit;
|
||||||
|
|
||||||
void uba_eval_int (void);
|
void uba_eval_int (void);
|
||||||
t_stat abus_reset (DEVICE *dptr);
|
t_stat abus_reset (DEVICE *dptr);
|
||||||
|
char *abus_description (DEVICE *dptr);
|
||||||
t_stat vax860_boot (int32 flag, char *ptr);
|
t_stat vax860_boot (int32 flag, char *ptr);
|
||||||
t_stat vax860_boot_parse (int32 flag, char *ptr);
|
t_stat vax860_boot_parse (int32 flag, char *ptr);
|
||||||
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
|
t_stat cpu_boot (int32 unitno, DEVICE *dptr);
|
||||||
|
@ -177,7 +178,8 @@ DEVICE abus_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &abus_reset,
|
NULL, NULL, &abus_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&abus_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Special boot command, overrides regular boot */
|
/* Special boot command, overrides regular boot */
|
||||||
|
@ -682,6 +684,12 @@ sim_vm_cmd = vax860_cmd;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *abus_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "bus controller";
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
/* Build dib_tab from device list */
|
/* Build dib_tab from device list */
|
||||||
|
|
||||||
t_stat build_dib_tab (void)
|
t_stat build_dib_tab (void)
|
||||||
|
|
|
@ -92,6 +92,7 @@ extern int32 fault_PC; /* fault PC */
|
||||||
extern UNIT cpu_unit;
|
extern UNIT cpu_unit;
|
||||||
|
|
||||||
t_stat sbia_reset (DEVICE *dptr);
|
t_stat sbia_reset (DEVICE *dptr);
|
||||||
|
char *sbia_description (DEVICE *dptr);
|
||||||
void sbi_set_tmo (int32 pa);
|
void sbi_set_tmo (int32 pa);
|
||||||
t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
|
t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
|
||||||
t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
|
t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
|
||||||
|
@ -127,7 +128,8 @@ DEVICE sbia_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &sbia_reset,
|
NULL, NULL, &sbia_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&sbia_description
|
||||||
};
|
};
|
||||||
|
|
||||||
int32 sbia_rd (int32 pa, int32 lnt)
|
int32 sbia_rd (int32 pa, int32 lnt)
|
||||||
|
@ -300,6 +302,11 @@ sbi_csr = SBICSR_SCOEN | SBICSR_SCIEN;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *sbia_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "SBI adapter";
|
||||||
|
}
|
||||||
|
|
||||||
/* Show nexus */
|
/* Show nexus */
|
||||||
|
|
||||||
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||||
|
|
|
@ -245,10 +245,14 @@ t_stat rlcs_svc (UNIT *uptr);
|
||||||
t_stat tti_reset (DEVICE *dptr);
|
t_stat tti_reset (DEVICE *dptr);
|
||||||
t_stat tto_reset (DEVICE *dptr);
|
t_stat tto_reset (DEVICE *dptr);
|
||||||
t_stat clk_reset (DEVICE *dptr);
|
t_stat clk_reset (DEVICE *dptr);
|
||||||
|
char *tti_description (DEVICE *dptr);
|
||||||
|
char *tto_description (DEVICE *dptr);
|
||||||
|
char *clk_description (DEVICE *dptr);
|
||||||
|
char *tmr_description (DEVICE *dptr);
|
||||||
|
char *rlcs_description (DEVICE *dptr);
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr);
|
t_stat clk_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat clk_detach (UNIT *uptr);
|
t_stat clk_detach (UNIT *uptr);
|
||||||
t_stat tmr_reset (DEVICE *dptr);
|
t_stat tmr_reset (DEVICE *dptr);
|
||||||
t_stat lc_reset (DEVICE *dptr);
|
|
||||||
t_stat rlcs_reset (DEVICE *dptr);
|
t_stat rlcs_reset (DEVICE *dptr);
|
||||||
t_stat rlcs_attach (UNIT *uptr, char *cptr);
|
t_stat rlcs_attach (UNIT *uptr, char *cptr);
|
||||||
int32 icr_rd (t_bool interp);
|
int32 icr_rd (t_bool interp);
|
||||||
|
@ -295,7 +299,8 @@ DEVICE tti_dev = {
|
||||||
4, 10, 31, 1, 16, 8,
|
4, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tti_reset,
|
NULL, NULL, &tti_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tti_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TTO data structures
|
/* TTO data structures
|
||||||
|
@ -335,7 +340,8 @@ DEVICE tto_dev = {
|
||||||
4, 10, 31, 1, 16, 8,
|
4, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tto_reset,
|
NULL, NULL, &tto_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tto_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TODR and TMR data structures */
|
/* TODR and TMR data structures */
|
||||||
|
@ -359,7 +365,8 @@ DEVICE clk_dev = {
|
||||||
1, 0, 8, 4, 0, 32,
|
1, 0, 8, 4, 0, 32,
|
||||||
NULL, NULL, &clk_reset,
|
NULL, NULL, &clk_reset,
|
||||||
NULL, &clk_attach, &clk_detach,
|
NULL, &clk_attach, &clk_detach,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&clk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
UNIT tmr_unit = { UDATA (&tmr_svc, 0, 0) }; /* timer */
|
||||||
|
@ -380,7 +387,8 @@ DEVICE tmr_dev = {
|
||||||
1, 0, 0, 0, 0, 0,
|
1, 0, 0, 0, 0, 0,
|
||||||
NULL, NULL, &tmr_reset,
|
NULL, NULL, &tmr_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tmr_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Console storage structures
|
/* Console storage structures
|
||||||
|
@ -412,7 +420,8 @@ DEVICE rlcs_dev = {
|
||||||
1, 10, 24, 1, 16, 16,
|
1, 10, 24, 1, 16, 16,
|
||||||
NULL, NULL, &rlcs_reset,
|
NULL, NULL, &rlcs_reset,
|
||||||
NULL, &rlcs_attach, NULL,
|
NULL, &rlcs_attach, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rlcs_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Terminal MxPR routines
|
/* Terminal MxPR routines
|
||||||
|
@ -613,6 +622,11 @@ sim_activate_abs (&tti_unit[ID_CT], KBD_WAIT (tti_unit[ID_CT].wait, tmr_poll));
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tti_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal input";
|
||||||
|
}
|
||||||
|
|
||||||
/* Terminal output service (output character) */
|
/* Terminal output service (output character) */
|
||||||
|
|
||||||
t_stat tto_svc (UNIT *uptr)
|
t_stat tto_svc (UNIT *uptr)
|
||||||
|
@ -660,6 +674,11 @@ sim_cancel (&tto_unit[ID_LC]);
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tto_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal output";
|
||||||
|
}
|
||||||
|
|
||||||
/* Programmable timer
|
/* Programmable timer
|
||||||
|
|
||||||
The architected VAX timer, which increments at 1Mhz, cannot be
|
The architected VAX timer, which increments at 1Mhz, cannot be
|
||||||
|
@ -822,6 +841,11 @@ if (clk_unit.filebuf == NULL) { /* make sure the TODR is
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *clk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "time of year clock";
|
||||||
|
}
|
||||||
|
|
||||||
/* CLK attach */
|
/* CLK attach */
|
||||||
|
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr)
|
t_stat clk_attach (UNIT *uptr, char *cptr)
|
||||||
|
@ -864,6 +888,11 @@ todr_resync (); /* resync TODR */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tmr_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "interval timer";
|
||||||
|
}
|
||||||
|
|
||||||
/* TODR routines */
|
/* TODR routines */
|
||||||
|
|
||||||
int32 todr_rd (void)
|
int32 todr_rd (void)
|
||||||
|
@ -1129,6 +1158,11 @@ sim_cancel (&rlcs_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *rlcs_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Console RL02 disk";
|
||||||
|
}
|
||||||
|
|
||||||
t_stat rlcs_attach (UNIT *uptr, char *cptr)
|
t_stat rlcs_attach (UNIT *uptr, char *cptr)
|
||||||
{
|
{
|
||||||
uint32 p;
|
uint32 p;
|
||||||
|
|
|
@ -388,6 +388,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat cpu_show_virt (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat cpu_show_virt (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat cpu_set_idle (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat cpu_set_idle (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat cpu_show_idle (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat cpu_show_idle (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *cpu_description (DEVICE *dptr);
|
||||||
int32 cpu_get_vsw (int32 sw);
|
int32 cpu_get_vsw (int32 sw);
|
||||||
SIM_INLINE int32 get_istr (int32 lnt, int32 acc);
|
SIM_INLINE int32 get_istr (int32 lnt, int32 acc);
|
||||||
int32 ReadOcta (int32 va, int32 *opnd, int32 j, int32 acc);
|
int32 ReadOcta (int32 va, int32 *opnd, int32 j, int32 acc);
|
||||||
|
@ -491,7 +492,8 @@ DEVICE cpu_dev = {
|
||||||
&cpu_ex, &cpu_dep, &cpu_reset,
|
&cpu_ex, &cpu_dep, &cpu_reset,
|
||||||
&cpu_boot, NULL, NULL,
|
&cpu_boot, NULL, NULL,
|
||||||
NULL, DEV_DYNM | DEV_DEBUG, 0,
|
NULL, DEV_DYNM | DEV_DEBUG, 0,
|
||||||
cpu_deb, &cpu_set_size, NULL, &cpu_help, NULL, NULL
|
cpu_deb, &cpu_set_size, NULL, &cpu_help, NULL, NULL,
|
||||||
|
&cpu_description
|
||||||
};
|
};
|
||||||
|
|
||||||
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
|
t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||||
|
@ -500,6 +502,24 @@ fprintf (st, "model=");
|
||||||
return cpu_print_model (st);
|
return cpu_print_model (st);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *cpu_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
static char buf[80];
|
||||||
|
uint32 min_mem = 4096, max_mem = 0;
|
||||||
|
MTAB *mptr;
|
||||||
|
|
||||||
|
for (mptr = dptr->modifiers; mptr && (mptr->mask != 0); mptr++) {
|
||||||
|
if (mptr->valid != &cpu_set_size)
|
||||||
|
continue;
|
||||||
|
if ((mptr->match >> 20) < min_mem)
|
||||||
|
min_mem = (mptr->match >> 20);
|
||||||
|
if ((mptr->match >> 20) > max_mem)
|
||||||
|
max_mem = (mptr->match >> 20);
|
||||||
|
}
|
||||||
|
sprintf (buf, "VAX CPU with %dMB-%dMB of memory", (int)min_mem, (int)max_mem);
|
||||||
|
return buf;
|
||||||
|
}
|
||||||
|
|
||||||
t_stat sim_instr (void)
|
t_stat sim_instr (void)
|
||||||
{
|
{
|
||||||
volatile int32 opc, cc; /* used by setjmp */
|
volatile int32 opc, cc; /* used by setjmp */
|
||||||
|
|
|
@ -132,6 +132,7 @@ t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc);
|
t_stat qba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *qba_description (DEVICE *dptr);
|
||||||
|
|
||||||
/* Qbus adapter data structures
|
/* Qbus adapter data structures
|
||||||
|
|
||||||
|
@ -178,7 +179,8 @@ DEVICE qba_dev = {
|
||||||
1, 16, CQMAWIDTH, 2, 16, 16,
|
1, 16, CQMAWIDTH, 2, 16, 16,
|
||||||
&qba_ex, &qba_dep, &qba_reset,
|
&qba_ex, &qba_dep, &qba_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&qba_dib, DEV_QBUS
|
&qba_dib, DEV_QBUS, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&qba_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* IO page dispatches */
|
/* IO page dispatches */
|
||||||
|
@ -818,3 +820,8 @@ if (cptr) {
|
||||||
fprintf (of, "Invalid argument\n");
|
fprintf (of, "Invalid argument\n");
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *qba_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "Qbus adapter";
|
||||||
|
}
|
||||||
|
|
|
@ -102,6 +102,7 @@ static const int32 cvtacc[16] = { 0, 0,
|
||||||
t_stat tlb_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
|
t_stat tlb_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
|
||||||
t_stat tlb_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
|
t_stat tlb_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
|
||||||
t_stat tlb_reset (DEVICE *dptr);
|
t_stat tlb_reset (DEVICE *dptr);
|
||||||
|
char *tlb_description (DEVICE *dptr);
|
||||||
|
|
||||||
TLBENT fill (uint32 va, int32 lnt, int32 acc, int32 *stat);
|
TLBENT fill (uint32 va, int32 lnt, int32 acc, int32 *stat);
|
||||||
extern int32 ReadIO (uint32 pa, int32 lnt);
|
extern int32 ReadIO (uint32 pa, int32 lnt);
|
||||||
|
@ -129,7 +130,8 @@ DEVICE tlb_dev = {
|
||||||
"TLB", tlb_unit, tlb_reg, NULL,
|
"TLB", tlb_unit, tlb_reg, NULL,
|
||||||
2, 16, VA_N_TBI * 2, 1, 16, 32,
|
2, 16, VA_N_TBI * 2, 1, 16, 32,
|
||||||
&tlb_ex, &tlb_dep, &tlb_reset,
|
&tlb_ex, &tlb_dep, &tlb_reset,
|
||||||
NULL, NULL, NULL
|
NULL, NULL, NULL, NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tlb_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Read and write virtual
|
/* Read and write virtual
|
||||||
|
@ -626,3 +628,8 @@ for (i = 0; i < VA_TBSIZE; i++)
|
||||||
stlb[i].tag = ptlb[i].tag = stlb[i].pte = ptlb[i].pte = -1;
|
stlb[i].tag = ptlb[i].tag = stlb[i].pte = ptlb[i].pte = -1;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tlb_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "translation buffer";
|
||||||
|
}
|
|
@ -119,6 +119,9 @@ t_stat clk_reset (DEVICE *dptr);
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr);
|
t_stat clk_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat clk_detach (UNIT *uptr);
|
t_stat clk_detach (UNIT *uptr);
|
||||||
t_stat todr_resync (void);
|
t_stat todr_resync (void);
|
||||||
|
char *tti_description (DEVICE *dptr);
|
||||||
|
char *tto_description (DEVICE *dptr);
|
||||||
|
char *clk_description (DEVICE *dptr);
|
||||||
|
|
||||||
extern int32 sysd_hlt_enb (void);
|
extern int32 sysd_hlt_enb (void);
|
||||||
extern int32 fault_PC;
|
extern int32 fault_PC;
|
||||||
|
@ -159,7 +162,8 @@ DEVICE tti_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tti_reset,
|
NULL, NULL, &tti_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&tti_dib, 0
|
&tti_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tti_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* TTO data structures
|
/* TTO data structures
|
||||||
|
@ -198,7 +202,8 @@ DEVICE tto_dev = {
|
||||||
1, 10, 31, 1, 16, 8,
|
1, 10, 31, 1, 16, 8,
|
||||||
NULL, NULL, &tto_reset,
|
NULL, NULL, &tto_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&tto_dib, 0
|
&tto_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&tto_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* CLK data structures
|
/* CLK data structures
|
||||||
|
@ -239,7 +244,8 @@ DEVICE clk_dev = {
|
||||||
1, 0, 8, 4, 0, 32,
|
1, 0, 8, 4, 0, 32,
|
||||||
NULL, NULL, &clk_reset,
|
NULL, NULL, &clk_reset,
|
||||||
NULL, &clk_attach, &clk_detach,
|
NULL, &clk_attach, &clk_detach,
|
||||||
&clk_dib, 0
|
&clk_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&clk_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Clock and terminal MxPR routines
|
/* Clock and terminal MxPR routines
|
||||||
|
@ -350,6 +356,11 @@ sim_activate (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tti_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal input";
|
||||||
|
}
|
||||||
|
|
||||||
/* Terminal output routines
|
/* Terminal output routines
|
||||||
|
|
||||||
tto_svc process event (character typed)
|
tto_svc process event (character typed)
|
||||||
|
@ -384,6 +395,11 @@ sim_cancel (&tto_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tto_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console terminal output";
|
||||||
|
}
|
||||||
|
|
||||||
/* Clock routines
|
/* Clock routines
|
||||||
|
|
||||||
clk_svc process event (clock tick)
|
clk_svc process event (clock tick)
|
||||||
|
@ -508,6 +524,11 @@ if (clk_unit.filebuf == NULL) { /* make sure the TODR is
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *clk_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "time of year clock";
|
||||||
|
}
|
||||||
|
|
||||||
/* CLK attach */
|
/* CLK attach */
|
||||||
|
|
||||||
t_stat clk_attach (UNIT *uptr, char *cptr)
|
t_stat clk_attach (UNIT *uptr, char *cptr)
|
||||||
|
|
|
@ -234,16 +234,21 @@ static uint32 rom_delay = 0;
|
||||||
t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat rom_reset (DEVICE *dptr);
|
t_stat rom_reset (DEVICE *dptr);
|
||||||
|
char *rom_description (DEVICE *dptr);
|
||||||
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||||
t_stat nvr_reset (DEVICE *dptr);
|
t_stat nvr_reset (DEVICE *dptr);
|
||||||
t_stat nvr_attach (UNIT *uptr, char *cptr);
|
t_stat nvr_attach (UNIT *uptr, char *cptr);
|
||||||
t_stat nvr_detach (UNIT *uptr);
|
t_stat nvr_detach (UNIT *uptr);
|
||||||
|
char *nvr_description (DEVICE *dptr);
|
||||||
t_stat csi_reset (DEVICE *dptr);
|
t_stat csi_reset (DEVICE *dptr);
|
||||||
|
char *csi_description (DEVICE *dptr);
|
||||||
t_stat cso_reset (DEVICE *dptr);
|
t_stat cso_reset (DEVICE *dptr);
|
||||||
t_stat cso_svc (UNIT *uptr);
|
t_stat cso_svc (UNIT *uptr);
|
||||||
|
char *cso_description (DEVICE *dptr);
|
||||||
t_stat tmr_svc (UNIT *uptr);
|
t_stat tmr_svc (UNIT *uptr);
|
||||||
t_stat sysd_reset (DEVICE *dptr);
|
t_stat sysd_reset (DEVICE *dptr);
|
||||||
|
char *sysd_description (DEVICE *dptr);
|
||||||
|
|
||||||
int32 rom_rd (int32 pa);
|
int32 rom_rd (int32 pa);
|
||||||
int32 nvr_rd (int32 pa);
|
int32 nvr_rd (int32 pa);
|
||||||
|
@ -318,7 +323,8 @@ DEVICE rom_dev = {
|
||||||
1, 16, ROMAWIDTH, 4, 16, 32,
|
1, 16, ROMAWIDTH, 4, 16, 32,
|
||||||
&rom_ex, &rom_dep, &rom_reset,
|
&rom_ex, &rom_dep, &rom_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&rom_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* NVR data structures
|
/* NVR data structures
|
||||||
|
@ -340,7 +346,8 @@ DEVICE nvr_dev = {
|
||||||
1, 16, NVRAWIDTH, 4, 16, 32,
|
1, 16, NVRAWIDTH, 4, 16, 32,
|
||||||
&nvr_ex, &nvr_dep, &nvr_reset,
|
&nvr_ex, &nvr_dep, &nvr_reset,
|
||||||
NULL, &nvr_attach, &nvr_detach,
|
NULL, &nvr_attach, &nvr_detach,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&nvr_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* CSI data structures
|
/* CSI data structures
|
||||||
|
@ -376,7 +383,7 @@ DEVICE csi_dev = {
|
||||||
1, 10, 31, 1, 8, 8,
|
1, 10, 31, 1, 8, 8,
|
||||||
NULL, NULL, &csi_reset,
|
NULL, NULL, &csi_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&csi_dib, 0
|
&csi_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL
|
||||||
};
|
};
|
||||||
|
|
||||||
/* CSO data structures
|
/* CSO data structures
|
||||||
|
@ -412,7 +419,7 @@ DEVICE cso_dev = {
|
||||||
1, 10, 31, 1, 8, 8,
|
1, 10, 31, 1, 8, 8,
|
||||||
NULL, NULL, &cso_reset,
|
NULL, NULL, &cso_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&cso_dib, 0
|
&cso_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL
|
||||||
};
|
};
|
||||||
|
|
||||||
/* SYSD data structures
|
/* SYSD data structures
|
||||||
|
@ -469,7 +476,8 @@ DEVICE sysd_dev = {
|
||||||
2, 16, 16, 1, 16, 8,
|
2, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &sysd_reset,
|
NULL, NULL, &sysd_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
&sysd_dib, 0
|
&sysd_dib, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&sysd_description
|
||||||
};
|
};
|
||||||
|
|
||||||
/* ROM: read only memory - stored in a buffered file
|
/* ROM: read only memory - stored in a buffered file
|
||||||
|
@ -595,6 +603,11 @@ if (rom == NULL)
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *rom_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "read-only memory";
|
||||||
|
}
|
||||||
|
|
||||||
/* NVR: non-volatile RAM - stored in a buffered file */
|
/* NVR: non-volatile RAM - stored in a buffered file */
|
||||||
|
|
||||||
int32 nvr_rd (int32 pa)
|
int32 nvr_rd (int32 pa)
|
||||||
|
@ -688,6 +701,11 @@ if ((uptr->flags & UNIT_ATT) == 0)
|
||||||
return r;
|
return r;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *nvr_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "non-volatile memory";
|
||||||
|
}
|
||||||
|
|
||||||
/* CSI: console storage input */
|
/* CSI: console storage input */
|
||||||
|
|
||||||
int32 csrs_rd (void)
|
int32 csrs_rd (void)
|
||||||
|
@ -720,6 +738,11 @@ CLR_INT (CSI);
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *csi_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console storage input";
|
||||||
|
}
|
||||||
|
|
||||||
/* CSO: console storage output */
|
/* CSO: console storage output */
|
||||||
|
|
||||||
int32 csts_rd (void)
|
int32 csts_rd (void)
|
||||||
|
@ -771,6 +794,11 @@ sim_cancel (&cso_unit); /* deactivate unit */
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *cso_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "console storage output";
|
||||||
|
}
|
||||||
|
|
||||||
/* SYSD: SSC access mechanisms and devices
|
/* SYSD: SSC access mechanisms and devices
|
||||||
|
|
||||||
- IPR space read/write routines
|
- IPR space read/write routines
|
||||||
|
@ -1503,6 +1531,11 @@ int32 tmr1_inta (void)
|
||||||
return tmr_tivr[1];
|
return tmr_tivr[1];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *tmr_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "non-volatile memory";
|
||||||
|
}
|
||||||
|
|
||||||
/* Machine check */
|
/* Machine check */
|
||||||
|
|
||||||
int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta)
|
int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta)
|
||||||
|
@ -1643,6 +1676,10 @@ ssc_otp = 0;
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *sysd_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "system devices";
|
||||||
|
}
|
||||||
|
|
||||||
t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
|
t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr)
|
||||||
{
|
{
|
||||||
|
|
|
@ -63,6 +63,7 @@ int32 wtc_mode = WTC_MODE_VMS;
|
||||||
|
|
||||||
t_stat wtc_set (UNIT *uptr, int32 val, char *cptr, void *desc);
|
t_stat wtc_set (UNIT *uptr, int32 val, char *cptr, void *desc);
|
||||||
t_stat wtc_show (FILE *st, UNIT *uptr, int32 val, void *desc);
|
t_stat wtc_show (FILE *st, UNIT *uptr, int32 val, void *desc);
|
||||||
|
char *wtc_description (DEVICE *dptr);
|
||||||
t_stat wtc_reset (DEVICE *dptr);
|
t_stat wtc_reset (DEVICE *dptr);
|
||||||
void wtc_set_valid (void);
|
void wtc_set_valid (void);
|
||||||
void wtc_set_invalid (void);
|
void wtc_set_invalid (void);
|
||||||
|
@ -87,7 +88,8 @@ DEVICE wtc_dev = {
|
||||||
1, 16, 16, 1, 16, 8,
|
1, 16, 16, 1, 16, 8,
|
||||||
NULL, NULL, &wtc_reset,
|
NULL, NULL, &wtc_reset,
|
||||||
NULL, NULL, NULL,
|
NULL, NULL, NULL,
|
||||||
NULL, 0
|
NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||||
|
&wtc_description
|
||||||
};
|
};
|
||||||
|
|
||||||
int32 wtc_rd (int32 pa)
|
int32 wtc_rd (int32 pa)
|
||||||
|
@ -213,3 +215,8 @@ void wtc_set_invalid (void)
|
||||||
{
|
{
|
||||||
wtc_csrd &= ~WTC_CSRD_VRT;
|
wtc_csrd &= ~WTC_CSRD_VRT;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
char *wtc_description (DEVICE *dptr)
|
||||||
|
{
|
||||||
|
return "watch chip";
|
||||||
|
}
|
||||||
|
|
36
scp.c
36
scp.c
|
@ -371,7 +371,7 @@ t_stat show_break (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
|
||||||
t_stat show_on (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
|
t_stat show_on (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, char *cptr);
|
||||||
t_stat show_device (FILE *st, DEVICE *dptr, int32 flag);
|
t_stat show_device (FILE *st, DEVICE *dptr, int32 flag);
|
||||||
t_stat show_unit (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag);
|
t_stat show_unit (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag);
|
||||||
t_stat show_all_mods (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flg);
|
int show_all_mods (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flg);
|
||||||
t_stat show_one_mod (FILE *st, DEVICE *dptr, UNIT *uptr, MTAB *mptr, char *cptr, int32 flag);
|
t_stat show_one_mod (FILE *st, DEVICE *dptr, UNIT *uptr, MTAB *mptr, char *cptr, int32 flag);
|
||||||
t_stat sim_check_console (int32 sec);
|
t_stat sim_check_console (int32 sec);
|
||||||
t_stat sim_save (FILE *sfile);
|
t_stat sim_save (FILE *sfile);
|
||||||
|
@ -717,6 +717,7 @@ static CTAB cmd_table[] = {
|
||||||
"sh{ow} con{figuration} show configuration\n"
|
"sh{ow} con{figuration} show configuration\n"
|
||||||
"sh{ow} cons{ole} {arg} show console options\n"
|
"sh{ow} cons{ole} {arg} show console options\n"
|
||||||
"sh{ow} dev{ices} show devices\n"
|
"sh{ow} dev{ices} show devices\n"
|
||||||
|
"sh{ow} sys{tem} show system devices with descriptions\n"
|
||||||
"sh{ow} m{odifiers} show modifiers for all devices\n"
|
"sh{ow} m{odifiers} show modifiers for all devices\n"
|
||||||
"sh{ow} s{how} show SHOW commands for all devices\n"
|
"sh{ow} s{how} show SHOW commands for all devices\n"
|
||||||
"sh{ow} n{ames} show logical names\n"
|
"sh{ow} n{ames} show logical names\n"
|
||||||
|
@ -739,7 +740,7 @@ static CTAB cmd_table[] = {
|
||||||
"sh{ow} clocks show calibrated timers\n"
|
"sh{ow} clocks show calibrated timers\n"
|
||||||
"sh{ow} on show on condition actions\n" },
|
"sh{ow} on show on condition actions\n" },
|
||||||
{ "DO", &do_cmd, 1,
|
{ "DO", &do_cmd, 1,
|
||||||
"do {-V} {-O} {-E} {-Q} <file> {arg,arg...}\b"
|
"do {-V} {-O} {-E} {-Q} <file> {arg,arg...}\n"
|
||||||
" process command file\n" },
|
" process command file\n" },
|
||||||
{ "GOTO", &goto_cmd, 1,
|
{ "GOTO", &goto_cmd, 1,
|
||||||
"goto <label> goto label in command file\n" },
|
"goto <label> goto label in command file\n" },
|
||||||
|
@ -2337,6 +2338,7 @@ SHTAB *shtb, *shptr;
|
||||||
static SHTAB show_glob_tab[] = {
|
static SHTAB show_glob_tab[] = {
|
||||||
{ "CONFIGURATION", &show_config, 0 },
|
{ "CONFIGURATION", &show_config, 0 },
|
||||||
{ "DEVICES", &show_config, 1 },
|
{ "DEVICES", &show_config, 1 },
|
||||||
|
{ "SYSTEM", &show_config, 2 },
|
||||||
{ "QUEUE", &show_queue, 0 },
|
{ "QUEUE", &show_queue, 0 },
|
||||||
{ "TIME", &show_time, 0 },
|
{ "TIME", &show_time, 0 },
|
||||||
{ "MODIFIERS", &show_mod_names, 0 },
|
{ "MODIFIERS", &show_mod_names, 0 },
|
||||||
|
@ -2448,10 +2450,14 @@ t_stat show_device (FILE *st, DEVICE *dptr, int32 flag)
|
||||||
{
|
{
|
||||||
uint32 j, udbl, ucnt;
|
uint32 j, udbl, ucnt;
|
||||||
UNIT *uptr;
|
UNIT *uptr;
|
||||||
|
int mods;
|
||||||
|
|
||||||
fprintf (st, "%s", sim_dname (dptr)); /* print dev name */
|
fprintf (st, "%s", sim_dname (dptr)); /* print dev name */
|
||||||
|
if ((flag == 2) && dptr->description) {
|
||||||
|
fprintf (st, "\t%s\n", dptr->description(dptr));
|
||||||
|
}
|
||||||
if (qdisable (dptr)) { /* disabled? */
|
if (qdisable (dptr)) { /* disabled? */
|
||||||
fprintf (st, ", disabled\n");
|
fprintf (st, "\tdisabled\n");
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
for (j = ucnt = udbl = 0; j < dptr->numunits; j++) { /* count units */
|
for (j = ucnt = udbl = 0; j < dptr->numunits; j++) { /* count units */
|
||||||
|
@ -2461,15 +2467,17 @@ for (j = ucnt = udbl = 0; j < dptr->numunits; j++) { /* count units */
|
||||||
else if (uptr->flags & UNIT_DISABLE)
|
else if (uptr->flags & UNIT_DISABLE)
|
||||||
udbl++; /* count user-disabled */
|
udbl++; /* count user-disabled */
|
||||||
}
|
}
|
||||||
show_all_mods (st, dptr, dptr->units, MTAB_VDV); /* show dev mods */
|
mods = show_all_mods (st, dptr, dptr->units, MTAB_VDV); /* show dev mods */
|
||||||
if (dptr->numunits == 0)
|
if (dptr->numunits == 0) {
|
||||||
fprintf (st, "\n");
|
if (mods)
|
||||||
|
fprintf (st, "\n");
|
||||||
|
}
|
||||||
else {
|
else {
|
||||||
if (ucnt == 0)
|
if (ucnt == 0)
|
||||||
fprintf (st, ", all units disabled\n");
|
fprintf (st, "%sall units disabled\n", mods ? ", " : "\t");
|
||||||
else if ((ucnt > 1) || (udbl > 0))
|
else if ((ucnt > 1) || (udbl > 0))
|
||||||
fprintf (st, ", %d units\n", ucnt + udbl);
|
fprintf (st, "%s%d units\n", mods ? ", " : "\t", ucnt + udbl);
|
||||||
else if (flag)
|
else if (mods || (flag == 1) || ((flag == 2) && !dptr->description))
|
||||||
fprintf (st, "\n");
|
fprintf (st, "\n");
|
||||||
}
|
}
|
||||||
if (flag) /* dev only? */
|
if (flag) /* dev only? */
|
||||||
|
@ -2807,9 +2815,11 @@ if ((dptr->flags & DEV_DEBUG) && dptr->debflags) {
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
t_stat show_all_mods (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag)
|
int show_all_mods (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag)
|
||||||
{
|
{
|
||||||
MTAB *mptr;
|
MTAB *mptr;
|
||||||
|
t_bool first_mod = TRUE;
|
||||||
|
int mods_shown = 0;
|
||||||
|
|
||||||
if (dptr->modifiers == NULL)
|
if (dptr->modifiers == NULL)
|
||||||
return SCPE_OK;
|
return SCPE_OK;
|
||||||
|
@ -2817,11 +2827,13 @@ for (mptr = dptr->modifiers; mptr->mask != 0; mptr++) {
|
||||||
if (mptr->pstring && ((mptr->mask & MTAB_XTD)?
|
if (mptr->pstring && ((mptr->mask & MTAB_XTD)?
|
||||||
((mptr->mask & flag) && !(mptr->mask & MTAB_NMO)):
|
((mptr->mask & flag) && !(mptr->mask & MTAB_NMO)):
|
||||||
((MTAB_VUN & flag) && ((uptr->flags & mptr->mask) == mptr->match)))) {
|
((MTAB_VUN & flag) && ((uptr->flags & mptr->mask) == mptr->match)))) {
|
||||||
fputs (", ", st);
|
fputs (first_mod ? "\t" : ", ", st);
|
||||||
|
first_mod = FALSE;
|
||||||
show_one_mod (st, dptr, uptr, mptr, NULL, 0);
|
show_one_mod (st, dptr, uptr, mptr, NULL, 0);
|
||||||
|
++mods_shown;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
return SCPE_OK;
|
return mods_shown;
|
||||||
}
|
}
|
||||||
|
|
||||||
t_stat show_one_mod (FILE *st, DEVICE *dptr, UNIT *uptr, MTAB *mptr,
|
t_stat show_one_mod (FILE *st, DEVICE *dptr, UNIT *uptr, MTAB *mptr,
|
||||||
|
|
|
@ -325,10 +325,14 @@ struct sim_device {
|
||||||
/* mem size routine */
|
/* mem size routine */
|
||||||
char *lname; /* logical name */
|
char *lname; /* logical name */
|
||||||
t_stat (*help)(FILE *st, struct sim_device *dptr,
|
t_stat (*help)(FILE *st, struct sim_device *dptr,
|
||||||
struct sim_unit *uptr, int32 flag, char *cptr); /* help */
|
struct sim_unit *uptr, int32 flag, char *cptr);
|
||||||
|
/* help */
|
||||||
t_stat (*attach_help)(FILE *st, struct sim_device *dptr,
|
t_stat (*attach_help)(FILE *st, struct sim_device *dptr,
|
||||||
struct sim_unit *uptr, int32 flag, char *cptr); /* attach help */
|
struct sim_unit *uptr, int32 flag, char *cptr);
|
||||||
|
/* attach help */
|
||||||
void *help_ctx; /* Context available to help routines */
|
void *help_ctx; /* Context available to help routines */
|
||||||
|
char *(*description)(struct sim_device *dptr);
|
||||||
|
/* Device Description */
|
||||||
};
|
};
|
||||||
|
|
||||||
/* Device flags */
|
/* Device flags */
|
||||||
|
|
Loading…
Add table
Reference in a new issue