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I1401, VAX, PDP11: Fix nested comments consistently with Supnik-Current branch

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This commit is contained in:
Mark Pizzolato 2018-06-03 20:59:36 -07:00
parent 54516bb175
commit cc6140fd31
6 changed files with 11 additions and 10 deletions
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4
I1401/i1401_iq.c
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@ -93,8 +93,8 @@ ind[IN_INC] = 0; /* clear inq clear */
switch (mod) { /* case on mod */ switch (mod) { /* case on mod */
case BCD_R: /* input */ case BCD_R: /* input */
/* if (ind[IN_INR] == 0) */ // if (ind[IN_INR] == 0)
/* return SCPE_OK; *//* return if no req */ // return SCPE_OK; /* return if no req */
ind[IN_INR] = 0; /* clear req */ ind[IN_INR] = 0; /* clear req */
inq_puts ("[Enter]\r\n"); /* prompt */ inq_puts ("[Enter]\r\n"); /* prompt */
for (i = 0; M[BS] != (BCD_GRPMRK + WM); i++) { /* until GM + WM */ for (i = 0; M[BS] != (BCD_GRPMRK + WM); i++) { /* until GM + WM */

1
I1620/i1620_defs.h
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@ -248,6 +248,7 @@ enum opcodes {
#define DEFIO_ACTIVATE(uptr) sim_activate (uptr, (uptr)->wait) #define DEFIO_ACTIVATE(uptr) sim_activate (uptr, (uptr)->wait)
#define DEFIO_ACTIVATE_ABS(uptr) sim_activate_abs (uptr, (uptr)->wait) #define DEFIO_ACTIVATE_ABS(uptr) sim_activate_abs (uptr, (uptr)->wait)
#endif #endif
/* Function declarations */ /* Function declarations */
t_stat cpuio_set_inp (uint32 op, uint32 dev, UNIT *uptr); t_stat cpuio_set_inp (uint32 op, uint32 dev, UNIT *uptr);

2
PDP11/pdp11_rq.c
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@ -2032,7 +2032,7 @@ if (bc & 1) /* odd byte cnt? */
return (ST_HST | SB_HST_OC); return (ST_HST | SB_HST_OC);
if (bc & 0xF0000000) /* 'reasonable' bc? */ if (bc & 0xF0000000) /* 'reasonable' bc? */
return (ST_CMD | I_BCNT); return (ST_CMD | I_BCNT);
/* if (lbn & 0xF0000000) return (ST_CMD | I_LBN); *//* 'reasonable' lbn? */ // if (lbn & 0xF0000000) return (ST_CMD | I_LBN); /* 'reasonable' lbn? */
if (lbn >= maxlbn) { /* accessing RCT? */ if (lbn >= maxlbn) { /* accessing RCT? */
if (lbn >= (maxlbn + drv_tab[dtyp].rcts)) /* beyond copy 1? */ if (lbn >= (maxlbn + drv_tab[dtyp].rcts)) /* beyond copy 1? */
return (ST_CMD | I_LBN); /* lbn err */ return (ST_CMD | I_LBN); /* lbn err */

4
PDP11/pdp11_tq.c
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@ -845,8 +845,8 @@ else { /* valid cmd */
tq_enqt (&uptr->pktq, pkt); /* do later */ tq_enqt (&uptr->pktq, pkt); /* do later */
return OK; return OK;
} }
/* if (tq_cmf[cmd] & MD_CDL) *//* clr cch lost? */ // if (tq_cmf[cmd] & MD_CDL) /* clr cch lost? */
/* uptr->flags = uptr->flags & ~UNIT_CDL; */ // uptr->flags = uptr->flags & ~UNIT_CDL;
if ((mdf & MD_CSE) && (uptr->flags & UNIT_SXC)) /* clr ser exc? */ if ((mdf & MD_CSE) && (uptr->flags & UNIT_SXC)) /* clr ser exc? */
uptr->flags = uptr->flags & ~UNIT_SXC; uptr->flags = uptr->flags & ~UNIT_SXC;
memset (uptr->results, 0, sizeof (struct tq_req_results)); /* init request state */ memset (uptr->results, 0, sizeof (struct tq_req_results)); /* init request state */

8
PDP11/pdp11_xu.c
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@ -1016,8 +1016,8 @@ int32 xu_command(CTLR* xu)
xu->var->rrlen = xu->var->udb[5]; xu->var->rrlen = xu->var->udb[5];
xu->var->rxnext = 0; xu->var->rxnext = 0;
xu->var->txnext = 0; xu->var->txnext = 0;
// xu_dump_rxring(xu); // xu_dump_rxring(xu);
// xu_dump_txring(xu); // xu_dump_txring(xu);
break; break;
@ -1200,7 +1200,7 @@ void xu_process_receive(CTLR* xu)
sim_debug(DBG_TRC, xu->dev, "xu_process_receive(), buffers: %d\n", xu->var->rrlen); sim_debug(DBG_TRC, xu->dev, "xu_process_receive(), buffers: %d\n", xu->var->rrlen);
/* xu_dump_rxring(xu); *//* debug receive ring */ // xu_dump_rxring(xu); /* debug receive ring */
/* process only when in the running state, and host buffers are available */ /* process only when in the running state, and host buffers are available */
if ((state != STATE_RUNNING) || no_buffers) if ((state != STATE_RUNNING) || no_buffers)
@ -1375,7 +1375,7 @@ void xu_process_receive(CTLR* xu)
/* set or clear interrupt, depending on what happened */ /* set or clear interrupt, depending on what happened */
xu_setclrint(xu, 0); xu_setclrint(xu, 0);
// xu_dump_rxring(xu); /* debug receive ring */ // xu_dump_rxring(xu); /* debug receive ring */
} }

2
VAX/vaxmod_defs.h
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@ -197,7 +197,7 @@ extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc
/* CMCTL registers */ /* CMCTL registers */
/* #define CMCTLSIZE (18 << 2) *//* 18 registers */ // #define CMCTLSIZE (18 << 2) /* 18 registers */
#define CMCTLSIZE (19 << 2) /* KA655X extra reg */ #define CMCTLSIZE (19 << 2) /* KA655X extra reg */
#define CMCTLBASE (REGBASE + 0x100) /* CMCTL addr base */ #define CMCTLBASE (REGBASE + 0x100) /* CMCTL addr base */