Fixes bugs in multiply and divide introduced in 3.8-1; fixes XR and double precision bugs (from Adrian Wise)
This commit is contained in:
Mark Pizzolato
parent
041e192fa9
commit
cc890aec1c
2 changed files with 34 additions and 18 deletions
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@ -1,6 +1,6 @@
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/* h316_cpu.c: Honeywell 316/516 CPU simulator
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Copyright (c) 1999-2010, Robert M. Supnik
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Copyright (c) 1999-2011, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -25,6 +25,8 @@
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cpu H316/H516 CPU
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19-Nov-11 RMS Fixed XR behavior (from Adrian Wise)
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19-Nov-11 RMS Fixed bugs in double precision, normalization, SC (from Adrian Wise)
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10-Jan-10 RMS Fixed bugs in LDX, STX introduced in 3.8-1 (from Theo Engel)
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28-Apr-07 RMS Removed clock initialization
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03-Apr-06 RMS Fixed bugs in LLL, LRL (from Theo Engel)
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@ -51,7 +53,7 @@
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C overflow flag
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EXT extend mode flag
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DP double precision mode flag
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SC<1:5> shift count
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SC<1:6> shift count
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SR[1:4]<0> sense switches 1-4
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The Honeywell 316/516 has six instruction formats: memory reference,
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@ -195,6 +197,18 @@
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h316_defs.h add interrupt request definition
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h316_cpu.c add device dispatch table entry
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h316_sys.c add sim_devices table entry
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Notes on the behavior of XR:
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- XR is "shadowed" by memory location 0 as seen by the program currently
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executing. Thus, in extend mode, this is always absolute location 0.
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However, if extend mode is off, this is location 0, if the program is
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executing in the lower bank, or location 040000, if the program is
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executing in the upper bank. Writing XR writes the shadowed memory
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location, and vice versa.
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- However, the front panel console always equates XR to absolute location
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0, regardless of extend mode. There is no direct examine or deposit
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to XR; the user must examine or deposit location 0.
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*/
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#include "h316_defs.h"
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@ -234,6 +248,7 @@ uint16 M[MAXMEMSIZE] = { 0 }; /* memory */
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int32 saved_AR = 0; /* A register */
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int32 saved_BR = 0; /* B register */
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int32 saved_XR = 0; /* X register */
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int32 XR = 0; /* live copy - must be global */
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int32 PC = 0; /* P register */
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int32 C = 0; /* C register */
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int32 ext = 0; /* extend mode */
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@ -302,7 +317,7 @@ REG cpu_reg[] = {
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{ ORDATA (P, PC, 15) },
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{ ORDATA (A, saved_AR, 16) },
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{ ORDATA (B, saved_BR, 16) },
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{ ORDATA (X, XR, 16) },
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{ ORDATA (X, saved_XR, 16) },
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{ ORDATA (SC, sc, 16) },
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{ FLDATA (C, C, 0) },
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{ FLDATA (EXT, ext, 0) },
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@ -388,6 +403,8 @@ int32 Operate (int32 MB, int32 AR);
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BR = (BR & SIGN) | ((x) & MMASK)
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#define PUTDBL_U(x) AR = ((x) >> 16) & DMASK; \
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BR = (x) & DMASK
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#define PUTDBL_Z(x) AR = ((x) >> 15) & DMASK; \
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BR = (x) & MMASK
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#define SEXT(x) (((x) & SIGN)? ((x) | ~DMASK): ((x) & DMASK))
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#define NEWA(c,n) (ext? (((c) & ~X_AMASK) | ((n) & X_AMASK)): \
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(((c) & ~NX_AMASK) | ((n) & NX_AMASK)))
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@ -559,7 +576,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
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t1 = GETDBL_S (AR, BR); /* get A'B */
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t2 = GETDBL_S (Read (Y & ~1), Read (Y | 1));
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t1 = Add31 (t1, t2); /* 31b add */
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PUTDBL_S (t1);
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PUTDBL_Z (t1);
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sc = 0;
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}
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else AR = Add16 (AR, Read (Y)); /* no, 16b add */
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@ -572,7 +589,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
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t1 = GETDBL_S (AR, BR); /* get A'B */
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t2 = GETDBL_S (Read (Y & ~1), Read (Y | 1));
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t1 = Add31 (t1, -t2); /* 31b sub */
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PUTDBL_S (t1);
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PUTDBL_Z (t1);
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sc = 0;
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}
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else AR = Add16 (AR, (-Read (Y)) & DMASK); /* no, 16b sub */
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@ -624,6 +641,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
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if (reason = Ea (MB & ~IDX, &Y)) /* eff addr */
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break;
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XR = Read (Y); /* load XR */
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M[M_XR] = XR; /* update mem too */
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break;
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case 016: case 036: case 056: case 076: /* MPY */
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@ -631,7 +649,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
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if (reason = Ea (MB, &Y)) /* eff addr */
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break;
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t1 = SEXT (AR) * SEXT (Read (Y));
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PUTDBL_S (t1);
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PUTDBL_Z (t1);
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sc = 0;
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}
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else reason = stop_inst;
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@ -719,15 +737,15 @@ switch (I_GETOP (MB)) { /* case on <1:6> */
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CLR_INT (INT_MPE);
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if (MB & m11) { /* SCA, INK */
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if (MB & m15) /* INK */
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AR = (C << 15) | (dp << 14) | (pme << 13) | (sc & 037);
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AR = (C << 15) | (dp << 14) | (pme << 13) | (sc & 077);
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else if (cpu_unit.flags & UNIT_HSA) /* SCA */
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AR = sc & 037;
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AR = sc & 077;
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else reason = stop_inst;
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}
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else if (MB & m10) { /* NRM */
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if (cpu_unit.flags & UNIT_HSA) {
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for (sc = 0;
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(sc <= 32) && ((AR & SIGN) != ((AR << 1) & SIGN));
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(sc < 32) && ((AR & SIGN) == ((AR << 1) & SIGN));
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sc++) {
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AR = (AR & SIGN) | ((AR << 1) & MMASK) |
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((BR >> 14) & 1);
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@ -1050,6 +1068,8 @@ void Write (int32 addr, int32 val)
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{
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if (((addr == 0) || (addr >= 020)) && MEM_ADDR_OK (addr))
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M[addr] = val;
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if (addr == M_XR) /* write XR loc? */
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XR = val; /* update XR */
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return;
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}
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@ -1292,15 +1312,10 @@ return SCPE_OK;
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t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw)
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{
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int32 d;
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if (addr >= MEMSIZE)
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return SCPE_NXM;
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if (addr == 0)
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d = saved_XR;
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else d = M[addr];
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if (vptr != NULL)
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*vptr = d & DMASK;
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*vptr = M[addr] & DMASK;
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return SCPE_OK;
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}
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@ -1312,7 +1327,7 @@ if (addr >= MEMSIZE)
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return SCPE_NXM;
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if (addr == 0)
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saved_XR = val & DMASK;
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else M[addr] = val & DMASK;
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M[addr] = val & DMASK;
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return SCPE_OK;
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}
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@ -1,6 +1,6 @@
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/* h316_defs.h: Honeywell 316/516 simulator definitions
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Copyright (c) 1999-2010, Robert M. Supnik
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Copyright (c) 1999-2011, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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19-Nov-11 RMS Removed XR macro, added XR_LOC macro (from Adrian Wise)
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22-May-10 RMS Added check for 64b definitions
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15-Feb-05 RMS Added start button interrupt
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01-Dec-04 RMS Added double precision constants
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@ -65,10 +66,10 @@
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#define DP_SIGN 010000000000
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#define DMASK 0177777 /* data mask */
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#define MMASK (DMASK & ~SIGN) /* magnitude mask */
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#define XR M[0]
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#define M_CLK 061 /* clock location */
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#define M_RSTINT 062 /* restrict int */
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#define M_INT 063 /* int location */
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#define M_XR (ext? 0: (PC & 040000)) /* XR location */
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/* CPU options */
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