diff --git a/I650/650_test.ini b/I650/650_test.ini new file mode 100644 index 00000000..53acb3a0 --- /dev/null +++ b/I650/650_test.ini @@ -0,0 +1,14 @@ + +cd sw + +; set debug -n debug.txt +; set debug stdout +; set cpu debug=cmd;data;detail + +; set throttle 11k + +do Build_soap_from_source.ini +do soap_and_run.ini soap_example_1_src.txt 1000 +do Build_is_from_decks.ini ntr lbox +do is_run.ini is_example_1_src.txt + diff --git a/I650/i650_cdp.c b/I650/i650_cdp.c new file mode 100644 index 00000000..5b10c3fa --- /dev/null +++ b/I650/i650_cdp.c @@ -0,0 +1,733 @@ +/* i650_cdp.c: IBM 650 Card punch. + + Copyright (c) 2018, Roberto Sancho + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + ROBERTO SANCHO BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + This is the standard card punch. + + These units each buffer one record in local memory and signal + ready when the buffer is full or empty. The channel must be + ready to recieve/transmit data when they are activated since + they will transfer their block during chan_cmd. All data is + transmitted as BCD characters. + +*/ + +#include "i650_defs.h" +#include "sim_card.h" + +#define UNIT_CDP UNIT_ATTABLE | MODE_026 + +/* std devices. data structures + + cdp_dev Card Punch device descriptor + cdp_unit Card Punch unit descriptor + cdp_reg Card Punch register list + cdp_mod Card Punch modifiers list +*/ + +uint32 cdp_cmd(UNIT *, uint16, uint16); +t_stat cdp_srv(UNIT *); +t_stat cdp_reset(DEVICE *); +t_stat cdp_attach(UNIT *, CONST char *); +t_stat cdp_detach(UNIT *); +t_stat cdp_help(FILE *, DEVICE *, UNIT *, int32, const char *); +const char *cdp_description(DEVICE *dptr); +t_stat cdp_set_wiring (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat cdp_show_wiring (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +t_stat cdp_set_echo (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat cdp_show_echo (FILE *st, UNIT *uptr, int32 val, CONST void *desc); + +UNIT cdp_unit[] = { + {UDATA(cdp_srv, UNIT_CDP, 0), 600}, // unit 0 is the printing mechanism of 407 + {UDATA(cdp_srv, UNIT_CDP, 0), 600}, + {UDATA(cdp_srv, UNIT_CDP, 0), 600}, + {UDATA(cdp_srv, UNIT_CDP, 0), 600}, +}; + +MTAB cdp_mod[] = { + {MTAB_XTD | MTAB_VUN, 0, "FORMAT", "FORMAT", &sim_card_set_fmt, &sim_card_show_fmt, NULL, "Set card format"}, + {MTAB_XTD | MTAB_VUN, 0, "WIRING", "WIRING", &cdp_set_wiring, &cdp_show_wiring, NULL, "Set card punch/print control panel Wiring"}, + {MTAB_XTD | MTAB_VUN, 0, "ECHO", "ECHO", &cdp_set_echo, &cdp_show_echo, NULL, "Set console printout for punched cards"}, + {MTAB_XTD | MTAB_VUN, 1, "PRINT", "PRINT", &cdp_set_echo, &cdp_show_echo, NULL, "Set printout on CDP0 unit for punched cards"}, + {0} +}; + +DEVICE cdp_dev = { + "CDP", cdp_unit, NULL, cdp_mod, + 4, 8, 15, 1, 8, 8, + NULL, NULL, NULL, NULL, &cdp_attach, &cdp_detach, + &cdp_dib, DEV_DISABLE | DEV_DEBUG, 0, crd_debug, + NULL, NULL, &cdp_help, NULL, NULL, &cdp_description +}; + +static struct card_wirings wirings[] = { + {WIRING_8WORD, "8WORD"}, + {WIRING_SOAP, "SOAP"}, + {WIRING_IS, "IS"}, + {0, 0}, +}; + +// vars where card is encoded for punching +char card_buf[120]; +int card_nbuf; + +// vars where card is encoded for printing +char card_lpt[120]; +int card_nlpt; + +void encode_char(int cPunch, int cLpt) +{ + if ((cPunch) && (card_nbuf < 80)) { + card_buf[card_nbuf++] = cPunch; + } + if ((cLpt) && (card_nlpt < 120)) { + card_lpt[card_nlpt++] = cLpt; + } +} + +void encode_lpt_spc(int nSpaces) +{ + while (nSpaces-- >0) encode_char(0, 32); +} + +void encode_lpt_str(const char * buf) +{ + while (*buf) encode_char(0, *buf++); +} + +void encode_lpt_num(t_int64 d, int l) +{ + char s[20]; + int i,n; + + d=AbsWord(d); + for (i=9;i>=0;i--) { + n = (int) (d % 10); + d = d / 10; + s[i] = '0' + n; + } + s[10] = 0; + encode_lpt_str(&s[10-l]); +} + +#define wf_NNNNNNNNNNs 0 +#define wf_NN_NNNN_NNNNs 1 +#define wf_sN_NNNNNNN_NN 3 +#define wf_sN_NNN_NNN_NNN 4 + +void encode_lpt_word(t_int64 d, int NegZero, int wFormat) +{ + int n; + int neg=0; + + if (d < 0) {d=-d; neg=1;} else if ((d==0) && (NegZero)) neg=1; + if (wFormat == wf_NN_NNNN_NNNNs) { + n = Shift_Digits(&d, 2); encode_lpt_num(n, 2); encode_lpt_spc(1); + n = Shift_Digits(&d, 4); encode_lpt_num(n, 4); encode_lpt_spc(1); + n = Shift_Digits(&d, 4); encode_lpt_num(n, 4); + encode_char(0, neg ? '-':' '); + } else if (wFormat == wf_sN_NNNNNNN_NN) { + encode_char(0, neg ? '-':'+'); + n = Shift_Digits(&d, 1); encode_lpt_num(n, 1); encode_lpt_spc(1); + n = Shift_Digits(&d, 7); encode_lpt_num(n, 7); encode_lpt_spc(1); + n = Shift_Digits(&d, 2); encode_lpt_num(n, 2); + } else if (wFormat == wf_sN_NNN_NNN_NNN) { + encode_char(0, neg ? '-':'+'); + n = Shift_Digits(&d, 1); encode_lpt_num(n, 1); encode_lpt_spc(1); + n = Shift_Digits(&d, 3); encode_lpt_num(n, 3); encode_lpt_spc(1); + n = Shift_Digits(&d, 3); encode_lpt_num(n, 3); encode_lpt_spc(1); + n = Shift_Digits(&d, 3); encode_lpt_num(n, 3); + } else { // default: wFormat == wf_NNNNNNNNNNs + encode_lpt_num(d,10); + encode_char(0, neg ? '-':' '); + } +} + +// set pch_word[10] with encoded word d. +// if d negative, sign on last digit (units digit) +// if bSetHiPuch=1, set HiPunch on last digit. +// if bSetHiPuch=2, set HiPunch on last digit and on second digit. +void sprintf_word(char * pch_word, t_int64 d, int NegZero, int bSetHiPuch) +{ + int i,n,neg, hi; + + if (d < 0) { + neg = 1; + d = -d; + } else if ((d == 0) && (NegZero)) { + neg = 1; // Negative Zero -> also puncho X(11) on last 0 digit + } else { + neg = 0; + } + for (i=9;i>=0;i--) { + hi = 0; + if ((i==1) && (bSetHiPuch == 2)) hi = 1; // Set Hi Punch on second digit + if ((i==9) && (bSetHiPuch > 0)) hi = 1; // Set Hi Punch on last digit (units digit) + n = (int) (d % 10); + d = d / 10; + n = n + hi * 10; + if ((neg == 1) && (i==9)) n = n + 20; // Set negative punch X(11) on last digit + pch_word[i] = digits_ascii[n]; + } + pch_word[10] = 0; +} + +void encode_pch_str(const char * buf) +{ + while (*buf) { + encode_char(*buf++, 0); + } +} + + +void encode_8word_wiring(int addr) +{ + // encode 8 numerical words per card + // get the decoded data from drum at addr + int i, NegZero; + t_int64 d; + char pch_word[20]; + + // punch card + for(i=0;i<8;i++) { + ReadDrum(addr + i, &d, &NegZero); + sprintf_word(pch_word, d, NegZero, 0); + encode_pch_str(pch_word); + } + + // print out card contents + // 8 words in format NN NNNN NNNN+ + for(i=0;i<8;i++) { + ReadDrum(addr + i, &d, &NegZero); + encode_lpt_word(d, NegZero, wf_NN_NNNN_NNNNs); + encode_lpt_spc(1); + } +} + +void encode_soap_wiring(int addr) +{ + // encode soap card simulating soap control panel wiring for 533 + // from SOAP II manual at http://www.bitsavers.org/pdf/ibm/650/24-4000-0_SOAPII.pdf + // storage in output block + // Word 1977: | <- Location -> | Alphabetic + // 1978: | <- Data Addr -> | Alphabetic + // 1979: | <- Inst Addr -> | Alphabetic + // +-+-+-|-+-+-|-+-|-+-| + // 1980: | Op Code |DTg|ITg| Alphabetic + // +-+-+-|-+-+-|-+-|-+-| + // 1981: | <- Remarks -> | Alphabetic + // 1982: | <- Remarks -> | Alphabetic + // 1983: |<-Assembled Instr->| + // +-+-|-+-+-+-|-+-+-|-| + // 1984: | |N N N N| |T| N N N N=Location, T=Type (0 if Blank) + // 1985: | |N N N N| N N N N=Card Number + // 1986: |a|b|c|d|e|f|g|h|i|j| a = 0/8 (for non blank type) + // b = 0/8 (negative) + // c = 0/8 (bypass) + // d = 0/8 (punch a) =8 -> do not print Loc op da ir + // e = 0/8 (punch b) =8 -> punch availability table + // f = 0/8 (800X instruction) + // g = 0/8 (blank out L) + // h = 0/8 (blank out D) + // i = 0/8 (blank out I) + // j = 0/8 (blank out OP) + // + // SOAP printout format + // | Sg | Location | OpCode | Data Addr | Tg | Instr Addr | Tg | Remarks | Drum Addr | NN NNNN NNNN[-] (signed word value at this drum addr) + // SOAP punch format (load card, 1 word per card) + // simulates punching over prepunched 1-word load card + // | word1 | nnnn | 24 addr 800? | NNNNNNNNNN[-] | source soap line + // nnnn=card number + // addr=drum address where the word is loaded + // NNNNNNNNNN=word to be loaded at addr, with sign + + char loc[6], data_addr[6], inst_addr[6], OpCode[6], Data_Tag[6], Instr_Tag[6], rem1[6], rem2[6]; + char pch_word[20]; + t_int64 d, instr; + int location, CardNum, ty; + int b_non_blank, neg, b_blk_op, b_blk_i, b_blk_d, b_blk_l, b_800X, b_pch_b, b_pch_a, b_bypass; // punch control flags + int i, sv_card_nbuf, n; + int pat1, pat2; + + word_to_ascii(loc, 1, 5, DRUM[addr + 0]); + word_to_ascii(data_addr, 1, 5, DRUM[addr + 1]); + word_to_ascii(inst_addr, 1, 5, DRUM[addr + 2]); + word_to_ascii(OpCode, 1, 3, DRUM[addr + 3]); + word_to_ascii(Data_Tag, 4, 1, DRUM[addr + 3]); + word_to_ascii(Instr_Tag, 5, 1, DRUM[addr + 3]); + word_to_ascii(rem1, 1, 5, DRUM[addr + 4]); + word_to_ascii(rem2, 1, 5, DRUM[addr + 5]); + instr = DRUM[addr + 6]; + location = (int) ((DRUM[addr + 7] / D4) % D4); + ty = (int) ( DRUM[addr + 7] % 10); + CardNum = (int) ( DRUM[addr + 8] % D4); + d = DRUM[addr + 9]; + b_blk_op = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_blk_i = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_blk_d = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_blk_l = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_800X = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_pch_b = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_pch_a = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_bypass = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + neg = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + b_non_blank = ((int) (d % 10) == 8) ? 1:0; d = d / 10; + + // printf("bits %06d%04d%c ", printfw(DRUM[addr + 9])); // to echo the status digits of punched card + + // generate card + if (b_pch_b) { + // punch availability table (pat pseudo-op output) + for(i=0;i<8;i++) { + sprintf_word(pch_word, DRUM[addr + i], 0, 1); + encode_pch_str(pch_word); + } + } else { + if (b_pch_a) { + // punch non generating code card + encode_pch_str("0?0000800?"); // load card + sprintf(pch_word, " %04d", CardNum); // card number + encode_pch_str(pch_word); + encode_pch_str(" "); // two blank words + encode_pch_str(" "); + if (b_non_blank) encode_pch_str("1"); else encode_pch_str(" "); + } else { + // punch generating code card + if (b_800X) { + encode_pch_str("6I1954800?"); // load card for word to be stored in 800X addr + } else { + encode_pch_str("6I1954195C"); // load card for word to be stored in drum + } + sprintf(pch_word, " %04d", CardNum); // card number + encode_pch_str(pch_word); + sprintf(pch_word, "24%04d800?", location);// addr to place the loaded word + encode_pch_str(pch_word); + sprintf_word(pch_word, AbsWord(instr) * (neg ? -1:1), ((neg) && (instr == 0)) ? 1:0, 1); + encode_pch_str(pch_word); + encode_char(ty == 0 ? ' ' : '0'+ty, 0); + } + encode_pch_str(" "); + sv_card_nbuf = card_nbuf; // save pch bufer current pos + encode_pch_str(loc); encode_pch_str(OpCode); + encode_pch_str(data_addr); encode_pch_str(Data_Tag); + encode_pch_str(inst_addr); encode_pch_str(Instr_Tag); + encode_pch_str(rem1); encode_pch_str(rem2); + // convert to lowercase for punching + for (i=sv_card_nbuf;i= 'A') && (card_buf[i] <= 'Z')) + card_buf[i] = card_buf[i] - 'A' + 'a'; + card_buf[card_nbuf] = 0; + } + + // generate printout + if (b_pch_b) { + // print availability table (pat pseudo-op output) + for(i=0; i<4; i++) { + d = DRUM[addr + i*2]; + pat1 = (int) ((d / D4) % D4); + pat2 = (int) ( d % D4); + d = DRUM[addr + i*2 + 1]; + encode_lpt_num(pat1, 4); + encode_lpt_spc(2); + encode_lpt_num(d, 10); + encode_lpt_spc(2); + encode_lpt_num(pat2, 4); + encode_lpt_spc(5); + } + } else if (ty == 1) { + // print coment line + encode_lpt_str("1"); + encode_lpt_spc(14); + encode_lpt_str(loc); encode_lpt_str(OpCode); + encode_lpt_str(data_addr); encode_lpt_str(Data_Tag); + encode_lpt_str(inst_addr); encode_lpt_str(Instr_Tag); + encode_lpt_str(rem1); encode_lpt_str(rem2); + } else { + encode_lpt_spc(1); + encode_lpt_str(loc); + encode_lpt_spc(2); encode_char(0, neg ? '-':' '); encode_lpt_spc(1); + encode_lpt_str(OpCode); encode_lpt_spc(3); + encode_lpt_str(data_addr); encode_lpt_str(Data_Tag); encode_lpt_spc(2); + encode_lpt_str(inst_addr); encode_lpt_str(Instr_Tag); encode_lpt_spc(5); + encode_lpt_str(rem1); encode_lpt_str(rem2); + if (b_pch_a) { + // blank op -> do not print location and intruction + if (b_bypass) { + encode_lpt_spc(4); + encode_lpt_str("BYPASS"); + } + } else { + encode_lpt_spc(4); + if (b_blk_l) { encode_lpt_spc(4); } else encode_lpt_num(location, 4); + encode_lpt_spc(2); encode_char(0, neg ? '-':' '); encode_lpt_spc(1); + d = instr; + n = Shift_Digits(&d, 2); // operation code (2 digits) + if (b_blk_op) { encode_lpt_spc(2); } else encode_lpt_num(n, 2); + encode_lpt_spc(2); + n = Shift_Digits(&d, 4); // data addr (4 digits) + if (b_blk_d) { encode_lpt_spc(4); } else encode_lpt_num(n, 4); + encode_lpt_spc(2); + n = Shift_Digits(&d, 4); // instr addr (4 digits) + if (b_blk_i) { encode_lpt_spc(4); } else encode_lpt_num(n, 4); + encode_lpt_spc(1); + if (b_blk_l) encode_lpt_str("BLANK L"); else + if (b_blk_op) encode_lpt_str("BLANK OP"); else + if (b_blk_d) encode_lpt_str("BLANK D"); else + if (b_blk_i) encode_lpt_str("BLANK I"); + } + } +} + +void encode_is_wiring(int addr) +{ + // encode Floationg Decimal Interpretive System (IS) card simulating control panel wiring for 533 as described + // in manual at http://www.bitsavers.org/pdf/ibm/650/28-4024_FltDecIntrpSys + // storage in output block + // +-+-+-+-+-+-|-+-+-+-| + // Word 1977: |Trc|N N N N| | Location + // 1978: | |N N N N| | Word Count + // +-------------------+ + // 1979: | word1 | + // 1980: | word2 | + // 1981: | word3 | + // 1982: | word4 | + // 1983: | word5 | + // 1984: | word6 | + // +-------------------+ + // 1985: | Problem Number | + // 1986: | |N N N N| | Card Number + // +-------------------+ + // + // if word at 1977 is negative, a load card is punched, but no printout is generated + // if word at 1977 is positive, regular output card format is used on punch + // Column: 1 2 3 4 | 5 6 | 7 8 9 | 10 | 11 | 12 - 21 | 22 | 23 - 32 | 33 | 34 - 43 | 44 | 45 - 54 | 55 | 56 - 65 | 66 | 67 - 76 | 77 78 79 | 80 + // Card | | | Location | wc | s1 | Word1 | s2 | Word2 | s3 | Word3 | s4 | Word4 | s5 | Word5 | s6 | Word6 | Problem | + // Num | if location is > 9999, will use column 6 Num + // wordN is printed as +N NNNNNNN NN (IT sci notation) + // + // IT printout format for non tracing cards: + // | Location | Word1 | Word2 | Word3 | Word4 | Word5 | Word6 + // wordN is printed as +N NNNNNNN NN (IT sci notation) + // + // IT printout format for tracing cards (Trc digits in word 1977 are non-zero): + // | Location | Word1 | Word2 | Word3 | Word4 | Word5 | Word6 + // word1 to 3 are printed as +N NNN NNN NNN (IT instruction format) + // word4 to 6 are printed as +N NNNNNNN NN (IT sci notation) + // + int i, NegZero; + t_int64 d; + int CardNum, loc, wc, PrNum, bTraceCard; + char pch_word[20]; + int bSetHiPunch; + + bSetHiPunch = (DRUM[addr] < 0) ? 2 : 0; // first bSetHiPunch is 2 if word negative (signals a load card must be punched) + + loc = (int) ((DRUM[addr] / D4) % D4); + CardNum = (int) ((DRUM[addr+9] / D4) % D4); + wc = (int) ((DRUM[addr+1] / D4) % D4); + PrNum = (int) ( DRUM[addr+8]); + bTraceCard = (DRUM[addr] / D8) > 0 ? 1 : 0; // if to higher digits are nonzero -> is a trace card + + if (bSetHiPunch) { + // punch a load card + for(i=0;i<8;i++) { + ReadDrum(addr + i, &d, &NegZero); + if ((i==0) && (d < 0)) d = -d; // get absolute value for DRUM[addr + 0] + sprintf_word(pch_word, d, NegZero, bSetHiPunch); + if (bSetHiPunch==2) bSetHiPunch = 1; // if bSetHiPunch is 2 change it to bSetHiPunch = 1 + encode_pch_str(pch_word); + } + } else { + // punch a card using output format + if (loc < 1000) { + sprintf(pch_word, "%04d %03d%01d", CardNum, loc, wc); + } else { + sprintf(pch_word, "%04d %04d%01d", CardNum, loc, wc); + } + encode_pch_str(pch_word); + for(i=0;i<6;i++) { + if (i 999) PrNum = 999; + sprintf(pch_word, "%03d", PrNum); + encode_pch_str(pch_word); + } + + if (bSetHiPunch) { + // load card, does not generate printout + // mark lpt output buffer to not print + if (card_nlpt == 0) { + card_lpt[card_nlpt++] = 0; + } + } else { + // not load card -> do normal printout for card + if (wc > 6) wc = 6; + if (loc < 1000) { + encode_lpt_spc(1); + encode_lpt_num(loc, 3); + } else { + encode_lpt_num(loc, 4); + } + for(i=2;i<2+wc;i++) { + encode_lpt_spc(2); + ReadDrum(addr + i, &d, &NegZero); + if ((bTraceCard) && (i<5)) { + // if printing a trace card, first three words are printed as intructions (+N NNN NNN NNN) + encode_lpt_word(d, NegZero, wf_sN_NNN_NNN_NNN); + } else { + // print numbers adding spaces to ease reading IT floating point format (+N NNNNNNN NN) + encode_lpt_word(d, NegZero, wf_sN_NNNNNNN_NN); + } + } + } +} + +/* Card punch routine */ +uint32 cdp_cmd(UNIT * uptr, uint16 cmd, uint16 addr) +{ + int i,c,h; + struct _card_data *data; + uint32 wiring; + + /* Are we currently tranfering? */ + if (uptr->u5 & URCSTA_BUSY) + return SCPE_BUSY; + + /* Test ready */ + if ((uptr->flags & UNIT_ATT) == 0) { + sim_debug(DEBUG_CMD, &cdp_dev, "No cards (no file attached)\r\n"); + return SCPE_NOCARDS; + } + + // copy and translate drum memory words to chars to punch + // using the control panel wiring. + + wiring = (uptr->flags & UNIT_CARD_WIRING); + card_nbuf = card_nlpt = 0; + + if (wiring == WIRING_SOAP) { + // encode soap card simulating soap control panel wiring for 533 (gasp!) + encode_soap_wiring(addr); + } else if (wiring == WIRING_IS) { + // encode it card + encode_is_wiring(addr); + } else if (wiring == WIRING_8WORD) { + // encode 8 words per card + encode_8word_wiring(addr); + } else { + // default wiring: decode up to 8 numerical words per card + encode_8word_wiring(addr); + } + + if ((card_nlpt == 1) && (card_lpt[0] == 0)) { + // skip this line printout & echo + } else { + /* echo? */ + encode_char(0, 13); encode_char(0, 10); + if (uptr->flags & UNIT_CARD_ECHO) { + for (i=0;iflags & UNIT_CARD_PRINT) { + // printout will be directed to file attached to CDP0 unit, if any + if (cdp_unit[0].flags & UNIT_ATT) { + sim_fwrite(&card_lpt, 1, card_nlpt, cdp_unit[0].fileref); + } + } + } + + // trim right spaces for printing punch card + card_buf[card_nbuf] = 0; + sim_debug(DEBUG_DETAIL, &cpu_dev, "Punch Card: %s\r\n", card_buf); + + /* punch the cards */ + data = (struct _card_data *)uptr->up7; + for (i=0; i<80; i++) { + if (i >= card_nbuf) { + c = 32; + } else { + c = card_buf[i]; + } + if (c == 32) { + // no punch + data->image[i] = 0; + } else { + // punch char + h = ascii_to_hol[c & 127]; + data->image[i] = h; + } + } + sim_punch_card(uptr, NULL); + sim_debug(DEBUG_CMD, &cdp_dev, "PUNCH\r\n"); + uptr->u5 |= URCSTA_BUSY; + uptr->u4 = 0; + + uptr->u5 &= ~URCSTA_BUSY; + + return SCPE_OK; + +} + +/* Handle transfer of data for card punch */ +t_stat +cdp_srv(UNIT *uptr) { + + // I/O is synchronous. No need to set up srv + return SCPE_OK; +} + + +/* Set card read/punch control panel wiring */ +t_stat cdp_set_wiring (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ + int f; + + if (uptr == NULL) return SCPE_IERR; + if (cptr == NULL) return SCPE_ARG; + for (f = 0; wirings[f].name != 0; f++) { + if (strcmp (cptr, wirings[f].name) == 0) { + uptr->flags = (uptr->flags & ~UNIT_CARD_WIRING) | wirings[f].mode; + return SCPE_OK; + } + } + return SCPE_ARG; +} + +/* Show card read/punch control panel wiring */ +t_stat cdp_show_wiring (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ + int f; + + for (f = 0; wirings[f].name != 0; f++) { + if ((uptr->flags & UNIT_CARD_WIRING) == wirings[f].mode) { + fprintf (st, "%s wiring", wirings[f].name); + return SCPE_OK; + } + } + fprintf (st, "invalid control panel wiring (%d)", uptr->flags & UNIT_CARD_WIRING); + return SCPE_OK; +} + +/* Set card read/punch echo to console */ +t_stat cdp_set_echo (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ + int u = (uptr - cdp_unit); + t_stat r; + int num; + + if (uptr == NULL) return SCPE_IERR; + if (cptr == NULL) { + num = 1; // no param means set (=1) + } else { + num = (int) get_uint (cptr, 10, 1, &r); + if (r != SCPE_OK) return r; + } + if (u == 0) { + sim_printf("this option cannot be set for CDP0\r\n"); + return SCPE_ARG; + } + switch(val) { + case 0: + if (num== 0) { + uptr->flags = uptr->flags & ~UNIT_CARD_ECHO; + } else { + uptr->flags = uptr->flags | UNIT_CARD_ECHO; + } + break; + case 1: + if (num== 0) { + uptr->flags = uptr->flags & ~UNIT_CARD_PRINT; + } else { + uptr->flags = uptr->flags | UNIT_CARD_PRINT; + } + break; + } + return SCPE_OK; +} + +/* Show card read/punch control panel wiring */ +t_stat cdp_show_echo (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ + switch(val) { + case 0: + fprintf (st, (uptr->flags & UNIT_CARD_ECHO) ? "ECHO": "No ECHO"); + break; + case 1: + fprintf (st, (uptr->flags & UNIT_CARD_PRINT) ? "PRINT": "No PRINT"); + break; + } + return SCPE_OK; +} + +t_stat +cdp_attach(UNIT * uptr, CONST char *file) +{ + t_stat r; + + if ((r = sim_card_attach(uptr, file)) != SCPE_OK) + return r; + uptr->u5 = 0; + + return SCPE_OK; +} + +t_stat +cdp_detach(UNIT * uptr) +{ + return sim_card_detach(uptr); +} + +t_stat +cdp_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ + fprintf (st, "%s\r\n\r\n", cdp_description(dptr)); + fprintf (st, "The 533 Card Read-punch writes cards using the selected\r\n"); + fprintf (st, "control panel wiring to set the format of punched cards.\r\n"); + fprintf (st, "It is possible to simulate a 407 accounting machine for\r\n"); + fprintf (st, "printing using SET CDP1 PRINT=1. In this case, punched\r\n"); + fprintf (st, "cards will be printed to file attached to unit 0 (CDP0).\r\n"); + fprintf (st, "SET CDP ECHO=1 will display on console cards printout.\r\n"); + + sim_card_attach_help(st, dptr, uptr, flag, cptr); + fprint_set_help(st, dptr); + fprint_show_help(st, dptr); + return SCPE_OK; +} + +const char * +cdp_description(DEVICE *dptr) +{ + return "533 Card Punch + 407 Accounting for printing"; +} + + diff --git a/I650/i650_cdr.c b/I650/i650_cdr.c new file mode 100644 index 00000000..3295a0b2 --- /dev/null +++ b/I650/i650_cdr.c @@ -0,0 +1,556 @@ +/* i650_cdr.c: IBM 650 Card reader. + + Copyright (c) 2018, Roberto Sancho + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + ROBERTO SANCHO BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + This is the standard card reader. + + These units each buffer one record in local memory and signal + ready when the buffer is full or empty. The channel must be + ready to recieve/transmit data when they are activated since + they will transfer their block during chan_cmd. All data is + transmitted as BCD characters. + +*/ + +#include "i650_defs.h" +#include "sim_card.h" + +#define UNIT_CDR UNIT_ATTABLE | UNIT_RO | MODE_026 + + +/* std devices. data structures + + cdr_dev Card Reader device descriptor + cdr_unit Card Reader unit descriptor + cdr_reg Card Reader register list + cdr_mod Card Reader modifiers list +*/ + +uint32 cdr_cmd(UNIT *, uint16, uint16); +t_stat cdr_srv(UNIT *); +t_stat cdr_reset(DEVICE *); +t_stat cdr_attach(UNIT *, CONST char *); +t_stat cdr_detach(UNIT *); +t_stat cdr_help(FILE *, DEVICE *, UNIT *, int32, const char *); +const char *cdr_description(DEVICE *dptr); +t_stat cdr_set_wiring (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat cdr_show_wiring (FILE *st, UNIT *uptr, int32 val, CONST void *desc); + +UNIT cdr_unit[] = { + {UDATA(cdr_srv, UNIT_CDR, 0), 300}, // 4 readers. Unit 0 not used + {UDATA(cdr_srv, UNIT_CDR, 0), 300}, + {UDATA(cdr_srv, UNIT_CDR, 0), 300}, + {UDATA(cdr_srv, UNIT_CDR, 0), 300}, +}; + +MTAB cdr_mod[] = { + {MTAB_XTD | MTAB_VUN, 0, "FORMAT", "FORMAT", &sim_card_set_fmt, &sim_card_show_fmt, NULL, "Set card format"}, + {MTAB_XTD | MTAB_VUN, 0, "WIRING", "WIRING", &cdr_set_wiring, &cdr_show_wiring, NULL, "Set card read control panel Wiring"}, + {0} +}; + +DEVICE cdr_dev = { + "CDR", cdr_unit, NULL, cdr_mod, + 4, 8, 15, 1, 8, 8, + NULL, NULL, NULL, NULL, &cdr_attach, &sim_card_detach, + &cdr_dib, DEV_DISABLE | DEV_DEBUG, 0, crd_debug, + NULL, NULL, &cdr_help, NULL, NULL, &cdr_description +}; + +static struct card_wirings wirings[] = { + {WIRING_8WORD, "8WORD"}, + {WIRING_SOAP, "SOAP"}, + {WIRING_IS, "IS"}, + {0, 0}, +}; + + +// decode digit 0-9 read from card to get value and X(11) and Y(12) punch state (minus/HiPunch) +// return -1 if not a digit number +int decode_digit(char c1, int * HiPunch, int * NegPunch) +{ + int i,n; + + *HiPunch = *NegPunch = 0; + // N is 0..9 or ?A..I (0..9 with Y(12) High Punch set) + // or !J..R (0..9 with X(11) Minus Punch set). + // or &S..Z# (0..9 with both X(11) and Y(12) Punch set). + + if (c1 == 32) return 0; // space read as zero + for (i=0; i<40; i++) { + if (c1 == digits_ascii[i]) { + n = i % 10; + i = i / 10; + *HiPunch = (i & 1); + *NegPunch = (i >> 1); + return n; + } + } + return -1; // not a valid digit +} + +// get 10 digits word from buf, with sign. return 1 if HiPunch set on any digit +int decode_8word_wiring(char * buf, int addr) +{ + // decode up to 8 numerical words per card + // input card + // NNNNNNNNNN ... 8 times + // N is 0..9 or ?A..I (0..9 with Y(12) High Punch set) + // or !J..R (0..9 with X(11) Minus Punch set). + // or &S..Z# (0..9 with both X(11) and Y(12) Punch set). + // If last digit of word has X(11) punch whole word is set as negative value + // If N is a space, a 0 is assumed + // put the decoded data in drum at addr (if addr < 0 -> do not store in drum) + // return 1 if any colum has Y(12) hi-punch set + int c1,c2,wn,eor,iCol; + int HiPunch, hip; + int NegPunch, NegZero; + int nDigits; + t_int64 d; + + NegZero = 0; // flag set if negative zero is read + HiPunch = 0; // set to 1 if Y(12) high punch found + eor = 0; // signals end of card record + iCol = 0; // current read colum in card + for (wn=0;wn<8;wn++) { // one card generates 8 words in drum mem + d = 0; + nDigits=0; // number of digits + while (1) { + c1 = buf[iCol++]; + if (c1 < ' ') {eor = 1; break;} // end of card + c2 = decode_digit(c1, &hip, &NegPunch); + if (hip) HiPunch = 1; // if any column has Hi Punch Y(12) set, signal it + if (c2 < 0) c2 = 0; // nondigits chars interpreted as zero + d = d * 10 + c2; + nDigits++; + if (nDigits == 10) { + // end of word + if (NegPunch) { // has last digit a minus X(11) punch set? + d = -d; // yes, change sign of word read + if (d == 0) NegZero=1; // word read is minus zero + } + break; + } + } + if (nDigits == 0) break; // no well-formed word read -> terminate card processing + if (addr >= 0) WriteDrum(addr++, d, NegZero); // store word read from card into drum + if (eor) break; // end of card sensed -> terminate card processing + + } + return HiPunch; +} + + +t_int64 decode_num_word(char * buf, int nDigits, int bSpaceIsZero) +{ + t_int64 d; + int i,c; + + d = 0; + for (i=0;i '9')) { + d = -1; // not a number + break; + } + d = d * 10 + c - '0'; + } + if (d < 0) { + // not a number -> return all 9's + d = 0; + for (i=0;i | Alphabetic + // 1952: | <- Data Addr -> | Alphabetic + // 1953: | <- Inst Addr -> | Alphabetic + // +-+-+-|-+-+-|-+-|-+-| + // 1954: | Op Code |DTg|ITg| Alphabetic + // +-+-+-|-+-+-|-+-|-+-| + // 1955: | <- Remarks -> | Alphabetic + // 1956: | <- Remarks -> | Alphabetic + // +-+-+-+-+-+-|-+-+-+-| + // 1957: | |N N N N| L Absolute Part + // 1958: | |N N N N| D Absolute Part + // 1959: | |N N N N| I Absolute Part + // 1960: | |T b n| T=Type (0 if Blank), b=0/8 (for non blank type), n=0/8 (for negative) + // + int ty,neg; + + DRUM[addr + 0] = decode_alpha_word(&buf[42], 5); // Location (5 chars) + DRUM[addr + 1] = decode_alpha_word(&buf[50], 5); // Data Addr (5 chars) + DRUM[addr + 2] = decode_alpha_word(&buf[56], 5); // Inst Addr (5 chars) + DRUM[addr + 3] = decode_alpha_word(&buf[47], 3) * D4 + // OpCode (3 chars only) + decode_alpha_word(&buf[55], 1) * 100 + // Data Addr Tag (1 char only) + decode_alpha_word(&buf[61], 1); // Instr Addr Tag (1 char only) + DRUM[addr + 4] = decode_alpha_word(&buf[62], 5); // Remarks + DRUM[addr + 5] = decode_alpha_word(&buf[67], 5); // Remarks + + DRUM[addr + 6] = decode_num_word(&buf[43], 4, 0); // Absolute Part of location + DRUM[addr + 7] = decode_num_word(&buf[51], 4, 0); // Absolute Part of Data Addr + DRUM[addr + 8] = decode_num_word(&buf[57], 4, 0); // Absolute Part of Instr Addr + + if (buf[40] == '1') {ty = 18; } else + if (buf[40] == '2') {ty = 28; } else {ty = 0; } + neg = (buf[41] == '-') ? 8:0; + + DRUM[addr + 9] = ty * 10 + neg; // |T b n| T=Type (0 if Blank), b=0/8 (for non blank type), n=0/8 (for negative) +} + +int sformat(char * buf, const char * match) +{ + char m,c; + + while(1) { + m = *match++; + if (m == 0) break; + c = *buf++; + if (c == 0) return 0; // end of buf str before end of match string -> return 0 -> buf does not match + if ((m == ' ') && (c == ' ')) continue; + if ((m == 'N') && (c >= '0') && (c <= '9')) continue; + if ((m == '+') && ((c == '+') || (c == '-'))) continue; + return 0; // buf does not match -> return 0 -> buf does not match + } + return 1; // end of match string -> return 1 -> buf matches +} + +void decode_is_wiring(char * buf, int addr) +{ + // decode Floationg Decimal Interpretive System (IS) card simulating control panel wiring for 533 as described + // in manual at http://www.bitsavers.org/pdf/ibm/650/28-4024_FltDecIntrpSys + // input card + // Column: 1 2 3 4 | 5 6 | 7 8 9 | 10 | 11 | 12 - 21 | 22 | 23 - 32 | 33 | 34 - 43 | 44 | 45 - 54 | 55 | 56 - 65 | 66 | 67 - 76 | 77 78 79 | 80 + // Card | | Location | wc | s1 | Word1 | s2 | Word2 | s3 | Word3 | s4 | Word4 | s5 | Word5 | s6 | Word6 | Problem | + // Num | Num + // + // wc = Word Count (space for 1) + // s1 = sign of word 1 (space for +) + // Tr = Tracing identification + // + // Alternate input format to allow system deck loading + // Column: 1 2 | 3 | 4 5 6 | 7 | 8 9 10 11 | 12 | 13 - 24 + // Deck | sp | Card | | NNNN | | NN NNNN NNNN + // Num | | Num | + // + // Alternate input format to allow IT source program loading + // Column: 1 2 3 4 | 5 6 | 7 8 9 | 10 | 11 | 12 - 24 + // Card | Blank | Location | | sg | N NNN NNN NNN <- This is an IT instruction (format O1 A B C) + // Num | + // Column: 1 2 3 4 | 5 6 | 7 8 9 | 10 | 11 | 12 - 23 + // Card | Blank | Location | | sg | N NNNNNNN NN <- This is an IT float numeric constant (mantissa and exponent) + // Num | + // Column: 1 2 3 4 | 5 6 | 7 8 9 | 10 - 23 + // Card | Blank | Location | blanks <- This is an IT transfer card (location is start of IT program) + // Num | + // + // storage in input block + // +-+-+-+-+-+-|-+-+-+-| + // Word 1951: | |N N N N| | Location + // 1952: | |N N N N| | Word Count + // +-------------------+ + // 1953: | word1 | + // 1954: | word2 | + // 1955: | word3 | + // 1956: | word4 | + // 1957: | word5 | + // 1958: | word6 | + // +-------------------+ + // 1959: | Problem Number | + // +-------------------+ + // input card + // WordN is 0..9, + // sign is -,+, + // put the decoded data in drum at addr (if addr < 0 -> do not store in drum) + // card number is ignored on reading + + int wc,neg,i; + int NegZero; + t_int64 d; + + if ( sformat(&buf[6], " ")) { + // blank card: read as all zero, one word count + // this allows to have blank cards/comments card as long as the comment starts on column 27 of more + DRUM[addr + 1] = 1 * D4; // word count + } else if ( sformat(&buf[5], " NNN ")) { + // alternate format for loading IT program (IT transfer card) + DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // start location (3 digits) + DRUM[addr + 1] = 0; // word count = 0 + } else if ( sformat(&buf[5], " NNN +N NNN NNN NNN ")) { + // alternate format for loading IT program (IT instruction) + DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) + DRUM[addr + 1] = 1 * D4; // word count + NegZero = 0; + neg = (buf[10] == '-') ? 1:0; + d = decode_num_word(&buf[11], 1, 0) * 10 * D8 + // O1 + decode_num_word(&buf[13], 3, 0) * 100 * D4 + // O2 or A + decode_num_word(&buf[17], 3, 0) * 1000 + // B + decode_num_word(&buf[21], 3, 0); // C + if (neg) { + d=-d; + if (d==0) NegZero = 1; + } + WriteDrum(addr + 2, d, NegZero); + } else if ( sformat(&buf[5], " NNN +N NNNNNNN NN ")) { + // alternate format for loading IT program (numeric constant in float format) + DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) + DRUM[addr + 1] = 1 * D4; // word count + NegZero = 0; + neg = (buf[10] == '-') ? 1:0; + d = decode_num_word(&buf[11], 1, 0) * 10 * D8 + // integer part of mantissa + decode_num_word(&buf[13], 7, 0) * 100 + // factional part of mantissa + decode_num_word(&buf[21], 2, 0); // exponent + if (neg) { + d=-d; + if (d==0) NegZero = 1; + } + WriteDrum(addr + 2, d, NegZero); + } else if ( (sformat(&buf[6], " NNNN NN NNNN NNNN ")) || + (sformat(&buf[6], " NNNN NN NNNN ")) || + (sformat(&buf[6], " NNNN NN NNNN ")) || + (sformat(&buf[6], " NNNN NN ")) + ) { + // alternate format for loading main IT system deck + DRUM[addr + 0] = decode_num_word(&buf[7], 4, 0) * D4; // location (4 digits) + DRUM[addr + 1] = 1 * D4; // word count = 1 + DRUM[addr + 2] = decode_num_word(&buf[12], 2, 1) * D8 + // op + decode_num_word(&buf[15], 4, 1) * D4 + // data address + decode_num_word(&buf[20], 4, 1); // instr addr, no negative zero allowed + } else { + // regular IT read/punch format + DRUM[addr + 0] = decode_num_word(&buf[6], 3, 0) * D4; // location (3 digits) + wc = (int) decode_num_word(&buf[9], 1, 1); + if (wc > 6) wc = 6; + DRUM[addr + 1] = wc * D4; // word count + for (i=0;iu5 & URCSTA_BUSY) + return SCPE_BUSY; + + // clear read buffer in drum (where words read from cards will be stored) + for (i=0;i<10;i++) WriteDrum(addr + i, 0, 0); + + /* Test ready */ + if ((uptr->flags & UNIT_ATT) == 0) { + sim_debug(DEBUG_CMD, &cdr_dev, "No cards (no file attached)\r\n"); + return SCPE_NOCARDS; + } + + /* read the cards */ + sim_debug(DEBUG_CMD, &cdr_dev, "READ\r\n"); + uptr->u5 |= URCSTA_BUSY; + + switch(sim_read_card(uptr)) { + case SCPE_EOF: + sim_debug(DEBUG_DETAIL, &cdr_dev, "EOF\r\n"); + uptr->u5 = 0; + return SCPE_NOCARDS; + case SCPE_UNATT: + sim_debug(DEBUG_DETAIL, &cdr_dev, "Not Attached\r\n"); + uptr->u5 = 0; + return SCPE_NOCARDS; + case SCPE_IOERR: + sim_debug(DEBUG_DETAIL, &cdr_dev, "ERR\r\n"); + uptr->u5 = 0; + return SCPE_NOCARDS; + case SCPE_OK: + break; + } + + data = (struct _card_data *)uptr->up7; + + // make local copy of card + buf_len = data->ptr; + if (buf_len == 0) { + buf_len = data->len; + } + for (i=0;i<80;i++) { + if (i < buf_len) { + c = data->cbuff[i]; + if (c < ' ') c = ' '; + buf[i] = c; + } else { + buf[i] = ' '; + } + } + buf[80] = 0; // terminate string + + // trim right spaces for printing read card + for (i=80;i>=0;i--) if (buf[i] > 32) break; + c = buf[i+1]; buf[i+1]=0; + sim_debug(DEBUG_DETAIL, &cpu_dev, "Read Card: %s\r\n", buf); + buf[i+1]=c; + + // check if it is a load card (Y(12) = HiPunch set on any column of card) signales it + if (decode_8word_wiring(buf, -1)) { + uptr->u5 |= URCSTA_LOAD; + } else { + uptr->u5 &= ~URCSTA_LOAD; + } + + wiring = (uptr->flags & UNIT_CARD_WIRING); + + // translate chars read from card and copy to drum memory words + // using the control panel wiring. + if (uptr->u5 & URCSTA_LOAD) { + // load card -> use 8 words per card encoding + decode_8word_wiring(buf, addr); + } else if (wiring == WIRING_SOAP) { + // decode soap card simulating soap control panel wiring for 533 (gasp!) + decode_soap_wiring(buf, addr); + } else if (wiring == WIRING_IS) { + // decode it card + decode_is_wiring(buf, addr); + } else { + // default wiring: decode up to 8 numerical words per card. Can be a load card + decode_8word_wiring(buf, addr); + } + + uptr->u5 &= ~URCSTA_BUSY; + + return SCPE_OK; +} + +/* Handle transfer of data for card reader */ + +t_stat +cdr_srv(UNIT *uptr) { + + // I/O is synchronous. No need to set up svr + return SCPE_OK; +} + +/* Set card read/punch control panel wiring */ +t_stat cdr_set_wiring (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ + int f; + + if (uptr == NULL) return SCPE_IERR; + if (cptr == NULL) return SCPE_ARG; + for (f = 0; wirings[f].name != 0; f++) { + if (strcmp (cptr, wirings[f].name) == 0) { + uptr->flags = (uptr->flags & ~UNIT_CARD_WIRING) | wirings[f].mode; + return SCPE_OK; + } + } + return SCPE_ARG; +} + +/* Show card read/punch control panel wiring */ +t_stat cdr_show_wiring (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ + int f; + + for (f = 0; wirings[f].name != 0; f++) { + if ((uptr->flags & UNIT_CARD_WIRING) == wirings[f].mode) { + fprintf (st, "%s wiring", wirings[f].name); + return SCPE_OK; + } + } + fprintf (st, "invalid control panel wiring (%d)", uptr->flags & UNIT_CARD_WIRING); + return SCPE_OK; +} + + +t_stat +cdr_attach(UNIT * uptr, CONST char *file) +{ + t_stat r; + + if ((r = sim_card_attach(uptr, file)) != SCPE_OK) + return r; + uptr->u5 = 0; + uptr->u4 = 0; + uptr->u6 = 0; + return SCPE_OK; +} + +t_stat +cdr_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ + fprintf (st, "%s\r\n\r\n", cdr_description(dptr)); + fprintf (st, "The 533 Card Read-punch supported a load mode, and\r\n"); + fprintf (st, "several predefined control panel wiring. Default\r\n"); + fprintf (st, "wiring is up to 8 numeric words per card.\r\n\r\n"); + sim_card_attach_help(st, dptr, uptr, flag, cptr); + fprint_set_help(st, dptr); + fprint_show_help(st, dptr); + return SCPE_OK; +} + +const char * +cdr_description(DEVICE *dptr) +{ + return "533 Card Read-Ounch unit"; +} + + diff --git a/I650/i650_cpu.c b/I650/i650_cpu.c new file mode 100644 index 00000000..952e323f --- /dev/null +++ b/I650/i650_cpu.c @@ -0,0 +1,1074 @@ +/* i650_cpu.c: IBM 650 CPU simulator + + Copyright (c) 2018, Roberto Sancho + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + ROBERTO SANCHO BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + cpu IBM 650 central processor + + From Wikipedia: The IBM 650 Magnetic Drum Data-Processing Machine is one of + IBM's early computers, and the world’s first mass-produced computer. It was + announced in 1953 and in 1956 enhanced as the IBM 650 RAMAC with the + addition of up to four disk storage units. Almost 2,000 systems were + produced, the last in 1962. + + The 650 was a two-address, bi-quinary coded decimal computer (both data and + addresses were decimal), with memory on a rotating magnetic drum. Character + support was provided by the input/output units converting punched card + alphabetical and special character encodings to/from a two-digit decimal + code. + + Rotating drum memory provided 1,000, 2,000, or 4,000 words of memory (a + signed 10-digit number or five characters per word) at addresses 0000 to + 0999, 1999, or 3999 respectively. + + Instructions read from the drum went to a program register (in current + terminology, an instruction register). Data read from the drum went through + a 10-digit distributor. The 650 had a 20-digit accumulator, divided into + 10-digit lower and upper accumulators with a common sign. Arithmetic was + performed by a one-digit adder. The console (10 digit switches, one sign + switch, and 10 bi-quinary display lights), distributor, lower and upper + accumulators were all addressable; 8000, 8001, 8002, 8003 respectively. + + The 650 instructions consisted of a two-digit operation code, a four-digit + data address and the four-digit address of the next instruction. The sign + was ignored on the basic machine, but was used on machines with optional + features. The base machine had 44 operation codes. Additional operation + codes were provided for options, such as floating point, core storage, + index registers and additional I/O devices. With all options installed, + there were 97 operation codes. + + The programmer visible system state for the IBM 650 is: + + CSW <10:1> Console Switches + ACC[0] <10:1> Lower Accumulator register + ACC[1] <10:1> Upper Accumulator register + DIST <10:1> Distributor + OV<0:0> Overflow flag + + The 650 had one basic instuction format. + Intructions are stores as 10 digits (0-9) words in drum memory + + 10 9 | 8 7 6 5 | 4 3 2 1 | 0 + -----+---------+---------+----- + op | Data | Instr | Sign + code | Addr | Addr + + First two digits are opcodes + digits 8-5 is data address referenced by opcode + digits 4-1 is instruction address: address of next instruction + + Instruction support as described in BitSavers 22-6060-2_650_OperMan.pdf + +*/ + +#include "i650_defs.h" + +extern const char * get_opcode_data(int opcode, int * ReadData); + +#define UNIT_V_MSIZE (UNIT_V_UF + 0) +#define UNIT_MSIZE (7 << UNIT_V_MSIZE) +#define UNIT_V_CPUMODEL (UNIT_V_UF + 4) +#define UNIT_MODEL (0x01 << UNIT_V_CPUMODEL) +#define CPU_MODEL ((cpu_unit.flags >> UNIT_V_CPUMODEL) & 0x01) +#define MODEL(x) (x << UNIT_V_CPUMODEL) +#define MEMAMOUNT(x) (x << UNIT_V_MSIZE) +//XXX #define OPTION_FLOAT (1 << (UNIT_V_CPUMODEL + 1)) + +t_stat cpu_ex(t_value * vptr, t_addr addr, UNIT * uptr, int32 sw); +t_stat cpu_dep(t_value val, t_addr addr, UNIT * uptr, int32 sw); +t_stat cpu_reset(DEVICE * dptr); +t_stat cpu_set_size(UNIT * uptr, int32 val, CONST char *cptr, void *desc); +t_stat cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *cpu_description (DEVICE *dptr); + +void mem_init(void); +t_int64 DRUM[MAXMEMSIZE] = {0}; +int DRUM_NegativeZeroFlag[MAXMEMSIZE] = {0}; + +// cpu registers +t_int64 ACC[2]; /* lower, upper accumulator. 10 digits (=one word) each*/ +t_int64 DIST; /* ditributor. 10 digits */ +int OV; /* Overflow flag */ +t_int64 CSW = 0; /* Console Switches, 10 digits */ +int CSWProgStop = 1; /* Console programmed stop switch */ +int CSWOverflowStop = 0; /* Console stop on overflow switch */ +t_int64 PR; /* Program Register: hold current instr in execution, 10 digits*/ +int AR; /* Address Register: address references to drum */ +int AccNegativeZeroFlag = 0; // set to 1 if acc has a negative zero +int DistNegativeZeroFlag = 0; // set to 1 if distributor has a negative zero +int IC; // addr of current intr in execution, just for debugginf purposes. IBM 650 has no program counter + +void (*sim_vm_init) (void) = &mem_init; + + +/* CPU data structures + + cpu_dev CPU device descriptor + cpu_unit CPU unit descriptor + cpu_reg CPU register list + cpu_mod CPU modifiers list +*/ + +UNIT cpu_unit = + { UDATA(NULL, MEMAMOUNT(0)|MODEL(0x0), 1000), 10 }; + + +REG cpu_reg[] = { + {DRDATAD(IC, IC, 16, "Current Instruction"), REG_FIT}, + {HRDATAD(DIST, DIST, 64, "Distributor"), REG_VMIO|REG_FIT}, + {HRDATAD(ACCLO, ACC[0], 64, "Lower Accumulator"), REG_VMIO|REG_FIT}, + {HRDATAD(ACCUP, ACC[1], 64, "Upper Accumulator"), REG_VMIO|REG_FIT}, + {HRDATAD(PR, PR, 64, "Program Register"), REG_VMIO|REG_FIT}, + {DRDATAD(AR, AR, 16, "Address Register"), REG_FIT}, + {ORDATAD(OV, OV, 1, "Overflow"), REG_FIT}, + {HRDATAD(CSW, CSW, 64, "Console Switches"), REG_VMIO|REG_FIT}, + {ORDATAD(CSWPS, CSWProgStop, 1, "Console Switch Program Stop"), REG_FIT}, + {ORDATAD(CSWOS, CSWOverflowStop, 1, "Console Switch Overflow Stop"), REG_FIT}, + {NULL} +}; + +MTAB cpu_mod[] = { + {UNIT_MSIZE, MEMAMOUNT(0), "1K", "1K", &cpu_set_size}, + {UNIT_MSIZE, MEMAMOUNT(1), "2K", "2K", &cpu_set_size}, + {UNIT_MSIZE, MEMAMOUNT(2), "4K", "4K", &cpu_set_size}, + {0} +}; + +DEVICE cpu_dev = { + "CPU", &cpu_unit, cpu_reg, cpu_mod, + 1, 10, 12, 1, 10, 64, + &cpu_ex, &cpu_dep, &cpu_reset, NULL, NULL, NULL, + NULL, DEV_DEBUG, 0, dev_debug, + NULL, NULL, &cpu_help, NULL, NULL, &cpu_description +}; + +// return 0 if drum addr invalid +int IsDrumAddrOk(int AR) +{ + if ((AR < 0) || (AR >= (int)MEMSIZE) || (AR >= MAXMEMSIZE)) return 0; + return 1; +} + +// return 0 if write addr invalid +int WriteDrum(int AR, t_int64 d, int NegZero) +{ + if (IsDrumAddrOk(AR) == 0) return 0; + if (d) NegZero = 0; // sanity check on Minus Zero + DRUM[AR] = d; + DRUM_NegativeZeroFlag[AR] = NegZero; + return 1; +} + +// return 0 if drum addr invalid +int ReadDrum(int AR, t_int64 * d, int * NegZero) +{ + if (IsDrumAddrOk(AR) == 0) return 0; + *d = DRUM[AR]; + *NegZero = DRUM_NegativeZeroFlag[AR]; + if (*d) { + *NegZero = 0; // sanity check on Minus Zero + DRUM_NegativeZeroFlag[AR] = 0; + } + return 1; +} + +// return 0 if read addr invalid +int ReadAddr(int AR, t_int64 * d, int * NegZero) +{ + int r; + + if (AR == 8000) {*d = CSW; *NegZero=0; r=1; } else + if (AR == 8001) {*d = DIST; *NegZero=DistNegativeZeroFlag; r=1; } else + if (AR == 8002) {*d = ACC[0]; *NegZero=AccNegativeZeroFlag; r=1; } else + if (AR == 8003) {*d = ACC[1]; *NegZero=AccNegativeZeroFlag; r=1; } else + { r=ReadDrum(AR, d, NegZero); } + if (*d) *NegZero = 0; // sanity check on Minus Zero + return r; +} + +int bAccNegComplement; // flag to signals acc has complemented a negative ass (== sign adjust) + // needed to compute execution cycles taken by the intruction + +// add to accumulator, set Overflow +void AddToAcc(t_int64 a1, t_int64 a0) +{ + OV = 0; AccNegativeZeroFlag = 0; + bAccNegComplement = 0; + + ACC[0] += a0; + ACC[1] += a1; + + // adjust carry from Lower ACC to Upper Acc + if (ACC[0] >= D10) { ACC[0] -= D10; ACC[1]++; } + if (ACC[0] <= -D10) { ACC[0] += D10; ACC[1]--; } + + // ajust sign + if ((ACC[0] > 0) && (ACC[1] < 0)) { + ACC[0] -= D10; ACC[1]++; + bAccNegComplement = 1; + } + if ((ACC[0] < 0) && (ACC[1] > 0)) { + ACC[0] += D10; ACC[1]--; + bAccNegComplement = 1; + } + + // check overflow + if ((ACC[1] >= D10) || (ACC[1] <= -D10)) { + ACC[1] = ACC[1] % D10; + OV=1; + } +} + +// shift acc 1 digit. If direction > 0 to the left, if direction < 0 to the right. +// Return overflow digit (with sign) +int ShiftAcc(int direction) +{ + t_int64 a0, a1; + int neg = 0; + int n, m; + + a1 = ACC[1]; if (a1 < 0) {a1 = -a1; neg = 1;} + a0 = ACC[0]; if (a0 < 0) {a0 = -a0; neg = 1;} + + if (direction > 0) { // shift left + n = Shift_Digits(&a1, 1); // n = Upper Acc high digit shifted out on the left + m = Shift_Digits(&a0, 1); // m = intermediate digit that goes from one acc to the other + a1 = a1 + (t_int64) m; + } else if (direction < 0) { // shift right + m = Shift_Digits(&a1, -1); // m = intermediate digit that goes from one acc to the other + n = Shift_Digits(&a0, -1); // n = Lower Acc units digit shifted out on the right + a0 = a0 + (t_int64) m * (1000000000L); + } + if (neg) {a1=-a1; a0=-a0; n=-n;} + + ACC[0] = a0; + ACC[1] = a1; + if ((neg == 1) && (a0 == 0) && (a1 == 0)) AccNegativeZeroFlag = 1; + return n; +} + + +t_int64 SetDA(t_int64 d, int DA) +{ + int neg = 0; + + int op, nn, IA; + + if (DA < 0) DA=-DA; + if (d < 0) {d=-d; neg=1;} + + // extract parts of word + op = Shift_Digits(&d, 2); + nn = Shift_Digits(&d, 4); // discard current DA + IA = Shift_Digits(&d, 4); + // rebuild word with new DA + d = (t_int64) op * D8 + + (t_int64) DA * D4 + + (t_int64) IA; + if (neg) d=-d; + return d; +} + +// set last 4 digits in d with IA contents +t_int64 SetIA(t_int64 d, int IA) +{ + int neg = 0; + + if (IA < 0) IA=-IA; + if (d < 0) {d=-d; neg=1;} + d = d - ( d % D4); + d = d + (IA % D4); + if (neg) d=-d; + return d; +} + +// set last 2 digits in d with IA contents +t_int64 SetIA2(t_int64 d, int n) +{ + int neg = 0; + + if (n < 0) n=-n; + if (d < 0) {d=-d; neg=1;} + d = d - ( d % 100); + d = d + ( n % 100); + if (neg) d=-d; + return d; +} + +t_stat +sim_instr(void) +{ + t_stat reason; + t_int64 d; + int n, i, sgn, r; + int opcode = 0; + int bReadData, bWriteDrum; + int instr_count = 0; /* Number of instructions to execute */ + const char * opname; /* points to opcode name */ + int PRNegZero; + + int IA; // Instr Address: addr of next inst + int DA; // Data Address; addr of data to be used by current inst + + int DrumAddr; // address where drum is currently positioned (0-49) + int MachineCycle, bBranchTaken, CpuStepsRemaining, WaitForInterlock; + int InterLockCount[3]; // interlock counters + #define IL_RD1 1 // interlock on drum area 01-10/51-60 used in reading for cdr1 + #define IL_WR1 2 // interlock on drum area 27-36/77-86 used in writing for cdp1 + + if (sim_step != 0) { + instr_count = sim_step; + sim_cancel_step(); + } + + reason = 0; + + MachineCycle = CpuStepsRemaining = 0; + bReadData = bWriteDrum = 0; + DrumAddr = 0; + + WaitForInterlock = 0; + InterLockCount[IL_RD1] = InterLockCount[IL_WR1] = 0; + + while (reason == 0) { /* loop until halted */ + + if (sim_interval <= 0) { /* event queue? */ + reason = sim_process_event(); + if (reason != SCPE_OK) { + break; /* process */ + } + } + + /* Main instruction fetch/decode loop */ + sim_interval -= 1; /* count down */ + + // simulate the rotating drum: incr current drum position + DrumAddr = ++DrumAddr % 50; + // if any interlock set, make it expire + if (InterLockCount[IL_RD1]) InterLockCount[IL_RD1]--; + if (InterLockCount[IL_WR1]) InterLockCount[IL_WR1]--; + + if (MachineCycle == 0) { + /* Only check for break points during actual fetch */ + if (sim_brk_summ && sim_brk_test(IC, SWMASK('E'))) { + reason = STOP_IBKPT; + break; + } + // should wait for drum to fetch inst? + if ((AR >= 0) && (AR < (int)MEMSIZE)) { + if ((AR % 50) != DrumAddr) continue; // yes + } + CpuStepsRemaining = 0; // init inst execution + bReadData = bWriteDrum = 0; + MachineCycle = 1; // decode instr + } if (MachineCycle == 2) { + // should wait for cpu to exec the inst? + if (--CpuStepsRemaining > 0) continue; // yes + CpuStepsRemaining = 0; + // should wait for interlock release? + if (WaitForInterlock) { + if (InterLockCount[WaitForInterlock]) continue; // yes + WaitForInterlock = 0; + } + // should wait for drum to fetch data? + if ((bReadData) && (AR >= 0) && (AR < (int)MEMSIZE)) { + if ((AR % 50) != DrumAddr) continue; // yes + } + MachineCycle = 3; // exec instr + } if (MachineCycle == 4) { + // should wait for cpu to exec the inst? + if (--CpuStepsRemaining > 0) continue; // yes + CpuStepsRemaining = 0; + // should wait for drum to store data? + if ((bWriteDrum) && (AR >= 0) && (AR < (int)MEMSIZE)) { + if ((AR % 50) != DrumAddr) continue; // yes + } + MachineCycle = 5; // terminate the instr execution + } + // here, MachineCicly is either 1 (decode), 3 (exec), 5 (exec2) + + if (MachineCycle == 1) { + // fetch current intruction from mem, save current instr addr in IC + IC = AR; + if (0==ReadAddr(AR, &PR, &PRNegZero)) { + reason = STOP_ADDR; + goto end_of_while; + } + // decode inst + d = PR; + opcode = Shift_Digits(&d, 2); // current inste opcode + DA = Shift_Digits(&d, 4); // addr of data used by current instr + IA = Shift_Digits(&d, 4); // addr of next instr + opname = get_opcode_data(opcode, &bReadData); + if (opname == NULL) { + reason = STOP_UUO; // unknown opcode + goto end_of_while; + } + sim_debug(DEBUG_CMD, &cpu_dev, "Exec %04d: %02d %-6s %04d %04d\r\n", IC, opcode, opname, DA, IA); + + if ((opcode == OP_NOOP) && (IC == 0) && (IA == 0)) { + // if loop on NOOP on addr zero -> machine idle -> stop cpu + reason = STOP_HALT; + goto end_of_while; + } + // check if opcode should wait for and already set interlock + if ((opcode == OP_RD) && (InterLockCount[IL_RD1])) { + WaitForInterlock = IL_RD1; + } else if ((opcode == OP_PCH) && (InterLockCount[IL_WR1])) { + WaitForInterlock = IL_WR1; + } else { + WaitForInterlock = 0; + } + + AR = DA; + CpuStepsRemaining = 1; + MachineCycle = 2; + continue; + } + + + if (MachineCycle == 3) { + // fetch data from drum if needed + if (bReadData) { + r = ReadAddr(AR, &DIST, &DistNegativeZeroFlag); + sim_debug(DEBUG_DATA, &cpu_dev, "... Read %04d: %06d%04d%c\r\n", + AR, printfd); + if (r==0) { + reason = STOP_ADDR; + goto end_of_while; + } + } else { + if (0==IsDrumAddrOk(AR)) { // even if no data is fetched from drum, DA addr must be a valid one + sim_debug(DEBUG_DETAIL, &cpu_dev, "Invalid AR addr %d ERROR\r\n", AR); + reason = STOP_ADDR; + goto end_of_while; + } + } + bWriteDrum = 0; // set to 1 by opcode if it is necessary to write dist back to drum + bBranchTaken = 0; // flag if branch is taken + + switch(opcode) { + case OP_NOOP : // No operation + break; + case OP_STOP : // Stop if console switch is set to stop, otherwise continue as a NO-OP + if (CSWProgStop) { + reason = STOP_PROG; + goto end_of_while; + } + break; + // arithmetic + case OP_RAL: // Reset and Add into Lower + case OP_RSL: // Reset and Subtract into Lower + case OP_RAABL: // Reset and Add Absolute into Lower + case OP_RSABL: // Reset and Subtract Absolute into Lower + d = DIST; + if ((opcode == OP_RAABL) || (opcode == OP_RSABL)) d = AbsWord(d); + if ((opcode == OP_RSL) || (opcode == OP_RSABL)) d = -d; + OV = 0; AccNegativeZeroFlag = 0; + ACC[1] = 0; + ACC[0] = d; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + // sequence chart for Add/Substract + // (1) (0..49) (1) (0/1) (2) (0/2) (1) + // Enable Search Data to Wait Dist to Complement Remove A + // Dist Data dist for even Acc Neg Sum interlock + // (1) (1) (1) (0..49) + // Restart IA to AR Enable PR Search next + // Signal Inst + CpuStepsRemaining = 1+1+2+1; + if ((DrumAddr % 2) != 0) CpuStepsRemaining++; // using lower acc -> wait for even + // no need to complement neg sum + break; + case OP_AL: // Add to Lower + case OP_SL: // Subtract from Lower + case OP_AABL: // Add Absolute to lower + case OP_SABL: // Subtract Absolute from lower + if ((opcode == OP_AL) && (ACC[1] == 0) && (ACC[0] == 0) && (AccNegativeZeroFlag) && + (DIST == 0) && (DistNegativeZeroFlag)) { + // special case as stated in Operation manual 22(22-6060-2_650_OperMan.pdf), page 95 + // Acc result on minus zero if acc contains minus zero and AU or AL with a drum + // location that contains minus zero + OV=0; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: 0000000000 0000000000- (Minus Zero), OV: 0\r\n"); + // acc keeps the minus zero it already has + break; + } + d = DIST; + if ((opcode == OP_AABL) || (opcode == OP_SABL)) d = AbsWord(d); + if ((opcode == OP_SL) || (opcode == OP_SABL)) d = -d; + AddToAcc(0,d); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + CpuStepsRemaining = 1+1+2+1; + if ((DrumAddr % 2) != 0) CpuStepsRemaining++; // using lower acc -> wait for even + if (bAccNegComplement) CpuStepsRemaining += 2; // acc sign change -> need to complement neg sum + break; + case OP_RAU: // Reset and Add into Upper + case OP_RSU: // Reset and Subtract into Upper + case OP_AU: // Add to Upper + case OP_SU: // Substract from Upper + if ((opcode == OP_AU) && (ACC[1] == 0) && (ACC[0] == 0) && (AccNegativeZeroFlag) && + (DIST == 0) && (DistNegativeZeroFlag)) { + // special case as stated in Operation manual 22(22-6060-2_650_OperMan.pdf), page 95 + // Acc result on minus zero if acc contains minus zero and AU or AL with a drum + // location that contains minus zero + OV=0; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: 0000000000 0000000000- (Minus Zero), OV: 0\r\n"); + // acc keeps the minus zero it already has + break; + } + d = DIST; + if ((opcode == OP_RAU) || (opcode == OP_RSU)) ACC[1] = ACC[0] = 0; + if ((opcode == OP_SU) || (opcode == OP_RSU)) d = -d; + AddToAcc(d,0); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + CpuStepsRemaining = 1+1+2+1; + if ((DrumAddr % 2) == 0) CpuStepsRemaining++; // using upper acc -> wait for odd + if (bAccNegComplement) CpuStepsRemaining += 2; // acc sign change -> need to complement neg sum + break; + // Multiply/divide + case OP_MULT: // Multiply + if ((ACC[1] == 0) && (ACC[0] == 1) && (DIST == 0) && (DistNegativeZeroFlag)) { + // special case as stated in Operation manual 22(22-6060-2_650_OperMan.pdf), page 95 + // Acc result on minus zero if a drum location that contains minus zero + // is multiplied by +1 + OV = 0; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: 0000000000 0000000000- (Minus Zero), OV: 0\r\n"); + // acc set to minus zero + ACC[1] = ACC[0] = 0; + AccNegativeZeroFlag = 1; + break; + } + OV = 0; + sgn = (DIST < 0) ? -1:1; if (ACC[0] < 0) sgn = -sgn; + d = AbsWord(DIST); + ACC[0] = AbsWord(ACC[0]); + ACC[1] = AbsWord(ACC[1]); + for(i=0;i<10;i++) { + n = ShiftAcc(1); + while (n-- > 0) { + AddToAcc(0, d); + if (OV) {i=10; break;} + } + } + if (sgn < 0) { + ACC[0] = -ACC[0]; + ACC[1] = -ACC[1]; + } + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + // sequence chart for Multiply/Divide + // (1) (0..49) (1) (0/1) (20..200) (1) + // Enable Search Data to Wait Mult/Div Remove A + // Dist Data dist for even loop interlock + // (1) (1) (1) (0..49) + // Restart IA to AR Enable PR Search next + // Signal Inst + CpuStepsRemaining = 1+1+1+1; + if ((DrumAddr % 2) != 0) CpuStepsRemaining++; // wait for even + if (i < 0) i=0; if (i>9) i=9; // i holds the number of loops done + CpuStepsRemaining += 20*(i+1); + break; + case OP_DIV: // Divide + case OP_DIVRU: // Divide and reset upper accumulator + if (DIST == 0) { + OV = 1; + sim_debug(DEBUG_DETAIL, &cpu_dev, "Divide By Zero -> OV set \r\n"); + } else if (AbsWord(DIST) <= AbsWord(ACC[1])) { + OV = 1; + sim_debug(DEBUG_DETAIL, &cpu_dev, "Quotient Overflow -> OV set and ERROR\r\n"); + reason = STOP_OV; // quotient overfow allways stops the machine + } else { + OV = 0; + sgn = (DIST < 0) ? -1:1; if (ACC[0] < 0) sgn = -sgn; + d = AbsWord(DIST); + ACC[0] = AbsWord(ACC[0]); + ACC[1] = AbsWord(ACC[1]); + for(i=0;i<10;i++) { + ShiftAcc(1); + while (d <= ACC[1]) { + AddToAcc(-d, 0); + ACC[0]++; + } + } + if (sgn < 0) { + ACC[0] = -ACC[0]; + ACC[1] = -ACC[1]; + } + if (opcode == OP_DIVRU) { + ACC[1] = 0; + } + CpuStepsRemaining = 1+1+1+1; + if ((DrumAddr % 2) != 0) CpuStepsRemaining++; // wait for even + // i holds the number of loops done + if (i < 0) i=0; if (i>9) i=9; + CpuStepsRemaining += 20*(i+1) + 40; + } + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + break; + // shift + case OP_SLT: // Shift Left + case OP_SRT: // Shift Right + case OP_SRD: // Shift Right and Round + n = AR % 10; // number of digits to shift + d = 0; + while (n-- > 0) { + d = ShiftAcc((opcode == OP_SLT) ? 1:-1); + } + if (opcode == OP_SRD) { + if (d <= - 5) AddToAcc(0,-1); + if (d >= 5) AddToAcc(0,+1); + OV = 0; + } + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + // sequence chart for shift + // (1) (0/1) (2) (1) + // Enable Wait Per Remove A + // Sh count for even shift interlock + // (0/1) (1) (1) (0..49) + // Restart IA to AR Enable PR Search next + // Signal Inst + CpuStepsRemaining = 1+1+1; + if ((DrumAddr % 2) != 0) CpuStepsRemaining++; // wait for even + n = AR % 10; // number of shifts done + if (n > 0) CpuStepsRemaining += 2*n; + if (opcode == OP_SRD) CpuStepsRemaining++; + break; + case OP_SCT : // Shift accumulator left and count + n = 10 - AR % 10; // shift count (nine's complement of unit digit of DA) + if (n==10) n=0; + if (ACC[1] == 0) { + // upper acc is zero -> will have 10 or more shifts + ACC[1] = ACC[0]; + ACC[0] = 10; + if (n) { + OV = 1; // overflow because n <> 0 + } else { + if (Get_HiDigit(ACC[1]) == 0) OV = 1; // overflow because not just 10 shifts + } + } else if (Get_HiDigit(ACC[1]) != 0) { + // no shift will be done + ACC[0] = SetIA2(ACC[0], 0); // replace last two digits by 00 + } else { + while (Get_HiDigit(ACC[1]) == 0) { + ShiftAcc(1); // shift left + if (n==10) { + OV = 1; + break; + } + n++; + } + ACC[0] = SetIA2(ACC[0], n); // replace last two digits by 00 + } + AccNegativeZeroFlag = 0; + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + CpuStepsRemaining = 1+1+1; + if ((DrumAddr % 2) != 0) CpuStepsRemaining++; // wait for even + n = AR % 10; // number of shifts done + if (n > 0) CpuStepsRemaining += 2*n; + if (opcode == OP_SRD) CpuStepsRemaining++; + break; + // load and store + case OP_STL: // Store Lower in Mem + case OP_STU: // Store Upper in Mem + if ((ACC[0] == 0) && (ACC[0] == 0) && (AccNegativeZeroFlag)) { + DistNegativeZeroFlag = 1; + } else { + DistNegativeZeroFlag = 0; + } + DIST = (opcode == OP_STU) ? ACC[1] : ACC[0]; + // sequence chart for store + // (1) (0/1) (1) (0..49) (1) (1) (1) + // Enable Wait L/U acc Search Store IA to AR Enable PR + // Dist for even to dist data data + // or odd + CpuStepsRemaining = 1+1+1+1+1; + if ((DrumAddr % 2) == ( (opcode == OP_STU) ? 0:1)) CpuStepsRemaining++; // wait for odd/even + bWriteDrum = 1; // to write DIST in drum at AR + break; + case OP_STD: // store distributor + CpuStepsRemaining = 1+1+1+1; + bWriteDrum = 1; // to write DIST in drum at AR + break; + case OP_STDA: // Store Lower Data Address + n = ((ACC[0] / D4) % D4); // get data addr xxDDDDxxxx from lower Acc + d = SetDA(DIST, n); // replace it in distributor + if ((d == 0) && ((DIST < 0) || ( (DIST == 0) && (DistNegativeZeroFlag) ))) { + // if dist results in zero but was negative or negative zero before replacing digits + // then it is set to minus zero + DistNegativeZeroFlag = 1; + } else { + DistNegativeZeroFlag = 0; + } + DIST = d; + CpuStepsRemaining = 1+1+1+1; + if ((DrumAddr % 2) == 0) CpuStepsRemaining++; // wait for even + bWriteDrum = 1; // to write DIST in drum at AR + break; + case OP_STIA: // Store Lower Instruction Address + n = (ACC[0] % D4); // get inst addr xxyyyyAAAA + d = SetIA(DIST, n); // replace it in distributor + if ((d == 0) && ((DIST < 0) || ( (DIST == 0) && (DistNegativeZeroFlag) ))) { + // if dist results in zero but was negative or negative zero before replacing digits + // then it is set to minus zero + DistNegativeZeroFlag = 1; + } else { + DistNegativeZeroFlag = 0; + } + DIST = d; + CpuStepsRemaining = 1+1+1+1; + if ((DrumAddr % 2) == 0) CpuStepsRemaining++; // wait for even + bWriteDrum = 1; // to write DIST in drum at AR + break; + case OP_LD: // Load Distributor + CpuStepsRemaining = 1+1+1+1; + break; + case OP_TLU : // Table lookup + sim_debug(DEBUG_DATA, &cpu_dev, "... Search DIST: %06d%04d%c\r\n", + printfd); + AR = (DA / 50) * 50; // set AR to start of band based on DA + AR--; n=-1; + while (1) { + int dNegZero; + AR++; n++; + if (0==IsDrumAddrOk(AR)) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "Invalid AR addr %d ERROR\r\n", AR); + reason = STOP_ADDR; + goto end_of_while; + } + if ((AR % 50) > 47) continue; // skip addr 48 & 49 of band that cannot be used for tables + if (0==ReadAddr(AR, &d, &dNegZero)) { // read table argument + reason = STOP_ADDR; + goto end_of_while; + } + if (AbsWord(d) >= AbsWord(DIST)) break; // found + } + // set the result as xxNNNNxxxx in lower acc + ACC[0] = SetDA(ACC[0], DA+n); + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + CpuStepsRemaining = 1+1+1+1+1+1; + if ((DrumAddr % 2) == 0) CpuStepsRemaining++; // wait for even + CpuStepsRemaining += n; // number of reads to find the argument searched for + break; + // branch + case OP_BRD1: case OP_BRD2: case OP_BRD3: case OP_BRD4: case OP_BRD5: // Branch on 8 in distributor positions 1-10 + case OP_BRD6: case OP_BRD7: case OP_BRD8: case OP_BRD9: case OP_BRD10: + sim_debug(DEBUG_DATA, &cpu_dev, "... Check DIST: %06d%04d%c\r\n", + printfd); + d = DIST; + n = opcode - OP_BRD10; if (n == 0) n = 10; + while (--n > 0) d = d / 10; + d = d % 10; + if (d == 8) { + IA = AR; // IA (next instr addr) will be taken from AR. Branch taken + sim_debug(DEBUG_DETAIL, &cpu_dev, "Digit is %d -> Branch Taken\r\n", (int32) d); + bBranchTaken = 1; + } else if (d == 9) { + // IA kept as already set. Branch not taken + sim_debug(DEBUG_DETAIL, &cpu_dev, "Digit is %d -> Branch Not Taken\r\n", (int32) d); + } else { + // any other value for tested digit -> stop + sim_debug(DEBUG_DETAIL, &cpu_dev, "Digit is %d -> Branch ERROR\r\n", (int32) d); + reason = STOP_ERRO; + } + CpuStepsRemaining = 1+1; + if (bBranchTaken) CpuStepsRemaining++; + break; + case OP_BRNZU: // Branch on Non-Zero in Upper + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + if (ACC[1] != 0) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "Upper ACC not Zero -> Branch Taken\r\n"); + IA = AR; + bBranchTaken = 1; + } + CpuStepsRemaining = 1; + if (bBranchTaken) CpuStepsRemaining++; + if ((DrumAddr % 2) == 0) CpuStepsRemaining++; // wait for even + break; + case OP_BRNZ: // Branch on Non-Zero + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + if ((ACC[1] != 0) || (ACC[0] != 0)) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "ACC not Zero -> Branch Taken\r\n"); + IA = AR; + bBranchTaken = 1; + } + CpuStepsRemaining = 1; + if (bBranchTaken) CpuStepsRemaining++; + if ((DrumAddr % 2) != 0) CpuStepsRemaining++; // wait for odd + break; + case OP_BRMIN: // Branch on Minus + sim_debug(DEBUG_DETAIL, &cpu_dev, "... ACC: %06d%04d %06d%04d%c, OV: %d\r\n", + printfa, + OV); + if (AccNegative) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "ACC is Negative -> Branch Taken\r\n"); + IA = AR; + bBranchTaken = 1; + } + CpuStepsRemaining = 1; + if (bBranchTaken) CpuStepsRemaining++; + break; + case OP_BROV: // Branch on Overflow + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Check OV: %d\r\n", OV); + if (OV) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "OV Set -> Branch Taken\r\n"); + IA = AR; + bBranchTaken = 1; + } + CpuStepsRemaining = 1; + if (bBranchTaken) CpuStepsRemaining++; + break; + // Card I/O + case OP_RD : // Read a card + AR = (DA / 50) * 50 + 1; // Read Band is XX01 to XX10 or XX51 to XX60 + { + uint32 r; + int i; + char s[6]; + + r = cdr_cmd(&cdr_unit[1], IO_RDS,AR); + if (r == SCPE_NOCARDS) { + //XXX SCPE_BUSY + reason = STOP_CARD; + goto end_of_while; + } + for (i=0;i<10;i++) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Read Card %04d: %06d%04d%c '%s'\r\n", + AR+i, printfw(DRUM[AR+i],DRUM_NegativeZeroFlag[AR+i]), + word_to_ascii(s, 1, 5, DRUM[AR+i])); + } + if (cdr_unit[1].u5 & URCSTA_LOAD) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Is a LOAD Card\r\n"); + IA = DA; // load card -> next inste is taken from DA + } + } + // 300 msec read cycle, 270 available for computing + CpuStepsRemaining = 312; // 30 msec / 0.096 msec word time; + // set interlock + InterLockCount[IL_RD1] = 3120; // 300 msec for read card processing + break; + case OP_PCH : // Punch a card + AR = (DA / 50) * 50 + 27; // Read Band is XX27 to XX36 or XX77 to XX86 + { + uint32 r; + int i; + char s[6]; + + for (i=0;i<10;i++) { + sim_debug(DEBUG_DETAIL, &cpu_dev, "... Punch Card %04d: %06d%04d%c '%s'\r\n", + AR+i, printfw(DRUM[AR+i],DRUM_NegativeZeroFlag[AR+i]), + word_to_ascii(s, 1, 5, DRUM[AR+i])); + } + r = cdp_cmd(&cdp_unit[1], IO_WRS,AR); + if (r == SCPE_NOCARDS) { + //XXX SCPE_BUSY + reason = STOP_CARD; + goto end_of_while; + } + } + // 600 msec punch cycle, 565 available for computing + CpuStepsRemaining = 365; // 35 msec / 0.096 msec word time; + // set interlock + InterLockCount[IL_WR1] = 6250; // 600 msec for punch card processing + break; + default: + reason = STOP_UUO; + break; + } + if (reason) goto end_of_while; + if ((OV) && (CSWOverflowStop)) { + reason = STOP_OV; + goto end_of_while; + } + MachineCycle = 4; + if (CpuStepsRemaining > 2) CpuStepsRemaining -= 2; // decrease by 2 as each inst passes at minimum two times by DrumAddr++ + continue; + } /* end of opcode switch */ + + if (MachineCycle == 5) { + if (bWriteDrum) { + sim_debug(DEBUG_DATA, &cpu_dev, "... Write %04d: %06d%04d%c\r\n", + AR, printfd); + if (0==WriteDrum(AR, DIST, DistNegativeZeroFlag)) { + reason = STOP_ADDR; + goto end_of_while; + } + } + MachineCycle = 6; + continue; + } +end_of_while: + // set AR to point to next instr + AR = IA; + + if (instr_count != 0 && --instr_count == 0) { + if (reason == 0) { + IC = AR; + // if cpu not stoped (just stepped) set IC so next inst to be executed is shown. + // if cpu stopped because some error (reason != 0), does not advance IC so instr shown is offending one + reason = SCPE_STEP; + } + return reason; + } + MachineCycle = 0; // ready to process to next instr + + } /* end while */ + + // flush 407 printout + if ((cdp_unit[0].flags & UNIT_ATT) && (cdp_unit[0].fileref)) { + fflush(cdp_unit[0].fileref); + } + + /* Simulation halted */ + + return reason; +} + + +/* Initialize memory to all plus zero */ +void +mem_init() { + int i; + for(i = 0; i < MAXMEMSIZE; i++) + DRUM[i] = DRUM_NegativeZeroFlag[i] = 0; +} + + +/* Reset routine */ +t_stat +cpu_reset(DEVICE * dptr) +{ + + ACC[0] = ACC[1] = DIST = 0; + PR = AR = OV = 0; + AccNegativeZeroFlag = 0; + DistNegativeZeroFlag = 0; + IC = 0; + + sim_brk_types = sim_brk_dflt = SWMASK('E'); + return SCPE_OK; +} + +/* Memory examine */ + +t_stat +cpu_ex(t_value * vptr, t_addr addr, UNIT * uptr, int32 sw) +{ + t_int64 d; + int NegZero; + t_value val; + + if (0==ReadAddr(addr, &d, &NegZero)) { + return SCPE_NXM; + } + if (vptr != NULL) { + if (NegZero) { + val = NEGZERO_value; // val has this special value to represent -0 (minus zero == negative zero) + } else { + val = (t_value) d; + } + *vptr = val; + } + + return SCPE_OK; +} + +/* Memory deposit */ + +t_stat +cpu_dep(t_value val, t_addr addr, UNIT * uptr, int32 sw) +{ + t_int64 d; + if (addr >= MEMSIZE) + return SCPE_NXM; + d = val; + if (val == NEGZERO_value) { + DRUM[addr] = 0; // Minus Zero is coded as val = NEGZERO_value constant + DRUM_NegativeZeroFlag[addr] = 1; + } else { + DRUM[addr] = d; + DRUM_NegativeZeroFlag[addr] = 0; + } + return SCPE_OK; +} + +t_stat +cpu_set_size(UNIT * uptr, int32 val, CONST char *cptr, void *desc) +{ + int mc = 0; + uint32 i; + int32 v; + + v = val >> UNIT_V_MSIZE; + if (v == 0) {v = 1000;} else + if (v == 1) {v = 2000;} else + if (v == 2) {v = 4000;} else v = 0; + if ((v <= 0) || (v > MAXMEMSIZE)) + return SCPE_ARG; + for (i = v-1; i < MEMSIZE; i++) { + if (DRUM[i] != 0) { + mc = 1; + break; + } + } + if ((mc != 0) && (!get_yn("Really truncate memory [N]?", FALSE))) + return SCPE_OK; + cpu_unit.flags &= ~UNIT_MSIZE; + cpu_unit.flags |= val; + MEMSIZE = v; + for (i = MEMSIZE; i < MAXMEMSIZE; i++) + DRUM[i] = DRUM_NegativeZeroFlag[i] = 0; + return SCPE_OK; +} + + +t_stat +cpu_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) { + fprintf (st, "These switches are recognized when examining or depositing in CPU memory:\r\n\r\n"); + fprintf (st, " -c examine/deposit characters, 5 per word\r\n"); + fprintf (st, " -m examine/deposit IBM 650 instructions\r\n\r\n"); + fprintf (st, "The memory of the CPU can be set to 1000, 2000 or 4000 words.\r\n\r\n"); + fprintf (st, " sim> SET CPU nK\r\n\r\n"); + fprint_set_help(st, dptr); + fprint_show_help(st, dptr); + return SCPE_OK; +} + +const char * cpu_description (DEVICE *dptr) { + return "IBM 650 CPU"; +} + diff --git a/I650/i650_defs.h b/I650/i650_defs.h new file mode 100644 index 00000000..dc336331 --- /dev/null +++ b/I650/i650_defs.h @@ -0,0 +1,247 @@ +/* i650_defs.h: IBM 650 simulator definitions + + Copyright (c) 2018, Roberto Sancho + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + ROBERTO SANCHO BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ + +#include "sim_defs.h" /* simulator defns */ + +/* Simulator stop codes */ + +#define STOP_HALT 1 /* HALT */ +#define STOP_IBKPT 2 /* breakpoint */ +#define STOP_UUO 3 /* invalid opcode */ +#define STOP_CARD 4 /* Stop on card reader/punch error (no card in hopper, read/punch failure, no cards, stop pressed on cdr/cdp*/ +#define STOP_PROG 5 /* Programmed stop */ +#define STOP_OV 6 /* Overflow stop */ +#define STOP_ERRO 7 /* Error in opcode execution: BRD in witch position tested not 8 or 9, TLU failure */ +#define STOP_ADDR 8 /* Address stop: Store attempt on addr 800X, address out of drum mem */ + + +/* Memory */ +#define MAXMEMSIZE (4000) +#define MEMSIZE cpu_unit.capac /* actual memory size */ +#define MEMMASK (MEMSIZE - 1) /* Memory bits */ + +#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) +extern t_int64 DRUM[MAXMEMSIZE]; +extern int DRUM_NegativeZeroFlag[MAXMEMSIZE]; + +extern int WriteDrum(int AR, t_int64 d, int NegZero); +extern int ReadDrum(int AR, t_int64 * d, int * NegZero); + +/* digits contants */ +#define D10 (10000000000LL) // ten digits (10 zeroes) +#define D8 (100000000L) // eight digits (8 zeroes) +#define D4 (10000L) // four digits (4 zeroes) + + +/* Device information block */ +struct dib { + uint8 upc; /* Units per channel */ + uint32 (*cmd)(UNIT *up, uint16 cmd, uint16 dev);/* Issue command. */ + void (*ini)(UNIT *up, t_bool f); +}; + +typedef struct dib DIB; + +/* Debuging controls */ +#define DEBUG_CMD 0x0000010 /* Show device commands */ +#define DEBUG_DETAIL 0x0000020 /* Show details */ +#define DEBUG_EXP 0x0000040 /* Show error conditions */ +#define DEBUG_DATA 0x0000080 /* Show data details */ + +extern DEBTAB dev_debug[]; +extern DEBTAB crd_debug[]; + +/* Returns from read/write */ +#define DATA_OK 0 /* Data transfered ok */ +#define TIME_ERROR 1 /* Channel did not transfer last operation */ +#define END_RECORD 2 /* End of record */ + +/* Returns from device commands */ +#define SCPE_BUSY (1) /* Device is active */ +#define SCPE_NOCARDS (2) /* No cards to read or ti write */ + +/* Global device definitions */ +#ifdef CPANEL +extern DEVICE cp_dev; +#endif + +extern DIB cdr_dib; +extern DEVICE cdr_dev; +extern uint32 cdr_cmd(UNIT *, uint16, uint16); +extern UNIT cdr_unit[]; + +extern DIB cdp_dib; +extern DEVICE cdp_dev; +extern uint32 cdp_cmd(UNIT *, uint16, uint16); +extern UNIT cdp_unit[]; + +/* Device status information stored in u5 */ +#define URCSTA_ERR 0002 /* Error reading record */ +#define URCSTA_BUSY 0010 /* Device is busy */ +#define URCSTA_LOAD 01000 /* Load flag for 533 card reader */ + + +/* Character codes in IBM 650 as stated in p4 Andree Programming the IBM 650 Mag Drum + Also stated in www.bitsavers.org/pdf/ibm/650/28-4028_FOR_TRANSIT.pdf p37 +*/ +#define CHR_BLANK 00 +#define CHR_DOT 18 // card code: 12-3-8 . +#define CHR_RPARENT 19 // 12-4-8 ) +#define CHR_AMPERSAND 20 // 12 + +#define CHR_DOLLAR 28 // 11-3-8 $ +#define CHR_STAR 29 // 11-4-8 * +#define CHR_NEG 30 // 11 - minus sign for negative value +#define CHR_SLASH 31 // 0-1 / +#define CHR_COMMA 38 // 0-3-8 , +#define CHR_LPARENT 39 // 0-4-8 ( +#define CHR_EQUAL 48 // 3-8 = +#define CHR_MINUS 49 // 4-8 - +#define CHR_A 61 +#define CHR_B 62 +#define CHR_C 63 +#define CHR_D 64 +#define CHR_E 65 +#define CHR_F 66 +#define CHR_G 67 +#define CHR_H 68 +#define CHR_I 69 +#define CHR_J 71 +#define CHR_K 72 +#define CHR_L 73 +#define CHR_M 74 +#define CHR_N 75 +#define CHR_O 76 +#define CHR_P 77 +#define CHR_Q 78 +#define CHR_R 79 +#define CHR_S 82 +#define CHR_T 83 +#define CHR_U 84 +#define CHR_V 85 +#define CHR_W 86 +#define CHR_X 87 +#define CHR_Y 88 +#define CHR_Z 89 +#define CHR_0 90 +#define CHR_1 91 +#define CHR_2 92 +#define CHR_3 93 +#define CHR_4 94 +#define CHR_5 95 +#define CHR_6 96 +#define CHR_7 97 +#define CHR_8 98 +#define CHR_9 99 + +extern char digits_ascii[40]; +extern char mem_to_ascii[100]; +extern int ascii_to_NN(int ch); +extern uint16 ascii_to_hol[128]; + + +/* Generic devices common to all */ +extern DEVICE cpu_dev; +extern UNIT cpu_unit; +extern REG cpu_reg[]; +extern int cycle_time; + +/* I/O Command codes */ +#define IO_RDS 1 /* Read record */ +#define IO_WRS 4 /* Write one record */ + + +extern const char *cpu_description(DEVICE *dptr); + +/* Opcodes */ +#define OP_AABL 17 // Add absolute to lower accumulator +#define OP_AL 15 // Add to lower accumulator +#define OP_AU 10 // Add to upper accumulator +#define OP_BRNZ 45 // Branch on accumulator non-zero +#define OP_BRMIN 46 // Branch on minus accumulator +#define OP_BRNZU 44 // Branch on non-zero in upper accumulator +#define OP_BROV 47 // Branch on overflow +#define OP_BRD1 91 // Branch on 8 in distributor positions 1-10 +#define OP_BRD2 92 +#define OP_BRD3 93 +#define OP_BRD4 94 +#define OP_BRD5 95 +#define OP_BRD6 96 +#define OP_BRD7 97 +#define OP_BRD8 98 +#define OP_BRD9 99 +#define OP_BRD10 90 +#define OP_DIV 14 // Divide +#define OP_DIVRU 64 // Divide and reset upper accumulator +#define OP_LD 69 // Load distributor +#define OP_MULT 19 // Multiply +#define OP_NOOP 00 // No operation +#define OP_PCH 71 // Punch a card +#define OP_RD 70 // Read a card +#define OP_RAABL 67 // Reset accumulator and add absolute to lower accumulator +#define OP_RAL 65 // Reset accumulator and add to lower accumulator +#define OP_RAU 60 // Reset accumulator and add to upper accumulator +#define OP_RSABL 68 // Reset accumulator and subtract absolute from lower accumulator +#define OP_RSL 66 // Reset accumulator and subtract from lower accumulator +#define OP_RSU 61 // Reset accumulator and subtract from upper accumulator +#define OP_SLT 35 // Shift accumulator left +#define OP_SCT 36 // Shift accumulator left and count +#define OP_SRT 30 // Shift accumulator right +#define OP_SRD 31 // Shift accumulator right and round accumulator +#define OP_STOP 01 // Stop if console switch is set to stop, otherwise continue as a NO-OP +#define OP_STD 24 // Store distributor into memory +#define OP_STDA 22 // Store lower accumulator data address into distributor, then store distributor into memory +#define OP_STIA 23 // Store lower accumulator instruction address into distributor, then store distributor into memory +#define OP_STL 20 // Store lower accumulator into memory +#define OP_STU 21 // Store upper accumulator into memory +#define OP_SABL 18 // Subtract absolute from lower accumulator +#define OP_SL 16 // Subtract from lower accumulator +#define OP_SU 11 // Subtract from upper accumulator +#define OP_TLU 84 // Table lookup + +#define NEGZERO_value 0x7fffFFFFffffFFFF +#define AccNegative (((AccNegativeZeroFlag) || (ACC[1]<0) || (ACC[0]<0)) ? 1:0) +#define AbsWord(d) ((d < 0) ? -d:d) +#define printfw(d,negzero) (int32) AbsWord(d/D4), (int32) AbsWord(d%D4), ((d<0) || (negzero)) ? '-':'+' +#define printfd printfw(DIST, DistNegativeZeroFlag) +#define printfa (int32) AbsWord(ACC[1]/D4),(int32) AbsWord(ACC[1]%D4), printfw(AbsWord(ACC[0]), AccNegative) + +/* Standard control panel wiring for card read/punch/print */ + +#define UNIT_CARD_WIRING ( 0xF00 << UNIT_V_CARD_MODE) +#define WIRING_8WORD ( 0x000 << UNIT_V_CARD_MODE) +#define WIRING_SOAP ( 0x100 << UNIT_V_CARD_MODE) +#define WIRING_IS ( 0x200 << UNIT_V_CARD_MODE) +#define UNIT_CARD_ECHO ( 0x1000 << UNIT_V_CARD_MODE) +#define UNIT_CARD_PRINT ( 0x2000 << UNIT_V_CARD_MODE) + +struct card_wirings { + uint32 mode; + const char *name; +}; + +/* Decimal helper functions */ +extern int Get_HiDigit(t_int64 d); +extern int Shift_Digits(t_int64 * d, int nDigits); +extern char * word_to_ascii(char * buf, int CharStart, int CharLen, t_int64 d); + + diff --git a/I650/i650_sys.c b/I650/i650_sys.c new file mode 100644 index 00000000..012edd1c --- /dev/null +++ b/I650/i650_sys.c @@ -0,0 +1,518 @@ +/* i650_sys.c: IBM 650 Simulator system interface. + + Copyright (c) 2018, Roberto Sancho + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + ROBERTO SANCHO BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +*/ + +#include "i650_defs.h" +#include "sim_card.h" +#include + +/* SCP data structures and interface routines + + sim_name simulator name string + sim_PC pointer to saved PC register descriptor + sim_emax number of words for examine + sim_devices array of pointers to simulated devices + sim_stop_messages array of pointers to stop messages + sim_load binary loader +*/ + +char sim_name[] = "IBM 650"; + +REG *sim_PC = &cpu_reg[0]; + +int32 sim_emax = 1; + +DEVICE *sim_devices[] = { + &cpu_dev, + &cdr_dev, + &cdp_dev, +//XXX &mta_dev, + NULL +}; + +/* Device addressing words */ + +DIB cdr_dib = { 1, &cdr_cmd, NULL }; +DIB cdp_dib = { 3, &cdp_cmd, NULL }; +//XXX DIB mt_dib = { CH_TYP_76XX, NUM_UNITS_MT, 0000, 0000, &mt_cmd, &mt_ini }; + +/* Simulator stop codes */ +const char *sim_stop_messages[] = { + "Unknown error", + "HALT instruction", + "Breakpoint", + "Unknown Opcode", + "Card Read/Punch Error", + "Programmed Stop", + "Overflow", + "Opcode Execution Error", + "Address Error", + 0 +}; + +/* Simulator debug controls */ +DEBTAB dev_debug[] = { + {"CMD", DEBUG_CMD}, + {"DATA", DEBUG_DATA}, + {"DETAIL", DEBUG_DETAIL}, + {"EXP", DEBUG_EXP}, + {0, 0} +}; + +DEBTAB crd_debug[] = { + {"CMD", DEBUG_CMD}, + {"DATA", DEBUG_DATA}, + {"DETAIL", DEBUG_DETAIL}, + {"EXP", DEBUG_EXP}, + {0, 0} +}; + +// code of char in IBM 650 memory +char mem_to_ascii[100] = { +/* 00 */ ' ', '~', '~', '~', '~', '~', '~', '~', '~', '~', +/* 10 */ '~', '~', '~', '~', '~', '~', '~', '~', '.', ')', +/* 20 */ '+', '~', '~', '~', '~', '~', '~', '~', '$', '*', +/* 30 */ '-', '/', '~', '~', '~', '~', '~', '~', ',', '(', +/* 40 */ '~', '~', '~', '~', '~', '~', '~', '~', '=', '-', +/* 50 */ '~', '~', '~', '~', '~', '~', '~', '~', '~', '~', +/* 60 */ '~', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', +/* 70 */ '~', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', +/* 80 */ '~', '~', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', +/* 90 */ '0', '1', '2', '3', '4', '5', '6', '7', '8', '9' +}; + +// representation of word digit 0-9 in card including Y(12) and X(11) punchs +char digits_ascii[40] = { + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', /* 0-9 */ + '?', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', /* 0-9 w/HiPunch Y(12) */ + '!', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', /* 0-9 w/Negative Punch X(11) */ + '&', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z', '#' /* 0-9 with botch Negative Punch X(11) and HiPunch Y(12)*/ +}; + +uint16 ascii_to_hol[128] = { + /* Control */ + 0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000, /*0-37*/ + /*Control*/ + 0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000, + /*Control*/ + 0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000, + /*Control*/ + 0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000,0xf000, + /* sp ! " # $ % & ' */ + /* none Y28 78 T28 Y38 T48 XT 48 */ + 0x000, 0x600, 0x006, 0x282, 0x442, 0x222, 0xA00, 0x022, /* 40 - 77 */ + /* ( ) * + , - . / */ + /* T48 X48 Y48 X T38 T X38 T1 */ + 0x222, 0x822, 0x422, 0x800, 0x242, 0x400, 0x842, 0x300, + /* 0 1 2 3 4 5 6 7 */ + /* T 1 2 3 4 5 6 7 */ + 0x200, 0x100, 0x080, 0x040, 0x020, 0x010, 0x008, 0x004, + /* 8 9 : ; < = > ? */ + /* 8 9 58 Y68 X68 38 68 X28 */ + 0x002, 0x001, 0x012, 0x40A, 0x80A, 0x042, 0x00A, 0x882, + /* @ A B C D E F G */ + /* 82 X1 X2 X3 X4 X5 X6 X7 */ + 0x022, 0x900, 0x880, 0x840, 0x820, 0x810, 0x808, 0x804, /* 100 - 137 */ + /* H I J K L M N O */ + /* X8 X9 Y1 Y2 Y3 Y4 Y5 Y6 */ + 0x802, 0x801, 0x500, 0x480, 0x440, 0x420, 0x410, 0x408, + /* P Q R S T U V W */ + /* Y7 Y8 Y9 T2 T3 T4 T5 T6 */ + 0x404, 0x402, 0x401, 0x280, 0x240, 0x220, 0x210, 0x208, + /* X Y Z [ \ ] ^ _ */ + /* T7 T8 T9 X58 X68 T58 T78 28 */ + 0x204, 0x202, 0x201, 0x812, 0x20A, 0x412, 0x406, 0x082, + /* ` a b c d e f g */ + 0x212, 0xB00, 0xA80, 0xA40, 0xA20, 0xA10, 0xA08, 0xA04, /* 140 - 177 */ + /* h i j k l m n o */ + 0xA02, 0xA01, 0xD00, 0xC80, 0xC40, 0xC20, 0xC10, 0xC08, + /* p q r s t u v w */ + 0xC04, 0xC02, 0xC01, 0x680, 0x640, 0x620, 0x610, 0x608, + /* x y z { | } ~ del */ + /* Y78 X78 78 79 */ + 0x604, 0x602, 0x601, 0x406, 0x806,0x0006,0x0005,0xf000 +}; + + + +/* Load a card image file into memory. */ + +t_stat +sim_load(FILE * fileref, CONST char *cptr, CONST char *fnam, int flag) +{ + /* Currently not implimented until I know format of load files */ + return SCPE_NOFNC; +} + +/* Symbol tables */ +typedef struct _opcode +{ + uint16 opbase; + const char *name; + uint8 bReadData; // =1 if inst fetchs data from memory +} +t_opcode; + +/* Opcodes */ +t_opcode base_ops[] = { + {OP_AABL, "AABL", 1}, + {OP_AL, "AL", 1}, + {OP_AU, "AU", 1}, + {OP_BRNZ, "BRNZ", 0}, + {OP_BRMIN, "BRMIN", 0}, + {OP_BRNZU, "BRNZU", 0}, + {OP_BROV, "BROV", 0}, + {OP_BRD1, "BRD1", 0}, + {OP_BRD2, "BRD2", 0}, + {OP_BRD3, "BRD3", 0}, + {OP_BRD4, "BRD4", 0}, + {OP_BRD5, "BRD5", 0}, + {OP_BRD6, "BRD6", 0}, + {OP_BRD7, "BRD7", 0}, + {OP_BRD8, "BRD8", 0}, + {OP_BRD9, "BRD9", 0}, + {OP_BRD10, "BRD10", 0}, + {OP_DIV, "DIV", 1}, + {OP_DIVRU, "DIVRU", 1}, + {OP_LD, "LD", 1}, + {OP_MULT, "MULT", 1}, + {OP_NOOP, "NOOP", 0}, + {OP_PCH, "PCH", 0}, + {OP_RD, "RD", 0}, + {OP_RAABL, "RAABL", 1}, + {OP_RAL, "RAL", 1}, + {OP_RAU, "RAU", 1}, + {OP_RSABL, "RSABL", 1}, + {OP_RSL, "RSL", 1}, + {OP_RSU, "RSU", 1}, + {OP_SLT, "SLT", 0}, + {OP_SCT, "SCT", 0}, + {OP_SRT, "SRT", 0}, + {OP_SRD, "SRD", 0}, + {OP_STOP, "STOP", 0}, + {OP_STD, "STD", 0}, + {OP_STDA, "STDA", 0}, + {OP_STIA, "STIA", 0}, + {OP_STL, "STL", 0}, + {OP_STU, "STU", 0}, + {OP_SABL, "SABL", 1}, + {OP_SL, "SL", 1}, + {OP_SU, "SU", 1}, + {OP_TLU, "TLU", 0}, + {0, NULL, 0} +}; + +/* Print out an instruction */ +void +print_opcode(FILE * of, t_int64 val, t_opcode * tab) +{ + + int sgn; + int IA; + int DA; + int op; + int n; + + if (val < 0) {sgn = -1; val = -val;} else sgn = 1; + op = Shift_Digits(&val, 2); // opcode + DA = Shift_Digits(&val, 4); // data address + IA = Shift_Digits(&val, 4); // intruction address + + while (tab->name != NULL) { + if (tab->opbase == op) { + fputs(tab->name, of); + n = strlen(tab->name); + while (n++<6) fputc(' ', of); + fprintf(of, "%04d ", DA); + fputc(' ', of); + fprintf(of, "%04d ", IA); + return; + } + tab++; + } + fprintf(of, " %d Unknown opcode", op); +} + +/* Symbolic decode + + Inputs: + *of = output stream + addr = current PC + *val = pointer to values + *uptr = pointer to unit + sw = switches + Outputs: + return = status code +*/ + +t_stat +fprint_sym(FILE * of, t_addr addr, t_value * val, UNIT * uptr, int32 sw) +{ + t_int64 inst; + int NegZero; + int ch; + + if (*val == NEGZERO_value) { + inst = 0; + NegZero = 1; + } else { + inst = *val; + NegZero = 0; + } + + /* Print value in decimal */ + fputc(' ', of); + fprintf(of, "%06d%04d%c", printfw(inst,NegZero)); // fprintf 10 digits word n, with sign + inst = AbsWord(inst); + + if (sw & SWMASK('C') ) { + int i; + + fputs(" '", of); + for (i=0;i<5;i++) { + ch = Shift_Digits(&inst, 2); + fputc(mem_to_ascii[ch], of); + } + fputc('\'', of); + } + + if (sw & SWMASK('M')) { + fputs(" ", of); + inst = AbsWord(inst); + print_opcode(of, inst, base_ops); + } + return SCPE_OK; +} + +t_opcode * +find_opcode(char *op, t_opcode * tab) +{ + while (tab->name != NULL) { + if (*tab->name != '\0' && strcmp(op, tab->name) == 0) + return tab; + tab++; + } + return NULL; +} + +/* read n digits, optionally with sign NNNN[+|-] + + Inputs: + *cptr = pointer to input string + sgnFlag = 1 to allow signed value + Outputs: + d = parsed value +*/ + +CONST char * parse_sgn(int *neg, CONST char *cptr) +{ + *neg=0; + while (isspace(*cptr)) cptr++; + if (*cptr == '+') { + cptr++; + } else if (*cptr == '-') { + cptr++; *neg = 1; + } + return cptr; +} + +CONST char * parse_n(t_int64 *d, CONST char *cptr, int n) +{ + int i = 0; + + *d = 0; + while (1) { + if ((n == 10) && (isspace(*cptr))) { + cptr++; // on 10 digit words, allow spaces + continue; + } + if (*cptr < '0' || *cptr > '9') break; + if (i++ > n) { + cptr++; + } else { + *d = (*d * 10) + (*cptr++ - '0'); + } + } + if (n == 4) {*d = *d % D4; } else + if (n == 10) {*d = *d % D10;} + return cptr; +} + + +/* Symbolic input + + Inputs: + *cptr = pointer to input string + addr = current PC + uptr = pointer to unit + *val = pointer to output values + sw = switches + Outputs: + status = error status +*/ + +// convert ascii char to two digits IBM 650 code +int ascii_to_NN(int ch) +{ + int i; + + if ((ch >= 'a') && (ch <= 'z')) ch = ch -'a'+'A'; + for (i=0;i<100;i++) if (mem_to_ascii[i] == ch) return i; + return 0; +} + +t_stat parse_sym(CONST char *cptr, t_addr addr, UNIT * uptr, t_value * val, int32 sw) +{ + t_int64 d; + int da, ia; + char ch, opcode[100]; + t_opcode *op; + int i; + int neg, IsNeg; + + while (isspace(*cptr)) cptr++; + d = 0; IsNeg = 0; + if (sw & SWMASK('M')) { + /* Grab opcode */ + cptr = parse_sgn(&neg, cptr); + if (neg) IsNeg = 1; + + cptr = get_glyph(cptr, opcode, 0); + + op = find_opcode(opcode, base_ops); + if (op == 0) return STOP_UUO; + + while (isspace(*cptr)) cptr++; + /* Collect first argument: da */ + cptr = parse_n(&d, cptr, 4); + da = (int) d; + + /* Skip blanks */ + while (isspace(*cptr)) cptr++; + /* Collect second argument: ia */ + cptr = parse_n(&d, cptr, 4); + ia = (int) d; + // construct inst + d = op->opbase * (t_int64) D8 + da * (t_int64) D4 + (t_int64) ia; + } else if (sw & SWMASK('C')) { + d = 0; + for(i=0; i<5;i++) { + d = d * 100; + ch = *cptr; + if (ch == '\0') continue; + cptr++; + d = d + ascii_to_NN(ch); + } + } else { + cptr = parse_sgn(&neg, cptr); + if (neg) IsNeg = 1; + cptr = parse_n(&d, cptr, 10); + } + cptr = parse_sgn(&neg, cptr); + if (neg) IsNeg = 1; + if ((IsNeg) && (d == 0)) { + *val = NEGZERO_value; // val has this special value to represent -0 (minus zero == negative zero) + } else { + if (IsNeg) d=-d; + *val = (t_value) d; + } + return SCPE_OK; +} + +// get data for opcode +// return pointer to opcode name if opcode found, else NULL +const char * get_opcode_data(int opcode, int * bReadData) +{ + t_opcode * tab = base_ops; + + *bReadData = 0; + while (tab->name != NULL) { + if (tab->opbase == opcode) { + *bReadData = tab->bReadData; + return tab->name; + } + tab++; + } + return NULL; +} + + +/* Helper functions */ + +// set in buf string ascii chars form word d ( chars: c1c2c3c4c5 ) +// starts at char start (1..5), for CharLen chars (0..5) +// to convert the full word use (buf, 1, 5, d) +char * word_to_ascii(char * buf, int CharStart, int CharLen, t_int64 d) +{ + int i,c1,c2; + char * buf0; + + buf0 = buf; // save start of buffer + for (i=0;i<5;i++) { // 5 alpha chars per word + c1 = Shift_Digits(&d, 2); + c2 = mem_to_ascii[c1]; + if (i < CharStart-1) continue; + if (i >= CharStart+CharLen-1) continue; + *buf++ = c2; + } + *buf++ = 0; + return buf0; +} + + + +// return hi digit (digit 10) al leftmost position in number (no sign) +int Get_HiDigit(t_int64 d) +{ + return (int) ((AbsWord(d) * 10) / D10); +} + +// shift d value for nDigits positions (max 7) +// if nDigit > 0 shift left, if < 0 then shift right +// return value of shifted digits (without sign) +int Shift_Digits(t_int64 * d, int nDigits) +{ + int i,n; + int neg = 0; + + if (nDigits == 0) return 0; // no shift + + if (*d < 0) {*d=-*d; neg = 1;} + + n = 0; + if (nDigits > 0) { // shift left + for (i=0;i nul + +:add_extra_decks +if "%1" == "" goto run + +set env deck="void" +if -i "%1" == "TR" set env deck="is_trace_src.txt" +if -i "%1" == "LBOX" set env deck="is_set_loopbox.txt" +if %deck == "void" goto next_extra + +! copy deck_in.dck a.dck > nul +! copy a.dck + %deck deck_in.dck > nul +! del a.dck > nul + +:next_extra +shift +goto add_extra_decks +:run + +att cdr1 deck_in.dck +set cdr1 wiring=is + +; execute the loader to create Interpretive system deck + +echo *** +echo *** run system loader +echo *** + +d ar 0880 +go + +; generate a 1-word load card deck with whole interpretive system, ready to run + +echo *** +echo *** run is system generation to create +echo interpretive system (is) 1-word per card load deck +echo *** + +att cdp1 -n -q is.dck +set cdp1 echo, print, wiring=is + +d ar 0801 +go + +:end + diff --git a/I650/sw/Build_soap_from_source.ini b/I650/sw/Build_soap_from_source.ini new file mode 100644 index 00000000..24d409c9 --- /dev/null +++ b/I650/sw/Build_soap_from_source.ini @@ -0,0 +1,28 @@ + +; set console -n log=log.txt +; set debug -n debug.txt +; set debug stdout +; set cpu debug=cmd;data;detail + + +set cpu 2k + +set cdr1 wiring=soap + +; prepare deck: SOAP (condensed deck as 7 word per card format) then SOAP source code to assemblre + +! copy soapII_condensed_card.dck + soap_src.txt deck_in.dck > nul + +att cdr1 deck_in.dck +att cdp1 -n -q deck_out.dck +set cdp1 echo, print, wiring=soap +att cdp0 -n -q print.txt + +; load soap deck (condensed soap deck autostarts) +d csw 7019511951 +d ar 8000 +go + + +:end + diff --git a/I650/sw/is.dck b/I650/sw/is.dck new file mode 100644 index 00000000..9b4d3472 --- /dev/null +++ b/I650/sw/is.dck @@ -0,0 +1,1100 @@ +6I1954195C000000000A240900800?651653130H000000000?000000000?000000000?000000000? +6I1954195C000000000B240901800?010000090A000000000?000000000?000000000?000000000? +6I1954195C000000000C240902800?651958126C000000000?000000000?000000000?000000000? +6I1954195C000000000D240903800?300008122A000000000?000000000?000000000?000000000? +6I1954195C000000000E240904800?000000094C000000000?000000000?000000000?000000000? +6I1954195C000000000F240905800?651959131C000000000?000000000?000000000?000000000? +6I1954195C000000000G240906800?300008117E000000000?000000000?000000000?000000000? +6I1954195C000000000H240907800?000000095G000000000?000000000?000000000?000000000? +6I1954195C000000000I240908800?651951145E000000000?000000000?000000000?000000000? +6I1954195C000000001?240909800?000000101C000000000?000000000?000000000?000000000? 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+6I1954195C000000109A241990800?000000999I000000000?000000000?000000000?000000000? +6I1954195C000000109B241991800?601986197A000000000?000000000?000000000?000000000? +6I1954195C000000109C241992800?151024198G000000000?000000000?000000000?000000000? +6I1954195C000000109D241993800?151024198G000000000?000000000?000000000?000000000? +6I1954195C000000109E241994800?151024198G000000000?000000000?000000000?000000000? +6I1954195C000000109F241995800?151024198G000000000?000000000?000000000?000000000? +6I1954195C000000109G241996800?151024198G000000000?000000000?000000000?000000000? +6I1954195C000000109H241997800?711977194G000000000?000000000?000000000?000000000? +6I1954195C000000109I241998800?461966131E000000000?000000000?000000000?000000000? +6I1954195C000000110?241999800?461975196A000000000?000000000?000000000?000000000? diff --git a/I650/sw/is_example_1_src.txt b/I650/sw/is_example_1_src.txt new file mode 100644 index 00000000..49993d8d --- /dev/null +++ b/I650/sw/is_example_1_src.txt @@ -0,0 +1,68 @@ + + prime number generator using the sieve of eratosthenes + converted to ibm 650 floating poing interpretive system (is) + + uses two extra o2 codes: o2=800 (set lbox) and o2=453 (tr zero) + + warning: comments are allowed past column 28 but some characters + are forbidden: uppercase letters, question mark, exclamation, number char, + ampersand char. if these chars are used, the line (i.e. the card for this + line) will be interpreted as a load card, and program will crash on trying + to execute it. + + + 100 -9 000 201 400 initp -move i1 prime initp: prime[c]=1 + 101 +0 001 050 100 loop c 050 initp c++; if c<50 goto initp + + 102 +9 000 201 300 move i1 num num=1 + + 103 +1 300 201 300 loop1 add num i1 num loop1: num++ + + 104 +2 300 203 000 sub num i50 last + 105 +0 201 120 106 tr sgn loope cont if num >= 50 goto loope + + 106 +0 800 002 300 set lbox b num b=num + 107 -9 000 400 000 -move prime last last=prime[b] + 108 +0 453 103 110 tr zero loop1 cont if last = 0 goto loop1 + + 110 +9 000 300 301 move num mult mult=num + + 111 +1 300 301 301 loop2 add num mult mult loop2: mult=mult+num + + 112 +2 301 203 000 sub mult i50 last + 113 +0 201 103 114 tr sgn loop1 cont if mult >= 50 goto loop1 (go to b if +, go to c if -) + + 114 +0 800 003 301 set lbox c mult c=mult + 115 -9 000 200 400 -move zero prime prime[c]=0 + + 116 +0 203 000 111 tr loop2 goto loop2 + + 120 +9 000 201 300 loope move i1 num loope: num=1 + 121 +0 800 002 202 set lbox b i2 b=2 + + 122 +1 300 201 300 prt1 add num i1 num prt1: num++ + + 123 -9 000 400 000 -move prime last last=prime[b] + 124 +0 453 127 126 tr zero prt2 cont if last = 0 goto prt2 + + 126 +0 410 300 300 pch num num punch num + + 127 +0 010 050 122 prt2 loop b 050 prt1 prt2: b++; if b<50 goto prt1 + + 128 +0 000 000 000 unc stop end + + constants + + 200 +0 0000000 50 zero + 201 +1 0000000 50 i1 + 202 +2 0000000 50 i2 + 203 +5 0000000 51 i50 + + variables + + 300 +0 0000000 50 num current number to check for being prime + 301 +0 0000000 50 mult multiple + 400 +0 0000000 50 prime array of numbers 400-449 + + 100 program start address + diff --git a/I650/sw/is_main_src.txt b/I650/sw/is_main_src.txt new file mode 100644 index 00000000..f47e1736 --- /dev/null +++ b/I650/sw/is_main_src.txt @@ -0,0 +1,1145 @@ + + 1 1 1095 60 1098 1014 + 1 2 1014 10 1024 1729 increase i to i+1 + 1 3 1043 21 1098 8001 svpc stu pc save current it program counter (see cards 26 and 27 below) + 1 4 8001 60 1107 rau read inst at pc start dissection system instr. + 1 5 1107 46 1112 1061 brmin loopb go to loop box if instr < 0 shall the loop box be used + 1 6 1061 30 0003 1019 srt 0003 + 1 7 1019 20 1023 1026 stl c store c + 1 8 1026 60 8003 1033 rau + 1 9 1033 30 0003 1041 srt 0003 + 1 10 1041 20 1045 1048 stl b store b + 1 11 1048 60 8003 1105 rau + 1 12 1105 30 0003 1063 srt 0003 + 1 13 1063 44 1067 1076 brnzu is an o2 operation called for + 1 14 1067 10 1020 8003 + 1 15 8003 69 8002 1081 + + 1 16 1112 11 1017 1046 + 1 17 1046 61 8003 1061 + + 1 18 1076 60 8001 1034 + 1 19 1034 10 1037 8003 + 1 20 8003 65 1045 + + 1 21 1098 60 1107 + 1 22 1024 00 0001 + 1 23 1020 69 8002 1081 + 1 24 1037 65 1045 1000 + + 1 25 1017 00 + + 1 26 1729 69 1732 1735 ld svmlt restore the multiplication + 1 27 1735 24 1539 1043 std 1539 svpc continue routine (o1=3) to normal + + 1 28 1732 35 0002 1445 svmlt (the trig. program makes special use of it) + + + 2 1 1000 30 0003 1119 + 2 2 1119 15 1030 8002 + 2 3 8002 60 1096 + 2 4 1096 69 9999 1120 + + 2 5 1200 30 0003 1059 + 2 6 1059 15 1162 8002 + 2 7 8002 60 1016 + 2 8 1016 01 1120 + + 2 9 1201 10 1009 1015 + 2 10 1015 46 1120 1069 + 2 11 1120 60 1023 1027 + 2 12 1069 60 8002 1027 + + 2 13 1202 60 1009 1013 + + 2 14 1013 30 0002 1021 + 2 15 1021 67 8002 1029 + 2 16 1029 30 0001 1036 + 2 17 1036 16 1045 1012 + 2 18 1012 46 1095 1120 + + 2 19 1203 60 1023 1027 + 2 20 1027 30 0003 1035 + 2 21 1035 10 1038 1043 + + 2 22 1204 65 1023 1127 + 2 23 1127 30 0003 1040 + 2 24 1040 69 1145 1151 + 2 25 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card + 7 2 1333 60 1242 1124 set an instruction for return + 7 3 1124 24 1278 1194 from read routine + 7 4 1194 20 1178 reset 000 + 7 5 1178 24 1017 1175 reset the loop box + 7 6 1175 24 1986 1344 reset the card counter + 7 7 1344 60 1952 1042 rau wc get word count from read card test the word count,n. if n <> 0, + 7 8 1042 45 1364 1377 brnz getw branch if wrds to load go to read to move n words + 7 9 1377 69 1959 1376 ld prnum no words. get problem num if n=0, put the problem number + 7 10 1376 24 1985 1397 std 1985 sv pr num on punch loc into the punch band + 7 11 1397 69 1976 1345 ld 1976 ld trace/no trace decide if tracing is required + 7 12 1345 24 1061 1018 std 1061 sv on gen interpret (dep on contents of 1976) + 7 13 1018 60 1951 1126 rau loc get loc from read card store the address of the + 7 14 1126 10 1038 1729 au c goto store result and exec op first programmer instruction, + 7 15 1038 60 1107 go to execute it (gen.int.) + 7 17 1242 70 1951 1344 constant (return from read) + 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1739 24 1293 1505 +19 115 1505 69 1261 1585 +19 116 1585 24 1539 1698 +19 117 1698 20 1289 1555 +19 118 1555 60 1167 1578 + +19 119 1384 21 1303 +19 120 1385 21 1304 +19 121 1261 35 0002 1293 +19 122 1167 17 4532 9348 + + +20 1 1305 69 1758 1761 + +20 2 1355 69 1908 1761 + +20 3 1761 24 1264 1917 +20 4 1917 30 0003 1925 +20 5 1925 15 1928 8002 +20 6 8002 60 1941 +20 7 1941 21 1297 1900 +20 8 1900 30 0002 1757 +20 9 1757 21 1265 1768 +20 10 1768 46 1771 1772 +20 11 1771 69 1774 1778 +20 12 1772 69 1775 1778 +20 13 1778 24 1283 1786 +20 14 1786 68 8002 1795 +20 15 1795 15 1568 1773 +20 16 1773 35 0001 1779 +20 17 1779 44 1783 1784 +20 18 1783 46 1937 1930 +20 19 1784 30 0005 1897 +20 20 1897 69 1901 1754 +20 21 1754 22 1260 1763 +20 22 1763 46 1766 1918 +20 23 1918 16 1921 1926 +20 24 1926 46 1929 1930 +20 25 1930 60 1297 1264 +20 26 1929 65 1265 1769 +20 27 1769 69 1922 1777 +20 28 1766 60 1919 1923 +20 29 1923 64 1265 1770 +20 30 1770 69 1924 1777 +20 31 1777 24 1285 1788 +20 32 1788 35 0001 1260 +20 33 1260 30 1781 +20 34 1781 67 8002 1789 +20 35 1789 20 1293 1796 +20 36 1796 15 1799 1752 +20 37 1752 44 1755 1756 +20 38 1755 60 1759 1913 +20 39 1913 19 1293 1927 +20 40 1927 35 0001 1933 +20 41 1933 10 1665 1920 +20 42 1920 21 1277 1780 +20 43 1780 60 1293 1797 +20 44 1797 11 1759 1764 +20 45 1764 64 1277 1902 +20 46 1902 69 1905 1909 +20 47 1756 65 1293 1147 +20 48 1147 35 0001 1753 +20 49 1753 69 1906 1909 +20 50 1909 24 1267 1570 +20 51 1570 20 1278 1931 +20 52 1931 60 8002 1939 +20 53 1939 19 8001 1945 +20 54 1945 21 1250 1903 +20 55 1903 61 8003 1911 +20 56 1911 19 1776 1940 +20 57 1940 60 8003 1149 +20 58 1149 10 1856 1762 + +20 59 1762 19 1250 1790 +20 60 1790 60 8003 1798 +20 61 1798 11 1855 1914 +20 62 1914 19 1250 1938 +20 63 1938 60 8003 1148 +20 64 1148 10 1853 1760 +20 65 1760 19 1250 1787 +20 66 1787 60 8003 1146 +20 67 1146 11 1852 1907 +20 68 1907 19 1250 1904 +20 69 1904 30 0001 1912 +20 70 1912 60 8003 1782 +20 71 1782 10 1785 1791 +20 72 1791 19 1278 1932 +20 73 1932 60 8003 1143 +20 74 1267 10 1285 +20 75 1285 00 8003 +20 76 1943 15 1701 1910 +20 77 1910 35 0001 1934 +20 78 1934 44 1942 1793 +20 79 1942 31 0003 1915 +20 80 1915 35 0002 1935 +20 81 1793 31 0002 1916 +20 82 1916 35 0001 1935 +20 83 1935 60 8002 1944 +20 84 1944 36 1765 +20 85 1765 11 8002 1864 +20 86 1864 10 1518 1283 +20 87 1283 00 8003 1264 +20 88 1264 00 +20 89 1936 60 1794 1655 +20 90 1937 65 1701 1910 + +20 91 1758 00 1445 +20 92 1908 21 1283 1936 +20 93 1928 60 1941 +20 94 1774 61 8003 1264 +20 95 1775 60 8003 1264 +20 96 1568 49 +20 97 1901 30 1781 +20 98 1921 00 0003 +20 99 1922 65 8003 1910 +20 100 1919 00 0100 +20 101 1224 66 8003 1943 +20 102 1799 97 2000 +20 103 1759 06 +20 104 1665 10 +20 105 1905 10 1731 1285 +20 106 1906 10 1580 1285 +20 107 1785 20 +20 108 1731 05 4041 9500 +20 109 1580 00 +20 110 1701 15 7079 6327 +20 111 1518 00 0050 +20 112 1794 57 2957 8051 +20 113 1801 50 + +20 114 1143 19 1801 1267 + diff --git a/I650/sw/is_run.ini b/I650/sw/is_run.ini new file mode 100644 index 00000000..03f0522f --- /dev/null +++ b/I650/sw/is_run.ini @@ -0,0 +1,48 @@ + +; set console -n log=log.txt +; set debug -n debug.txt +; set debug stdout +; set cpu debug=cmd;data;detail + + +; params: %1 source card deck to run with Floating Point Interpretive System (IS) +; %2 input card deck (if empty, do not attach input card + +; Load IS deck into (1 word per card format), but does not execute it + +set cpu 2k + +echo *** +echo *** load is deck into drum +echo *** + +att cdr1 -q is.dck + +d csw 7019519999 +d ar 8000 +go + +; now put IS program cards in reader and load them + +! copy %1 deck_in.dck > nul +if "%2" == "" goto run +! copy %1 + %2 deck_in.dck > nul +:run + +att cdr1 deck_in.dck +set cdr1 wiring=is + +att cdp1 -n -q deck_out_run.dck +set cdp1 echo, print, wiring=is +att cdp0 -n -q print.txt + +echo *** +echo *** load and run IS program +echo *** + +d csw 7019511333 +d ar 8000 +go + +:end + diff --git a/I650/sw/is_set_loopbox.txt b/I650/sw/is_set_loopbox.txt new file mode 100644 index 00000000..87228cc7 --- /dev/null +++ b/I650/sw/is_set_loopbox.txt @@ -0,0 +1,77 @@ + + deck 21. extra instr for general computing + set loopbox O2=800 + tr zero O2=453 + +21 1 1800 00 0000 0970 set loopbox: 0 800 00r nnn + if r=0 resets loopbox (= 000 000 000) + if r=1 sets loopbox for a-param, with value 0-999 from float + contents of register nnn. clears loobox value + for b and c. if float value at register is outside + range 0-999 program stops at 2222 + if r=2 sets loobox for b + if r=3 sets loobox for c + +21 2 0998 00 1000 0000 param1m (const to decrement param) +21 3 0997 35 0006 0987 bxa slt 0006 svlb +21 4 0996 35 0003 0987 bxb slt 0003 svlb +21 5 0995 00 0000 0987 bxc nop svlb +21 6 0994 60 0000 0950 fldc rau 0000 setb1 +21 7 0993 00 0000 0000 shbx +21 8 0992 00 0000 0000 svfc +21 9 0991 01 0000 0000 hi01 +21 10 0990 50 0000 0000 hi50 + + +21 11 0970 65 1045 0971 ral paramb is nnn0000000 +21 12 0971 45 0972 0987 brnz (cont) svlb +21 13 0972 16 0998 0973 sl param1m +21 14 0973 45 0975 0977 brnz (cont) seta +21 15 0975 16 0998 0976 sl param1m +21 16 0976 45 0979 0978 brnz setc setb +21 17 0977 69 0997 0980 seta ld bxa setbx +21 18 0978 69 0996 0980 setb ld bxb setbx +21 19 0979 69 0995 0980 setc ld bxc setbx +21 20 0980 24 0993 0981 setbx std shbx +21 21 0981 65 1023 0982 ral paramc lower acc is nnn0000000 +21 22 0982 30 0003 0983 srt 3 00 0nnn 000 +21 23 0983 15 0994 8002 al fldc 8002 + 8002 rau [c] setb1 read float value at [c] as nnnxxxxxee +21 24 0984 35 0003 0985 setb2 slt 3 upper acc is 000000nnn +21 25 0985 16 8002 0986 setb3 sl 8002 clear lower acc +21 26 0986 69 0993 8001 ld shbx 8001 + 8001 slt [0,3,6] upper acc is 000 000 nnn, 000 nnn 000, or nnn 000 000 +21 27 0987 21 1017 1095 svlb stu lbox 1095 save loopbox + +21 28 0950 21 0992 0951 setb1 stu svfc save [c] float value +21 29 0951 44 0952 0987 brnzu svlb if [c] is zero go to save loopbox +21 30 0952 46 1315 0953 brmin 1315 if [c] is <0 go to 2222 stop +21 31 0953 35 0008 0954 slt 8 upper acc is ee00000000 +21 32 0954 11 0990 0955 su hi50 +21 33 0955 44 0956 0962 brnzu i00n jump if [c] is in range 0-9 +21 34 0956 11 0991 0957 su hi01 +21 35 0957 44 0958 0961 brnzu i0nn jump if [c] is in range 10-99 +21 36 0958 11 0991 0959 su hi01 +21 37 0959 44 1315 0960 brnzu 1315 innn jump if [c] is in range 100-999, else go to 2222 stop +21 38 0960 69 0969 0963 innn ld stnnn ixxx +21 39 0961 69 0968 0963 i0nn ld stn0n ixxx +21 40 0962 69 0967 0963 i00n ld st00n ixxx +21 41 0963 24 0984 0964 ixxx std setb2 +21 42 0964 65 0992 0984 ral svfc setb2 + +21 43 1453 60 1009 0965 rau last get last result + + tr zero: 0 453 bbb ccc + goto b if last result is zero + goto c if last result is non zero + +21 44 0965 30 0002 0966 srt 2 +21 45 0966 44 1120 0974 brnzu gotoc gotob +21 46 0974 60 1045 1027 gotob rau paramb goto + +21 47 0967 35 0001 0985 st00n slt 1 setb3 +21 48 0968 35 0002 0985 st0nn slt 2 setb3 +21 49 0969 35 0003 0985 stnnn slt 3 setb3 + +21 50 0988 00 0000 0000 vacant location +21 51 0989 00 0000 0000 vacant location diff --git a/I650/sw/is_sys_load_src.txt b/I650/sw/is_sys_load_src.txt new file mode 100644 index 00000000..f6c13f4f --- /dev/null +++ b/I650/sw/is_sys_load_src.txt @@ -0,0 +1,97 @@ + 1 + 1 interpretive system (is) loader + 1 creates a 1-word load cards + 1 deck by reading cards as + 1 writen in manual + 1 + 1 this program is manually + 1 assembled (just using soap to + 1 load it) as is (1956) predates + 1 soap (1957) + 1 + 0880 70 1951 0881 rdcrd rd loc read card + 0881 60 1951 0892 rau loc lbl1 prepare accumulator for move + 0882 10 0870 0883 lbl2 au stw + 0883 15 0871 0884 al ldw + 0884 10 1952 0885 au wc + 0885 21 0874 0886 stu nwc + 0886 11 1952 8002 su wc + 8002 69 1953 8003 ld w move one word form card read area + 8003 24 0000 0887 std + 0887 15 0872 0888 nxt al iaddr increase address by 1 + 0888 10 8001 0889 au 8001 + 0889 11 0874 0890 su nwc test for end of moving + 0890 44 0891 0880 brnzu lbl3 rdcrd + 0891 10 0874 8002 lbl3 au nwc nxt return to move another word + 0892 44 0893 0880 lbl1 brnzu rdcrd if loc is zero read next card + 0893 11 0873 0894 su i2000 + 0894 46 0895 0880 brmin rdcrd if loc >= 2000 read next card + 0895 10 0873 0882 au i2000 lbl2 + 1 + 1 constants + 1 + 0870 24 0000 0887 stw std 0000 nxt store word + 0871 69 1953 8003 ldw ld w load word from card read + 0872 00 0001 0000 iaddr + 0873 00 2000 0000 i2000 + 0874 00 0000 0000 nwc temp variable + 1 + 1 card read area + 1 + 1 1951 00 1002 0000 loc location + 1 1952 00 0002 0000 wc word count + 1 1953 00 3333 4444 W word1 + 1 1954 00 5555 6666 word2 + 1 1955 00 0000 0000 word3 + 1 1956 00 0000 0000 word4 + 1 1957 00 0000 0007 word5 + 1 1958 00 0000 0008 word6 + 1 + 1 + 1 generate system + 1 punch the whole is system on a 1 + 1 word per card format + 1 from 0900 to 1999 + 1 + 0801 65 0852 0802 lblw ral loc1 prepare accumulator for move + 0802 10 0850 0803 au stw2 + 0803 15 0851 8002 al ldw2 + 8002 69 0000 8003 ld move one word to card punch area + 8003 24 0000 0804 std ww + 0804 65 0852 0805 p1w ral loc1 set word loc in card punch area + 0805 15 0854 0806 al wloc0 + 0806 20 1979 0807 stl wloc + 0807 10 1978 0808 au cnum set card number in card punch area + 0808 10 0855 0809 au icard + 0809 21 1978 0810 stu cnum + 0810 71 1977 0811 pch1w pch 1977 punch 1w card + 0811 65 0852 0812 ral loc1 + 0812 16 0853 0813 sl loc2 + 0813 46 0814 9999 brmin 9999 if loc1 >= loc2 terminate + 0814 15 0853 0815 al loc2 + 0815 15 0872 0816 al iaddr increment loc1 + 0816 20 0852 0801 stl loc1 lblw go punch next word + 1 + 1 constants + 1 + 0850 24 1980 0804 stw2 std wdata p1w store word for punch + 0851 69 0000 8003 ldw2 ld 0000 load word + 0852 00 0900 0000 loc1 first location to punch + 0853 00 1999 0000 loc2 last location to punch + 0854 24 0000 8000 wloc0 word location on 1e load card format + 0855 00 0000 0001 icard just one + 1 + 1 card punch area (1 word per card load card) + 1 make first word negative so is control panel + 1 punchs a load card with y(12) hi punch set + 1 + - 1977 69 1954 1953 + 1978 00 0000 0000 cnum card number + 1979 24 0000 8000 wloc word location + 1980 00 0000 0000 wdata word data in load card + 1981 00 0000 0000 + 1982 00 0000 0000 + 1983 00 0000 0000 + 1984 00 0000 0000 + 1985 00 0000 0000 + 1986 00 0000 0000 diff --git a/I650/sw/is_trace_src.txt b/I650/sw/is_trace_src.txt new file mode 100644 index 00000000..f012e85b --- /dev/null +++ b/I650/sw/is_trace_src.txt @@ -0,0 +1,59 @@ +10 1 1061 21 1980 1386 +10 2 1386 30 0003 1946 +10 3 1946 20 1023 1947 +10 4 1947 60 8003 1948 +10 5 1948 30 0003 1949 +10 6 1949 20 1045 1950 +10 7 1950 60 8003 1961 +10 8 1961 24 1260 1962 +10 9 1962 30 0003 1963 +10 10 1963 44 1965 1968 +10 11 1965 65 8002 1966 +10 12 1966 30 0003 1967 +10 13 1967 15 1998 8002 +10 14 8002 60 1968 +10 15 1968 21 1982 1969 +10 16 1969 65 1045 1970 +10 17 1970 30 0003 1971 +10 18 1971 15 1999 8002 +10 19 8002 69 1972 +10 20 1972 24 1983 1973 +10 21 1973 69 1974 +10 22 1974 24 1984 1975 +10 23 1975 69 1017 1987 +10 24 1987 24 1981 1988 +10 25 1988 65 1098 1989 +10 26 1989 24 1977 1990 +10 27 1990 15 1997 8002 +10 28 8002 69 +10 29 1991 24 1979 1992 +10 30 1992 65 1986 1993 +10 31 1993 15 1024 1994 +10 32 1994 20 1986 1995 +10 33 1995 71 1977 1996 +10 34 1996 60 1260 1105 + +10 35 1450 69 1976 1331 +10 36 1331 24 1061 1095 + +10 37 1451 69 1154 1358 +10 38 1358 24 1061 1095 + +10 39 1452 69 1976 1332 +10 40 1332 24 1061 1091 +10 41 1091 65 1098 1165 +10 42 1165 16 1173 1334 +10 43 1334 69 1141 8002 +10 44 8002 24 1095 + +10 45 1997 09 0884 +10 46 1998 60 1968 +10 47 1999 69 1972 +10 48 1141 04 5400 +10 49 1173 36 0012 +10 50 1154 30 0003 1019 +10 51 1978 00 0006 0008 +10 52 1964 00 1095 +10 53 1976 21 1980 1386 +10 54 1024 00 0001 +10 55 1958 44 1965 1968 diff --git a/I650/sw/soapII.dck b/I650/sw/soapII.dck new file mode 100644 index 00000000..26acff42 --- /dev/null +++ b/I650/sw/soapII.dck @@ -0,0 +1,1400 @@ +0?0000800? 0001 1 soap 2 +0?0000800? 0002 1 +0?0000800? 0003 1 symbolic optimal assembly prog +0?0000800? 0004 1 +0?0000800? 0005 1 for the +0?0000800? 0006 1 +0?0000800? 0007 1 ibm 650 +0?0000800? 0008 1 +0?0000800? 0009 1 data processing system +0?0000800? 0010 1 +0?0000800? 0011 regs0000 0399 symbol tab +0?0000800? 0012 rege0400 0599 equiv tabl +0?0000800? 0013 rega0600 0799 avail tabl +0?0000800? 0014 regn0800 0899 num op tab +0?0000800? 0015 blr 1000 1000 entry +0?0000800? 0016 blr 1001 1012 pseudo ent +0?0000800? 0017 blr 1021 1049 reg table +0?0000800? 0018 regc1050 1164 sym op tab +0?0000800? 0019 bla 1098 1099 +0?0000800? 0020 bla 1148 1149 +0?0000800? 0021 blr 1900 1900 manual pat +0?0000800? 0022 synreadc 1950 +0?0000800? 0023 blr 1951 1962 read area +0?0000800? 0024 regt1990 1992 type +0?0000800? 0025 regp1977 1986 punch area +0?0000800? 0026 blr 1998 1999 +0?0000800? 0027 equxxxx1 1961 +0?0000800? 0028 equxxxx2 1962 +0?0000800? 0029 blr 1563 1570 type2 +0?0000800? 0030 bla 1565 1565 +0?0000800? 0031 bla 1569 1569 +0?0000800? 0032 regb0900 0901 sub 2 +0?0000800? 0033 regh0902 0904 type 2 +0?0000800? 0034 regm0905 0907 +0?0000800? 0035 regq0908 0909 +0?0000800? 0036 regr1200 1207 sub 5 +0?0000800? 0037 regu1250 1259 sub 13 +0?0000800? 0038 regv0910 0912 equ syn +0?0000800? 0039 regx0913 0914 type 0 +0?0000800? 0040 regy0915 0916 equ syn +0?0000800? 0041 regz0917 0919 +0?0000800? 0042 regw0920 0922 +0?0000800? 0043 blr 0923 0968 multiple r +0?0000800? 0044 regi1300 1307 sub 13 +0?0000800? 0045 1 +0?0000800? 0046 1 control program +0?0000800? 0047 1 +6I1954195C 0048241000800?691950135C 1000lddreadc sub16 entry +0?0000800? 0049 1 +6I1954195C 0050241950800?701999199H readcrcd 1999 1998 read card +6I1954195C 0051241998800?691951135D 1998ldd 1951 transfer +6I1954195C 0052241354800?241977098? stdp0001 alphabetic +6I1954195C 0053240980800?691952135E ldd 1952 input +6I1954195C 0054241355800?241978098A stdp0002 to +6I1954195C 0055240981800?691953135F ldd 1953 output +6I1954195C 0056241356800?241979098B stdp0003 +6I1954195C 0057240982800?691954135G ldd 1954 +6I1954195C 0058241357800?241980098C stdp0004 +6I1954195C 0059240983800?691955120H ldd 1955 +6I1954195C 0060241208800?241981098D stdp0005 +6I1954195C 0061240984800?691956120I ldd 1956 +6I1954195C 0062241209800?241982098E stdp0006 +6I1954195C 0063240985800?651985098I ralp0009 step +6I1954195C 0064240989800?150992099G alo1ixxx card +6I1954195C 0065240997800?201985098H stlp0009 number +6I1954195C 0066240988800?601960101E rau 1960 store +6I1954195C 0067241015800?300002097A srt 0002 control +6I1954195C 0068240971800?211984098G stup0008 info +6I1954195C 0069240987800?100990099E auptorg +6I1954195C 0070240995800?201986800C stlp0010 8003 transfer +6I1954800? 0071248003800?000000999I 8003nop 0000 9999 to type +0?0000800? 0072 1 +6I1954195C 0073241350800?711977195? punchpchp0001 readc punch read +0?0000800? 0074 1 +6I1954195C 0075241400800?601950140E setccraureadc sub10 sudo exit +0?0000800? 0076 1 +6I1954195C 0077241900800?691950140C 1900lddreadc sub14 manual pat +6I1954195C 0078241990800?690993099F t0001lddx subr3 type 0 +0?0000800? 0079 1 +6I1954195C 0080240913800?691016096I x0001ldd procl 650 +6I1954195C 0081241016800?691019097B ldd procd command or +6I1954195C 0082241019800?691350145C lddpunch proci constants +0?0000800? 0083 1 +6I1954195C 0084240914800?000000800C x0002nop 0000 8003 pseudo op +0?0000800? 0085 1 +6I1954195C 0086241991800?601950140E t0002raureadc sub10 type 1 com +0?0000800? 0087 1 +6I1954195C 0088240993800?000000091C x 00 0000 x0001 +0?0000800? 0089 1 +0?0000800? 0090 1 relocate routine +0?0000800? 0091 1 +0?0000800? 0092 hedt +6I1954195C 0093241992800?691195099F t0003lddq subr3 process op +6I1954195C 0094240909800?000000101C q0002nop 0000 illop illegal op +6I1954195C 0095240908800?651951145E q0001ral 1951 is l fixed +6I1954195C 0096241455800?350002121A slt 0002 +6I1954195C 0097241211800?441165116F nzu rel +6I1954195C 0098241165800?601957126A rau 1957 fixed l +6I1954195C 0099241261800?111014116I sup2000i drum core +6I1954195C 0100241169800?461172097C bmi fc +6I1954195C 0101241172800?108001097I aup 8001 res fixed drum +6I1954195C 0102240973800?651957131A fc ral 1957 setl fixed core +6I1954195C 0103241450800?651961131A sr ralxxxx1 setl set l +6I1954195C 0104241311800?350004117A setl slt 0004 +6I1954195C 0105241171800?691984118G lddp0008 +6I1954195C 0106241187800?221984123G sdap0008 prod +6I1954195C 0107241166800?601957136A rel rau 1957 drum core +6I1954195C 0108241361800?111014121I sup2000i +6I1954195C 0109241219800?461222117C bmi rc +6I1954195C 0110241222800?100975117I aupddiff relocate +6I1954195C 0111241179800?461182118C bmi bl drum addr +6I1954195C 0112241182800?101014097I aup2000i res +6I1954195C 0113240979800?211961121D res stuxxxx1 +6I1954195C 0114241214800?691450150C lddsr sub2r reserve l +6I1954195C 0115241173800?651957141A rc ral 1957 relocate +6I1954195C 0116241411800?151264126I alocdiff core +6I1954195C 0117241269800?161272097G slo9060 +6I1954195C 0118240977800?461180118C bmi bl +6I1954195C 0119241180800?158001131A alo 8001 setl +6I1954195C 0120241183800?601237099A bl rauprod sub12 blank l +0?0000800? 0121 1 +0?0000800? 0122 regj0944 0944 d type 2 +0?0000800? 0123 regg0941 0941 +0?0000800? 0124 1 +6I1954195C 0125241237800?691190119C prod lddproi set d exit +6I1954195C 0126241193800?241196099I stdexitx +6I1954195C 0127240999800?601952140G rau 1952 what is d +6I1954195C 0128241407800?691210121C lddh subr4 +6I1954195C 0129240902800?651958126C h0001ral 1958 relocate +6I1954195C 0130241263800?161014131I slo2000i d or c +6I1954195C 0131241319800?461564156C bmi 1564 1563 +6I1954195C 0132240903800?300008122A h0002srt 0008 c d or f +6I1954195C 0133241221800?100974800C aup1500 8003 +6I1954195C 0134241563800?651264136I 1563ralcdiff cdd c +6I1954195C 0135241564800?650975136I 1564ralddiff cdd d +6I1954195C 0136241566800?651958094D 1566ral 1958 j0001 f +6I1954195C 0137241369800?151958094D cdd alo 1958 j0001 +6I1954195C 0138240904800?000000094C h0003nop 0000 g0003 symbolic +0?0000800? 0139 1 +0?0000800? 0140 regj0960 0960 i +0?0000800? 0141 regf0955 0955 +0?0000800? 0142 1 +6I1954195C 0143241190800?691350155C proi lddpunch set i exit +6I1954195C 0144241553800?241196109I stdexitx +6I1954195C 0145241099800?601953145G rau 1953 what is i +6I1954195C 0146241457800?691260121C lddm subr4 +6I1954195C 0147240905800?651959131C m0001ral 1959 relocate +6I1954195C 0148241313800?161014141I slo2000i d or c +6I1954195C 0149241419800?461568156G bmi 1568 1567 +6I1954195C 0150240906800?300008117E m0002srt 0008 c d or f +6I1954195C 0151241175800?100978800C aup1504 8003 +6I1954195C 0152241567800?651264146I 1567ralcdiff cdi c +6I1954195C 0153241568800?650975146I 1568ralddiff cdi d +6I1954195C 0154241570800?651959096? 1570ral 1959 j0001 f +6I1954195C 0155241469800?151959096? cdi alo 1959 j0001 +6I1954195C 0156240907800?000000095G m0003nop 0000 f0003 symbolic +0?0000800? 0157 1 +6I1954195C 0158241195800?000000090H q 00 0000 q0001 constants +6I1954195C 0159241272800?000000906? 9060 00 0000 9060 +6I1954195C 0160241210800?000000090B h 00 0000 h0001 +6I1954195C 0161240974800?000000150? 1500 00 0000 1500 +6I1954195C 0162241260800?000000090E m 00 0000 m0001 +6I1954195C 0163240978800?000000150D 1504 00 0000 1504 +6I1954195C 0164241961800?010000196A xxxx1 01 0000 xxxx1 eraseable +0?0000800? 0165 hed +0?0000800? 0166 1 +0?0000800? 0167 1 bop routine +0?0000800? 0168 1 +6I1954195C 0169241001800?691404135C 1001ldd sub16 initialize +6I1954195C 0170241404800?601950140E raureadc sub10 punch +0?0000800? 0171 1 +0?0000800? 0172 1 blr routine +0?0000800? 0173 1 +6I1954195C 0174241002800?651959136C 1002ral 1959 blr reserve +6I1954195C 0175241363800?161958141C blr slo 1958 fwa to +6I1954195C 0176241413800?108001127A aup 8001 lwa +6I1954195C 0177241271800?691400150C lddsetcc sub2r +0?0000800? 0178 1 +0?0000800? 0179 1 rbr routine +0?0000800? 0180 1 +6I1954195C 0181241012800?600975122I 1012rauddiff +6I1954195C 0182241229800?151959136C alo 1959 blr +0?0000800? 0183 1 +0?0000800? 0184 1 bla routine +0?0000800? 0185 1 +6I1954195C 0186241003800?691406130I 1003lddh8xxx set drum +6I1954195C 0187241309800?241212121E stddrumt tag to 8 +6I1954195C 0188241215800?651959146C ral 1959 unreserve +6I1954195C 0189241463800?161958151C slo 1958 fwa +6I1954195C 0190241513800?108001132A aup 8001 to +6I1954195C 0191241321800?691400160C lddsetcc sub2u lwa +0?0000800? 0192 1 +0?0000800? 0193 1 reg routine +0?0000800? 0194 1 +0?0000800? 0195 hedr +6I1954195C 0196241004800?651952150G 1004ral 1952 is +6I1954195C 0197241507800?300008122E srt 0008 region +6I1954195C 0198241225800?161178123C slo90xxx character +6I1954195C 0199241233800?460986100B bmi 1002 alphabetic +6I1954195C 0200240986800?151189124C alo29xxx +6I1954195C 0201241243800?461002119G bmi 1002 +6I1954195C 0202241197800?350004155G slt 0004 store +6I1954195C 0203241557800?151310126E alost region +6I1954195C 0204241265800?101958161C aup 1958 origin +6I1954195C 0205241613800?101216800B auph9xxx 8002 +6I1954800? 0206248002800?219999100B 8002stu 9999 1002 +0?0000800? 0207 1 +6I1954195C 0208241310800?211021100B st stu 1021 1002 constants +0?0000800? 0209 hed +0?0000800? 0210 1 +0?0000800? 0211 1 equ req and syn routine +0?0000800? 0212 1 +0?0000800? 0213 hedz +6I1954195C 0214241005800?691406135I 1005lddh8xxx both equ +6I1954195C 0215241006800?691216135I 1006lddh9xxx both syn +6I1954195C 0216241359800?241262131E both stdtag +6I1954195C 0217241315800?601953160G rau 1953 what is i +6I1954195C 0218241607800?691360121C lddz subr4 +6I1954195C 0219240917800?651959091E z0001ral 1959 y0001 absolute +6I1954195C 0220240918800?691371117D z0002lddy subr9 regional +6I1954195C 0221240915800?201519132B y0001stle td +6I1954195C 0222240916800?651986119A y0002ralp0010 bp reg error +6I1954195C 0223240919800?691372127E z0003lddw subr6 symbolic +6I1954195C 0224240920800?651223091E w0001ralequiv y0001 s defined +6I1954195C 0225240921800?651986119A w0002ralp0010 bp s undefind +6I1954195C 0226240922800?651986119A w0003ralp0010 bp s tab full +0?0000800? 0227 1 +6I1954195C 0228241322800?601952165G td rau 1952 head d +6I1954195C 0229241657800?691410166C ldd sub15 and equate +6I1954195C 0230241410800?691713127E lddv subr6 to e +6I1954195C 0231240912800?651986119A v0003ralp0010 bp s tab full +6I1954195C 0232240910800?151519127C v0001aloe sd +6I1954195C 0233240911800?151519127C v0002aloe sd +6I1954195C 0234241273800?690976127I sd lddtt subr7 +0?0000800? 0235 1 +6I1954195C 0236240976800?691262136E tt lddtag test tag +6I1954195C 0237241365800?901400097? bdosetcc +6I1954195C 0238240970800?601519132C raue reserve e +6I1954195C 0239241323800?691400150C lddsetcc sub2r +0?0000800? 0240 1 +6I1954195C 0241241011800?691406140I 1011lddh8xxx req +6I1954195C 0242241409800?241262141E stdtag routine +6I1954195C 0243241415800?651959176C ral 1959 is i +6I1954195C 0244241763800?161014156I slo2000i drum o cor +6I1954195C 0245241569800?461422137C bmid +6I1954195C 0246241373800?151264161I alocdiff cd +6I1954195C 0247241422800?150975161I d aloddiff cd +6I1954195C 0248241619800?151014091E cd alo2000i y0001 +0?0000800? 0249 1 +6I1954195C 0250241360800?000000091G z 00 0000 z0001 constants +6I1954195C 0251241371800?000089091E y 00 0089 y0001 +6I1954195C 0252241372800?000000092? w 00 0000 w0001 +6I1954195C 0253241713800?000000091? v 00 0000 v0001 +6I1954195C 0254241500800?008800000? 88 00 8800 0000 +0?0000800? 0255 1 +6I1954195C 0256241191800?151500150E bp alo88 by pass +6I1954195C 0257241505800?201986135? stlp0010 punch +0?0000800? 0258 1 +6I1954195C 0259241262800?010000126B tag 01 0000 tag eraseable +6I1954195C 0260241519800?010000151I e 01 0000 e +0?0000800? 0261 hed +0?0000800? 0262 1 +0?0000800? 0263 1 alf routine +0?0000800? 0264 1 +6I1954195C 0265241007800?691460096I 1007ldd procl proces loc +6I1954195C 0266241460800?691952155E ldd 1952 +6I1954195C 0267241555800?241983118F stdp0007 +6I1954195C 0268241186800?651953170G ral 1953 replace +6I1954195C 0269241707800?451350146A nzepunch blank i +6I1954195C 0270241461800?691314101G lddsoap2 by +6I1954195C 0271241017800?241979135? stdp0003 punch soap2 +6I1954195C 0272241314800?827661779B soap2alfsoap2 soap2 constant +0?0000800? 0273 1 +0?0000800? 0274 1 pat routine +0?0000800? 0275 1 +6I1954195C 0276241008800?601511140E 1008rau sub10 +6I1954195C 0277241511800?691950140C lddreadc sub14 +0?0000800? 0278 1 +0?0000800? 0279 1 hed routine +0?0000800? 0280 1 +6I1954195C 0281241009800?651952175G 1009ral 1952 store +6I1954195C 0282241757800?300008132E srt 0008 heading +6I1954195C 0283241325800?201329140? stl0000h setcc character +0?0000800? 0284 1 +0?0000800? 0285 1 rel routine +0?0000800? 0286 1 +0?0000800? 0287 hedm +6I1954195C 0288241010800?651952180G 1010ral 1952 set +6I1954195C 0289241807800?451510156A nze sdd drum +6I1954195C 0290241510800?651958156A ral 1958 sdd and +6I1954195C 0291241561800?200975122H sdd stlddiff core +6I1954195C 0292241228800?651953185G ral 1953 deltas +6I1954195C 0293241857800?451560161A nze scd +6I1954195C 0294241560800?651959161A ral 1959 scd +6I1954195C 0295241611800?201264140? scd stlcdiff setcc +0?0000800? 0296 1 +6I1954195C 0297240975800?010000097E ddiff 01 0000 ddiff eraseable +6I1954195C 0298241264800?010000126D cdiff 01 0000 cdiff +0?0000800? 0299 hed +0?0000800? 0300 1 +0?0000800? 0301 1 load availablity table +0?0000800? 0302 1 +0?0000800? 0303 hedl +6I1954195C 0304241999800?651951160E 1999ral 1951 calc +6I1954195C 0305241605800?300004146E srt 0004 loc +6I1954195C 0306241465800?350004137E slt 0004 w2 +6I1954195C 0307241375800?158002128C alo 8002 +6I1954195C 0308241283800?158002124A alo 8002 +6I1954195C 0309241241800?150994114I aloc1 +6I1954195C 0310241149800?101352800C aupc2 8003 +6I1954800? 0311248003800?699995800B 8003ldd 9995 8002 load +6I1954800? 0312248002800?249994124G 8002std 9994 tup table +6I1954195C 0313241247800?111550165E tup suptw +6I1954195C 0314241655800?441459195? nzu readc +6I1954195C 0315241459800?101312116G auptwp2 +6I1954195C 0316241167800?151020800C alo1dxxx 8003 +0?0000800? 0317 1 +6I1954195C 0318240994800?240600124G c1 stda0001 tup constants +6I1954195C 0319241352800?691952800B c2 ldd 1952 8002 +6I1954195C 0320241550800?691958800B tw ldd 1958 8002 +6I1954195C 0321241312800?691960800B twp2 ldd 1960 8002 +0?0000800? 0322 hed +0?0000800? 0323 1 optimizing table +0?0000800? 0324 1 +6I1954195C 0325240800800?000404099H n0001 00 0404 0998 nop +6I1954195C 0326240801800?000404099H n0002 00 0404 0998 hlt +6I1954195C 0327240802800?332322099I n0003 33 2322 0999 ufa +6I1954195C 0328240803800?000505099H n0004 00 0505 0998 rtc +6I1954195C 0329240804800?000505099H n0005 00 0505 0998 rtn +6I1954195C 0330240805800?000505099H n0006 00 0505 0998 rta +6I1954195C 0331240806800?000505099H n0007 00 0505 0998 wtn +6I1954195C 0332240807800?000505099H n0008 00 0505 0998 wta +6I1954195C 0333240808800?331212099I n0009 33 1212 0999 lib +6I1954195C 0334240809800?330202099I n0010 33 0202 0999 ldi +6I1954195C 0335240810800?330504099I n0011 33 0504 0999 aup +6I1954195C 0336240811800?330504099I n0012 33 0504 0999 sup +6I1954195C 0337240812800?999999999I n0013 99 9999 9999 not used +6I1954195C 0338240813800?999999999I n0014 99 9999 9999 not used +6I1954195C 0339240814800?331110099I n0015 33 1110 0999 div +6I1954195C 0340240815800?330504099I n0016 33 0504 0999 alo +6I1954195C 0341240816800?330504099I n0017 33 0504 0999 slo +6I1954195C 0342240817800?330504099I n0018 33 0504 0999 aml +6I1954195C 0343240818800?330504099I n0019 33 0504 0999 sml +6I1954195C 0344240819800?332120099I n0020 33 2120 0999 mpy +6I1954195C 0345240820800?540303099I n0021 54 0303 0999 stl +6I1954195C 0346240821800?450303099I n0022 45 0303 0999 stu +6I1954195C 0347240822800?340303099I n0023 34 0303 0999 sda +6I1954195C 0348240823800?340303099I n0024 34 0303 0999 sia +6I1954195C 0349240824800?330303099I n0025 33 0303 0999 std +6I1954195C 0350240825800?440505099H n0026 44 0505 0998 nts +6I1954195C 0351240826800?000505099H n0027 00 0505 0998 bin +6I1954195C 0352240827800?000505099H n0028 00 0505 0998 set +6I1954195C 0353240828800?331212099I n0029 33 1212 0999 sib +6I1954195C 0354240829800?330202099I n0030 33 0202 0999 sti +6I1954195C 0355240830800?000000098H n0031 00 0000 0988 srt +6I1954195C 0356240831800?000000088H n0032 00 0000 0888 srd +6I1954195C 0357240832800?332726099I n0033 33 2726 0999 fad +6I1954195C 0358240833800?332726099I n0034 33 2726 0999 fsb +6I1954195C 0359240834800?330000099I n0035 33 0000 0999 fdv +6I1954195C 0360240835800?000000098H n0036 00 0000 0988 slt +6I1954195C 0361240836800?000000098H n0037 00 0000 0988 sct +6I1954195C 0362240837800?332726099I n0038 33 2726 0999 fam +6I1954195C 0363240838800?332726099I n0039 33 2726 0999 fsm +6I1954195C 0364240839800?330000099I n0040 33 0000 0999 fmp +6I1954195C 0365240840800?330404099H n0041 33 0404 0998 nza +6I1954195C 0366240841800?330404099H n0042 33 0404 0998 bmz +6I1954195C 0367240842800?330404099H n0043 33 0404 0998 nzb +6I1954195C 0368240843800?330404099H n0044 33 0404 0998 bmb +6I1954195C 0369240844800?340405099H n0045 34 0405 0998 nzu +6I1954195C 0370240845800?430504099H n0046 43 0504 0998 nze +6I1954195C 0371240846800?330404099H n0047 33 0404 0998 bmi +6I1954195C 0372240847800?330505099H n0048 33 0505 0998 bov +6I1954195C 0373240848800?330404099H n0049 33 0404 0998 nzc +6I1954195C 0374240849800?330404099H n0050 33 0404 0998 bmc +6I1954195C 0375240850800?000000089H n0051 00 0000 0898 axa +6I1954195C 0376240851800?000000089H n0052 00 0000 0898 sxa +6I1954195C 0377240852800?000000089H n0053 00 0000 0898 axb +6I1954195C 0378240853800?000000089H n0054 00 0000 0898 sxb +6I1954195C 0379240854800?440505099H n0055 44 0505 0998 nef +6I1954195C 0380240855800?000505099H n0056 00 0505 0998 rwd +6I1954195C 0381240856800?000505099H n0057 00 0505 0998 wtm +6I1954195C 0382240857800?000505099H n0058 00 0505 0998 bst +6I1954195C 0383240858800?000000089H n0059 00 0000 0898 axc +6I1954195C 0384240859800?000000089H n0060 00 0000 0898 sxc +6I1954195C 0385240860800?330504099I n0061 33 0504 0999 rau +6I1954195C 0386240861800?330504099I n0062 33 0504 0999 rsu +6I1954195C 0387240862800?999999999I n0063 99 9999 9999 not used +6I1954195C 0388240863800?999999999I n0064 99 9999 9999 not used +6I1954195C 0389240864800?331110099I n0065 33 1110 0999 dvr +6I1954195C 0390240865800?330504099I n0066 33 0504 0999 ral +6I1954195C 0391240866800?330504099I n0067 33 0504 0999 rsl +6I1954195C 0392240867800?330504099I n0068 33 0504 0999 ram +6I1954195C 0393240868800?330504099I n0069 33 0504 0999 rsm +6I1954195C 0394240869800?330303099I n0070 33 0303 0999 ldd +6I1954195C 0395240870800?000000099I n0071 00 0000 0999 rd1 +6I1954195C 0396240871800?000000099I n0072 00 0000 0999 wr1 +6I1954195C 0397240872800?000000099I n0073 00 0000 0999 rc1 +6I1954195C 0398240873800?000000099I n0074 00 0000 0999 rd2 +6I1954195C 0399240874800?000000099I n0075 00 0000 0999 wr2 +6I1954195C 0400240875800?000000099I n0076 00 0000 0999 rc2 +6I1954195C 0401240876800?000000099I n0077 00 0000 0999 rd3 +6I1954195C 0402240877800?000000099I n0078 00 0000 0999 wr3 +6I1954195C 0403240878800?000000099I n0079 00 0000 0999 rc3 +6I1954195C 0404240879800?000505099I n0080 00 0505 0999 rpy +6I1954195C 0405240880800?000000089H n0081 00 0000 0898 raa +6I1954195C 0406240881800?000000089H n0082 00 0000 0898 rsa +6I1954195C 0407240882800?000000089H n0083 00 0000 0898 rab +6I1954195C 0408240883800?000000089H n0084 00 0000 0898 rsb +6I1954195C 0409240884800?330506099I n0085 33 0506 0999 tlu +6I1954195C 0410240885800?000606099H n0086 00 0606 0998 sds +6I1954195C 0411240886800?000606099H n0087 00 0606 0998 rds +6I1954195C 0412240887800?000606099H n0088 00 0606 0998 wds +6I1954195C 0413240888800?000000089H n0089 00 0000 0898 rac +6I1954195C 0414240889800?000000089H n0090 00 0000 0898 rsc +6I1954195C 0415240890800?440505099H n0091 44 0505 0998 bdo +6I1954195C 0416240891800?330505099H n0092 33 0505 0998 bd1 +6I1954195C 0417240892800?330505099H n0093 33 0505 0998 bd2 +6I1954195C 0418240893800?330505099H n0094 33 0505 0998 bd3 +6I1954195C 0419240894800?330505099H n0095 33 0505 0998 bd4 +6I1954195C 0420240895800?330505099H n0096 33 0505 0998 bd5 +6I1954195C 0421240896800?330505099H n0097 33 0505 0998 bd6 +6I1954195C 0422240897800?330505099H n0098 33 0505 0998 bd7 +6I1954195C 0423240898800?330505099H n0099 33 0505 0998 bd8 +6I1954195C 0424240899800?440505099H n0100 44 0505 0998 bd9 +0?0000800? 0425 1 +0?0000800? 0426 1 symbolic op table +0?0000800? 0427 1 +6I1954195C 0428241050800?617366100G c0001 61 7366 1007 alf +6I1954195C 0429241051800?617376001E c0002 61 7376 0015 alo +6I1954195C 0430241052800?617473001G c0003 61 7473 0017 aml +6I1954195C 0431241053800?618477001? c0004 61 8477 0010 aup +6I1954195C 0432241054800?618761005? c0005 61 8761 0050 axa +6I1954195C 0433241055800?618762005B c0006 61 8762 0052 axb +6I1954195C 0434241056800?618763005H c0007 61 8763 0058 axc +6I1954195C 0435241057800?626476009? c0008 62 6476 0090 bdo +6I1954195C 0436241058800?626491009A c0009 62 6491 0091 bd1 +6I1954195C 0437241059800?626492009B c0010 62 6492 0092 bd2 +6I1954195C 0438241060800?626493009C c0011 62 6493 0093 bd3 +6I1954195C 0439241061800?626494009D c0012 62 6494 0094 bd4 +6I1954195C 0440241062800?626495009E c0013 62 6495 0095 bd5 +6I1954195C 0441241063800?626496009F c0014 62 6496 0096 bd6 +6I1954195C 0442241064800?626497009G c0015 62 6497 0097 bd7 +6I1954195C 0443241065800?626498009H c0016 62 6498 0098 bd8 +6I1954195C 0444241066800?626499009I c0017 62 6499 0099 bd9 +6I1954195C 0445241067800?626975002F c0018 62 6975 0026 bin +6I1954195C 0446241068800?627361100C c0019 62 7361 1003 bla +6I1954195C 0447241069800?627379100B c0020 62 7379 1002 blr +6I1954195C 0448241070800?627461004A c0021 62 7461 0041 bma +6I1954195C 0449241071800?627462004C c0022 62 7462 0043 bmb +6I1954195C 0450241072800?627463004I c0023 62 7463 0049 bmc +6I1954195C 0451241073800?627469004F c0024 62 7469 0046 bmi +6I1954195C 0452241074800?627677100A c0025 62 7677 1001 bop +6I1954195C 0453241075800?627685004G c0026 62 7685 0047 bov +6I1954195C 0454241076800?628283005G c0027 62 8283 0057 bst +6I1954195C 0455241077800?646985001D c0028 64 6985 0014 div +6I1954195C 0456241078800?648579006D c0029 64 8579 0064 dvr +6I1954195C 0457241079800?657884100E c0030 65 7884 1005 equ +6I1954195C 0458241080800?666164003B c0031 66 6164 0032 fad +6I1954195C 0459241081800?666174003G c0032 66 6174 0037 fam +6I1954195C 0460241082800?666485003D c0033 66 6485 0034 fdv +6I1954195C 0461241083800?667477003I c0034 66 7477 0039 fmp +6I1954195C 0462241084800?668262003C c0035 66 8262 0033 fsb +6I1954195C 0463241085800?668274003H c0036 66 8274 0038 fsm +6I1954195C 0464241086800?686564100I c0037 68 6564 1009 hed +6I1954195C 0465241087800?687383000A c0038 68 7383 0001 hlt +6I1954195C 0466241088800?736464006I c0039 73 6464 0069 ldd +6I1954195C 0467241089800?736469000I c0040 73 6469 0009 ldi +6I1954195C 0468241090800?736962000H c0041 73 6962 0008 lib +6I1954195C 0469241091800?747788001I c0042 74 7788 0019 mpy +6I1954195C 0470241092800?756566005D c0043 75 6566 0054 nef +6I1954195C 0471241093800?757677000? c0044 75 7677 0000 nop +6I1954195C 0472241094800?758382002E c0045 75 8382 0025 nts +6I1954195C 0473241095800?758961004? c0046 75 8961 0040 nza +6I1954195C 0474241096800?758962004B c0047 75 8962 0042 nzb +6I1954195C 0475241097800?758963004H c0048 75 8963 0048 nzc +6I1954195C 0476241100800?758965004E c0051 75 8965 0045 nze +6I1954195C 0477241101800?758984004D c0052 75 8984 0044 nzu +6I1954195C 0478241102800?776183100H c0053 77 6183 1008 pat +6I1954195C 0479241103800?776368007A c0054 77 6368 0071 pch +6I1954195C 0480241104800?796161008? c0055 79 6161 0080 raa +6I1954195C 0481241105800?796162008B c0056 79 6162 0082 rab +6I1954195C 0482241106800?796163008H c0057 79 6163 0088 rac +6I1954195C 0483241107800?796173006E c0058 79 6173 0065 ral +6I1954195C 0484241108800?796174006G c0059 79 6174 0067 ram +6I1954195C 0485241109800?796184006? c0060 79 6184 0060 rau +6I1954195C 0486241110800?796279101B c0061 79 6279 1012 rbr +6I1954195C 0487241111800?796364007? c0062 79 6364 0070 rcd +6I1954195C 0488241112800?796391007B c0063 79 6391 0072 rc1 +6I1954195C 0489241113800?796392007E c0064 79 6392 0075 rc2 +6I1954195C 0490241114800?796393007H c0065 79 6393 0078 rc3 +6I1954195C 0491241115800?796482008F c0066 79 6482 0086 rds +6I1954195C 0492241116800?796491007? c0067 79 6491 0070 rd1 +6I1954195C 0493241117800?796492007C c0068 79 6492 0073 rd2 +6I1954195C 0494241118800?796493007F c0069 79 6493 0076 rd3 +6I1954195C 0495241119800?796567100D c0070 79 6567 1004 reg +6I1954195C 0496241120800?796573101? c0071 79 6573 1010 rel +6I1954195C 0497241121800?796578101A c0072 79 6578 1011 req +6I1954195C 0498241122800?797788007I c0073 79 7788 0079 rpy +6I1954195C 0499241123800?798261008A c0074 79 8261 0081 rsa +6I1954195C 0500241124800?798262008C c0075 79 8262 0083 rsb +6I1954195C 0501241125800?798263008I c0076 79 8263 0089 rsc +6I1954195C 0502241126800?798273006F c0077 79 8273 0066 rsl +6I1954195C 0503241127800?798274006H c0078 79 8274 0068 rsm +6I1954195C 0504241128800?798284006A c0079 79 8284 0061 rsu +6I1954195C 0505241129800?798361000E c0080 79 8361 0005 rta +6I1954195C 0506241130800?798363000C c0081 79 8363 0003 rtc +6I1954195C 0507241131800?798375000D c0082 79 8375 0004 rtn +6I1954195C 0508241132800?798664005E c0083 79 8664 0055 rwd +6I1954195C 0509241133800?826383003F c0084 82 6383 0036 sct +6I1954195C 0510241134800?826461002B c0085 82 6461 0022 sda +6I1954195C 0511241135800?826482008E c0086 82 6482 0085 sds +6I1954195C 0512241136800?826583002G c0087 82 6583 0027 set +6I1954195C 0513241137800?826961002C c0088 82 6961 0023 sia +6I1954195C 0514241138800?826962002H c0089 82 6962 0028 sib +6I1954195C 0515241139800?827376001F c0090 82 7376 0016 slo +6I1954195C 0516241140800?827383003E c0091 82 7383 0035 slt +6I1954195C 0517241141800?827473001H c0092 82 7473 0018 sml +6I1954195C 0518241142800?827964003A c0093 82 7964 0031 srd +6I1954195C 0519241143800?827983003? c0094 82 7983 0030 srt +6I1954195C 0520241144800?828364002D c0095 82 8364 0024 std +6I1954195C 0521241145800?828369002I c0096 82 8369 0029 sti +6I1954195C 0522241146800?828373002? c0097 82 8373 0020 stl +6I1954195C 0523241147800?828384002A c0098 82 8384 0021 stu +6I1954195C 0524241150800?828477001A c0101 82 8477 0011 sup +6I1954195C 0525241151800?828761005A c0102 82 8761 0051 sxa +6I1954195C 0526241152800?828762005C c0103 82 8762 0053 sxb +6I1954195C 0527241153800?828763005I c0104 82 8763 0059 sxc +6I1954195C 0528241154800?828875100F c0105 82 8875 1006 syn +6I1954195C 0529241155800?837384008D c0106 83 7384 0084 tlu +6I1954195C 0530241156800?846661000B c0107 84 6661 0002 ufa +6I1954195C 0531241157800?866482008G c0108 86 6482 0087 wds +6I1954195C 0532241158800?867991007A c0109 86 7991 0071 wr1 +6I1954195C 0533241159800?867992007D c0110 86 7992 0074 wr2 +6I1954195C 0534241160800?867993007G c0111 86 7993 0077 wr3 +6I1954195C 0535241161800?868361000G c0112 86 8361 0007 wta +6I1954195C 0536241162800?868374005F c0113 86 8374 0056 wtm +6I1954195C 0537241163800?868375000F c0114 86 8375 0006 wtn +6I1954195C 0538241164800?999999000A c0115 99 9999 0001 table end +0?0000800? 0539 1 +0?0000800? 0540 1 sub 1 store k in fwa to lwa +0?0000800? 0541 1 +0?0000800? 0542 hed1 +6I1954195C 0543241600800?241196119I subr1stdexitx store exit +6I1954195C 0544241199800?211961136D stuxxxx1 store k +6I1954195C 0545241364800?691217117? lddfwa set +6I1954195C 0546241170800?221217122? sdafwa fwa +6I1954195C 0547241220800?350004118A slt 0004 lwa +6I1954195C 0548241181800?221962151E sdaxxxx2 addresses +6I1954195C 0549241515800?601217142A raufwa +6I1954195C 0550241421800?151961800C aloxxxx1 8003 +6I1954800? 0551248003800?209999140B 8003stl 9999 next store k +6I1954195C 0552241402800?111962126G next supxxxx2 end of +6I1954195C 0553241267800?441471119F nzu exitx loop test +6I1954195C 0554241471800?108001137I aup 8001 +6I1954195C 0555241379800?101020800C aup1dxxx 8003 step +0?0000800? 0556 1 +6I1954195C 0557241217800?209998140B fwa stl 9998 next constants +6I1954195C 0558241962800?010000196B xxxx2 01 0000 xxxx2 eraseable +0?0000800? 0559 hed +0?0000800? 0560 1 +0?0000800? 0561 1 sub 2 reserve unreserve +0?0000800? 0562 1 +0?0000800? 0563 hed2 +6I1954195C 0564241503800?241813131F sub2rstdexity reserve +6I1954195C 0565241316800?691769147B lddz ru entry +6I1954195C 0566241603800?241813136F sub2ustdexity unreserve +6I1954195C 0567241366800?691565147B ldd1i ru entry +6I1954195C 0568241472800?241246129I ru stdw set w +6I1954195C 0569241299800?201653155F stln store n +6I1954195C 0570241556800?168001191C slo 8001 calc ao +6I1954195C 0571241913800?108003157A aup 8003 and po +6I1954195C 0572241571800?300003147I srt 0003 +6I1954195C 0573241479800?211284128G stux +6I1954195C 0574241287800?118001124E sup 8001 +6I1954195C 0575241245800?350001145A slt 0001 +6I1954195C 0576241451800?211606160I stup +6I1954195C 0577241609800?118001136G sup 8001 +6I1954195C 0578241367800?350002147C slt 0002 +6I1954195C 0579241473800?108003128A aup 8003 +6I1954195C 0580241281800?101284123I aupx +6I1954195C 0581241239800?151606171A alop +6I1954195C 0582241711800?350004162A slt 0004 +6I1954195C 0583241621800?151506176A aloc1 +6I1954195C 0584241761800?200901155D stlb0002 +6I1954195C 0585241554800?691188129A lddc2 +6I1954195C 0586241291800?221231133D sdaspr +6I1954195C 0587241334800?101337142C aupc3 su +6I1954195C 0588241423800?211401160D su stusa +6I1954195C 0589241604800?101558800C aupc4 8003 +6I1954800? 0590248003800?659992090A 8003ral 9992 b0002 +6I1954195C 0591240901800?350009152A b0002slt 0009 xx +6I1954195C 0592241521800?211176142I xx stuuh +6I1954195C 0593241429800?350001118E slt 0001 +6I1954195C 0594241185800?658002129C ral 8002 +6I1954195C 0595241293800?101246135A aupw +6I1954195C 0596241351800?300001190G srt 0001 +6I1954195C 0597241907800?101176123A aupuh spr +6I1954195C 0598241231800?300009140A spr srt 0009 sa +6I1954195C 0599241401800?209983090? sa stl 9983 b0001 +6I1954195C 0600240900800?651653130H b0001raln is n zero +6I1954195C 0601241308800?451362181C nze exity +6I1954195C 0602241362800?161565166I slo1i reduce n +6I1954195C 0603241669800?201653145F stln by 1 +6I1954195C 0604241456800?601401170E rausa is ai +6I1954195C 0605241705800?111358186C supa197 in last +6I1954195C 0606241863800?461266131G bmi tp block of +6I1954195C 0607241266800?101719142C aupa201 su 4 +0?0000800? 0608 1 +6I1954195C 0609241317800?651231123E tp ralspr is p 9 +6I1954195C 0610241235800?161188134C sloc2 +6I1954195C 0611241343800?451296129G nze zp +6I1954195C 0612241296800?151249170C aloc5 step p +6I1954195C 0613241703800?691506150I lddc1 +6I1954195C 0614241509800?220901145D sdab0002 +6I1954195C 0615241454800?201231118D stlspr +6I1954195C 0616241184800?601401175E rausa reduce ai +6I1954195C 0617241755800?111408142C supc6 su by 196 +0?0000800? 0618 1 +6I1954195C 0619241297800?691506155I zp lddc1 set p +6I1954195C 0620241559800?240901150D stdb0002 to zero +6I1954195C 0621241504800?691458166A lddc7 +6I1954195C 0622241661800?241231123D stdspr +6I1954195C 0623241234800?601401180E rausa reduce ai +6I1954195C 0624241805800?111508142C supc8 su by 195 +0?0000800? 0625 1 +6I1954195C 0626241506800?350000152A c1 slt 0000 xx constants +6I1954195C 0627241188800?300009140A c2 srt 0009 sa +6I1954195C 0628241337800?200600090? c3 stla0001 b0001 +6I1954195C 0629241558800?450000000A c4 45 0000 0001 +6I1954195C 0630241565800?000000000A 1i 00 0000 0001 +6I1954195C 0631241358800?200796090? a197 stla0197 b0001 +6I1954195C 0632241719800?200800090? a201 stla0201 b0001 +6I1954195C 0633241249800?300010140A c5 srt 0010 sa +6I1954195C 0634241408800?000196000? c6 00 0196 0000 +6I1954195C 0635241458800?300000140A c7 srt 0000 sa +6I1954195C 0636241508800?000195000? c8 00 0195 0000 +6I1954195C 0637241769800?000000000? z 00 0000 0000 +6I1954195C 0638241246800?010000124F w 01 0000 w eraseable +6I1954195C 0639241653800?010000165C n 01 0000 n +6I1954195C 0640240901800?010000090A b0002 01 0000 b0002 +6I1954195C 0641241231800?010000123A spr 01 0000 spr +6I1954195C 0642241401800?010000140A sa 01 0000 sa +6I1954195C 0643241176800?010000117F uh 01 0000 uh +6I1954195C 0644241284800?010000128D x 01 0000 x +0?0000800? 0645 hed +0?0000800? 0646 1 +0?0000800? 0647 1 sub 3 process op code +0?0000800? 0648 1 +0?0000800? 0649 hed3 +6I1954195C 0650240996800?241196134I subr3stdexitx store exit +6I1954195C 0651241349800?651954165I ral 1954 +6I1954195C 0652241659800?300004181I srt 0004 is op +6I1954195C 0653241819800?451522101C nze illop blank +6I1954195C 0654241522800?350006138G slt 0006 is op +6I1954195C 0655241387800?441341119B nzu num numeric +6I1954195C 0656241341800?300002134G srt 0002 +6I1954195C 0657241347800?201961141D stlxxxx1 search +6I1954195C 0658241414800?168001167A slo 8001 symbolic +6I1954195C 0659241671800?841050185E tluc0001 op table +6I1954195C 0660241855800?151608800B alo1 8002 +6I1954800? 0661248002800?659997150A 8002ral 9997 next is +6I1954195C 0662241501800?161961161E next sloxxxx1 sym op +6I1954195C 0663241615800?350006152I slt 0006 legal +6I1954195C 0664241529800?441013138D nzuillop +6I1954195C 0665241384800?350001139A slt 0001 test for +6I1954195C 0666241391800?441295134F nzupseu pseudo op +6I1954195C 0667241346800?350001175C slt 0001 sno store num +6I1954195C 0668241753800?201983123F sno stlp0007 650 op +6I1954195C 0669241236800?300004139G srt 0004 get optim +6I1954195C 0670241397800?151650800B alo3 8002 constants +6I1954800? 0671248002800?699996139I 8002ldd 9996 nex +6I1954195C 0672241399800?241452119F nex stdoptim exitx +0?0000800? 0673 1 +6I1954195C 0674241192800?161345144I num slo4 form +6I1954195C 0675241449800?350002190E slt 0002 numeric +6I1954195C 0676241905800?168002196C slo 8002 op +6I1954195C 0677241963800?300001186I srt 0001 code +6I1954195C 0678241869800?158001175C alo 8001 sno +0?0000800? 0679 1 +6I1954195C 0680241013800?651986144A illopralp0010 illegal op +6I1954195C 0681241441800?151194149I alo5 set 8 +6I1954195C 0682241499800?201986128I stlp0010 for blank +6I1954195C 0683241289800?691242139I ldd6 nex op +0?0000800? 0684 1 +6I1954195C 0685241295800?350003180C pseu slt 0003 pseudo +6I1954195C 0686241803800?151196155A aloexitx op +6I1954195C 0687241551800?150992800B alo1ixxx 8002 +0?0000800? 0688 1 +6I1954195C 0689241608800?650000150A 1 ral 0000 next constants +6I1954195C 0690241700800?100000000? 2 10 0000 0000 +6I1954195C 0691241650800?690800139I 3 lddn0001 nex +6I1954195C 0692241345800?909000000? 4 90 9000 0000 +6I1954195C 0693241194800?000000000H 5 00 0000 0008 +6I1954195C 0694241242800?550505099I 6 55 0505 0999 +0?0000800? 0695 hed +0?0000800? 0696 1 +0?0000800? 0697 1 sub 4 what is address +0?0000800? 0698 1 +0?0000800? 0699 hed4 +6I1954195C 0700241213800?241416191I subr4stdexitz store exit +6I1954195C 0701241919800?211961146D stuxxxx1 store addr +6I1954195C 0702241464800?300008133C srt 0008 is c5 +6I1954195C 0703241333800?441437141F nzu exitz blank +6I1954195C 0704241437800?211962166E stuxxxx2 save c5 +6I1954195C 0705241665800?608002152C rau 8002 are low 4 +6I1954195C 0706241523800?101178138C aup90xxx characters +6I1954195C 0707241383800?471286128F bovloop loop numeric +6I1954195C 0708241286800?101339139C loop auph1 +6I1954195C 0709241393800?471396099H bov sym +6I1954195C 0710241396800?350002185C slt 0002 +6I1954195C 0711241853800?441286165H nzuloop +6I1954195C 0712241658800?651962141G ralxxxx2 low 4 num +6I1954195C 0713241417800?161178143C slo90xxx is c5 +6I1954195C 0714241433800?461336099H bmi sym alphabetic +6I1954195C 0715241336800?151189144C alo29xxx +6I1954195C 0716241443800?460998144G bmisym +6I1954195C 0717241447800?650992149G ral1ixxx regional +6I1954195C 0718241497800?101961171E aupxxxx1 aex +6I1954195C 0719241715800?151416172A aex aloexitz +6I1954195C 0720241721800?168002800A slo 8002 8001 +6I1954195C 0721240998800?601961176E sym rauxxxx1 hed symbol +6I1954195C 0722241765800?691018166C ldd sub15 +6I1954195C 0723241018800?151771142E alo2ixxx step exit +6I1954195C 0724241425800?211230171E stuhsymb aex +6I1954195C 0725241339800?100000000? h1 10 0000 0000 +6I1954195C 0726241230800?010000123? hsymb 01 0000 hsymb eraseable +0?0000800? 0727 hed +0?0000800? 0728 1 +0?0000800? 0729 1 sub 5 test absolute address +0?0000800? 0730 1 +0?0000800? 0731 hed5 +6I1954195C 0732241750800?241416196I subr5stdexitz store exit +6I1954195C 0733241969800?201961151D stlxxxx1 store a +6I1954195C 0734241514800?350004147E slt 0004 +6I1954195C 0735241475800?168002148C slo 8002 +6I1954195C 0736241483800?841200165F tlur0001 tlu +6I1954195C 0737241656800?151709800B aloget 8002 range +6I1954800? 0738248002800?609972117G 8002rau 9972 x table +6I1954195C 0739241177800?350006149A x slt 0006 +6I1954195C 0740241491800?300006170F srt 0006 +6I1954195C 0741241706800?101416182A aupexitz +6I1954195C 0742241821800?151961181E aloxxxx1 +6I1954195C 0743241815800?118003800A sup 8003 8001 +6I1954195C 0744241709800?600000117G get rau 0000 x +6I1954195C 0745241200800?001999000? r0001 00 1999 0000 range +6I1954195C 0746241201800?007999000C r0002 00 7999 0003 table +6I1954195C 0747241202800?008003000A r0003 00 8003 0001 +6I1954195C 0748241203800?008004000C r0004 00 8004 0003 +6I1954195C 0749241204800?008007000A r0005 00 8007 0001 +6I1954195C 0750241205800?008999000C r0006 00 8999 0003 +6I1954195C 0751241206800?009059000B r0007 00 9059 0002 +6I1954195C 0752241207800?999999000C r0008 99 9999 0003 +0?0000800? 0753 hed +0?0000800? 0754 1 +0?0000800? 0755 1 sub 6 symbol test routine +0?0000800? 0756 1 +0?0000800? 0757 hed6 +6I1954195C 0758241275800?241416132? subr6stdexitz store exit +6I1954195C 0759241320800?211601165D stus store symb +6I1954195C 0760241654800?691758186A lddswof set switch +6I1954195C 0761241861800?241610176D stdsw off +6I1954195C 0762241764800?191517123H mpysc scramble +6I1954195C 0763241238800?658002154G ral 8002 symbol +6I1954195C 0764241547800?350003180F slt 0003 giving +6I1954195C 0765241806800?191759133? mpycf lo +6I1954195C 0766241330800?300001158G srt 0001 +6I1954195C 0767241587800?350004159G slt 0004 set +6I1954195C 0768241597800?151850185F alol1p1 test +6I1954195C 0769241856800?201865116H stllop1 word +6I1954195C 0770241168800?161020152E slo1dxxx +6I1954195C 0771241525800?201903148G stllo sli save lo +6I1954195C 0772241487800?201614800A sli stlli 8001 init li +6I1954800? 0773248001800?659990139E 8001ral 9990 a is cont of +6I1954195C 0774241395800?451098154I a nze und li zero +6I1954195C 0775241098800?161601175F slos is cont of +6I1954195C 0776241756800?451610181A nzesw def li symb +6I1954195C 0777241610800?651614127? sw ralli off is li +6I1954195C 0778241270800?161573122G off slolmax maximum +6I1954195C 0779241227800?451280133A nze max +6I1954195C 0780241280800?151533148G alolmp1 sli step li +6I1954195C 0781241800800?161903170H on slolo is li equa +6I1954195C 0782241708800?451412166D nze swsym to lo +6I1954195C 0783241412800?151865148G alolop1 sli step li +6I1954195C 0784241331800?691434153G max lddswon set +6I1954195C 0785241537800?241610171D stdsw switch on +6I1954195C 0786241714800?651467148G rall1 sli zero li +0?0000800? 0787 1 +6I1954195C 0788241549800?651416187A und ralexitz undefined +6I1954195C 0789241871800?150992164G alo1ixxx step +6I1954195C 0790241647800?201416137? stlexitz exit +6I1954195C 0791241370800?651614142? ralli +6I1954195C 0792241420800?161467192A slol1 +6I1954195C 0793241921800?201575127H stllsymb asu +0?0000800? 0794 1 +6I1954195C 0795241811800?651614147? def ralli defined +6I1954195C 0796241470800?691278138A lddasu subr8 get +6I1954195C 0797241278800?101601141F asu aups exitz equivalent +0?0000800? 0798 1 +6I1954195C 0799241664800?010111121H swsymhlt 0111 symof s tab full +6I1954195C 0800241218800?691971122D symoflddsymon set sw sym +6I1954195C 0801241224800?241664197A stdswsym symon on +6I1954195C 0802241971800?651416157B symonralexitz +6I1954195C 0803241572800?151771800B alo2ixxx 8002 +0?0000800? 0804 1 +6I1954195C 0805241758800?651614127? swof ralli off constants +6I1954195C 0806241434800?651614180? swon ralli on +6I1954195C 0807241517800?100100100A sc 10 0100 1001 +6I1954195C 0808241759800?000000000D cf 00 0000 0004 +6I1954195C 0809241467800?650000139E l1 ral 0000 a +6I1954195C 0810241850800?650001139E l1p1 ral 0001 a +6I1954195C 0811241573800?650399139E lmax rale0000 a +6I1954195C 0812241533800?650400139E lmp1 rale0001 a +6I1954195C 0813241601800?010000160A s 01 0000 s erasable +6I1954195C 0814241610800?010000161? sw 01 0000 sw +6I1954195C 0815241903800?010000190C lo 01 0000 lo +6I1954195C 0816241614800?010000161D li 01 0000 li +6I1954195C 0817241575800?010000157E lsymb 01 0000 lsymb +0?0000800? 0818 hed +0?0000800? 0819 1 +0?0000800? 0820 1 sub 7 store symbol and equiv +0?0000800? 0821 1 +0?0000800? 0822 hed7 +6I1954195C 0823241279800?241416152? subr7stdexitz store exit +6I1954195C 0824241520800?691623122F lddss +6I1954195C 0825241226800?221962800A sdaxxxx2 8001 store +6I1954800? 0826248001800?219988154A 8001stu 9988 a symbol +6I1954195C 0827241541800?118001159I a sup 8001 +6I1954195C 0828241599800?201961181D stlxxxx1 save e +6I1954195C 0829241814800?300004162E srt 0004 +6I1954195C 0830241625800?141771123B div2ixxx calculate +6I1954195C 0831241232800?350004149C slt 0004 location +6I1954195C 0832241493800?151446165A aloc1 of +6I1954195C 0833241651800?691704180H lddc2 e +6I1954195C 0834241808800?221911186D sdasel and +6I1954195C 0835241864800?691617162? lddc3 store +6I1954195C 0836241620800?221673127F sdaser +6I1954195C 0837241276800?201431148D stlobee +6I1954195C 0838241484800?168001159A slo 8001 +6I1954195C 0839241591800?151961143A aloxxxx1 obee +6I1954195C 0840241431800?699986138I obee ldd 9986 b +6I1954195C 0841241389800?441673124D b nzuser +6I1954195C 0842241244800?350004191A slt 0004 sel +6I1954195C 0843241623800?219987154A ss stu 9987 a constants +6I1954195C 0844241446800?690400138I c1 ldde0001 b +6I1954195C 0845241704800?229985141F c2 sda 9985 exitz +6I1954195C 0846241617800?239984141F c3 sia 9984 exitz +6I1954195C 0847241431800?010000143A obee 01 0000 obee erasable +6I1954195C 0848241911800?010000191A sel 01 0000 sel +6I1954195C 0849241673800?010000167C ser 01 0000 ser +0?0000800? 0850 hed +0?0000800? 0851 1 +0?0000800? 0852 1 sub 8 given sym loc get equiv +0?0000800? 0853 1 +0?0000800? 0854 hed8 +6I1954195C 0855241381800?241534163G subr8stdexit store exit +6I1954195C 0856241637800?698003129D ldd 8003 +6I1954195C 0857241294800?221575132H sdalsymb store l +6I1954195C 0858241328800?658001128E ral 8001 +6I1954195C 0859241285800?141288114H div2dxxx +6I1954195C 0860241148800?350004180I slt 0004 +6I1954195C 0861241809800?151462800B aloe1 8002 +6I1954800? 0862248002800?699975137H 8002ldd 9975 tr +6I1954195C 0863241378800?441481128B tr nzu lh +6I1954195C 0864241481800?678001143I ram 8001 lr get e rh +6I1954195C 0865241282800?678001148I lh ram 8001 get e lh +6I1954195C 0866241489800?300004143I srt 0004 lr +6I1954195C 0867241439800?698003149F lr ldd 8003 +6I1954195C 0868241496800?231223132F siaequiv +6I1954195C 0869241326800?651575153D rallsymb exit +6I1954195C 0870241462800?690400137H e1 ldde0001 tr constant +6I1954195C 0871241534800?010000153D exit 01 0000 exit eraseable +6I1954195C 0872241223800?010000122C equiv 01 0000 equiv +0?0000800? 0873 hed +0?0000800? 0874 1 +0?0000800? 0875 1 sub 9 calculate reg address +0?0000800? 0876 hed9 +6I1954195C 0877241174800?241416167? subr9stdexitz store exit +6I1954195C 0878241670800?300008153I srt 0008 +6I1954195C 0879241539800?658003169G ral 8003 +6I1954195C 0880241697800?350004185H slt 0004 +6I1954195C 0881241858800?151512800B aloc 8002 is +6I1954800? 0882248002800?659991144E 8002ral 9991 nex region +6I1954195C 0883241445800?901649170A nex bdoill defined +6I1954195C 0884241701800?350001190H slt 0001 +6I1954195C 0885241908800?658002166G ral 8002 +6I1954195C 0886241667800?300001172C srt 0001 +6I1954195C 0887241723800?691416172? lddexitz +6I1954195C 0888241720800?961773167E bd6 l +6I1954195C 0889241773800?951376142H bd5d i +6I1954195C 0890241675800?151957156B l alo 1957 all +6I1954195C 0891241376800?151958156B d alo 1958 all +6I1954195C 0892241428800?151959156B i alo 1959 all +6I1954195C 0893241562800?160992174G all slo1ixxx +6I1954195C 0894241747800?461649141F bmiill exitz +6I1954195C 0895241649800?651416162B ill ralexitz undefined +6I1954195C 0896241622800?150992800B alo1ixxx 8002 or illeg +0?0000800? 0897 1 +6I1954195C 0898241512800?650960144E c ral 0960 nex constant +0?0000800? 0899 hed +0?0000800? 0900 1 sub 10 set cc 8 and punch +0?0000800? 0901 1 +6I1954195C 0902241405800?151986164A sub10alop0010 +6I1954195C 0903241641800?151344169I alo84th +6I1954195C 0904241699800?201986158I stlp0010 +6I1954195C 0905241589800?711977800C pchp0001 8003 +0?0000800? 0906 1 +6I1954195C 0907241344800?000800000? 84th 00 0800 0000 constant +0?0000800? 0908 1 +0?0000800? 0909 1 sub 11 find and reserve best +0?0000800? 0910 1 +0?0000800? 0911 hed0 +6I1954195C 0912241801800?691212196E sub11ldddrumt test +6I1954195C 0913241965800?901770182? bdo sex drum tag +6I1954195C 0914241770800?201725147H stlexit is adr l +6I1954195C 0915241478800?961531163C bd6di +6I1954195C 0916241633800?658003174A ral 8003 ssw l +6I1954195C 0917241531800?691634178G di lddf d or i +6I1954195C 0918241787800?221961196D sdaxxxx1 sub13 find optim +6I1954195C 0919241851800?350004176B gda slt 0004 dynam adr +6I1954195C 0920241762800?158002167B alo 8002 +6I1954195C 0921241672800?158002174A alo 8002 ssw +6I1954195C 0922241741800?691444179G ssw lddoff set sw off +6I1954195C 0923241797800?241584183G stdsw +6I1954195C 0924241837800?151290149E aloa1p1 get table +6I1954195C 0925241495800?201915126H stlbp1 start addr +6I1954195C 0926241268800?161020177E slo1dxxx +6I1954195C 0927241775800?201804161B stlao sai save ao +6I1954195C 0928241612800?201687800A sai stlai 8001 +6I1954800? 0929248001800?609975157I 8001rau 9975 ta is locat +6I1954195C 0930241579800?441583158D ta nzuyes sw available +6I1954195C 0931241584800?601687169A sw rauai swof +6I1954195C 0932241691800?161394174I swof sloamax is ai max +6I1954195C 0933241749800?451502175D nze max +6I1954195C 0934241502800?151906161B aloamp1 sai step ai +6I1954195C 0935241751800?161804185I swon sloao is ai equa +6I1954195C 0936241859800?451662191D nze full to ao +6I1954195C 0937241662800?151915161B alobp1 sai step ai +6I1954195C 0938241754800?691909171B max lddon set sw on +6I1954195C 0939241712800?241584173G stdsw +6I1954195C 0940241737800?651240161B rala1 sai set ai to +0?0000800? 0941 1 +6I1954195C 0942241914800?010222131H full hlt 0222 drum paked +6I1954195C 0943241318800?691216187? lddh9xxx set drum +6I1954195C 0944241870800?241212146F stddrumt tag to 9 +6I1954195C 0945241466800?651725182? ralexit sex step exit +6I1954195C 0946241820800?150992800B sex alo1ixxx 8002 +0?0000800? 0947 1 +6I1954195C 0948241583800?360000166? yes sct 0000 reserve +6I1954195C 0949241660800?350001171G slt 0001 location +6I1954195C 0950241717800?300001182C srt 0001 found +6I1954195C 0951241823800?201962151F stlxxxx2 save p +6I1954195C 0952241516800?118003187C sup 8003 +6I1954195C 0953241873800?350004168C slt 0004 +6I1954195C 0954241683800?108001179A aup 8001 +6I1954195C 0955241791800?151494800B alosrp 8002 +6I1954800? 0956248002800?300009172B 8002srt 0009 sca nulify sct +6I1954195C 0957241722800?608003162I sca rau 8003 +6I1954195C 0958241629800?151687184A aloai +6I1954195C 0959241841800?691544184G lddst +6I1954195C 0960241847800?221901800A sdaeras 8001 +6I1954800? 0961248001800?219972182E 8001stu 9972 ca +6I1954195C 0962241825800?118001173C ca sup 8001 calculate +6I1954195C 0963241733800?161240154E sloa1 location +6I1954195C 0964241545800?300004171? srt 0004 found +6I1954195C 0965241710800?141616142F div4i +6I1954195C 0966241426800?191679155B mpy500 +6I1954195C 0967241552800?158003176? alo 8003 +6I1954195C 0968241760800?118001176G sup 8001 +6I1954195C 0969241767800?101962181G aupxxxx2 +6I1954195C 0970241817800?191920134? mpy50 +6I1954195C 0971241340800?158003189G alo 8003 +6I1954195C 0972241897800?118001172E sup 8001 exit +6I1954195C 0973241634800?000000185A f 00 0000 gda constants +6I1954195C 0974241444800?651687169A off ralai swof +6I1954195C 0975241290800?600601157I a1p1 raua0002 ta +6I1954195C 0976241394800?600799157I amax raua0200 ta +6I1954195C 0977241906800?600800157I amp1 raua0201 ta +6I1954195C 0978241909800?651687175A on ralai swon +6I1954195C 0979241240800?600600157I a1 raua0001 ta +6I1954195C 0980241494800?300000172B srp srt 0000 sca +6I1954195C 0981241544800?219999182E st stu 9999 ca +6I1954195C 0982241616800?000000000D 4i 00 0000 0004 +6I1954195C 0983241679800?000000050? 500 00 0000 0500 +6I1954195C 0984241920800?000000005? 50 00 0000 0050 +6I1954195C 0985241602800?658001181? fon ral 8001 stepx +6I1954195C 0986241804800?010000180D ao 01 0000 ao erasable +6I1954195C 0987241687800?010000168G ai 01 0000 ai +6I1954195C 0988241915800?010000191E bp1 01 0000 bp1 +6I1954195C 0989241725800?010000172E exit 01 0000 exit +0?0000800? 0990 hed +0?0000800? 0991 1 +0?0000800? 0992 1 sub 12 set blank l 8 +0?0000800? 0993 1 +6I1954195C 0994240991800?151986189A sub12alop0010 +6I1954195C 0995241891800?151594179I alo87th +6I1954195C 0996241799800?201986800C stlp0010 8003 +0?0000800? 0997 1 +6I1954195C 0998241594800?000000800? 87th 00 0000 8000 constant +0?0000800? 0999 1 +0?0000800? 1000 1 sub 13 cal optimum dynamic adr +0?0000800? 1001 1 +0?0000800? 1002 hedy +6I1954195C 1003241964800?241416197? sub13stdexitz store exit +6I1954195C 1004241970800?951923187E bd5 i d or i +6I1954195C 1005241923800?651452186? raloptim d +6I1954195C 1006241860800?350001186G slt 0001 +6I1954195C 1007241867800?168002192E slo 8002 +6I1954195C 1008241925800?350001158A slt 0001 +6I1954195C 1009241581800?158001163I alo 8001 +6I1954195C 1010241639800?300003194G srt 0003 seo +6I1954195C 1011241875800?651452191? i raloptim i +6I1954195C 1012241910800?921666171F bd2shop shift test +6I1954195C 1013241716800?931772182B bd3xas xas test +6I1954195C 1014241822800?350002194G slt 0002 seo +6I1954195C 1015241947800?201961176F seo stlxxxx1 save ev od +6I1954195C 1016241766800?651872127G ralopreg is base +6I1954195C 1017241277800?141771133B div2ixxx even or od +6I1954195C 1018241332800?608003168I rau 8003 +6I1954195C 1019241689800?151961181F aloxxxx1 +6I1954195C 1020241816800?441922197B nzu rb +6I1954195C 1021241922800?350002172I slt 0002 +6I1954195C 1022241729800?658002197B ral 8002 rb +6I1954195C 1023241972800?300008194A rb srt 0008 get base +6I1954195C 1024241941800?151872132G aloopreg plus delta +6I1954195C 1025241327800?141380139? div50 mod 50 +6I1954195C 1026241390800?658003141F ral 8003 exitz +0?0000800? 1027 1 +6I1954195C 1028241666800?651983188G shop ralp0007 tlu units +6I1954195C 1029241887800?300004199G srt 0004 digit of +6I1954195C 1030241997800?350009191G slt 0009 d address +6I1954195C 1031241917800?168002197E slo 8002 +6I1954195C 1032241975800?841250181B tluu0001 +6I1954195C 1033241812800?151866800B alogu 8002 +6I1954800? 1034248002800?659969197C 8002ral 9969 top +6I1954195C 1035241973800?350002177I top slt 0002 +6I1954195C 1036241779800?691452186B lddoptim is op srd +6I1954195C 1037241862800?931916194G bd3 seo +6I1954195C 1038241916800?350004194G slt 0004 seo srd +0?0000800? 1039 1 +6I1954195C 1040241772800?651983193G xas ralp0007 tlu +6I1954195C 1041241937800?300004119H srt 0004 d address +6I1954195C 1042241198800?350006196F slt 0006 +6I1954195C 1043241966800?168002147F slo 8002 +6I1954195C 1044241476800?841300191B tlui0001 +6I1954195C 1045241912800?151967800B alogxd 8002 +6I1954800? 1046248002800?659968127D 8002ral 9968 nxt +6I1954195C 1047241274800?350004194G nxt slt 0004 seo +0?0000800? 1048 1 +6I1954195C 1049241250800?002322252D u0001 00 2322 2524 shift +6I1954195C 1050241251800?100706070F u0002 10 0706 0706 optimizing +6I1954195C 1051241252800?200706090H u0003 20 0706 0908 table +6I1954195C 1052241253800?300908111? u0004 30 0908 1110 +6I1954195C 1053241254800?401110131B u0005 40 1110 1312 +6I1954195C 1054241255800?501312151D u0006 50 1312 1514 +6I1954195C 1055241256800?601514171F u0007 60 1514 1716 +6I1954195C 1056241257800?701716191H u0008 70 1716 1918 +6I1954195C 1057241258800?801918212? u0009 80 1918 2120 +6I1954195C 1058241259800?902120232B u0010 90 2120 2322 +0?0000800? 1059 1 +6I1954195C 1060241300800?199906060? i0001 19 9906 0600 x accum +6I1954195C 1061241301800?799907070? i0002 79 9907 0700 add sub +6I1954195C 1062241302800?800008080? i0003 80 0008 0800 table +6I1954195C 1063241303800?800106060? i0004 80 0106 0600 +6I1954195C 1064241304800?800209080? i0005 80 0209 0800 +6I1954195C 1065241305800?800308090? i0006 80 0308 0900 +6I1954195C 1066241306800?905908080? i0007 90 5908 0800 +6I1954195C 1067241307800?999909090? i0008 99 9909 0900 +0?0000800? 1068 1 +6I1954195C 1069241866800?650000197C gu ral 0000 top constants +6I1954195C 1070241967800?650000127D gxd ral 0000 nxt +6I1954195C 1071241380800?000000005? 50 00 0000 0050 +0?0000800? 1072 hed +0?0000800? 1073 1 +0?0000800? 1074 1 sub 14 punch avail table +0?0000800? 1075 1 +0?0000800? 1076 hedp +6I1954195C 1077241403800?241196184I sub14stdexitx store exit +6I1954195C 1078241849800?691652136H ldd85th set punch +6I1954195C 1079241368800?241986173I stdp0010 8 +6I1954195C 1080241739800?691292159E ldda1 init a1 +6I1954195C 1081241595800?241961141H stdxxxx1 +6I1954195C 1082241418800?651324182I ralrs1 loop init rs +6I1954195C 1083241829800?101382800A loop aupc1 8001 +6I1954800? 1084248001800?209999170B 8001stl 9999 next set locat +6I1954195C 1085241702800?111468137D next suptw1 +6I1954195C 1086241374800?441377152H nzu srs +6I1954195C 1087241377800?101430133E aupc2 +6I1954195C 1088241335800?151338800C aloc3 8003 +6I1954195C 1089241528800?201962151H srs stlxxxx2 save rs +6I1954195C 1090241518800?601424187I rauc4 +6I1954195C 1091241879800?151961800B aloxxxx1 8002 +6I1954800? 1092248002800?699998800C 8002ldd 9998 8003 store +6I1954800? 1093248003800?249997175B 8003std 9997 tp av table +6I1954195C 1094241752800?111618147D tp suptw2 +6I1954195C 1095241474800?441427157H nzu pun +6I1954195C 1096241427800?101480138E aupc5 +6I1954195C 1097241385800?151388800B aloc6 8002 +6I1954195C 1098241578800?711977147G pun pchp0001 +6I1954195C 1099241477800?161530143E sloaim is ai max +6I1954195C 1100241435800?451438119F nze exitx +6I1954195C 1101241438800?151342124H aloamp1 step ai +6I1954195C 1102241248800?201961166H stlxxxx1 +6I1954195C 1103241668800?651962171H ralxxxx2 +6I1954195C 1104241718800?161524182I sloc7 loop +0?0000800? 1105 1 +6I1954195C 1106241382800?201977170B c1 stlp0001 next constants +6I1954195C 1107241430800?201985170B c2 stlp0009 next +6I1954195C 1108241338800?000500050? c3 00 0500 0500 +6I1954195C 1109241424800?241978175B c4 stdp0002 tp +6I1954195C 1110241480800?241986175B c5 stdp0010 tp +6I1954195C 1111241388800?000001000? c6 00 0001 0000 +6I1954195C 1112241524800?001499149I c7 00 1499 1499 +6I1954195C 1113241468800?201983170B tw1 stlp0007 next +6I1954195C 1114241618800?241984175B tw2 stdp0008 tp +6I1954195C 1115241652800?000080000? 85th 00 0080 0000 +6I1954195C 1116241292800?690600800C a1 ldda0001 8003 +6I1954195C 1117241324800?000000045? rs1 00 0000 0450 +6I1954195C 1118241530800?690799800C aim ldda0200 8003 +6I1954195C 1119241342800?690800800C amp1 ldda0201 8003 +0?0000800? 1120 hed +0?0000800? 1121 1 +0?0000800? 1122 1 sub 15 heading routine +0?0000800? 1123 1 +0?0000800? 1124 hedh +6I1954195C 1125241663800?241813176H sub15stdexity save exit +6I1954195C 1126241768800?698003157D ldd 8003 is c1 +6I1954195C 1127241574800?350008154C slt 0008 blank +6I1954195C 1128241543800?441298134H nzudh +6I1954195C 1129241348800?608001181H rau 8001 head +6I1954195C 1130241818800?101329181C aup0000h exity +6I1954195C 1131241298800?608001181C dh rau 8001 exity dont head +0?0000800? 1132 hed +0?0000800? 1133 1 +0?0000800? 1134 1 sub 16 initialization +0?0000800? 1135 1 +6I1954195C 1136241353800?241813186H sub16stdexity store exit +6I1954195C 1137241868800?651624192I rali1 +6I1954195C 1138241929800?211985148H stup0009 zero card +6I1954195C 1139241488800?241329143B std0000h zero head +6I1954195C 1140241432800?691485160? ldd subr1 zero sym t +6I1954195C 1141241485800?651538159C rali2 make drum +6I1954195C 1142241593800?101546180B aupi3 available +6I1954195C 1143241802800?691918160? ldd subr1 +6I1954195C 1144241918800?691406196H lddh8xxx set drum +6I1954195C 1145241968800?241212167D stddrumt tag to 8 +6I1954195C 1146241674800?691527158? lddi4 set swsym +6I1954195C 1147241580800?241664172D stdswsym off +6I1954195C 1148241724800?651577163A rali5 undefine +6I1954195C 1149241631800?101406177D auph8xxx regions +6I1954195C 1150241774800?691813160? lddexity subr1 +0?0000800? 1151 1 +6I1954195C 1152241624800?000000059I i1 00s0001 e0200 constants +6I1954195C 1153241538800?000600079I i2 00a0001 a0200 +6I1954195C 1154241546800?111111111A i3 11 1111 1111 +6I1954195C 1155241527800?010111121H i4 01 0111 symof +6I1954195C 1156241577800?001021104I i5 00 1021 1049 +6I1954195C 1157241852800?961824187D pacofbd6findi findl +0?0000800? 1158 1 +0?0000800? 1159 1 sub 17 calc 800x equivalent +0?0000800? 1160 1 +0?0000800? 1161 hedx +6I1954195C 1162241902800?691924162G sb17dldddeq di d equiv +6I1954195C 1163241854800?691974162G sb17ilddieq di i equiv +6I1954195C 1164241627800?241961152F di stdxxxx1 save tag +6I1954195C 1165241526800?211813157F stuexity store exit +6I1954195C 1166241576800?201962162F stlxxxx2 store 800x +6I1954195C 1167241626800?691961196D lddxxxx1 sub13 get optim +6I1954195C 1168241904800?201961167F sda stlxxxx1 dynam addr +6I1954195C 1169241676800?141771148B div2ixxx is dy addr +6I1954195C 1170241482800?441535138F nzuod ev even or od +6I1954195C 1171241535800?651588164C od ral8002 eo +6I1954195C 1172241386800?651789164C ev ral8003 eo +6I1954195C 1173241643800?161962172F eo sloxxxx2 +6I1954195C 1174241726800?451630168A nze add1 +6I1954195C 1175241630800?651961181C ralxxxx1 exity +6I1954195C 1176241681800?651961177F add1 ralxxxx1 +6I1954195C 1177241776800?150992181C alo1ixxx exity +0?0000800? 1178 1 +6I1954195C 1179241924800?000008190D deq 00 0008 sda constants +6I1954195C 1180241974800?000009190D ieq 00 0009 sda +6I1954195C 1181241588800?000000800B 8002 00 0000 8002 +6I1954195C 1182241789800?000000800C 8003 00 0000 8003 +0?0000800? 1183 hed +0?0000800? 1184 1 +0?0000800? 1185 1 sub 18 index address +0?0000800? 1186 1 +0?0000800? 1187 hedw +6I1954195C 1188241826800?241813187F indexstdexity store exit +6I1954195C 1189241876800?201961192F stlxxxx1 store addr +6I1954195C 1190241926800?601954197F rau 1954 +6I1954195C 1191241976800?350007169C slt 0007 +6I1954195C 1192241693800?691813167G lddexity +6I1954195C 1193241677800?951680153B bd5d d or i +6I1954195C 1194241532800?350002168? slt 0002 d +6I1954195C 1195241680800?300009172G d srt 0009 +6I1954195C 1196241727800?191014168D mpy2000i +6I1954195C 1197241684800?691813177G lddexity +6I1954195C 1198241777800?961730158B bd6ds drum 0 cor +6I1954195C 1199241582800?300001173? srt 0001 ds core +6I1954195C 1200241730800?151961181C ds aloxxxx1 exity +0?0000800? 1201 1 +6I1954195C 1202241813800?010000181C exity 01 0000 exity erasabele +0?0000800? 1203 hed +0?0000800? 1204 1 +0?0000800? 1205 1 sub 19 process location +0?0000800? 1206 1 +0?0000800? 1207 regd0923 0923 proc l +0?0000800? 1208 regg0925 0925 +0?0000800? 1209 regj0928 0928 +0?0000800? 1210 regk0931 0931 +0?0000800? 1211 regl0933 0933 +0?0000800? 1212 1 +0?0000800? 1213 heda +6I1954195C 1214240969800?241196189I proclstdexitx store exit +6I1954195C 1215241899800?601951182G rau 1951 is l blank +6I1954195C 1216241827800?441731163B nzunb +6I1954195C 1217241632800?691212187G ldddrumt blank test +6I1954195C 1218241877800?901781092D bdob d0002 drum tag +6I1954195C 1219241781800?651872192G b ralopreg setl blank +6I1954195C 1220241927800?350004198G setl slt 0004 set l +6I1954195C 1221241987800?691984163H lddp0008 to dr +6I1954195C 1222241638800?221984119F sdap0008 exitx +6I1954195C 1223241731800?691734121C nb lddg subr4 what is l +6I1954195C 1224240925800?651957093A g0001ral 1957 k0001 absolute +6I1954195C 1225240926800?691780117D g0002lddk subr9 regional +6I1954195C 1226240927800?691830127E g0003lddj subr6 symbolic +6I1954195C 1227240931800?691784175? k0001lddl subr5 test range +6I1954195C 1228240932800?601585183I k0002rau87th x reg error +6I1954195C 1229241839800?101986139B x aupp0010 set blank +6I1954195C 1230241392800?211986192G stup0010 setl l8 +6I1954195C 1231240933800?201872192G l0001stlopreg setl drum addr +6I1954195C 1232240934800?101688174C l0002aup86th 800x 800x +6I1954195C 1233240935800?691738144B l0003lddorceq 89x core addr +6I1954195C 1234240936800?601585183I l0004rau87th x other +6I1954195C 1235241743800?691596144B 800x lddorxeq 89x +6I1954195C 1236241442800?241872183I 89x stdopreg x +6I1954195C 1237240928800?651223093A j0001ralequiv k0001 sym defind +6I1954195C 1238240929800?651682180A j0002rald sub11 sym undef +6I1954195C 1239240930800?601585183I j0003rau87th x s tab full +6I1954195C 1240240923800?201872162H d0001stlopreg ss s eq found +6I1954195C 1241240924800?601585183I d0002rau87th x drum paked +6I1954195C 1242241628800?101230163E ss auphsymb store +6I1954195C 1243241635800?151575188? alolsymb symbol +6I1954195C 1244241880800?691781127I lddb subr7 +0?0000800? 1245 1 +6I1954195C 1246241734800?000000092E g 00 0000 g0001 constants +6I1954195C 1247241780800?000090093A k 00 0090 k0001 +6I1954195C 1248241830800?000000092H j 00 0000 j0001 +6I1954195C 1249241784800?000000093C l 00 0000 l0001 +6I1954195C 1250241682800?000090092C d 00 0090 d0001 +6I1954195C 1251241688800?000008000? 86th 00 0008 0000 +6I1954195C 1252241585800?000000800? 87th 00 0000 8000 +6I1954195C 1253241196800?010000119F exitx 01 0000 exitx eraseable +0?0000800? 1254 hed +0?0000800? 1255 1 +0?0000800? 1256 1 sub 20 process data address +0?0000800? 1257 1 +0?0000800? 1258 regd0937 0937 proc d +0?0000800? 1259 regf0939 0939 +0?0000800? 1260 regg0941 0941 +0?0000800? 1261 regj0944 0944 +0?0000800? 1262 regk0946 0946 +0?0000800? 1263 regl0949 0949 +0?0000800? 1264 1 +0?0000800? 1265 hedb +6I1954195C 1266240972800?241196194I procdstdexitx store exit +6I1954195C 1267241949800?601952167H rau 1952 is d blank +6I1954195C 1268241678800?441831173B nzunb +6I1954195C 1269241732800?651685180A rald sub11 find +6I1954195C 1270240937800?201492095B d0001stlorbal l0004 optimum +6I1954195C 1271240938800?601542139H d0002rau88th x drum paked +6I1954195C 1272241728800?691452177H bt lddoptim is op +6I1954195C 1273241778800?911196178C bd1exitx a branch +6I1954195C 1274241783800?201872119F stlopreg exitx d to or +6I1954195C 1275241398800?101986159B x aupp0010 set blank +6I1954195C 1276241592800?211986119F stup0010 exitx +6I1954195C 1277241831800?691834121C nb lddg subr4 what is d +6I1954195C 1278240941800?651958094D g0001ral 1958 j0001 absolute +6I1954195C 1279240942800?691645117D g0002lddj subr9 regional +6I1954195C 1280240943800?691646127E g0003lddk subr6 symbolic +6I1954195C 1281240944800?691448175? j0001lddl subr5 test range +6I1954195C 1282240945800?601542139H j0002rau88th x reg error +6I1954195C 1283240949800?691828182F l0001lddaxd index drum addr +6I1954195C 1284240950800?350004187H l0002slt 0004 800x 800x +6I1954195C 1285240951800?691928182F l0003lddaxc index core addr +6I1954195C 1286240952800?350004193? l0004slt 0004 sd other +6I1954195C 1287241878800?691983143F 800x lddp0007 set 800x d +6I1954195C 1288241436800?221983148F sdap0007 +6I1954195C 1289241486800?300004149H srt 0004 +6I1954195C 1290241498800?101881190B aupxeq sb17d get 800x e +6I1954195C 1291241931800?350004164B scd slt 0004 set core d +6I1954195C 1292241642800?691983153F lddp0007 +6I1954195C 1293241536800?221983158F sdap0007 +6I1954195C 1294241586800?300004154H srt 0004 +6I1954195C 1295241548800?691782196D lddceq sub13 get core e +6I1954195C 1296241832800?201738172H sceq stlorceq bt save core +6I1954195C 1297240946800?651223094D k0001ralequiv j0001 sym defind +6I1954195C 1298240947800?651882180A k0002ralf sub11 sym undef +6I1954195C 1299240948800?601542139H k0003rau88th x s tab full +6I1954195C 1300240939800?201793169F f0001stleq ss save eq +6I1954195C 1301240940800?601542139H f0002rau88th x drum paked +6I1954195C 1302241696800?101230173E ss auphsymb store +6I1954195C 1303241735800?151575193B alolsymb symbol +6I1954195C 1304241932800?691785127I ldd subr7 +6I1954195C 1305241785800?651793095B raleq l0004 +6I1954195C 1306241930800?691983163F sd lddp0007 set d addr +6I1954195C 1307241636800?221983168F sdap0007 +6I1954195C 1308241686800?300004172H srt 0004 bt +6I1954195C 1309241685800?000088093G d 00 0088 d0001 constants +6I1954195C 1310241834800?000000094A g 00 0000 g0001 +6I1954195C 1311241645800?000088094D j 00 0088 j0001 +6I1954195C 1312241448800?000000094I l 00 0000 l0001 +6I1954195C 1313241882800?000088093I f 00 0088 f0001 +6I1954195C 1314241646800?000000094F k 00 0000 k0001 +6I1954195C 1315241828800?000088093G axd 00 0088 d0001 +6I1954195C 1316241928800?000098193A axc 00 0098 scd +6I1954195C 1317241881800?201596172H xeq stlorxeq bt +6I1954195C 1318241782800?000008183B ceq 00 0008 sceq +6I1954195C 1319241542800?000000080? 88th 00 0000 0800 +6I1954195C 1320241793800?010000179C eq 01 0000 eq erasable +0?0000800? 1321 hed +0?0000800? 1322 1 +0?0000800? 1323 1 sub 21 process instr address +0?0000800? 1324 1 +0?0000800? 1325 regd0953 0953 proc i +0?0000800? 1326 regf0955 0955 +0?0000800? 1327 regg0958 0958 +0?0000800? 1328 regj0960 0960 +0?0000800? 1329 regk0962 0962 +0?0000800? 1330 regl0965 0965 +0?0000800? 1331 1 +0?0000800? 1332 hedc +6I1954195C 1333241453800?241196183C procistdexitx store exit +6I1954195C 1334241833800?601953188C rau 1953 is i blank +6I1954195C 1335241883800?441788183H nzunb +6I1954195C 1336241838800?601952193C rau 1952 is d blank +6I1954195C 1337241933800?441888193H nzudnb +6I1954195C 1338241938800?691212188D ldddrumt d i blank +6I1954195C 1339241884800?901988095I bdo g0002 test drum +6I1954195C 1340241988800?651492096H ralorbal l0004 tag +6I1954195C 1341241888800?651692180A dnb rald sub11 find best +6I1954195C 1342240953800?201492096H d0001stlorbal l0004 found +6I1954195C 1343240954800?651986174B d0002ralp0010 x drum paked +6I1954195C 1344241742800?151695193D x alo89th +6I1954195C 1345241934800?201986119F stlp0010 exitx +6I1954195C 1346241788800?691792121C nb lddf subr4 what is i +6I1954195C 1347240955800?651959096? f0001ral 1959 j0001 absolute +6I1954195C 1348240956800?691835117D f0002lddj subr9 regional +6I1954195C 1349240957800?691885127E f0003lddk subr6 symbolic +6I1954195C 1350240960800?691935175? j0001lddl subr5 test range +6I1954195C 1351240961800?651986174B j0002ralp0010 x reg error +6I1954195C 1352240965800?691736182F l0001lddaxd index drum addr +6I1954195C 1353240966800?691983178F l0002lddp0007 800x 800x +6I1954195C 1354240967800?691836182F l0003lddaxc index core addr +6I1954195C 1355240968800?691983188F l0004lddp0007 other +6I1954195C 1356241886800?231983193F siap0007 mor +6I1954195C 1357241786800?231983188I 800x siap0007 +6I1954195C 1358241889800?101842185D aupxeq sb17i get 800x e +6I1954195C 1359241939800?691983198I 90xx lddp0007 set core +6I1954195C 1360241989800?231983144? siap0007 address +6I1954195C 1361241440800?691843196D lddceq sub13 get core e +6I1954195C 1362240962800?651223096? k0001ralequiv j0001 sym defind +6I1954195C 1363240963800?651490180A k0002ralg sub11 sym undef +6I1954195C 1364240964800?651986174B k0003ralp0010 x s tab full +6I1954195C 1365240958800?691983154? g0001lddp0007 si found best +6I1954195C 1366240959800?651986174B g0002ralp0010 x drum paked +6I1954195C 1367241540800?231983159? si siap0007 +6I1954195C 1368241590800?101230164? auphsymb store +6I1954195C 1369241640800?151575169? alolsymb symbol +6I1954195C 1370241690800?691936127I lddmor subr7 +6I1954195C 1371241936800?691492174E mor lddorbal set or +6I1954195C 1372241745800?241872119F stdopreg exitx to orb +6I1954195C 1373241740800?201738193F sceq stlorceq mor save core +0?0000800? 1374 1 +6I1954195C 1375241692800?000089095C d 00 0089 d0001 constants +6I1954195C 1376241792800?000000095E f 00 0000 f0001 +6I1954195C 1377241835800?000089096? j 00 0089 j0001 +6I1954195C 1378241885800?000000096B k 00 0000 k0001 +6I1954195C 1379241935800?000000096E l 00 0000 l0001 +6I1954195C 1380241490800?000089095H g 00 0089 g0001 +6I1954195C 1381241695800?000000008? 89th 00 0000 0080 +6I1954195C 1382241736800?000089096H axd 00 0089 l0004 +6I1954195C 1383241836800?000099193I axc 00 0099 90xx +6I1954195C 1384241842800?201596193F xeq stlorxeq mor +6I1954195C 1385241843800?000009174? ceq 00 0009 sceq +0?0000800? 1386 hed +0?0000800? 1387 1 +6I1954195C 1388240992800?000000000A 1ixxx 00 0000 0001 constants +6I1954195C 1389241020800?000001000? 1dxxx 00 0001 0000 +6I1954195C 1390241771800?000000000B 2ixxx 00 0000 0002 +6I1954195C 1391241288800?000002000? 2dxxx 00 0002 0000 +6I1954195C 1392241406800?800000000? h8xxx 80 0000 0000 +6I1954195C 1393241216800?900000000? h9xxx 90 0000 0000 +6I1954195C 1394241178800?000000009? 90xxx 00 0000 0090 +6I1954195C 1395241189800?000000002I 29xxx 00 0000 0029 +6I1954195C 1396241014800?000000200? 2000i 00 0000 2000 constant +6I1954195C 1397240990800?000000199? torg 00 0000 t0001 +0?0000800? 1398 1 +0?0000800? 1399 pat +0A0000100? 1400 diff --git a/I650/sw/soapII_condensed_card.dck b/I650/sw/soapII_condensed_card.dck new file mode 100644 index 00000000..f0ce4cd7 --- /dev/null +++ b/I650/sw/soapII_condensed_card.dck @@ -0,0 +1,173 @@ +6I195219536919521951241995195469195519566919541953241996195769195880006919561955 +2D19971952691953195469195819572419981955691957195624199919997019950000 +2D000019967000489999240048199765000100302400301998690034003924003919992200440047 +2D004719963500040025240025199715800100312400311998220036003224003219996500350040 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a/I650/sw/soap_and_run.ini b/I650/sw/soap_and_run.ini new file mode 100644 index 00000000..ea845757 --- /dev/null +++ b/I650/sw/soap_and_run.ini @@ -0,0 +1,78 @@ + +; set console -n log=log.txt +; set debug -n debug.txt +; set debug stdout +; set cpu debug=cmd;data;detail + + +; params: %1 source card deck to assemble with soap +; %2 start address to run program (If empty, program not run) +; %3 input card deck (if empty, do not attach input card + +set cpu 2k + +; Load SOAP deck into core (1 word per card format), but does not execute it + +att cdr1 -q soapII.dck + +echo *** +echo *** load soap deck into drum +echo *** + +d csw 7019519999 +d ar 8000 +go + +; now put source cards in reader and start SOAP assembler + +att cdr1 %1 +set cdr1 wiring=soap + +att cdp1 -n -q deck_out.dck +set cdp1 echo, print, wiring=soap +att cdp0 -n -q print.txt + +echo *** +echo *** run soap +echo *** + +d ar 1000 +go + +if "%2" == "" goto end + +; load assembled deck into core + +det cdp1 +set cdr1 wiring=8WORD +att cdr1 deck_out.dck + +att cdp1 -n -q deck_out_run.dck +set cdp1 echo, print, wiring=8WORD + + +echo *** +echo *** load assembled program +echo *** + +d csw 7019519999 +d ar 8000 +go + +; attach input deck +if "%3" == "" goto run + +att cdr1 %3 + +; now execute the loaded deck +:run + +echo *** +echo *** run assembled program +echo *** + +d ar %2 +go + +:end + diff --git a/I650/sw/soap_example_1_src.txt b/I650/sw/soap_example_1_src.txt new file mode 100644 index 00000000..43861e99 --- /dev/null +++ b/I650/sw/soap_example_1_src.txt @@ -0,0 +1,39 @@ + 1 + 1 example 1 calculate f of x + 1 + 1 f(x) = a*x*x+b*x+c + 1 + 1 card output + 1 word1 word2 + 1 x f(x) + 1 + blr 1951 1960 read area + regp0027 0028 punch area + 1 + synstart 1000 prgm start + 1 + startnop 0000 setx + setx rauone stx set x + stx stup0001 to 1 + mpya calculate + alob f + rau 8002 + mpyp0001 + aloc + stlp0002 + pchp0001 punch + raup0001 is x max + supxmax + nzu 9999 + aupi01 stx step x + 1 + one 00 0000 0001 constants + xmax 00 0000 0100 + i01 00 0000 0101 + 1 + a 00 0000 0002 params + b 00 0000 0003 for f(x) + c 00 0000 0004 + 1 + -neg 00 0000 0006 + -negz 00 0000 0000 diff --git a/I650/sw/soap_listing.txt b/I650/sw/soap_listing.txt new file mode 100644 index 00000000..2ec76174 --- /dev/null +++ b/I650/sw/soap_listing.txt @@ -0,0 +1,1449 @@ +1 SOAP 2 +1 +1 SYMBOLIC OPTIMAL ASSEMBLY PROG +1 +1 FOR THE +1 +1 IBM 650 +1 +1 DATA PROCESSING SYSTEM +1 + REG S0000 0399 SYMBOL TAB + REG E0400 0599 EQUIV TABL + REG A0600 0799 AVAIL TABL + REG N0800 0899 NUM OP TAB + BLR 1000 1000 ENTRY + BLR 1001 1012 PSEUDO ENT + BLR 1021 1049 REG TABLE + REG C1050 1164 SYM OP TAB + BLA 1098 1099 + BLA 1148 1149 + BLR 1900 1900 MANUAL PAT + SYN READC 1950 + BLR 1951 1962 READ AREA + REG T1990 1992 TYPE + REG P1977 1986 PUNCH AREA + BLR 1998 1999 + EQU XXXX1 1961 + EQU XXXX2 1962 + BLR 1563 1570 TYPE2 + BLA 1565 1565 + BLA 1569 1569 + REG B0900 0901 SUB 2 + REG H0902 0904 TYPE 2 + REG M0905 0907 + REG Q0908 0909 + REG R1200 1207 SUB 5 + REG U1250 1259 SUB 13 + REG V0910 0912 EQU SYN + REG X0913 0914 TYPE 0 + REG Y0915 0916 EQU SYN + REG Z0917 0919 + REG W0920 0922 + BLR 0923 0968 MULTIPLE R + REG I1300 1307 SUB 13 +1 +1 CONTROL PROGRAM +1 + 1000 LDD READC SUB16 ENTRY 1000 69 1950 1353 +1 + READC RCD 1999 1998 READ CARD 1950 70 1999 1998 + 1998 LDD 1951 TRANSFER 1998 69 1951 1354 + STD P0001 ALPHABETIC 1354 24 1977 0980 + LDD 1952 INPUT 0980 69 1952 1355 + STD P0002 TO 1355 24 1978 0981 + LDD 1953 OUTPUT 0981 69 1953 1356 + STD P0003 1356 24 1979 0982 + LDD 1954 0982 69 1954 1357 + STD P0004 1357 24 1980 0983 + LDD 1955 0983 69 1955 1208 + STD P0005 1208 24 1981 0984 + LDD 1956 0984 69 1956 1209 + STD P0006 1209 24 1982 0985 + RAL P0009 STEP 0985 65 1985 0989 + ALO 1IXXX CARD 0989 15 0992 0997 + STL P0009 NUMBER 0997 20 1985 0988 + RAU 1960 STORE 0988 60 1960 1015 + SRT 0002 CONTROL 1015 30 0002 0971 + STU P0008 INFO 0971 21 1984 0987 + AUP TORG 0987 10 0990 0995 + STL P0010 8003 TRANSFER 0995 20 1986 8003 + 8003 NOP 0000 9999 TO TYPE 8003 00 0000 9999 +1 + PUNCH PCH P0001 READC PUNCH READ 1350 71 1977 1950 +1 + SETCC RAU READC SUB10 SUDO EXIT 1400 60 1950 1405 +1 + 1900 LDD READC SUB14 MANUAL PAT 1900 69 1950 1403 + T0001 LDD X SUBR3 TYPE 0 1990 69 0993 0996 +1 + X0001 LDD PROCL 650 0913 69 1016 0969 + LDD PROCD COMMAND OR 1016 69 1019 0972 + LDD PUNCH PROCI CONSTANTS 1019 69 1350 1453 +1 + X0002 NOP 0000 8003 PSEUDO OP 0914 00 0000 8003 +1 + T0002 RAU READC SUB10 TYPE 1 COM 1991 60 1950 1405 +1 + X 00 0000 X0001 0993 00 0000 0913 +1 +1 RELOCATE ROUTINE +1 + HED T + T0003 LDD Q SUBR3 PROCESS OP 1992 69 1195 0996 + Q0002 NOP 0000 ILLOP ILLEGAL OP 0909 00 0000 1013 + Q0001 RAL 1951 IS L FIXED 0908 65 1951 1455 + SLT 0002 1455 35 0002 1211 + NZU REL 1211 44 1165 1166 + RAU 1957 FIXED L 1165 60 1957 1261 + SUP 2000I DRUM CORE 1261 11 1014 1169 + BMI FC 1169 46 1172 0973 + AUP 8001 RES FIXED DRUM 1172 10 8001 0979 + FC RAL 1957 SETL FIXED CORE 0973 65 1957 1311 + SR RAL XXXX1 SETL SET L 1450 65 1961 1311 + SETL SLT 0004 1311 35 0004 1171 + LDD P0008 1171 69 1984 1187 + SDA P0008 PROD 1187 22 1984 1237 + REL RAU 1957 DRUM CORE 1166 60 1957 1361 + SUP 2000I 1361 11 1014 1219 + BMI RC 1219 46 1222 1173 + AUP DDIFF RELOCATE 1222 10 0975 1179 + BMI BL DRUM ADDR 1179 46 1182 1183 + AUP 2000I RES 1182 10 1014 0979 + RES STU XXXX1 0979 21 1961 1214 + LDD SR SUB2R RESERVE L 1214 69 1450 1503 + RC RAL 1957 RELOCATE 1173 65 1957 1411 + ALO CDIFF CORE 1411 15 1264 1269 + SLO 9060 1269 16 1272 0977 + BMI BL 0977 46 1180 1183 + ALO 8001 SETL 1180 15 8001 1311 + BL RAU PROD SUB12 BLANK L 1183 60 1237 0991 +1 + REG J0944 0944 D TYPE 2 + REG G0941 0941 +1 + PROD LDD PROI SET D EXIT 1237 69 1190 1193 + STD EXITX 1193 24 1196 0999 + RAU 1952 WHAT IS D 0999 60 1952 1407 + LDD H SUBR4 1407 69 1210 1213 + H0001 RAL 1958 RELOCATE 0902 65 1958 1263 + SLO 2000I D OR C 1263 16 1014 1319 + BMI 1564 1563 1319 46 1564 1563 + H0002 SRT 0008 C D OR F 0903 30 0008 1221 + AUP 1500 8003 1221 10 0974 8003 + 1563 RAL CDIFF CDD C 1563 65 1264 1369 + 1564 RAL DDIFF CDD D 1564 65 0975 1369 + 1566 RAL 1958 J0001 F 1566 65 1958 0944 + CDD ALO 1958 J0001 1369 15 1958 0944 + H0003 NOP 0000 G0003 SYMBOLIC 0904 00 0000 0943 +1 + REG J0960 0960 I + REG F0955 0955 +1 + PROI LDD PUNCH SET I EXIT 1190 69 1350 1553 + STD EXITX 1553 24 1196 1099 + RAU 1953 WHAT IS I 1099 60 1953 1457 + LDD M SUBR4 1457 69 1260 1213 + M0001 RAL 1959 RELOCATE 0905 65 1959 1313 + SLO 2000I D OR C 1313 16 1014 1419 + BMI 1568 1567 1419 46 1568 1567 + M0002 SRT 0008 C D OR F 0906 30 0008 1175 + AUP 1504 8003 1175 10 0978 8003 + 1567 RAL CDIFF CDI C 1567 65 1264 1469 + 1568 RAL DDIFF CDI D 1568 65 0975 1469 + 1570 RAL 1959 J0001 F 1570 65 1959 0960 + CDI ALO 1959 J0001 1469 15 1959 0960 + M0003 NOP 0000 F0003 SYMBOLIC 0907 00 0000 0957 +1 + Q 00 0000 Q0001 CONSTANTS 1195 00 0000 0908 + 9060 00 0000 9060 1272 00 0000 9060 + H 00 0000 H0001 1210 00 0000 0902 + 1500 00 0000 1500 0974 00 0000 1500 + M 00 0000 M0001 1260 00 0000 0905 + 1504 00 0000 1504 0978 00 0000 1504 + XXXX1 01 0000 XXXX1 ERASEABLE 1961 01 0000 1961 + HED +1 +1 BOP ROUTINE +1 + 1001 LDD SUB16 INITIALIZE 1001 69 1404 1353 + RAU READC SUB10 PUNCH 1404 60 1950 1405 +1 +1 BLR ROUTINE +1 + 1002 RAL 1959 BLR RESERVE 1002 65 1959 1363 + BLR SLO 1958 FWA TO 1363 16 1958 1413 + AUP 8001 LWA 1413 10 8001 1271 + LDD SETCC SUB2R 1271 69 1400 1503 +1 +1 RBR ROUTINE +1 + 1012 RAU DDIFF 1012 60 0975 1229 + ALO 1959 BLR 1229 15 1959 1363 +1 +1 BLA ROUTINE +1 + 1003 LDD H8XXX SET DRUM 1003 69 1406 1309 + STD DRUMT TAG TO 8 1309 24 1212 1215 + RAL 1959 UNRESERVE 1215 65 1959 1463 + SLO 1958 FWA 1463 16 1958 1513 + AUP 8001 TO 1513 10 8001 1321 + LDD SETCC SUB2U LWA 1321 69 1400 1603 +1 +1 REG ROUTINE +1 + HED R + 1004 RAL 1952 IS 1004 65 1952 1507 + SRT 0008 REGION 1507 30 0008 1225 + SLO 90XXX CHARACTER 1225 16 1178 1233 + BMI 1002 ALPHABETIC 1233 46 0986 1002 + ALO 29XXX 0986 15 1189 1243 + BMI 1002 1243 46 1002 1197 + SLT 0004 STORE 1197 35 0004 1557 + ALO ST REGION 1557 15 1310 1265 + AUP 1958 ORIGIN 1265 10 1958 1613 + AUP H9XXX 8002 1613 10 1216 8002 + 8002 STU 9999 1002 8002 21 9999 1002 +1 + ST STU 1021 1002 CONSTANTS 1310 21 1021 1002 + HED +1 +1 EQU REQ AND SYN ROUTINE +1 + HED Z + 1005 LDD H8XXX BOTH EQU 1005 69 1406 1359 + 1006 LDD H9XXX BOTH SYN 1006 69 1216 1359 + BOTH STD TAG 1359 24 1262 1315 + RAU 1953 WHAT IS I 1315 60 1953 1607 + LDD Z SUBR4 1607 69 1360 1213 + Z0001 RAL 1959 Y0001 ABSOLUTE 0917 65 1959 0915 + Z0002 LDD Y SUBR9 REGIONAL 0918 69 1371 1174 + Y0001 STL E TD 0915 20 1519 1322 + Y0002 RAL P0010 BP REG ERROR 0916 65 1986 1191 + Z0003 LDD W SUBR6 SYMBOLIC 0919 69 1372 1275 + W0001 RAL EQUIV Y0001 S DEFINED 0920 65 1223 0915 + W0002 RAL P0010 BP S UNDEFIND 0921 65 1986 1191 + W0003 RAL P0010 BP S TAB FULL 0922 65 1986 1191 +1 + TD RAU 1952 HEAD D 1322 60 1952 1657 + LDD SUB15 AND EQUATE 1657 69 1410 1663 + LDD V SUBR6 TO E 1410 69 1713 1275 + V0003 RAL P0010 BP S TAB FULL 0912 65 1986 1191 + V0001 ALO E SD 0910 15 1519 1273 + V0002 ALO E SD 0911 15 1519 1273 + SD LDD TT SUBR7 1273 69 0976 1279 +1 + TT LDD TAG TEST TAG 0976 69 1262 1365 + BDO SETCC 1365 90 1400 0970 + RAU E RESERVE E 0970 60 1519 1323 + LDD SETCC SUB2R 1323 69 1400 1503 +1 + 1011 LDD H8XXX REQ 1011 69 1406 1409 + STD TAG ROUTINE 1409 24 1262 1415 + RAL 1959 IS I 1415 65 1959 1763 + SLO 2000I DRUM O COR 1763 16 1014 1569 + BMI D 1569 46 1422 1373 + ALO CDIFF CD 1373 15 1264 1619 + D ALO DDIFF CD 1422 15 0975 1619 + CD ALO 2000I Y0001 1619 15 1014 0915 +1 + Z 00 0000 Z0001 CONSTANTS 1360 00 0000 0917 + Y 00 0089 Y0001 1371 00 0089 0915 + W 00 0000 W0001 1372 00 0000 0920 + V 00 0000 V0001 1713 00 0000 0910 + 88 00 8800 0000 1500 00 8800 0000 +1 + BP ALO 88 BY PASS 1191 15 1500 1505 + STL P0010 PUNCH 1505 20 1986 1350 +1 + TAG 01 0000 TAG ERASEABLE 1262 01 0000 1262 + E 01 0000 E 1519 01 0000 1519 + HED +1 +1 ALF ROUTINE +1 + 1007 LDD PROCL PROCES LOC 1007 69 1460 0969 + LDD 1952 1460 69 1952 1555 + STD P0007 1555 24 1983 1186 + RAL 1953 REPLACE 1186 65 1953 1707 + NZE PUNCH BLANK I 1707 45 1350 1461 + LDD SOAP2 BY 1461 69 1314 1017 + STD P0003 PUNCH SOAP2 1017 24 1979 1350 + SOAP2 ALF SOAP2 SOAP2 CONSTANT 1314 82 7661 7792 +1 +1 PAT ROUTINE +1 + 1008 RAU SUB10 1008 60 1511 1405 + LDD READC SUB14 1511 69 1950 1403 +1 +1 HED ROUTINE +1 + 1009 RAL 1952 STORE 1009 65 1952 1757 + SRT 0008 HEADING 1757 30 0008 1325 + STL 0000H SETCC CHARACTER 1325 20 1329 1400 +1 +1 REL ROUTINE +1 + HED M + 1010 RAL 1952 SET 1010 65 1952 1807 + NZE SDD DRUM 1807 45 1510 1561 + RAL 1958 SDD AND 1510 65 1958 1561 + SDD STL DDIFF CORE 1561 20 0975 1228 + RAL 1953 DELTAS 1228 65 1953 1857 + NZE SCD 1857 45 1560 1611 + RAL 1959 SCD 1560 65 1959 1611 + SCD STL CDIFF SETCC 1611 20 1264 1400 +1 + DDIFF 01 0000 DDIFF ERASEABLE 0975 01 0000 0975 + CDIFF 01 0000 CDIFF 1264 01 0000 1264 + HED +1 +1 LOAD AVAILABLITY TABLE +1 + HED L + 1999 RAL 1951 CALC 1999 65 1951 1605 + SRT 0004 LOC 1605 30 0004 1465 + SLT 0004 W2 1465 35 0004 1375 + ALO 8002 1375 15 8002 1283 + ALO 8002 1283 15 8002 1241 + ALO C1 1241 15 0994 1149 + AUP C2 8003 1149 10 1352 8003 + 8003 LDD 9995 8002 LOAD 8003 69 9995 8002 + 8002 STD 9994 TUP TABLE 8002 24 9994 1247 + TUP SUP TW 1247 11 1550 1655 + NZU READC 1655 44 1459 1950 + AUP TWP2 1459 10 1312 1167 + ALO 1DXXX 8003 1167 15 1020 8003 +1 + C1 STD A0001 TUP CONSTANTS 0994 24 0600 1247 + C2 LDD 1952 8002 1352 69 1952 8002 + TW LDD 1958 8002 1550 69 1958 8002 + TWP2 LDD 1960 8002 1312 69 1960 8002 + HED +1 OPTIMIZING TABLE +1 + N0001 00 0404 0998 NOP 0800 00 0404 0998 + N0002 00 0404 0998 HLT 0801 00 0404 0998 + N0003 33 2322 0999 UFA 0802 33 2322 0999 + N0004 00 0505 0998 RTC 0803 00 0505 0998 + N0005 00 0505 0998 RTN 0804 00 0505 0998 + N0006 00 0505 0998 RTA 0805 00 0505 0998 + N0007 00 0505 0998 WTN 0806 00 0505 0998 + N0008 00 0505 0998 WTA 0807 00 0505 0998 + N0009 33 1212 0999 LIB 0808 33 1212 0999 + N0010 33 0202 0999 LDI 0809 33 0202 0999 + N0011 33 0504 0999 AUP 0810 33 0504 0999 + N0012 33 0504 0999 SUP 0811 33 0504 0999 + N0013 99 9999 9999 NOT USED 0812 99 9999 9999 + N0014 99 9999 9999 NOT USED 0813 99 9999 9999 + N0015 33 1110 0999 DIV 0814 33 1110 0999 + N0016 33 0504 0999 ALO 0815 33 0504 0999 + N0017 33 0504 0999 SLO 0816 33 0504 0999 + N0018 33 0504 0999 AML 0817 33 0504 0999 + N0019 33 0504 0999 SML 0818 33 0504 0999 + N0020 33 2120 0999 MPY 0819 33 2120 0999 + N0021 54 0303 0999 STL 0820 54 0303 0999 + N0022 45 0303 0999 STU 0821 45 0303 0999 + N0023 34 0303 0999 SDA 0822 34 0303 0999 + N0024 34 0303 0999 SIA 0823 34 0303 0999 + N0025 33 0303 0999 STD 0824 33 0303 0999 + N0026 44 0505 0998 NTS 0825 44 0505 0998 + N0027 00 0505 0998 BIN 0826 00 0505 0998 + N0028 00 0505 0998 SET 0827 00 0505 0998 + N0029 33 1212 0999 SIB 0828 33 1212 0999 + N0030 33 0202 0999 STI 0829 33 0202 0999 + N0031 00 0000 0988 SRT 0830 00 0000 0988 + N0032 00 0000 0888 SRD 0831 00 0000 0888 + N0033 33 2726 0999 FAD 0832 33 2726 0999 + N0034 33 2726 0999 FSB 0833 33 2726 0999 + N0035 33 0000 0999 FDV 0834 33 0000 0999 + N0036 00 0000 0988 SLT 0835 00 0000 0988 + N0037 00 0000 0988 SCT 0836 00 0000 0988 + N0038 33 2726 0999 FAM 0837 33 2726 0999 + N0039 33 2726 0999 FSM 0838 33 2726 0999 + N0040 33 0000 0999 FMP 0839 33 0000 0999 + N0041 33 0404 0998 NZA 0840 33 0404 0998 + N0042 33 0404 0998 BMZ 0841 33 0404 0998 + N0043 33 0404 0998 NZB 0842 33 0404 0998 + N0044 33 0404 0998 BMB 0843 33 0404 0998 + N0045 34 0405 0998 NZU 0844 34 0405 0998 + N0046 43 0504 0998 NZE 0845 43 0504 0998 + N0047 33 0404 0998 BMI 0846 33 0404 0998 + N0048 33 0505 0998 BOV 0847 33 0505 0998 + N0049 33 0404 0998 NZC 0848 33 0404 0998 + N0050 33 0404 0998 BMC 0849 33 0404 0998 + N0051 00 0000 0898 AXA 0850 00 0000 0898 + N0052 00 0000 0898 SXA 0851 00 0000 0898 + N0053 00 0000 0898 AXB 0852 00 0000 0898 + N0054 00 0000 0898 SXB 0853 00 0000 0898 + N0055 44 0505 0998 NEF 0854 44 0505 0998 + N0056 00 0505 0998 RWD 0855 00 0505 0998 + N0057 00 0505 0998 WTM 0856 00 0505 0998 + N0058 00 0505 0998 BST 0857 00 0505 0998 + N0059 00 0000 0898 AXC 0858 00 0000 0898 + N0060 00 0000 0898 SXC 0859 00 0000 0898 + N0061 33 0504 0999 RAU 0860 33 0504 0999 + N0062 33 0504 0999 RSU 0861 33 0504 0999 + N0063 99 9999 9999 NOT USED 0862 99 9999 9999 + N0064 99 9999 9999 NOT USED 0863 99 9999 9999 + N0065 33 1110 0999 DVR 0864 33 1110 0999 + N0066 33 0504 0999 RAL 0865 33 0504 0999 + N0067 33 0504 0999 RSL 0866 33 0504 0999 + N0068 33 0504 0999 RAM 0867 33 0504 0999 + N0069 33 0504 0999 RSM 0868 33 0504 0999 + N0070 33 0303 0999 LDD 0869 33 0303 0999 + N0071 00 0000 0999 RD1 0870 00 0000 0999 + N0072 00 0000 0999 WR1 0871 00 0000 0999 + N0073 00 0000 0999 RC1 0872 00 0000 0999 + N0074 00 0000 0999 RD2 0873 00 0000 0999 + N0075 00 0000 0999 WR2 0874 00 0000 0999 + N0076 00 0000 0999 RC2 0875 00 0000 0999 + N0077 00 0000 0999 RD3 0876 00 0000 0999 + N0078 00 0000 0999 WR3 0877 00 0000 0999 + N0079 00 0000 0999 RC3 0878 00 0000 0999 + N0080 00 0505 0999 RPY 0879 00 0505 0999 + N0081 00 0000 0898 RAA 0880 00 0000 0898 + N0082 00 0000 0898 RSA 0881 00 0000 0898 + N0083 00 0000 0898 RAB 0882 00 0000 0898 + N0084 00 0000 0898 RSB 0883 00 0000 0898 + N0085 33 0506 0999 TLU 0884 33 0506 0999 + N0086 00 0606 0998 SDS 0885 00 0606 0998 + N0087 00 0606 0998 RDS 0886 00 0606 0998 + N0088 00 0606 0998 WDS 0887 00 0606 0998 + N0089 00 0000 0898 RAC 0888 00 0000 0898 + N0090 00 0000 0898 RSC 0889 00 0000 0898 + N0091 44 0505 0998 BDO 0890 44 0505 0998 + N0092 33 0505 0998 BD1 0891 33 0505 0998 + N0093 33 0505 0998 BD2 0892 33 0505 0998 + N0094 33 0505 0998 BD3 0893 33 0505 0998 + N0095 33 0505 0998 BD4 0894 33 0505 0998 + N0096 33 0505 0998 BD5 0895 33 0505 0998 + N0097 33 0505 0998 BD6 0896 33 0505 0998 + N0098 33 0505 0998 BD7 0897 33 0505 0998 + N0099 33 0505 0998 BD8 0898 33 0505 0998 + N0100 44 0505 0998 BD9 0899 44 0505 0998 +1 +1 SYMBOLIC OP TABLE +1 + C0001 61 7366 1007 ALF 1050 61 7366 1007 + C0002 61 7376 0015 ALO 1051 61 7376 0015 + C0003 61 7473 0017 AML 1052 61 7473 0017 + C0004 61 8477 0010 AUP 1053 61 8477 0010 + C0005 61 8761 0050 AXA 1054 61 8761 0050 + C0006 61 8762 0052 AXB 1055 61 8762 0052 + C0007 61 8763 0058 AXC 1056 61 8763 0058 + C0008 62 6476 0090 BDO 1057 62 6476 0090 + C0009 62 6491 0091 BD1 1058 62 6491 0091 + C0010 62 6492 0092 BD2 1059 62 6492 0092 + C0011 62 6493 0093 BD3 1060 62 6493 0093 + C0012 62 6494 0094 BD4 1061 62 6494 0094 + C0013 62 6495 0095 BD5 1062 62 6495 0095 + C0014 62 6496 0096 BD6 1063 62 6496 0096 + C0015 62 6497 0097 BD7 1064 62 6497 0097 + C0016 62 6498 0098 BD8 1065 62 6498 0098 + C0017 62 6499 0099 BD9 1066 62 6499 0099 + C0018 62 6975 0026 BIN 1067 62 6975 0026 + C0019 62 7361 1003 BLA 1068 62 7361 1003 + C0020 62 7379 1002 BLR 1069 62 7379 1002 + C0021 62 7461 0041 BMA 1070 62 7461 0041 + C0022 62 7462 0043 BMB 1071 62 7462 0043 + C0023 62 7463 0049 BMC 1072 62 7463 0049 + C0024 62 7469 0046 BMI 1073 62 7469 0046 + C0025 62 7677 1001 BOP 1074 62 7677 1001 + C0026 62 7685 0047 BOV 1075 62 7685 0047 + C0027 62 8283 0057 BST 1076 62 8283 0057 + C0028 64 6985 0014 DIV 1077 64 6985 0014 + C0029 64 8579 0064 DVR 1078 64 8579 0064 + C0030 65 7884 1005 EQU 1079 65 7884 1005 + C0031 66 6164 0032 FAD 1080 66 6164 0032 + C0032 66 6174 0037 FAM 1081 66 6174 0037 + C0033 66 6485 0034 FDV 1082 66 6485 0034 + C0034 66 7477 0039 FMP 1083 66 7477 0039 + C0035 66 8262 0033 FSB 1084 66 8262 0033 + C0036 66 8274 0038 FSM 1085 66 8274 0038 + C0037 68 6564 1009 HED 1086 68 6564 1009 + C0038 68 7383 0001 HLT 1087 68 7383 0001 + C0039 73 6464 0069 LDD 1088 73 6464 0069 + C0040 73 6469 0009 LDI 1089 73 6469 0009 + C0041 73 6962 0008 LIB 1090 73 6962 0008 + C0042 74 7788 0019 MPY 1091 74 7788 0019 + C0043 75 6566 0054 NEF 1092 75 6566 0054 + C0044 75 7677 0000 NOP 1093 75 7677 0000 + C0045 75 8382 0025 NTS 1094 75 8382 0025 + C0046 75 8961 0040 NZA 1095 75 8961 0040 + C0047 75 8962 0042 NZB 1096 75 8962 0042 + C0048 75 8963 0048 NZC 1097 75 8963 0048 + C0051 75 8965 0045 NZE 1100 75 8965 0045 + C0052 75 8984 0044 NZU 1101 75 8984 0044 + C0053 77 6183 1008 PAT 1102 77 6183 1008 + C0054 77 6368 0071 PCH 1103 77 6368 0071 + C0055 79 6161 0080 RAA 1104 79 6161 0080 + C0056 79 6162 0082 RAB 1105 79 6162 0082 + C0057 79 6163 0088 RAC 1106 79 6163 0088 + C0058 79 6173 0065 RAL 1107 79 6173 0065 + C0059 79 6174 0067 RAM 1108 79 6174 0067 + C0060 79 6184 0060 RAU 1109 79 6184 0060 + C0061 79 6279 1012 RBR 1110 79 6279 1012 + C0062 79 6364 0070 RCD 1111 79 6364 0070 + C0063 79 6391 0072 RC1 1112 79 6391 0072 + C0064 79 6392 0075 RC2 1113 79 6392 0075 + C0065 79 6393 0078 RC3 1114 79 6393 0078 + C0066 79 6482 0086 RDS 1115 79 6482 0086 + C0067 79 6491 0070 RD1 1116 79 6491 0070 + C0068 79 6492 0073 RD2 1117 79 6492 0073 + C0069 79 6493 0076 RD3 1118 79 6493 0076 + C0070 79 6567 1004 REG 1119 79 6567 1004 + C0071 79 6573 1010 REL 1120 79 6573 1010 + C0072 79 6578 1011 REQ 1121 79 6578 1011 + C0073 79 7788 0079 RPY 1122 79 7788 0079 + C0074 79 8261 0081 RSA 1123 79 8261 0081 + C0075 79 8262 0083 RSB 1124 79 8262 0083 + C0076 79 8263 0089 RSC 1125 79 8263 0089 + C0077 79 8273 0066 RSL 1126 79 8273 0066 + C0078 79 8274 0068 RSM 1127 79 8274 0068 + C0079 79 8284 0061 RSU 1128 79 8284 0061 + C0080 79 8361 0005 RTA 1129 79 8361 0005 + C0081 79 8363 0003 RTC 1130 79 8363 0003 + C0082 79 8375 0004 RTN 1131 79 8375 0004 + C0083 79 8664 0055 RWD 1132 79 8664 0055 + C0084 82 6383 0036 SCT 1133 82 6383 0036 + C0085 82 6461 0022 SDA 1134 82 6461 0022 + C0086 82 6482 0085 SDS 1135 82 6482 0085 + C0087 82 6583 0027 SET 1136 82 6583 0027 + C0088 82 6961 0023 SIA 1137 82 6961 0023 + C0089 82 6962 0028 SIB 1138 82 6962 0028 + C0090 82 7376 0016 SLO 1139 82 7376 0016 + C0091 82 7383 0035 SLT 1140 82 7383 0035 + C0092 82 7473 0018 SML 1141 82 7473 0018 + C0093 82 7964 0031 SRD 1142 82 7964 0031 + C0094 82 7983 0030 SRT 1143 82 7983 0030 + C0095 82 8364 0024 STD 1144 82 8364 0024 + C0096 82 8369 0029 STI 1145 82 8369 0029 + C0097 82 8373 0020 STL 1146 82 8373 0020 + C0098 82 8384 0021 STU 1147 82 8384 0021 + C0101 82 8477 0011 SUP 1150 82 8477 0011 + C0102 82 8761 0051 SXA 1151 82 8761 0051 + C0103 82 8762 0053 SXB 1152 82 8762 0053 + C0104 82 8763 0059 SXC 1153 82 8763 0059 + C0105 82 8875 1006 SYN 1154 82 8875 1006 + C0106 83 7384 0084 TLU 1155 83 7384 0084 + C0107 84 6661 0002 UFA 1156 84 6661 0002 + C0108 86 6482 0087 WDS 1157 86 6482 0087 + C0109 86 7991 0071 WR1 1158 86 7991 0071 + C0110 86 7992 0074 WR2 1159 86 7992 0074 + C0111 86 7993 0077 WR3 1160 86 7993 0077 + C0112 86 8361 0007 WTA 1161 86 8361 0007 + C0113 86 8374 0056 WTM 1162 86 8374 0056 + C0114 86 8375 0006 WTN 1163 86 8375 0006 + C0115 99 9999 0001 TABLE END 1164 99 9999 0001 +1 +1 SUB 1 STORE K IN FWA TO LWA +1 + HED 1 + SUBR1 STD EXITX STORE EXIT 1600 24 1196 1199 + STU XXXX1 STORE K 1199 21 1961 1364 + LDD FWA SET 1364 69 1217 1170 + SDA FWA FWA 1170 22 1217 1220 + SLT 0004 LWA 1220 35 0004 1181 + SDA XXXX2 ADDRESSES 1181 22 1962 1515 + RAU FWA 1515 60 1217 1421 + ALO XXXX1 8003 1421 15 1961 8003 + 8003 STL 9999 NEXT STORE K 8003 20 9999 1402 + NEXT SUP XXXX2 END OF 1402 11 1962 1267 + NZU EXITX LOOP TEST 1267 44 1471 1196 + AUP 8001 1471 10 8001 1379 + AUP 1DXXX 8003 STEP 1379 10 1020 8003 +1 + FWA STL 9998 NEXT CONSTANTS 1217 20 9998 1402 + XXXX2 01 0000 XXXX2 ERASEABLE 1962 01 0000 1962 + HED +1 +1 SUB 2 RESERVE UNRESERVE +1 + HED 2 + SUB2R STD EXITY RESERVE 1503 24 1456 1509 + LDD Z RU ENTRY 1509 69 1362 1565 + SUB2U STD EXITY UNRESERVE 1603 24 1456 1559 + LDD 1I RU ENTRY 1559 69 1412 1565 + RU STD W SET W 1565 24 1018 1521 + STL N STORE N 1521 20 1425 1278 + SLO 8001 CALC AO 1278 16 8001 1185 + AUP 8003 AND PO 1185 10 8003 1293 + SRT 0003 1293 30 0003 1351 + STU X 1351 21 1506 1609 + SUP 8001 1609 11 8001 1317 + SLT 0001 1317 35 0001 1423 + STU P 1423 21 1328 1231 + SUP 8001 1231 11 8001 1239 + SLT 0002 1239 35 0002 1245 + AUP 8003 1245 10 8003 1653 + AUP X 1653 10 1506 1661 + ALO P 1661 15 1328 1333 + SLT 0004 1333 35 0004 1343 + ALO C1 1343 15 1246 1401 + STL B0002 1401 20 0901 1454 + LDD C2 1454 69 1907 1610 + SDA SPR 1610 22 1813 1266 + AUP C3 SU 1266 10 1669 1473 + SU STU SA 1473 21 1378 1281 + AUP C4 8003 1281 10 1184 8003 + 8003 RAL 9992 B0002 8003 65 9992 0901 + B0002 SLT 0009 XX 0901 35 0009 1571 + XX STU UH 1571 21 1176 1429 + SLT 0001 1429 35 0001 1235 + RAL 8002 1235 65 8002 1393 + AUP W 1393 10 1018 1523 + SRT 0001 1523 30 0001 1479 + AUP UH SPR 1479 10 1176 1813 + SPR SRT 0009 SA 1813 30 0009 1378 + SA STL 9983 B0001 1378 20 9983 0900 + B0001 RAL N IS N ZERO 0900 65 1425 1529 + NZE EXITY 1529 45 1232 1456 + SLO 1I REDUCE N 1232 16 1412 1367 + STL N BY 1 1367 20 1425 1428 + RAU SA IS AI 1428 60 1378 1383 + SUP A197 IN LAST 1383 11 1236 1291 + BMI TP BLOCK OF 1291 46 1194 1295 + AUP A201 SU 4 1194 10 1297 1473 +1 + TP RAL SPR IS P 9 1295 65 1813 1417 + SLO C2 1417 16 1907 1711 + NZE ZP 1711 45 1414 1615 + ALO C5 STEP P 1414 15 1467 1621 + LDD C1 1621 69 1246 1249 + SDA B0002 1249 22 0901 1504 + STL SPR 1504 20 1813 1316 + RAU SA REDUCE AI 1316 60 1378 1433 + SUP C6 SU BY 196 1433 11 1286 1473 +1 + ZP LDD C1 SET P 1615 69 1246 1299 + STD B0002 TO ZERO 1299 24 0901 1554 + LDD C7 1554 69 1308 1761 + STD SPR 1761 24 1813 1366 + RAU SA REDUCE AI 1366 60 1378 1483 + SUP C8 SU BY 195 1483 11 1336 1473 +1 + C1 SLT 0000 XX CONSTANTS 1246 35 0000 1571 + C2 SRT 0009 SA 1907 30 0009 1378 + C3 STL A0001 B0001 1669 20 0600 0900 + C4 45 0000 0001 1184 45 0000 0001 + 1I 00 0000 0001 1412 00 0000 0001 + A197 STL A0197 B0001 1236 20 0796 0900 + A201 STL A0201 B0001 1297 20 0800 0900 + C5 SRT 0010 SA 1467 30 0010 1378 + C6 00 0196 0000 1286 00 0196 0000 + C7 SRT 0000 SA 1308 30 0000 1378 + C8 00 0195 0000 1336 00 0195 0000 + Z 00 0000 0000 1362 00 0000 0000 + W 01 0000 W ERASEABLE 1018 01 0000 1018 + N 01 0000 N 1425 01 0000 1425 + B0002 01 0000 B0002 0901 01 0000 0901 + SPR 01 0000 SPR 1813 01 0000 1813 + SA 01 0000 SA 1378 01 0000 1378 + UH 01 0000 UH 1176 01 0000 1176 + X 01 0000 X 1506 01 0000 1506 + HED +1 +1 SUB 3 PROCESS OP CODE +1 + HED 3 + SUBR3 STD EXITX STORE EXIT 0996 24 1196 1349 + RAL 1954 1349 65 1954 1659 + SRT 0004 IS OP 1659 30 0004 1719 + NZE ILLOP BLANK 1719 45 1472 1013 + SLT 0006 IS OP 1472 35 0006 1287 + NZU NUM NUMERIC 1287 44 1341 1192 + SRT 0002 1341 30 0002 1347 + STL XXXX1 SEARCH 1347 20 1961 1464 + SLO 8001 SYMBOLIC 1464 16 8001 1671 + TLU C0001 OP TABLE 1671 84 1050 1705 + ALO 1 8002 1705 15 1358 8002 + 8002 RAL 9997 NEXT IS 8002 65 9997 1451 + NEXT SLO XXXX1 SYM OP 1451 16 1961 1665 + SLT 0006 LEGAL 1665 35 0006 1579 + NZU ILLOP 1579 44 1013 1234 + SLT 0001 TEST FOR 1234 35 0001 1391 + NZU PSEU PSEUDO OP 1391 44 1345 1296 + SLT 0001 SNO STORE NUM 1296 35 0001 1703 + SNO STL P0007 650 OP 1703 20 1983 1386 + SRT 0004 GET OPTIM 1386 30 0004 1397 + ALO 3 8002 CONSTANTS 1397 15 1650 8002 + 8002 LDD 9996 NEX 8002 69 9996 1399 + NEX STD OPTIM EXITX 1399 24 1452 1196 +1 + NUM SLO 4 FORM 1192 16 1395 1449 + SLT 0002 NUMERIC 1449 35 0002 1755 + SLO 8002 OP 1755 16 8002 1863 + SRT 0001 CODE 1863 30 0001 1769 + ALO 8001 SNO 1769 15 8001 1703 +1 + ILLOP RAL P0010 ILLEGAL OP 1013 65 1986 1441 + ALO 5 SET 8 1441 15 1244 1499 + STL P0010 FOR BLANK 1499 20 1986 1289 + LDD 6 NEX OP 1289 69 1242 1399 +1 + PSEU SLT 0003 PSEUDO 1345 35 0003 1753 + ALO EXITX OP 1753 15 1196 1501 + ALO 1IXXX 8002 1501 15 0992 8002 +1 + 1 RAL 0000 NEXT CONSTANTS 1358 65 0000 1451 + 2 10 0000 0000 1700 10 0000 0000 + 3 LDD N0001 NEX 1650 69 0800 1399 + 4 90 9000 0000 1395 90 9000 0000 + 5 00 0000 0008 1244 00 0000 0008 + 6 55 0505 0999 1242 55 0505 0999 + HED +1 +1 SUB 4 WHAT IS ADDRESS +1 + HED 4 + SUBR4 STD EXITZ STORE EXIT 1213 24 1416 1819 + STU XXXX1 STORE ADDR 1819 21 1961 1514 + SRT 0008 IS C5 1514 30 0008 1533 + NZU EXITZ BLANK 1533 44 1337 1416 + STU XXXX2 SAVE C5 1337 21 1962 1715 + RAU 8002 ARE LOW 4 1715 60 8002 1573 + AUP 90XXX CHARACTERS 1573 10 1178 1583 + BOV LOOP LOOP NUMERIC 1583 47 1436 1436 + LOOP AUP H1 1436 10 1339 1443 + BOV SYM 1443 47 1346 0998 + SLT 0002 1346 35 0002 1803 + NZU LOOP 1803 44 1436 1408 + RAL XXXX2 LOW 4 NUM 1408 65 1962 1517 + SLO 90XXX IS C5 1517 16 1178 1633 + BMI SYM ALPHABETIC 1633 46 1486 0998 + ALO 29XXX 1486 15 1189 1493 + BMI SYM 1493 46 0998 1447 + RAL 1IXXX REGIONAL 1447 65 0992 1497 + AUP XXXX1 AEX 1497 10 1961 1765 + AEX ALO EXITZ 1765 15 1416 1721 + SLO 8002 8001 1721 16 8002 8001 + SYM RAU XXXX1 HED SYMBOL 0998 60 1961 1815 + LDD SUB15 1815 69 1168 1663 + ALO 2IXXX STEP EXIT 1168 15 1771 1475 + STU HSYMB AEX 1475 21 1230 1765 + H1 10 0000 0000 1339 10 0000 0000 + HSYMB 01 0000 HSYMB ERASEABLE 1230 01 0000 1230 + HED +1 +1 SUB 5 TEST ABSOLUTE ADDRE +1 + HED 5 + SUBR5 STD EXITZ STORE EXIT 1750 24 1416 1869 + STL XXXX1 STORE A 1869 20 1961 1614 + SLT 0004 1614 35 0004 1525 + SLO 8002 1525 16 8002 1683 + TLU R0001 TLU 1683 84 1200 1805 + ALO GET 8002 RANGE 1805 15 1458 8002 + 8002 RAU 9972 X TABLE 8002 60 9972 1177 + X SLT 0006 1177 35 0006 1491 + SRT 0006 1491 30 0006 1855 + AUP EXITZ 1855 10 1416 1821 + ALO XXXX1 1821 15 1961 1865 + SUP 8003 8001 1865 11 8003 8001 + GET RAU 0000 X 1458 60 0000 1177 + R0001 00 1999 0000 RANGE 1200 00 1999 0000 + R0002 00 7999 0003 TABLE 1201 00 7999 0003 + R0003 00 8003 0001 1202 00 8003 0001 + R0004 00 8004 0003 1203 00 8004 0003 + R0005 00 8007 0001 1204 00 8007 0001 + R0006 00 8999 0003 1205 00 8999 0003 + R0007 00 9059 0002 1206 00 9059 0002 + R0008 99 9999 0003 1207 99 9999 0003 + HED +1 +1 SUB 6 SYMBOL TEST ROUTINE +1 + HED 6 + SUBR6 STD EXITZ STORE EXIT 1275 24 1416 1919 + STU S STORE SYMB 1919 21 1224 1227 + LDD SWOF SET SWITCH 1227 69 1280 1733 + STD SW OFF 1733 24 1536 1389 + MPY SC SCRAMBLE 1389 19 1292 1913 + RAL 8002 SYMBOL 1913 65 8002 1871 + SLT 0003 GIVING 1871 35 0003 1629 + MPY CF LO 1629 19 1282 1853 + SRT 0001 1853 30 0001 1709 + SLT 0004 SET 1709 35 0004 1969 + ALO L1P1 TEST 1969 15 1522 1277 + STL LOP1 WORD 1277 20 1331 1284 + SLO 1DXXX 1284 16 1020 1575 + STL LO SLI SAVE LO 1575 20 1679 1332 + SLI STL LI 8001 INIT LI 1332 20 1387 8001 + 8001 RAL 9990 A IS CONT OF 8001 65 9990 1445 + A NZE UND LI ZERO 1445 45 1098 1549 + SLO S IS CONT OF 1098 16 1224 1729 + NZE SW DEF LI SYMB 1729 45 1536 1783 + SW RAL LI OFF IS LI 1536 65 1387 1541 + OFF SLO LMAX MAXIMUM 1541 16 1294 1599 + NZE MAX 1599 45 1502 1903 + ALO LMP1 SLI STEP LI 1502 15 1905 1332 + ON SLO LO IS LI EQUA 1800 16 1679 1833 + NZE SWSYM TO LO 1833 45 1586 1437 + ALO LOP1 SLI STEP LI 1586 15 1331 1332 + MAX LDD SWON SET 1903 69 1556 1759 + STD SW SWITCH ON 1759 24 1536 1439 + RAL L1 SLI ZERO LI 1439 65 1342 1332 +1 + UND RAL EXITZ UNDEFINED 1549 65 1416 1921 + ALO 1IXXX STEP 1921 15 0992 1547 + STL EXITZ EXIT 1547 20 1416 1270 + RAL LI 1270 65 1387 1591 + SLO L1 1591 16 1342 1597 + STL LSYMB ASU 1597 20 1551 1604 +1 + DEF RAL LI DEFINED 1783 65 1387 1641 + LDD ASU SUBR8 GET 1641 69 1604 1508 + ASU AUP S EXITZ EQUIVALENT 1604 10 1224 1416 +1 + SWSYM HLT 0111 SYMOF S TAB FULL 1437 01 0111 1691 + SYMOF LDD SYMON SET SW SYM 1691 69 1344 1647 + STD SWSYM SYMON ON 1647 24 1437 1344 + SYMON RAL EXITZ 1344 65 1416 1971 + ALO 2IXXX 8002 1971 15 1771 8002 +1 + SWOF RAL LI OFF CONSTANTS 1280 65 1387 1541 + SWON RAL LI ON 1556 65 1387 1800 + SC 10 0100 1001 1292 10 0100 1001 + CF 00 0000 0004 1282 00 0000 0004 + L1 RAL 0000 A 1342 65 0000 1445 + L1P1 RAL 0001 A 1522 65 0001 1445 + LMAX RAL E0000 A 1294 65 0399 1445 + LMP1 RAL E0001 A 1905 65 0400 1445 + S 01 0000 S ERASABLE 1224 01 0000 1224 + SW 01 0000 SW 1536 01 0000 1536 + LO 01 0000 LO 1679 01 0000 1679 + LI 01 0000 LI 1387 01 0000 1387 + LSYMB 01 0000 LSYMB 1551 01 0000 1551 + HED +1 +1 SUB 7 STORE SYMBOL AND EQ +1 + HED 7 + SUBR7 STD EXITZ STORE EXIT 1279 24 1416 1320 + LDD SS 1320 69 1623 1226 + SDA XXXX2 8001 STORE 1226 22 1962 8001 + 8001 STU 9988 A SYMBOL 8001 21 9988 1741 + A SUP 8001 1741 11 8001 1649 + STL XXXX1 SAVE E 1649 20 1961 1664 + SRT 0004 1664 30 0004 1625 + DIV 2IXXX CALCULATE 1625 14 1771 1381 + SLT 0004 LOCATION 1381 35 0004 1791 + ALO C1 OF 1791 15 1394 1699 + LDD C2 E 1699 69 1552 1606 + SDA SEL AND 1606 22 1809 1462 + LDD C3 STORE 1462 69 1915 1218 + SDA SER 1218 22 1572 1675 + STL OBEE 1675 20 1779 1382 + SLO 8001 1382 16 8001 1489 + ALO XXXX1 OBEE 1489 15 1961 1779 + OBEE LDD 9986 B 1779 69 9986 1539 + B NZU SER 1539 44 1572 1444 + SLT 0004 SEL 1444 35 0004 1809 + SS STU 9987 A CONSTANTS 1623 21 9987 1741 + C1 LDD E0001 B 1394 69 0400 1539 + C2 SDA 9985 EXITZ 1552 22 9985 1416 + C3 SIA 9984 EXITZ 1915 23 9984 1416 + OBEE 01 0000 OBEE ERASABLE 1779 01 0000 1779 + SEL 01 0000 SEL 1809 01 0000 1809 + SER 01 0000 SER 1572 01 0000 1572 + HED +1 +1 SUB 8 GIVEN SYM LOC GET EQU +1 + HED 8 + SUBR8 STD EXIT STORE EXIT 1508 24 1811 1714 + LDD 8003 1714 69 8003 1370 + SDA LSYMB STORE L 1370 22 1551 1654 + RAL 8001 1654 65 8001 1861 + DIV 2DXXX 1861 14 1764 1725 + SLT 0004 1725 35 0004 1285 + ALO E1 8002 1285 15 1188 8002 + 8002 LDD 9975 TR 8002 69 9975 1478 + TR NZU LH 1478 44 1431 1432 + RAM 8001 LR GET E RH 1431 67 8001 1589 + LH RAM 8001 GET E LH 1432 67 8001 1639 + SRT 0004 LR 1639 30 0004 1589 + LR LDD 8003 1589 69 8003 1396 + SIA EQUIV 1396 23 1223 1276 + RAL LSYMB EXIT 1276 65 1551 1811 + E1 LDD E0001 TR CONSTANT 1188 69 0400 1478 + EXIT 01 0000 EXIT ERASEABLE 1811 01 0000 1811 + EQUIV 01 0000 EQUIV 1223 01 0000 1223 + HED +1 +1 SUB 9 CALCULATE REG ADDRE + HED 9 + SUBR9 STD EXITZ STORE EXIT 1174 24 1416 1420 + SRT 0008 1420 30 0008 1689 + RAL 8003 1689 65 8003 1697 + SLT 0004 1697 35 0004 1558 + ALO C 8002 IS 1558 15 1911 8002 + 8002 RAL 9991 NEX REGION 8002 65 9991 1495 + NEX BDO ILL DEFINED 1495 90 1749 1850 + SLT 0001 1850 35 0001 1608 + RAL 8002 1608 65 8002 1617 + SRT 0001 1617 30 0001 1673 + LDD EXITZ 1673 69 1416 1470 + BD6 L 1470 96 1723 1775 + BD5 D I 1723 95 1326 1528 + L ALO 1957 ALL 1775 15 1957 1512 + D ALO 1958 ALL 1326 15 1958 1512 + I ALO 1959 ALL 1528 15 1959 1512 + ALL SLO 1IXXX 1512 16 0992 1747 + BMI ILL EXITZ 1747 46 1749 1416 + ILL RAL EXITZ UNDEFINED 1749 65 1416 1622 + ALO 1IXXX 8002 OR ILLEG 1622 15 0992 8002 +1 + C RAL 0960 NEX CONSTANT 1911 65 0960 1495 + HED +1 SUB 10 SET CC 8 AND PUNCH +1 + SUB10 ALO P0010 1405 15 1986 1841 + ALO 84TH 1841 15 1494 1799 + STL P0010 1799 20 1986 1739 + PCH P0001 8003 1739 71 1977 8003 +1 + 84TH 00 0800 0000 CONSTANT 1494 00 0800 0000 +1 +1 SUB 11 FIND AND RESERVE B +1 + HED 0 + SUB11 LDD DRUMT TEST 1601 69 1212 1965 + BDO SEX DRUM TAG 1965 90 1520 1620 + STL EXIT IS ADR L 1520 20 1825 1578 + BD6 DI 1578 96 1481 1883 + RAL 8003 SSW L 1883 65 8003 1891 + DI LDD F D OR I 1481 69 1334 1487 + SDA XXXX1 SUB13 FIND OPTIM 1487 22 1961 1814 + GDA SLT 0004 DYNAM ADR 1651 35 0004 1562 + ALO 8002 1562 15 8002 1672 + ALO 8002 SSW 1672 15 8002 1891 + SSW LDD OFF SET SW OFF 1891 69 1544 1797 + STD SW 1797 24 1701 1704 + ALO A1P1 GET TABLE 1704 15 1658 1963 + STL BP1 START ADDR 1963 20 1667 1670 + SLO 1DXXX 1670 16 1020 1875 + STL AO SAI SAVE AO 1875 20 1829 1482 + SAI STL AI 8001 1482 20 1537 8001 + 8001 RAU 9975 TA IS LOCAT 8001 60 9975 1879 + TA NZU YES SW AVAILABLE 1879 44 1933 1701 + SW RAU AI SWOF 1701 60 1537 1941 + SWOF SLO AMAX IS AI MAX 1941 16 1594 1849 + NZE MAX 1849 45 1602 1754 + ALO AMP1 SAI STEP AI 1602 15 1656 1482 + SWON SLO AO IS AI EQUA 1751 16 1829 1384 + NZE FULL TO AO 1384 45 1238 1789 + ALO BP1 SAI STEP AI 1238 15 1667 1482 + MAX LDD ON SET SW ON 1754 69 1708 1612 + STD SW 1612 24 1701 1804 + RAL A1 SAI SET AI TO 1804 65 1758 1482 +1 + FULL HLT 0222 DRUM PAKED 1789 01 0222 1543 + LDD H9XXX SET DRUM 1543 69 1216 1720 + STD DRUMT TAG TO 9 1720 24 1212 1466 + RAL EXIT SEX STEP EXIT 1466 65 1825 1620 + SEX ALO 1IXXX 8002 1620 15 0992 8002 +1 + YES SCT 0000 RESERVE 1933 36 0000 1706 + SLT 0001 LOCATION 1706 35 0001 1864 + SRT 0001 FOUND 1864 30 0001 1722 + STL XXXX2 SAVE P 1722 20 1962 1516 + SUP 8003 1516 11 8003 1773 + SLT 0004 1773 35 0004 1434 + AUP 8001 1434 10 8001 1392 + ALO SRP 8002 1392 15 1545 8002 + 8002 SRT 0009 SCA NULIFY SCT 8002 30 0009 1772 + SCA RAU 8003 1772 60 8003 1929 + ALO AI 1929 15 1537 1442 + LDD ST 1442 69 1595 1148 + SDA ERAS 8001 1148 22 1801 8001 + 8001 STU 9972 CA 8001 21 9972 1925 + CA SUP 8001 CALCULATE 1925 11 8001 1484 + SLO A1 LOCATION 1484 16 1758 1914 + SRT 0004 FOUND 1914 30 0004 1975 + DIV 4I 1975 14 1628 1839 + MPY 500 1839 19 1492 1964 + ALO 8003 1964 15 8003 1822 + SUP 8001 1822 11 8001 1330 + AUP XXXX2 1330 10 1962 1717 + MPY 50 1717 19 1770 1542 + ALO 8003 1542 15 8003 1899 + SUP 8001 EXIT 1899 11 8001 1825 + F 00 0000 GDA CONSTANTS 1334 00 0000 1651 + OFF RAL AI SWOF 1544 65 1537 1941 + A1P1 RAU A0002 TA 1658 60 0601 1879 + AMAX RAU A0200 TA 1594 60 0799 1879 + AMP1 RAU A0201 TA 1656 60 0800 1879 + ON RAL AI SWON 1708 65 1537 1751 + A1 RAU A0001 TA 1758 60 0600 1879 + SRP SRT 0000 SCA 1545 30 0000 1772 + ST STU 9999 CA 1595 21 9999 1925 + 4I 00 0000 0004 1628 00 0000 0004 + 500 00 0000 0500 1492 00 0000 0500 + 50 00 0000 0050 1770 00 0000 0050 + FON RAL 8001 STEPX 1851 65 8001 1859 + AO 01 0000 AO ERASABLE 1829 01 0000 1829 + AI 01 0000 AI 1537 01 0000 1537 + BP1 01 0000 BP1 1667 01 0000 1667 + EXIT 01 0000 EXIT 1825 01 0000 1825 + HED +1 +1 SUB 12 SET BLANK L 8 +1 + SUB12 ALO P0010 0991 15 1986 1592 + ALO 87TH 1592 15 1645 1949 + STL P0010 8003 1949 20 1986 8003 +1 + 87TH 00 0000 8000 CONSTANT 1645 00 0000 8000 +1 +1 SUB 13 CAL OPTIMUM DYNAMI +1 + HED Y + SUB13 STD EXITZ STORE EXIT 1814 24 1416 1820 + BD5 I D OR I 1820 95 1823 1376 + RAL OPTIM D 1823 65 1452 1808 + SLT 0001 1808 35 0001 1616 + SLO 8002 1616 16 8002 1426 + SLT 0001 1426 35 0001 1534 + ALO 8001 1534 15 8001 1642 + SRT 0003 SEO 1642 30 0003 1901 + I RAL OPTIM I 1376 65 1452 1858 + BD2 SHOP SHIFT TEST 1858 92 1662 1666 + BD3 XAS XAS TEST 1666 93 1870 1872 + SLT 0002 SEO 1872 35 0002 1901 + SEO STL XXXX1 SAVE EV OD 1901 20 1961 1716 + RAL OPREG IS BASE 1716 65 1920 1476 + DIV 2IXXX EVEN OR OD 1476 14 1771 1531 + RAU 8003 1531 60 8003 1889 + ALO XXXX1 1889 15 1961 1766 + NZU RB 1766 44 1970 1922 + SLT 0002 1970 35 0002 1327 + RAL 8002 RB 1327 65 8002 1922 + RB SRT 0008 GET BASE 1922 30 0008 1692 + ALO OPREG PLUS DELTA 1692 15 1920 1526 + DIV 50 MOD 50 1526 14 1380 1742 + RAL 8003 EXITZ 1742 65 8003 1416 +1 + SHOP RAL P0007 TLU UNITS 1662 65 1983 1587 + SRT 0004 DIGIT OF 1587 30 0004 1847 + SLT 0009 D ADDRESS 1847 35 0009 1767 + SLO 8002 1767 16 8002 1576 + TLU U0001 1576 84 1250 1756 + ALO GU 8002 1756 15 1909 8002 + 8002 RAL 9969 TOP 8002 65 9969 1873 + TOP SLT 0002 1873 35 0002 1430 + LDD OPTIM IS OP SRD 1430 69 1452 1806 + BD3 SEO 1806 93 1660 1901 + SLT 0004 SEO SRD 1660 35 0004 1901 +1 + XAS RAL P0007 TLU 1870 65 1983 1637 + SRT 0004 D ADDRESS 1637 30 0004 1897 + SLT 0006 1897 35 0006 1712 + SLO 8002 1712 16 8002 1972 + TLU I0001 1972 84 1300 1856 + ALO GXD 8002 1856 15 1710 8002 + 8002 RAL 9968 NXT 8002 65 9968 1923 + NXT SLT 0004 SEO 1923 35 0004 1901 +1 + U0001 00 2322 2524 SHIFT 1250 00 2322 2524 + U0002 10 0706 0706 OPTIMIZING 1251 10 0706 0706 + U0003 20 0706 0908 TABLE 1252 20 0706 0908 + U0004 30 0908 1110 1253 30 0908 1110 + U0005 40 1110 1312 1254 40 1110 1312 + U0006 50 1312 1514 1255 50 1312 1514 + U0007 60 1514 1716 1256 60 1514 1716 + U0008 70 1716 1918 1257 70 1716 1918 + U0009 80 1918 2120 1258 80 1918 2120 + U0010 90 2120 2322 1259 90 2120 2322 +1 + I0001 19 9906 0600 X ACCUM 1300 19 9906 0600 + I0002 79 9907 0700 ADD SUB 1301 79 9907 0700 + I0003 80 0008 0800 TABLE 1302 80 0008 0800 + I0004 80 0106 0600 1303 80 0106 0600 + I0005 80 0209 0800 1304 80 0209 0800 + I0006 80 0308 0900 1305 80 0308 0900 + I0007 90 5908 0800 1306 90 5908 0800 + I0008 99 9909 0900 1307 99 9909 0900 +1 + GU RAL 0000 TOP CONSTANTS 1909 65 0000 1873 + GXD RAL 0000 NXT 1710 65 0000 1923 + 50 00 0000 0050 1380 00 0000 0050 + HED +1 +1 SUB 14 PUNCH AVAIL TABLE +1 + HED P + SUB14 STD EXITX STORE EXIT 1403 24 1196 1652 + LDD 85TH SET PUNCH 1652 69 1906 1760 + STD P0010 8 1760 24 1986 1939 + LDD A1 INIT A1 1939 69 1792 1695 + STD XXXX1 1695 24 1961 1816 + RAL RS1 LOOP INIT RS 1816 65 1973 1377 + LOOP AUP C1 8001 1377 10 1480 8001 + 8001 STL 9999 NEXT SET LOCAT 8001 20 9999 1702 + NEXT SUP TW1 1702 11 1908 1866 + NZU SRS 1866 44 1274 1324 + AUP C2 1274 10 1427 1581 + ALO C3 8003 1581 15 1584 8003 + SRS STL XXXX2 SAVE RS 1324 20 1962 1916 + RAU C4 1916 60 1374 1530 + ALO XXXX1 8002 1530 15 1961 8002 + 8002 LDD 9998 8003 STORE 8002 69 9998 8003 + 8003 STD 9997 TP AV TABLE 8003 24 9997 1752 + TP SUP TW2 1752 11 1810 1966 + NZU PUN 1966 44 1424 1474 + AUP C5 1424 10 1477 1631 + ALO C6 8002 1631 15 1634 8002 + PUN PCH P0001 1474 71 1977 1527 + SLO AIM IS AI MAX 1527 16 1580 1335 + NZE EXITX 1335 45 1288 1196 + ALO AMP1 STEP AI 1288 15 1842 1947 + STL XXXX1 1947 20 1961 1817 + RAL XXXX2 1817 65 1962 1867 + SLO C7 LOOP 1867 16 1524 1377 +1 + C1 STL P0001 NEXT CONSTANTS 1480 20 1977 1702 + C2 STL P0009 NEXT 1427 20 1985 1702 + C3 00 0500 0500 1584 00 0500 0500 + C4 STD P0002 TP 1374 24 1978 1752 + C5 STD P0010 TP 1477 24 1986 1752 + C6 00 0001 0000 1634 00 0001 0000 + C7 00 1499 1499 1524 00 1499 1499 + TW1 STL P0007 NEXT 1908 20 1983 1702 + TW2 STD P0008 TP 1810 24 1984 1752 + 85TH 00 0080 0000 1906 00 0080 0000 + A1 LDD A0001 8003 1792 69 0600 8003 + RS1 00 0000 0450 1973 00 0000 0450 + AIM LDD A0200 8003 1580 69 0799 8003 + AMP1 LDD A0201 8003 1842 69 0800 8003 + HED +1 +1 SUB 15 HEADING ROUTINE +1 + HED H + SUB15 STD EXITY SAVE EXIT 1663 24 1456 1860 + LDD 8003 IS C1 1860 69 8003 1917 + SLT 0008 BLANK 1917 35 0008 1385 + NZU DH 1385 44 1989 1240 + RAU 8001 HEAD 1240 60 8001 1997 + AUP 0000H EXITY 1997 10 1329 1456 + DH RAU 8001 EXITY DONT HEAD 1989 60 8001 1456 + HED +1 +1 SUB 16 INITIALIZATION +1 + SUB16 STD EXITY STORE EXIT 1353 24 1456 1910 + RAL I1 1910 65 1967 1574 + STU P0009 ZERO CARD 1574 21 1985 1338 + STD 0000H ZERO HEAD 1338 24 1329 1532 + LDD SUBR1 ZERO SYM T 1532 69 1435 1600 + RAL I2 MAKE DRUM 1435 65 1388 1593 + AUP I3 AVAILABLE 1593 10 1446 1802 + LDD SUBR1 1802 69 1762 1600 + LDD H8XXX SET DRUM 1762 69 1406 1812 + STD DRUMT TAG TO 8 1812 24 1212 1268 + LDD I4 SET SWSYM 1268 69 1624 1577 + STD SWSYM OFF 1577 24 1437 1290 + RAL I5 UNDEFINE 1290 65 1643 1198 + AUP H8XXX REGIONS 1198 10 1406 1862 + LDD EXITY SUBR1 1862 69 1456 1600 +1 + I1 00 S0001 E0200 CONSTANTS 1967 00 0000 0599 + I2 00 A0001 A0200 1388 00 0600 0799 + I3 11 1111 1111 1446 11 1111 1111 + I4 01 0111 SYMOF 1624 01 0111 1691 + I5 00 1021 1049 1643 00 1021 1049 + PACOF BD6 FINDI FINDL 1852 96 1912 1318 +1 +1 SUB 17 CALC 800X EQUIVALE +1 + HED X + SB17D LDD DEQ DI D EQUIV 1902 69 1368 1674 + SB17I LDD IEQ DI I EQUIV 1854 69 1418 1674 + DI STD XXXX1 SAVE TAG 1674 24 1961 1468 + STU EXITY STORE EXIT 1468 21 1456 1518 + STL XXXX2 STORE 800X 1518 20 1962 1618 + LDD XXXX1 SUB13 GET OPTIM 1618 69 1961 1814 + SDA STL XXXX1 DYNAM ADDR 1904 20 1961 1668 + DIV 2IXXX IS DY ADDR 1668 14 1771 1681 + NZU OD EV EVEN OR OD 1681 44 1485 1636 + OD RAL 8002 EO 1485 65 1438 1693 + EV RAL 8003 EO 1636 65 1340 1693 + EO SLO XXXX2 1693 16 1962 1718 + NZE ADD1 1718 45 1724 1774 + RAL XXXX1 EXITY 1724 65 1961 1456 + ADD1 RAL XXXX1 1774 65 1961 1768 + ALO 1IXXX EXITY 1768 15 0992 1456 +1 + DEQ 00 0008 SDA CONSTANTS 1368 00 0008 1904 + IEQ 00 0009 SDA 1418 00 0009 1904 + 8002 00 0000 8002 1438 00 0000 8002 + 8003 00 0000 8003 1340 00 0000 8003 + HED +1 +1 SUB 18 INDEX ADDRESS +1 + HED W + INDEX STD EXITY STORE EXIT 1818 24 1456 1868 + STL XXXX1 STORE ADDR 1868 20 1961 1918 + RAU 1954 1918 60 1954 1968 + SLT 0007 1968 35 0007 1535 + LDD EXITY 1535 69 1456 1824 + BD5 D D OR I 1824 95 1627 1630 + SLT 0002 D 1630 35 0002 1627 + D SRT 0009 1627 30 0009 1248 + MPY 2000I 1248 19 1014 1585 + LDD EXITY 1585 69 1456 1874 + BD6 DS DRUM 0 COR 1874 96 1677 1680 + SRT 0001 DS CORE 1680 30 0001 1677 + DS ALO XXXX1 EXITY 1677 15 1961 1456 +1 + EXITY 01 0000 EXITY ERASABELE 1456 01 0000 1456 + HED +1 +1 SUB 19 PROCESS LOCATI +1 + REG D0923 0923 PROC L + REG G0925 0925 + REG J0928 0928 + REG K0931 0931 + REG L0933 0933 +1 + HED A + PROCL STD EXITX STORE EXIT 0969 24 1196 1924 + RAU 1951 IS L BLANK 1924 60 1951 1974 + NZU NB 1974 44 1727 1678 + LDD DRUMT BLANK TEST 1678 69 1212 1626 + BDO B D0002 DRUM TAG 1626 90 1730 0924 + B RAL OPREG SETL BLANK 1730 65 1920 1676 + SETL SLT 0004 SET L 1676 35 0004 1687 + LDD P0008 TO DR 1687 69 1984 1737 + SDA P0008 EXITX 1737 22 1984 1196 + NB LDD G SUBR4 WHAT IS L 1727 69 1780 1213 + G0001 RAL 1957 K0001 ABSOLUTE 0925 65 1957 0931 + G0002 LDD K SUBR9 REGIONAL 0926 69 1830 1174 + G0003 LDD J SUBR6 SYMBOLIC 0927 69 1880 1275 + K0001 LDD L SUBR5 TEST RANGE 0931 69 1684 1750 + K0002 RAU 87TH X REG ERROR 0932 60 1635 1390 + X AUP P0010 SET BLANK 1390 10 1986 1892 + STU P0010 SETL L8 1892 21 1986 1676 + L0001 STL OPREG SETL DRUM ADDR 0933 20 1920 1676 + L0002 AUP 86TH 800X 800X 0934 10 1787 1942 + L0003 LDD ORCEQ 89X CORE ADDR 0935 69 1488 1743 + L0004 RAU 87TH X OTHER 0936 60 1635 1390 + 800X LDD ORXEQ 89X 1942 69 1745 1743 + 89X STD OPREG X 1743 24 1920 1390 + J0001 RAL EQUIV K0001 SYM DEFIND 0928 65 1223 0931 + J0002 RAL D SUB11 SYM UNDEF 0929 65 1582 1601 + J0003 RAU 87TH X S TAB FULL 0930 60 1635 1390 + D0001 STL OPREG SS S EQ FOUND 0923 20 1920 1726 + D0002 RAU 87TH X DRUM PAKED 0924 60 1635 1390 + SS AUP HSYMB STORE 1726 10 1230 1685 + ALO LSYMB SYMBOL 1685 15 1551 1776 + LDD B SUBR7 1776 69 1730 1279 +1 + G 00 0000 G0001 CONSTANTS 1780 00 0000 0925 + K 00 0090 K0001 1830 00 0090 0931 + J 00 0000 J0001 1880 00 0000 0928 + L 00 0000 L0001 1684 00 0000 0933 + D 00 0090 D0001 1582 00 0090 0923 + 86TH 00 0008 0000 1787 00 0008 0000 + 87TH 00 0000 8000 1635 00 0000 8000 + EXITX 01 0000 EXITX ERASEABLE 1196 01 0000 1196 + HED +1 +1 SUB 20 PROCESS DATA ADDRE +1 + REG D0937 0937 PROC D + REG F0939 0939 + REG G0941 0941 + REG J0944 0944 + REG K0946 0946 + REG L0949 0949 +1 + HED B + PROCD STD EXITX STORE EXIT 0972 24 1196 1826 + RAU 1952 IS D BLANK 1826 60 1952 1876 + NZU NB 1876 44 1930 1731 + RAL D SUB11 FIND 1731 65 1734 1601 + D0001 STL ORBAL L0004 OPTIMUM 0937 20 1793 0952 + D0002 RAU 88TH X DRUM PAKED 0938 60 1843 1298 + BT LDD OPTIM IS OP 1926 69 1452 1976 + BD1 EXITX A BRANCH 1976 91 1196 1781 + STL OPREG EXITX D TO OR 1781 20 1920 1196 + X AUP P0010 SET BLANK 1298 10 1986 1893 + STU P0010 EXITX 1893 21 1986 1196 + NB LDD G SUBR4 WHAT IS D 1930 69 1784 1213 + G0001 RAL 1958 J0001 ABSOLUTE 0941 65 1958 0944 + G0002 LDD J SUBR9 REGIONAL 0942 69 1795 1174 + G0003 LDD K SUBR6 SYMBOLIC 0943 69 1496 1275 + J0001 LDD L SUBR5 TEST RANGE 0944 69 1348 1750 + J0002 RAU 88TH X REG ERROR 0945 60 1843 1298 + L0001 LDD AXD INDEX DRUM ADDR 0949 69 1777 1818 + L0002 SLT 0004 800X 800X 0950 35 0004 1827 + L0003 LDD AXC INDEX CORE ADDR 0951 69 1877 1818 + L0004 SLT 0004 SD OTHER 0952 35 0004 1927 + 800X LDD P0007 SET 800X D 1827 69 1983 1686 + SDA P0007 1686 22 1983 1736 + SRT 0004 1736 30 0004 1398 + AUP XEQ SB17D GET 800X E 1398 10 1728 1902 + SCD SLT 0004 SET CORE D 1778 35 0004 1440 + LDD P0007 1440 69 1983 1786 + SDA P0007 1786 22 1983 1836 + SRT 0004 1836 30 0004 1448 + LDD CEQ SUB13 GET CORE E 1448 69 1828 1814 + SCEQ STL ORCEQ BT SAVE CORE 1878 20 1488 1926 + K0001 RAL EQUIV J0001 SYM DEFIND 0946 65 1223 0944 + K0002 RAL F SUB11 SYM UNDEF 0947 65 1928 1601 + K0003 RAU 88TH X S TAB FULL 0948 60 1843 1298 + F0001 STL EQ SS SAVE EQ 0939 20 1943 1546 + F0002 RAU 88TH X DRUM PAKED 0940 60 1843 1298 + SS AUP HSYMB STORE 1546 10 1230 1735 + ALO LSYMB SYMBOL 1735 15 1551 1831 + LDD SUBR7 1831 69 1834 1279 + RAL EQ L0004 1834 65 1943 0952 + SD LDD P0007 SET D ADDR 1927 69 1983 1886 + SDA P0007 1886 22 1983 1936 + SRT 0004 BT 1936 30 0004 1926 + D 00 0088 D0001 CONSTANTS 1734 00 0088 0937 + G 00 0000 G0001 1784 00 0000 0941 + J 00 0088 J0001 1795 00 0088 0944 + L 00 0000 L0001 1348 00 0000 0949 + F 00 0088 F0001 1928 00 0088 0939 + K 00 0000 K0001 1496 00 0000 0946 + AXD 00 0088 D0001 1777 00 0088 0937 + AXC 00 0098 SCD 1877 00 0098 1778 + XEQ STL ORXEQ BT 1728 20 1745 1926 + CEQ 00 0008 SCEQ 1828 00 0008 1878 + 88TH 00 0000 0800 1843 00 0000 0800 + EQ 01 0000 EQ ERASABLE 1943 01 0000 1943 + HED +1 +1 SUB 21 PROCESS INSTR ADDR +1 + REG D0953 0953 PROC I + REG F0955 0955 + REG G0958 0958 + REG J0960 0960 + REG K0962 0962 + REG L0965 0965 +1 + HED C + PROCI STD EXITX STORE EXIT 1453 24 1196 1881 + RAU 1953 IS I BLANK 1881 60 1953 1931 + NZU NB 1931 44 1785 1837 + RAU 1952 IS D BLANK 1837 60 1952 1632 + NZU DNB 1632 44 1835 1887 + LDD DRUMT D I BLANK 1887 69 1212 1682 + BDO G0002 TEST DRUM 1682 90 1937 0959 + RAL ORBAL L0004 TAG 1937 65 1793 0968 + DNB RAL D SUB11 FIND BEST 1835 65 1538 1601 + D0001 STL ORBAL L0004 FOUND 0953 20 1793 0968 + D0002 RAL P0010 X DRUM PAKED 0954 65 1986 1993 + X ALO 89TH 1993 15 1596 1732 + STL P0010 EXITX 1732 20 1986 1196 + NB LDD F SUBR4 WHAT IS I 1785 69 1588 1213 + F0001 RAL 1959 J0001 ABSOLUTE 0955 65 1959 0960 + F0002 LDD J SUBR9 REGIONAL 0956 69 1782 1174 + F0003 LDD K SUBR6 SYMBOLIC 0957 69 1832 1275 + J0001 LDD L SUBR5 TEST RANGE 0960 69 1882 1750 + J0002 RAL P0010 X REG ERROR 0961 65 1986 1993 + L0001 LDD AXD INDEX DRUM ADDR 0965 69 1932 1818 + L0002 LDD P0007 800X 800X 0966 69 1983 1987 + L0003 LDD AXC INDEX CORE ADDR 0967 69 1884 1818 + L0004 LDD P0007 OTHER 0968 69 1983 1638 + SIA P0007 MOR 1638 23 1983 1688 + 800X SIA P0007 1987 23 1983 1738 + AUP XEQ SB17I GET 800X E 1738 10 1644 1854 + 90XX LDD P0007 SET CORE 1934 69 1983 1788 + SIA P0007 ADDRESS 1788 23 1983 1838 + LDD CEQ SUB13 GET CORE E 1838 69 1694 1814 + K0001 RAL EQUIV J0001 SYM DEFIND 0962 65 1223 0960 + K0002 RAL G SUB11 SYM UNDEF 0963 65 1885 1601 + K0003 RAL P0010 X S TAB FULL 0964 65 1986 1993 + G0001 LDD P0007 SI FOUND BEST 0958 69 1983 1888 + G0002 RAL P0010 X DRUM PAKED 0959 65 1986 1993 + SI SIA P0007 1888 23 1983 1938 + AUP HSYMB STORE 1938 10 1230 1935 + ALO LSYMB SYMBOL 1935 15 1551 1988 + LDD MOR SUBR7 1988 69 1688 1279 + MOR LDD ORBAL SET OR 1688 69 1793 1646 + STD OPREG EXITX TO ORB 1646 24 1920 1196 + SCEQ STL ORCEQ MOR SAVE CORE 1490 20 1488 1688 +1 + D 00 0089 D0001 CONSTANTS 1538 00 0089 0953 + F 00 0000 F0001 1588 00 0000 0955 + J 00 0089 J0001 1782 00 0089 0960 + K 00 0000 K0001 1832 00 0000 0962 + L 00 0000 L0001 1882 00 0000 0965 + G 00 0089 G0001 1885 00 0089 0958 + 89TH 00 0000 0080 1596 00 0000 0080 + AXD 00 0089 L0004 1932 00 0089 0968 + AXC 00 0099 90XX 1884 00 0099 1934 + XEQ STL ORXEQ MOR 1644 20 1745 1688 + CEQ 00 0009 SCEQ 1694 00 0009 1490 + HED +1 + 1IXXX 00 0000 0001 CONSTANTS 0992 00 0000 0001 + 1DXXX 00 0001 0000 1020 00 0001 0000 + 2IXXX 00 0000 0002 1771 00 0000 0002 + 2DXXX 00 0002 0000 1764 00 0002 0000 + H8XXX 80 0000 0000 1406 80 0000 0000 + H9XXX 90 0000 0000 1216 90 0000 0000 + 90XXX 00 0000 0090 1178 00 0000 0090 + 29XXX 00 0000 0029 1189 00 0000 0029 + 2000I 00 0000 2000 CONSTANT 1014 00 0000 2000 + TORG 00 0000 T0001 0990 00 0000 1990 +1 + PAT +0000 0000000000 0450 0500 0000000000 0950 1000 0000000000 1450 1500 0000000000 1950 +0001 0000000000 0451 0501 0000000000 0951 1001 0000000000 1451 1501 0000000000 1951 +0002 0000000000 0452 0502 0000000000 0952 1002 0000000000 1452 1502 0000000000 1952 +0003 0000000000 0453 0503 0000000000 0953 1003 0000000000 1453 1503 0000000000 1953 +0004 0000000000 0454 0504 0000000000 0954 1004 0000000000 1454 1504 0000000000 1954 +0005 0000000000 0455 0505 0000000000 0955 1005 0000000000 1455 1505 0000000000 1955 +0006 0000000000 0456 0506 0000000000 0956 1006 0000000000 1456 1506 0000000000 1956 +0007 0000000000 0457 0507 0000000000 0957 1007 0000000000 1457 1507 0000000000 1957 +0008 0000000000 0458 0508 0000000000 0958 1008 0000000000 1458 1508 0000000000 1958 +0009 0000000000 0459 0509 0000000000 0959 1009 0000000000 1459 1509 0000000000 1959 +0010 0000000000 0460 0510 0000000000 0960 1010 0000000000 1460 1510 0000000000 1960 +0011 0000000000 0461 0511 0000000000 0961 1011 0000000000 1461 1511 0000000000 1961 +0012 0000000000 0462 0512 0000000000 0962 1012 0000000000 1462 1512 0000000000 1962 +0013 0000000000 0463 0513 0000000000 0963 1013 0000000000 1463 1513 0000000000 1963 +0014 0000000000 0464 0514 0000000000 0964 1014 0000000000 1464 1514 0000000000 1964 +0015 0000000000 0465 0515 0000000000 0965 1015 0000000000 1465 1515 0000000000 1965 +0016 0000000000 0466 0516 0000000000 0966 1016 0000000000 1466 1516 0000000000 1966 +0017 0000000000 0467 0517 0000000000 0967 1017 0000000000 1467 1517 0000000000 1967 +0018 0000000000 0468 0518 0000000000 0968 1018 0000000000 1468 1518 0000000000 1968 +0019 0000000000 0469 0519 0000000000 0969 1019 0000000000 1469 1519 0000000000 1969 +0020 0000000000 0470 0520 0000000000 0970 1020 0000000000 1470 1520 0000000000 1970 +0021 0000000000 0471 0521 0000000000 0971 1021 0000000000 1471 1521 0000000000 1971 +0022 0000000000 0472 0522 0000000000 0972 1022 0000000000 1472 1522 0000000000 1972 +0023 0000000000 0473 0523 0000000000 0973 1023 0000000000 1473 1523 0000000000 1973 +0024 0000000000 0474 0524 0000000000 0974 1024 0000000000 1474 1524 0000000000 1974 +0025 0000000000 0475 0525 0000000000 0975 1025 0000000000 1475 1525 0000000000 1975 +0026 0000000000 0476 0526 0000000000 0976 1026 0000000000 1476 1526 0000000000 1976 +0027 0000000000 0477 0527 0000000000 0977 1027 0000000000 1477 1527 0000000000 1977 +0028 0000000000 0478 0528 0000000000 0978 1028 0000000000 1478 1528 0000000000 1978 +0029 0000000000 0479 0529 0000000000 0979 1029 0000000000 1479 1529 0000000000 1979 +0030 0000000000 0480 0530 0000000000 0980 1030 0000000000 1480 1530 0000000000 1980 +0031 0000000000 0481 0531 0000000000 0981 1031 0000000000 1481 1531 0000000000 1981 +0032 0000000000 0482 0532 0000000000 0982 1032 0000000000 1482 1532 0000000000 1982 +0033 0000000000 0483 0533 0000000000 0983 1033 0000000000 1483 1533 0000000000 1983 +0034 0000000000 0484 0534 0000000000 0984 1034 0000000000 1484 1534 0000000000 1984 +0035 0000000000 0485 0535 0000000000 0985 1035 0000000000 1485 1535 0000000000 1985 +0036 0000000000 0486 0536 0000000000 0986 1036 0000000000 1486 1536 0000000000 1986 +0037 0000000000 0487 0537 0000000000 0987 1037 0000000000 1487 1537 0000000000 1987 +0038 0000000000 0488 0538 0000000000 0988 1038 0000000000 1488 1538 0000000000 1988 +0039 0000000000 0489 0539 0000000000 0989 1039 0000000000 1489 1539 0000000000 1989 +0040 0000000000 0490 0540 0000000000 0990 1040 0000000000 1490 1540 1111111110 1990 +0041 0000000000 0491 0541 0000000000 0991 1041 0000000000 1491 1541 0000000000 1991 +0042 0000000000 0492 0542 0000000000 0992 1042 0000000000 1492 1542 0000000000 1992 +0043 0000000000 0493 0543 0000000000 0993 1043 0000000000 1493 1543 0000000000 1993 +0044 0000000000 0494 0544 0000000000 0994 1044 0000000000 1494 1544 0000111111 1994 +0045 0000000000 0495 0545 0000000000 0995 1045 0000000000 1495 1545 0000001111 1995 +0046 0000000000 0496 0546 0000000000 0996 1046 0000000000 1496 1546 0001111111 1996 +0047 0000000000 0497 0547 0000000000 0997 1047 0000000000 1497 1547 0000000000 1997 +0048 0000000000 0498 0548 0000000000 0998 1048 0000000001 1498 1548 1111111110 1998 +0049 0000000000 0499 0549 0000000000 0999 1049 0000000000 1499 1549 0000000000 1999 diff --git a/I650/sw/soap_src.txt b/I650/sw/soap_src.txt new file mode 100644 index 00000000..9ff3affd --- /dev/null +++ b/I650/sw/soap_src.txt @@ -0,0 +1,1399 @@ + 1 soap 2 + 1 + 1 symbolic optimal assembly prog + 1 + 1 for the + 1 + 1 ibm 650 + 1 + 1 data processing system + 1 + regs0000 0399 symbol tab + rege0400 0599 equiv tabl + rega0600 0799 avail tabl + regn0800 0899 num op tab + blr 1000 1000 entry + blr 1001 1012 pseudo ent + blr 1021 1049 reg table + regc1050 1164 sym op tab + bla 1098 1099 + bla 1148 1149 + blr 1900 1900 manual pat + synreadc 1950 + blr 1951 1962 read area + regt1990 1992 type + regp1977 1986 punch area + blr 1998 1999 + equxxxx1 1961 + equxxxx2 1962 + blr 1563 1570 type2 + bla 1565 1565 + bla 1569 1569 + regb0900 0901 sub 2 + regh0902 0904 type 2 + regm0905 0907 + regq0908 0909 + regr1200 1207 sub 5 + regu1250 1259 sub 13 + regv0910 0912 equ syn + regx0913 0914 type 0 + regy0915 0916 equ syn + regz0917 0919 + regw0920 0922 + blr 0923 0968 multiple r + regi1300 1307 sub 13 + 1 + 1 control program + 1 + 1000lddreadc sub16 entry + 1 + readcrcd 1999 1998 read card + 1998ldd 1951 transfer + stdp0001 alphabetic + ldd 1952 input + stdp0002 to + ldd 1953 output + stdp0003 + ldd 1954 + stdp0004 + ldd 1955 + stdp0005 + ldd 1956 + stdp0006 + ralp0009 step + alo1ixxx card + stlp0009 number + rau 1960 store + srt 0002 control + stup0008 info + auptorg + stlp0010 8003 transfer + 8003nop 0000 9999 to type + 1 + punchpchp0001 readc punch read + 1 + setccraureadc sub10 sudo exit + 1 + 1900lddreadc sub14 manual pat + t0001lddx subr3 type 0 + 1 + x0001ldd procl 650 + ldd procd command or + lddpunch proci constants + 1 + x0002nop 0000 8003 pseudo op + 1 + t0002raureadc sub10 type 1 com + 1 + x 00 0000 x0001 + 1 + 1 relocate routine + 1 + hedt + t0003lddq subr3 process op + q0002nop 0000 illop illegal op + q0001ral 1951 is l fixed + slt 0002 + nzu rel + rau 1957 fixed l + sup2000i drum core + bmi fc + aup 8001 res fixed drum + fc ral 1957 setl fixed core + sr ralxxxx1 setl set l + setl slt 0004 + lddp0008 + sdap0008 prod + rel rau 1957 drum core + sup2000i + bmi rc + aupddiff relocate + bmi bl drum addr + aup2000i res + res stuxxxx1 + lddsr sub2r reserve l + rc ral 1957 relocate + alocdiff core + slo9060 + bmi bl + alo 8001 setl + bl rauprod sub12 blank l + 1 + regj0944 0944 d type 2 + regg0941 0941 + 1 + prod lddproi set d exit + stdexitx + rau 1952 what is d + lddh subr4 + h0001ral 1958 relocate + slo2000i d or c + bmi 1564 1563 + h0002srt 0008 c d or f + aup1500 8003 + 1563ralcdiff cdd c + 1564ralddiff cdd d + 1566ral 1958 j0001 f + cdd alo 1958 j0001 + h0003nop 0000 g0003 symbolic + 1 + regj0960 0960 i + regf0955 0955 + 1 + proi lddpunch set i exit + stdexitx + rau 1953 what is i + lddm subr4 + m0001ral 1959 relocate + slo2000i d or c + bmi 1568 1567 + m0002srt 0008 c d or f + aup1504 8003 + 1567ralcdiff cdi c + 1568ralddiff cdi d + 1570ral 1959 j0001 f + cdi alo 1959 j0001 + m0003nop 0000 f0003 symbolic + 1 + q 00 0000 q0001 constants + 9060 00 0000 9060 + h 00 0000 h0001 + 1500 00 0000 1500 + m 00 0000 m0001 + 1504 00 0000 1504 + xxxx1 01 0000 xxxx1 eraseable + hed + 1 + 1 bop routine + 1 + 1001ldd sub16 initialize + raureadc sub10 punch + 1 + 1 blr routine + 1 + 1002ral 1959 blr reserve + blr slo 1958 fwa to + aup 8001 lwa + lddsetcc sub2r + 1 + 1 rbr routine + 1 + 1012rauddiff + alo 1959 blr + 1 + 1 bla routine + 1 + 1003lddh8xxx set drum + stddrumt tag to 8 + ral 1959 unreserve + slo 1958 fwa + aup 8001 to + lddsetcc sub2u lwa + 1 + 1 reg routine + 1 + hedr + 1004ral 1952 is + srt 0008 region + slo90xxx character + bmi 1002 alphabetic + alo29xxx + bmi 1002 + slt 0004 store + alost region + aup 1958 origin + auph9xxx 8002 + 8002stu 9999 1002 + 1 + st stu 1021 1002 constants + hed + 1 + 1 equ req and syn routine + 1 + hedz + 1005lddh8xxx both equ + 1006lddh9xxx both syn + both stdtag + rau 1953 what is i + lddz subr4 + z0001ral 1959 y0001 absolute + z0002lddy subr9 regional + y0001stle td + y0002ralp0010 bp reg error + z0003lddw subr6 symbolic + w0001ralequiv y0001 s defined + w0002ralp0010 bp s undefind + w0003ralp0010 bp s tab full + 1 + td rau 1952 head d + ldd sub15 and equate + lddv subr6 to e + v0003ralp0010 bp s tab full + v0001aloe sd + v0002aloe sd + sd lddtt subr7 + 1 + tt lddtag test tag + bdosetcc + raue reserve e + lddsetcc sub2r + 1 + 1011lddh8xxx req + stdtag routine + ral 1959 is i + slo2000i drum o cor + bmid + alocdiff cd + d aloddiff cd + cd alo2000i y0001 + 1 + z 00 0000 z0001 constants + y 00 0089 y0001 + w 00 0000 w0001 + v 00 0000 v0001 + 88 00 8800 0000 + 1 + bp alo88 by pass + stlp0010 punch + 1 + tag 01 0000 tag eraseable + e 01 0000 e + hed + 1 + 1 alf routine + 1 + 1007ldd procl proces loc + ldd 1952 + stdp0007 + ral 1953 replace + nzepunch blank i + lddsoap2 by + stdp0003 punch soap2 + soap2alfsoap2 soap2 constant + 1 + 1 pat routine + 1 + 1008rau sub10 + lddreadc sub14 + 1 + 1 hed routine + 1 + 1009ral 1952 store + srt 0008 heading + stl0000h setcc character + 1 + 1 rel routine + 1 + hedm + 1010ral 1952 set + nze sdd drum + ral 1958 sdd and + sdd stlddiff core + ral 1953 deltas + nze scd + ral 1959 scd + scd stlcdiff setcc + 1 + ddiff 01 0000 ddiff eraseable + cdiff 01 0000 cdiff + hed + 1 + 1 load availablity table + 1 + hedl + 1999ral 1951 calc + srt 0004 loc + slt 0004 w2 + alo 8002 + alo 8002 + aloc1 + aupc2 8003 + 8003ldd 9995 8002 load + 8002std 9994 tup table + tup suptw + nzu readc + auptwp2 + alo1dxxx 8003 + 1 + c1 stda0001 tup constants + c2 ldd 1952 8002 + tw ldd 1958 8002 + twp2 ldd 1960 8002 + hed + 1 optimizing table + 1 + n0001 00 0404 0998 nop + n0002 00 0404 0998 hlt + n0003 33 2322 0999 ufa + n0004 00 0505 0998 rtc + n0005 00 0505 0998 rtn + n0006 00 0505 0998 rta + n0007 00 0505 0998 wtn + n0008 00 0505 0998 wta + n0009 33 1212 0999 lib + n0010 33 0202 0999 ldi + n0011 33 0504 0999 aup + n0012 33 0504 0999 sup + n0013 99 9999 9999 not used + n0014 99 9999 9999 not used + n0015 33 1110 0999 div + n0016 33 0504 0999 alo + n0017 33 0504 0999 slo + n0018 33 0504 0999 aml + n0019 33 0504 0999 sml + n0020 33 2120 0999 mpy + n0021 54 0303 0999 stl + n0022 45 0303 0999 stu + n0023 34 0303 0999 sda + n0024 34 0303 0999 sia + n0025 33 0303 0999 std + n0026 44 0505 0998 nts + n0027 00 0505 0998 bin + n0028 00 0505 0998 set + n0029 33 1212 0999 sib + n0030 33 0202 0999 sti + n0031 00 0000 0988 srt + n0032 00 0000 0888 srd + n0033 33 2726 0999 fad + n0034 33 2726 0999 fsb + n0035 33 0000 0999 fdv + n0036 00 0000 0988 slt + n0037 00 0000 0988 sct + n0038 33 2726 0999 fam + n0039 33 2726 0999 fsm + n0040 33 0000 0999 fmp + n0041 33 0404 0998 nza + n0042 33 0404 0998 bmz + n0043 33 0404 0998 nzb + n0044 33 0404 0998 bmb + n0045 34 0405 0998 nzu + n0046 43 0504 0998 nze + n0047 33 0404 0998 bmi + n0048 33 0505 0998 bov + n0049 33 0404 0998 nzc + n0050 33 0404 0998 bmc + n0051 00 0000 0898 axa + n0052 00 0000 0898 sxa + n0053 00 0000 0898 axb + n0054 00 0000 0898 sxb + n0055 44 0505 0998 nef + n0056 00 0505 0998 rwd + n0057 00 0505 0998 wtm + n0058 00 0505 0998 bst + n0059 00 0000 0898 axc + n0060 00 0000 0898 sxc + n0061 33 0504 0999 rau + n0062 33 0504 0999 rsu + n0063 99 9999 9999 not used + n0064 99 9999 9999 not used + n0065 33 1110 0999 dvr + n0066 33 0504 0999 ral + n0067 33 0504 0999 rsl + n0068 33 0504 0999 ram + n0069 33 0504 0999 rsm + n0070 33 0303 0999 ldd + n0071 00 0000 0999 rd1 + n0072 00 0000 0999 wr1 + n0073 00 0000 0999 rc1 + n0074 00 0000 0999 rd2 + n0075 00 0000 0999 wr2 + n0076 00 0000 0999 rc2 + n0077 00 0000 0999 rd3 + n0078 00 0000 0999 wr3 + n0079 00 0000 0999 rc3 + n0080 00 0505 0999 rpy + n0081 00 0000 0898 raa + n0082 00 0000 0898 rsa + n0083 00 0000 0898 rab + n0084 00 0000 0898 rsb + n0085 33 0506 0999 tlu + n0086 00 0606 0998 sds + n0087 00 0606 0998 rds + n0088 00 0606 0998 wds + n0089 00 0000 0898 rac + n0090 00 0000 0898 rsc + n0091 44 0505 0998 bdo + n0092 33 0505 0998 bd1 + n0093 33 0505 0998 bd2 + n0094 33 0505 0998 bd3 + n0095 33 0505 0998 bd4 + n0096 33 0505 0998 bd5 + n0097 33 0505 0998 bd6 + n0098 33 0505 0998 bd7 + n0099 33 0505 0998 bd8 + n0100 44 0505 0998 bd9 + 1 + 1 symbolic op table + 1 + c0001 61 7366 1007 alf + c0002 61 7376 0015 alo + c0003 61 7473 0017 aml + c0004 61 8477 0010 aup + c0005 61 8761 0050 axa + c0006 61 8762 0052 axb + c0007 61 8763 0058 axc + c0008 62 6476 0090 bdo + c0009 62 6491 0091 bd1 + c0010 62 6492 0092 bd2 + c0011 62 6493 0093 bd3 + c0012 62 6494 0094 bd4 + c0013 62 6495 0095 bd5 + c0014 62 6496 0096 bd6 + c0015 62 6497 0097 bd7 + c0016 62 6498 0098 bd8 + c0017 62 6499 0099 bd9 + c0018 62 6975 0026 bin + c0019 62 7361 1003 bla + c0020 62 7379 1002 blr + c0021 62 7461 0041 bma + c0022 62 7462 0043 bmb + c0023 62 7463 0049 bmc + c0024 62 7469 0046 bmi + c0025 62 7677 1001 bop + c0026 62 7685 0047 bov + c0027 62 8283 0057 bst + c0028 64 6985 0014 div + c0029 64 8579 0064 dvr + c0030 65 7884 1005 equ + c0031 66 6164 0032 fad + c0032 66 6174 0037 fam + c0033 66 6485 0034 fdv + c0034 66 7477 0039 fmp + c0035 66 8262 0033 fsb + c0036 66 8274 0038 fsm + c0037 68 6564 1009 hed + c0038 68 7383 0001 hlt + c0039 73 6464 0069 ldd + c0040 73 6469 0009 ldi + c0041 73 6962 0008 lib + c0042 74 7788 0019 mpy + c0043 75 6566 0054 nef + c0044 75 7677 0000 nop + c0045 75 8382 0025 nts + c0046 75 8961 0040 nza + c0047 75 8962 0042 nzb + c0048 75 8963 0048 nzc + c0051 75 8965 0045 nze + c0052 75 8984 0044 nzu + c0053 77 6183 1008 pat + c0054 77 6368 0071 pch + c0055 79 6161 0080 raa + c0056 79 6162 0082 rab + c0057 79 6163 0088 rac + c0058 79 6173 0065 ral + c0059 79 6174 0067 ram + c0060 79 6184 0060 rau + c0061 79 6279 1012 rbr + c0062 79 6364 0070 rcd + c0063 79 6391 0072 rc1 + c0064 79 6392 0075 rc2 + c0065 79 6393 0078 rc3 + c0066 79 6482 0086 rds + c0067 79 6491 0070 rd1 + c0068 79 6492 0073 rd2 + c0069 79 6493 0076 rd3 + c0070 79 6567 1004 reg + c0071 79 6573 1010 rel + c0072 79 6578 1011 req + c0073 79 7788 0079 rpy + c0074 79 8261 0081 rsa + c0075 79 8262 0083 rsb + c0076 79 8263 0089 rsc + c0077 79 8273 0066 rsl + c0078 79 8274 0068 rsm + c0079 79 8284 0061 rsu + c0080 79 8361 0005 rta + c0081 79 8363 0003 rtc + c0082 79 8375 0004 rtn + c0083 79 8664 0055 rwd + c0084 82 6383 0036 sct + c0085 82 6461 0022 sda + c0086 82 6482 0085 sds + c0087 82 6583 0027 set + c0088 82 6961 0023 sia + c0089 82 6962 0028 sib + c0090 82 7376 0016 slo + c0091 82 7383 0035 slt + c0092 82 7473 0018 sml + c0093 82 7964 0031 srd + c0094 82 7983 0030 srt + c0095 82 8364 0024 std + c0096 82 8369 0029 sti + c0097 82 8373 0020 stl + c0098 82 8384 0021 stu + c0101 82 8477 0011 sup + c0102 82 8761 0051 sxa + c0103 82 8762 0053 sxb + c0104 82 8763 0059 sxc + c0105 82 8875 1006 syn + c0106 83 7384 0084 tlu + c0107 84 6661 0002 ufa + c0108 86 6482 0087 wds + c0109 86 7991 0071 wr1 + c0110 86 7992 0074 wr2 + c0111 86 7993 0077 wr3 + c0112 86 8361 0007 wta + c0113 86 8374 0056 wtm + c0114 86 8375 0006 wtn + c0115 99 9999 0001 table end + 1 + 1 sub 1 store k in fwa to lwa + 1 + hed1 + subr1stdexitx store exit + stuxxxx1 store k + lddfwa set + sdafwa fwa + slt 0004 lwa + sdaxxxx2 addresses + raufwa + aloxxxx1 8003 + 8003stl 9999 next store k + next supxxxx2 end of + nzu exitx loop test + aup 8001 + aup1dxxx 8003 step + 1 + fwa stl 9998 next constants + xxxx2 01 0000 xxxx2 eraseable + hed + 1 + 1 sub 2 reserve unreserve + 1 + hed2 + sub2rstdexity reserve + lddz ru entry + sub2ustdexity unreserve + ldd1i ru entry + ru stdw set w + stln store n + slo 8001 calc ao + aup 8003 and po + srt 0003 + stux + sup 8001 + slt 0001 + stup + sup 8001 + slt 0002 + aup 8003 + aupx + alop + slt 0004 + aloc1 + stlb0002 + lddc2 + sdaspr + aupc3 su + su stusa + aupc4 8003 + 8003ral 9992 b0002 + b0002slt 0009 xx + xx stuuh + slt 0001 + ral 8002 + aupw + srt 0001 + aupuh spr + spr srt 0009 sa + sa stl 9983 b0001 + b0001raln is n zero + nze exity + slo1i reduce n + stln by 1 + rausa is ai + supa197 in last + bmi tp block of + aupa201 su 4 + 1 + tp ralspr is p 9 + sloc2 + nze zp + aloc5 step p + lddc1 + sdab0002 + stlspr + rausa reduce ai + supc6 su by 196 + 1 + zp lddc1 set p + stdb0002 to zero + lddc7 + stdspr + rausa reduce ai + supc8 su by 195 + 1 + c1 slt 0000 xx constants + c2 srt 0009 sa + c3 stla0001 b0001 + c4 45 0000 0001 + 1i 00 0000 0001 + a197 stla0197 b0001 + a201 stla0201 b0001 + c5 srt 0010 sa + c6 00 0196 0000 + c7 srt 0000 sa + c8 00 0195 0000 + z 00 0000 0000 + w 01 0000 w eraseable + n 01 0000 n + b0002 01 0000 b0002 + spr 01 0000 spr + sa 01 0000 sa + uh 01 0000 uh + x 01 0000 x + hed + 1 + 1 sub 3 process op code + 1 + hed3 + subr3stdexitx store exit + ral 1954 + srt 0004 is op + nze illop blank + slt 0006 is op + nzu num numeric + srt 0002 + stlxxxx1 search + slo 8001 symbolic + tluc0001 op table + alo1 8002 + 8002ral 9997 next is + next sloxxxx1 sym op + slt 0006 legal + nzuillop + slt 0001 test for + nzupseu pseudo op + slt 0001 sno store num + sno stlp0007 650 op + srt 0004 get optim + alo3 8002 constants + 8002ldd 9996 nex + nex stdoptim exitx + 1 + num slo4 form + slt 0002 numeric + slo 8002 op + srt 0001 code + alo 8001 sno + 1 + illopralp0010 illegal op + alo5 set 8 + stlp0010 for blank + ldd6 nex op + 1 + pseu slt 0003 pseudo + aloexitx op + alo1ixxx 8002 + 1 + 1 ral 0000 next constants + 2 10 0000 0000 + 3 lddn0001 nex + 4 90 9000 0000 + 5 00 0000 0008 + 6 55 0505 0999 + hed + 1 + 1 sub 4 what is address + 1 + hed4 + subr4stdexitz store exit + stuxxxx1 store addr + srt 0008 is c5 + nzu exitz blank + stuxxxx2 save c5 + rau 8002 are low 4 + aup90xxx characters + bovloop loop numeric + loop auph1 + bov sym + slt 0002 + nzuloop + ralxxxx2 low 4 num + slo90xxx is c5 + bmi sym alphabetic + alo29xxx + bmisym + ral1ixxx regional + aupxxxx1 aex + aex aloexitz + slo 8002 8001 + sym rauxxxx1 hed symbol + ldd sub15 + alo2ixxx step exit + stuhsymb aex + h1 10 0000 0000 + hsymb 01 0000 hsymb eraseable + hed + 1 + 1 sub 5 test absolute address + 1 + hed5 + subr5stdexitz store exit + stlxxxx1 store a + slt 0004 + slo 8002 + tlur0001 tlu + aloget 8002 range + 8002rau 9972 x table + x slt 0006 + srt 0006 + aupexitz + aloxxxx1 + sup 8003 8001 + get rau 0000 x + r0001 00 1999 0000 range + r0002 00 7999 0003 table + r0003 00 8003 0001 + r0004 00 8004 0003 + r0005 00 8007 0001 + r0006 00 8999 0003 + r0007 00 9059 0002 + r0008 99 9999 0003 + hed + 1 + 1 sub 6 symbol test routine + 1 + hed6 + subr6stdexitz store exit + stus store symb + lddswof set switch + stdsw off + mpysc scramble + ral 8002 symbol + slt 0003 giving + mpycf lo + srt 0001 + slt 0004 set + alol1p1 test + stllop1 word + slo1dxxx + stllo sli save lo + sli stlli 8001 init li + 8001ral 9990 a is cont of + a nze und li zero + slos is cont of + nzesw def li symb + sw ralli off is li + off slolmax maximum + nze max + alolmp1 sli step li + on slolo is li equa + nze swsym to lo + alolop1 sli step li + max lddswon set + stdsw switch on + rall1 sli zero li + 1 + und ralexitz undefined + alo1ixxx step + stlexitz exit + ralli + slol1 + stllsymb asu + 1 + def ralli defined + lddasu subr8 get + asu aups exitz equivalent + 1 + swsymhlt 0111 symof s tab full + symoflddsymon set sw sym + stdswsym symon on + symonralexitz + alo2ixxx 8002 + 1 + swof ralli off constants + swon ralli on + sc 10 0100 1001 + cf 00 0000 0004 + l1 ral 0000 a + l1p1 ral 0001 a + lmax rale0000 a + lmp1 rale0001 a + s 01 0000 s erasable + sw 01 0000 sw + lo 01 0000 lo + li 01 0000 li + lsymb 01 0000 lsymb + hed + 1 + 1 sub 7 store symbol and equiv + 1 + hed7 + subr7stdexitz store exit + lddss + sdaxxxx2 8001 store + 8001stu 9988 a symbol + a sup 8001 + stlxxxx1 save e + srt 0004 + div2ixxx calculate + slt 0004 location + aloc1 of + lddc2 e + sdasel and + lddc3 store + sdaser + stlobee + slo 8001 + aloxxxx1 obee + obee ldd 9986 b + b nzuser + slt 0004 sel + ss stu 9987 a constants + c1 ldde0001 b + c2 sda 9985 exitz + c3 sia 9984 exitz + obee 01 0000 obee erasable + sel 01 0000 sel + ser 01 0000 ser + hed + 1 + 1 sub 8 given sym loc get equiv + 1 + hed8 + subr8stdexit store exit + ldd 8003 + sdalsymb store l + ral 8001 + div2dxxx + slt 0004 + aloe1 8002 + 8002ldd 9975 tr + tr nzu lh + ram 8001 lr get e rh + lh ram 8001 get e lh + srt 0004 lr + lr ldd 8003 + siaequiv + rallsymb exit + e1 ldde0001 tr constant + exit 01 0000 exit eraseable + equiv 01 0000 equiv + hed + 1 + 1 sub 9 calculate reg address + hed9 + subr9stdexitz store exit + srt 0008 + ral 8003 + slt 0004 + aloc 8002 is + 8002ral 9991 nex region + nex bdoill defined + slt 0001 + ral 8002 + srt 0001 + lddexitz + bd6 l + bd5d i + l alo 1957 all + d alo 1958 all + i alo 1959 all + all slo1ixxx + bmiill exitz + ill ralexitz undefined + alo1ixxx 8002 or illeg + 1 + c ral 0960 nex constant + hed + 1 sub 10 set cc 8 and punch + 1 + sub10alop0010 + alo84th + stlp0010 + pchp0001 8003 + 1 + 84th 00 0800 0000 constant + 1 + 1 sub 11 find and reserve best + 1 + hed0 + sub11ldddrumt test + bdo sex drum tag + stlexit is adr l + bd6di + ral 8003 ssw l + di lddf d or i + sdaxxxx1 sub13 find optim + gda slt 0004 dynam adr + alo 8002 + alo 8002 ssw + ssw lddoff set sw off + stdsw + aloa1p1 get table + stlbp1 start addr + slo1dxxx + stlao sai save ao + sai stlai 8001 + 8001rau 9975 ta is locat + ta nzuyes sw available + sw rauai swof + swof sloamax is ai max + nze max + aloamp1 sai step ai + swon sloao is ai equa + nze full to ao + alobp1 sai step ai + max lddon set sw on + stdsw + rala1 sai set ai to + 1 + full hlt 0222 drum paked + lddh9xxx set drum + stddrumt tag to 9 + ralexit sex step exit + sex alo1ixxx 8002 + 1 + yes sct 0000 reserve + slt 0001 location + srt 0001 found + stlxxxx2 save p + sup 8003 + slt 0004 + aup 8001 + alosrp 8002 + 8002srt 0009 sca nulify sct + sca rau 8003 + aloai + lddst + sdaeras 8001 + 8001stu 9972 ca + ca sup 8001 calculate + sloa1 location + srt 0004 found + div4i + mpy500 + alo 8003 + sup 8001 + aupxxxx2 + mpy50 + alo 8003 + sup 8001 exit + f 00 0000 gda constants + off ralai swof + a1p1 raua0002 ta + amax raua0200 ta + amp1 raua0201 ta + on ralai swon + a1 raua0001 ta + srp srt 0000 sca + st stu 9999 ca + 4i 00 0000 0004 + 500 00 0000 0500 + 50 00 0000 0050 + fon ral 8001 stepx + ao 01 0000 ao erasable + ai 01 0000 ai + bp1 01 0000 bp1 + exit 01 0000 exit + hed + 1 + 1 sub 12 set blank l 8 + 1 + sub12alop0010 + alo87th + stlp0010 8003 + 1 + 87th 00 0000 8000 constant + 1 + 1 sub 13 cal optimum dynamic adr + 1 + hedy + sub13stdexitz store exit + bd5 i d or i + raloptim d + slt 0001 + slo 8002 + slt 0001 + alo 8001 + srt 0003 seo + i raloptim i + bd2shop shift test + bd3xas xas test + slt 0002 seo + seo stlxxxx1 save ev od + ralopreg is base + div2ixxx even or od + rau 8003 + aloxxxx1 + nzu rb + slt 0002 + ral 8002 rb + rb srt 0008 get base + aloopreg plus delta + div50 mod 50 + ral 8003 exitz + 1 + shop ralp0007 tlu units + srt 0004 digit of + slt 0009 d address + slo 8002 + tluu0001 + alogu 8002 + 8002ral 9969 top + top slt 0002 + lddoptim is op srd + bd3 seo + slt 0004 seo srd + 1 + xas ralp0007 tlu + srt 0004 d address + slt 0006 + slo 8002 + tlui0001 + alogxd 8002 + 8002ral 9968 nxt + nxt slt 0004 seo + 1 + u0001 00 2322 2524 shift + u0002 10 0706 0706 optimizing + u0003 20 0706 0908 table + u0004 30 0908 1110 + u0005 40 1110 1312 + u0006 50 1312 1514 + u0007 60 1514 1716 + u0008 70 1716 1918 + u0009 80 1918 2120 + u0010 90 2120 2322 + 1 + i0001 19 9906 0600 x accum + i0002 79 9907 0700 add sub + i0003 80 0008 0800 table + i0004 80 0106 0600 + i0005 80 0209 0800 + i0006 80 0308 0900 + i0007 90 5908 0800 + i0008 99 9909 0900 + 1 + gu ral 0000 top constants + gxd ral 0000 nxt + 50 00 0000 0050 + hed + 1 + 1 sub 14 punch avail table + 1 + hedp + sub14stdexitx store exit + ldd85th set punch + stdp0010 8 + ldda1 init a1 + stdxxxx1 + ralrs1 loop init rs + loop aupc1 8001 + 8001stl 9999 next set locat + next suptw1 + nzu srs + aupc2 + aloc3 8003 + srs stlxxxx2 save rs + rauc4 + aloxxxx1 8002 + 8002ldd 9998 8003 store + 8003std 9997 tp av table + tp suptw2 + nzu pun + aupc5 + aloc6 8002 + pun pchp0001 + sloaim is ai max + nze exitx + aloamp1 step ai + stlxxxx1 + ralxxxx2 + sloc7 loop + 1 + c1 stlp0001 next constants + c2 stlp0009 next + c3 00 0500 0500 + c4 stdp0002 tp + c5 stdp0010 tp + c6 00 0001 0000 + c7 00 1499 1499 + tw1 stlp0007 next + tw2 stdp0008 tp + 85th 00 0080 0000 + a1 ldda0001 8003 + rs1 00 0000 0450 + aim ldda0200 8003 + amp1 ldda0201 8003 + hed + 1 + 1 sub 15 heading routine + 1 + hedh + sub15stdexity save exit + ldd 8003 is c1 + slt 0008 blank + nzudh + rau 8001 head + aup0000h exity + dh rau 8001 exity dont head + hed + 1 + 1 sub 16 initialization + 1 + sub16stdexity store exit + rali1 + stup0009 zero card + std0000h zero head + ldd subr1 zero sym t + rali2 make drum + aupi3 available + ldd subr1 + lddh8xxx set drum + stddrumt tag to 8 + lddi4 set swsym + stdswsym off + rali5 undefine + auph8xxx regions + lddexity subr1 + 1 + i1 00s0001 e0200 constants + i2 00a0001 a0200 + i3 11 1111 1111 + i4 01 0111 symof + i5 00 1021 1049 + pacofbd6findi findl + 1 + 1 sub 17 calc 800x equivalent + 1 + hedx + sb17dldddeq di d equiv + sb17ilddieq di i equiv + di stdxxxx1 save tag + stuexity store exit + stlxxxx2 store 800x + lddxxxx1 sub13 get optim + sda stlxxxx1 dynam addr + div2ixxx is dy addr + nzuod ev even or od + od ral8002 eo + ev ral8003 eo + eo sloxxxx2 + nze add1 + ralxxxx1 exity + add1 ralxxxx1 + alo1ixxx exity + 1 + deq 00 0008 sda constants + ieq 00 0009 sda + 8002 00 0000 8002 + 8003 00 0000 8003 + hed + 1 + 1 sub 18 index address + 1 + hedw + indexstdexity store exit + stlxxxx1 store addr + rau 1954 + slt 0007 + lddexity + bd5d d or i + slt 0002 d + d srt 0009 + mpy2000i + lddexity + bd6ds drum 0 cor + srt 0001 ds core + ds aloxxxx1 exity + 1 + exity 01 0000 exity erasabele + hed + 1 + 1 sub 19 process location + 1 + regd0923 0923 proc l + regg0925 0925 + regj0928 0928 + regk0931 0931 + regl0933 0933 + 1 + heda + proclstdexitx store exit + rau 1951 is l blank + nzunb + ldddrumt blank test + bdob d0002 drum tag + b ralopreg setl blank + setl slt 0004 set l + lddp0008 to dr + sdap0008 exitx + nb lddg subr4 what is l + g0001ral 1957 k0001 absolute + g0002lddk subr9 regional + g0003lddj subr6 symbolic + k0001lddl subr5 test range + k0002rau87th x reg error + x aupp0010 set blank + stup0010 setl l8 + l0001stlopreg setl drum addr + l0002aup86th 800x 800x + l0003lddorceq 89x core addr + l0004rau87th x other + 800x lddorxeq 89x + 89x stdopreg x + j0001ralequiv k0001 sym defind + j0002rald sub11 sym undef + j0003rau87th x s tab full + d0001stlopreg ss s eq found + d0002rau87th x drum paked + ss auphsymb store + alolsymb symbol + lddb subr7 + 1 + g 00 0000 g0001 constants + k 00 0090 k0001 + j 00 0000 j0001 + l 00 0000 l0001 + d 00 0090 d0001 + 86th 00 0008 0000 + 87th 00 0000 8000 + exitx 01 0000 exitx eraseable + hed + 1 + 1 sub 20 process data address + 1 + regd0937 0937 proc d + regf0939 0939 + regg0941 0941 + regj0944 0944 + regk0946 0946 + regl0949 0949 + 1 + hedb + procdstdexitx store exit + rau 1952 is d blank + nzunb + rald sub11 find + d0001stlorbal l0004 optimum + d0002rau88th x drum paked + bt lddoptim is op + bd1exitx a branch + stlopreg exitx d to or + x aupp0010 set blank + stup0010 exitx + nb lddg subr4 what is d + g0001ral 1958 j0001 absolute + g0002lddj subr9 regional + g0003lddk subr6 symbolic + j0001lddl subr5 test range + j0002rau88th x reg error + l0001lddaxd index drum addr + l0002slt 0004 800x 800x + l0003lddaxc index core addr + l0004slt 0004 sd other + 800x lddp0007 set 800x d + sdap0007 + srt 0004 + aupxeq sb17d get 800x e + scd slt 0004 set core d + lddp0007 + sdap0007 + srt 0004 + lddceq sub13 get core e + sceq stlorceq bt save core + k0001ralequiv j0001 sym defind + k0002ralf sub11 sym undef + k0003rau88th x s tab full + f0001stleq ss save eq + f0002rau88th x drum paked + ss auphsymb store + alolsymb symbol + ldd subr7 + raleq l0004 + sd lddp0007 set d addr + sdap0007 + srt 0004 bt + d 00 0088 d0001 constants + g 00 0000 g0001 + j 00 0088 j0001 + l 00 0000 l0001 + f 00 0088 f0001 + k 00 0000 k0001 + axd 00 0088 d0001 + axc 00 0098 scd + xeq stlorxeq bt + ceq 00 0008 sceq + 88th 00 0000 0800 + eq 01 0000 eq erasable + hed + 1 + 1 sub 21 process instr address + 1 + regd0953 0953 proc i + regf0955 0955 + regg0958 0958 + regj0960 0960 + regk0962 0962 + regl0965 0965 + 1 + hedc + procistdexitx store exit + rau 1953 is i blank + nzunb + rau 1952 is d blank + nzudnb + ldddrumt d i blank + bdo g0002 test drum + ralorbal l0004 tag + dnb rald sub11 find best + d0001stlorbal l0004 found + d0002ralp0010 x drum paked + x alo89th + stlp0010 exitx + nb lddf subr4 what is i + f0001ral 1959 j0001 absolute + f0002lddj subr9 regional + f0003lddk subr6 symbolic + j0001lddl subr5 test range + j0002ralp0010 x reg error + l0001lddaxd index drum addr + l0002lddp0007 800x 800x + l0003lddaxc index core addr + l0004lddp0007 other + siap0007 mor + 800x siap0007 + aupxeq sb17i get 800x e + 90xx lddp0007 set core + siap0007 address + lddceq sub13 get core e + k0001ralequiv j0001 sym defind + k0002ralg sub11 sym undef + k0003ralp0010 x s tab full + g0001lddp0007 si found best + g0002ralp0010 x drum paked + si siap0007 + auphsymb store + alolsymb symbol + lddmor subr7 + mor lddorbal set or + stdopreg exitx to orb + sceq stlorceq mor save core + 1 + d 00 0089 d0001 constants + f 00 0000 f0001 + j 00 0089 j0001 + k 00 0000 k0001 + l 00 0000 l0001 + g 00 0089 g0001 + 89th 00 0000 0080 + axd 00 0089 l0004 + axc 00 0099 90xx + xeq stlorxeq mor + ceq 00 0009 sceq + hed + 1 + 1ixxx 00 0000 0001 constants + 1dxxx 00 0001 0000 + 2ixxx 00 0000 0002 + 2dxxx 00 0002 0000 + h8xxx 80 0000 0000 + h9xxx 90 0000 0000 + 90xxx 00 0000 0090 + 29xxx 00 0000 0029 + 2000i 00 0000 2000 constant + torg 00 0000 t0001 + 1 + pat diff --git a/README.md b/README.md index 4301ed23..468074e9 100644 --- a/README.md +++ b/README.md @@ -83,6 +83,8 @@ #### Hans-Åke Lund has implemented an SCELBI (SCientic-ELectronics-BIology) simulator. +#### Roberto Sancho has implemented an IBM 650 simulator. + ### New Host Platform support - HP-UX and AIX ### Simulator Front Panel API diff --git a/Visual Studio Projects/I650.vcproj b/Visual Studio Projects/I650.vcproj new file mode 100644 index 00000000..83be95a7 --- /dev/null +++ b/Visual Studio Projects/I650.vcproj @@ -0,0 +1,335 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/Simh.sln b/Visual Studio Projects/Simh.sln index f14d7ea1..69f7b2ec 100644 --- a/Visual Studio Projects/Simh.sln +++ b/Visual Studio Projects/Simh.sln @@ -244,10 +244,19 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "isys8024", "isys8024.vcproj EndProjectSection EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "imds-225", "imds-225.vcproj", "{A66F0D85-174F-4AFE-A44E-7FAE3D3727BC}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ibmpc", "ibmpc.vcproj", "{76EF8599-7AB0-4C8D-997B-AAEEE724A5D0}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "ibmpcxt", "ibmpcxt.vcproj", "{0026A4C2-655A-4C03-B6CA-B1EAF79FA4D1}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "scelbi", "scelbi.vcproj", "{1E92CC4B-9ED5-4CD4-BD35-061F25126523}" ProjectSection(ProjectDependencies) = postProject @@ -286,6 +295,11 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "I7010", "I7010.vcproj", "{5 {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} EndProjectSection EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "I650", "I650.vcproj", "{95B64699-4B93-4BFE-9024-0A2302D9B71A}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 @@ -532,6 +546,10 @@ Global {55A727F0-B5C8-48E8-9EF2-D5DAF679C520}.Debug|Win32.Build.0 = Debug|Win32 {55A727F0-B5C8-48E8-9EF2-D5DAF679C520}.Release|Win32.ActiveCfg = Release|Win32 {55A727F0-B5C8-48E8-9EF2-D5DAF679C520}.Release|Win32.Build.0 = Release|Win32 + {95B64699-4B93-4BFE-9024-0A2302D9B71A}.Debug|Win32.ActiveCfg = Debug|Win32 + {95B64699-4B93-4BFE-9024-0A2302D9B71A}.Debug|Win32.Build.0 = Debug|Win32 + {95B64699-4B93-4BFE-9024-0A2302D9B71A}.Release|Win32.ActiveCfg = Release|Win32 + {95B64699-4B93-4BFE-9024-0A2302D9B71A}.Release|Win32.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/doc/i650_doc.doc b/doc/i650_doc.doc new file mode 100644 index 00000000..fe8c0952 Binary files /dev/null and b/doc/i650_doc.doc differ diff --git a/makefile b/makefile index d10bcb07..8f2f6221 100644 --- a/makefile +++ b/makefile @@ -1388,6 +1388,12 @@ I7094 = ${I7094D}/i7094_cpu.c ${I7094D}/i7094_cpu1.c ${I7094D}/i7094_io.c \ I7094_OPT = -DUSE_INT64 -I ${I7094D} +I650D = I650 +I650 = ${I650D}/i650_cpu.c ${I650D}/i650_cdr.c ${I650D}/i650_cdp.c \ + ${I650D}/i650_sys.c +I650_OPT = -I ${I650D} -DUSE_INT64 -DUSE_SIM_CARD + + IBM1130D = Ibm1130 IBM1130 = ${IBM1130D}/ibm1130_cpu.c ${IBM1130D}/ibm1130_cr.c \ ${IBM1130D}/ibm1130_disk.c ${IBM1130D}/ibm1130_stddev.c \ @@ -1717,7 +1723,8 @@ ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 \ nova eclipse hp2100 hp3000 i1401 i1620 s3 altair altairz80 gri \ i7094 ibm1130 id16 id32 sds lgp h316 cdc1700 \ swtp6800mp-a swtp6800mp-a2 tx-0 ssem b5500 isys8010 isys8020 \ - isys8030 isys8024 imds-225 scelbi 3b2 i701 i704 i7010 i7070 i7080 i7090 + isys8030 isys8024 imds-225 scelbi 3b2 i701 i704 i7010 i7070 i7080 i7090 \ + i650 all : ${ALL} @@ -2137,6 +2144,12 @@ ${BIN}i701${EXE} : ${I701} ${SIM} ${MKDIRBIN} ${CC} ${I701} ${SIM} ${I701_OPT} $(CC_OUTSPEC) ${LDFLAGS} +i650 : $(BIN)i650$(EXE) + +${BIN}i650${EXE} : ${I650} ${SIM} + ${MKDIRBIN} + ${CC} ${I650} ${SIM} ${I650_OPT} $(CC_OUTSPEC) ${LDFLAGS} + # Front Panel API Demo/Test program frontpaneltest : ${BIN}frontpaneltest${EXE}