From d4082f383ee9d7b8dbc962fd26780eb80bedc5b2 Mon Sep 17 00:00:00 2001 From: Mark Pizzolato Date: Tue, 22 Nov 2016 22:29:32 -0800 Subject: [PATCH] PDP10: Added debug support to clock device (TIM) --- PDP10/pdp10_tim.c | 55 ++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 45 insertions(+), 10 deletions(-) diff --git a/PDP10/pdp10_tim.c b/PDP10/pdp10_tim.c index b5e39607..b0f0cd9b 100644 --- a/PDP10/pdp10_tim.c +++ b/PDP10/pdp10_tim.c @@ -191,12 +191,31 @@ static MTAB tim_mod[] = { { 0 } }; +/* Debug detail levels */ + +#define DEB_RRD 0001 /* reg reads */ +#define DEB_RWR 0002 /* reg writes */ +#define DEB_TPS 0004 /* Ticks Per Second changes */ +#define DEB_INT 0010 /* interrupts */ +#define DEB_TRC 0020 /* trace */ + +static DEBTAB tim_deb[] = { + { "RRD", DEB_RRD, "register reads" }, + { "RWR", DEB_RWR, "register writes" }, + { "TPS", DEB_TPS, "Ticks Per Second changes " }, + { "INT", DEB_INT, "interrupts" }, + { "TRACE", DEB_TRC, "trace" }, + { NULL, 0 } + }; + + DEVICE tim_dev = { "TIM", &tim_unit, tim_reg, tim_mod, 1, 0, 0, 0, 0, 0, NULL, NULL, &tim_reset, NULL, NULL, NULL, - &tcu_dib, DEV_UBUS + &tcu_dib, DEV_UBUS | DEV_DEBUG, + 0, tim_deb }; /* Timer instructions */ @@ -250,6 +269,7 @@ tempbase[1] &= ~((d10) TIM_BASE_RAZ); */ Write (ea, tempbase[0], prv); Write (INCA(ea), tempbase[1], prv); +sim_debug (DEB_RRD, &tim_dev, "rdtim() = %012" LL_FMT "o %012" LL_FMT "o\n", tempbase[0], tempbase[1]); return FALSE; } @@ -257,12 +277,14 @@ t_bool wrtim (a10 ea, int32 prv) { tim_base[0] = Read (ea, prv); tim_base[1] = CLRS (Read (INCA (ea), prv) & ~((d10) TIM_HWRE_MASK)); +sim_debug (DEB_RWR, &tim_dev, "wrtim(%012" LL_FMT "o, %012" LL_FMT "o)\n", tim_base[0], tim_base[1]); return FALSE; } t_bool rdint (a10 ea, int32 prv) { Write (ea, tim_interval, prv); +sim_debug (DEB_RRD, &tim_dev, "rdint() = %012" LL_FMT "o\n", tim_interval); return FALSE; } @@ -275,11 +297,13 @@ return FALSE; t_bool wrint (a10 ea, int32 prv) { tim_interval = CLRS (Read (ea, prv)); +sim_debug (DEB_RWR, &tim_dev, "wrint(%012" LL_FMT "o)\n", tim_interval); return update_interval (tim_interval); } static t_bool update_interval (d10 new_interval) { +int32 old_clk_tps = clk_tps; /* * The value provided is in hardware clicks. For a frequency of 4.1 * MHz, that means that dividing by 4096 (shifting 12 to the right) we get @@ -293,7 +317,9 @@ if (new_interval & TIM_HWRE_MASK) tim_new_period += 010000; /* clk_tps is the new number of clocks ticks per second */ clk_tps = (int32) ceil(((double)TIM_HW_FREQ /(double)tim_new_period) - 0.5); - +if (clk_tps != old_clk_tps) + sim_debug (DEB_TPS, &tim_dev, "update_interval() - clk_tps changed from %d to %d\n", old_clk_tps, clk_tps); + /* tmxr is polled every tim_mult clks. Compute the divisor matching the target. */ tim_mult = (clk_tps <= TIM_TMXR_FREQ) ? 1 : (clk_tps / TIM_TMXR_FREQ) ; @@ -317,13 +343,15 @@ static t_stat tim_svc (UNIT *uptr) { if (cpu_unit.flags & UNIT_KLAD) /* diags? */ tmr_poll = uptr->wait; /* fixed clock */ -else tmr_poll = sim_rtc_calb (clk_tps); /* else calibrate */ +else + tmr_poll = sim_rtc_calb (clk_tps); /* else calibrate */ sim_activate (uptr, tmr_poll); /* reactivate unit */ tmxr_poll = tmr_poll * tim_mult; /* set mux poll */ tim_incr_base (tim_base, tim_period); /* incr time base based on period of expired interval */ tim_period = tim_new_period; /* If interval has changed, update period */ apr_flg = apr_flg | APRF_TIM; /* request interrupt */ +sim_debug (DEB_INT, &tim_dev, "tim_svc(INT) tmr_poll=%d, tmxr_poll=%d, tim_period=%" LL_FMT "d\n", tmr_poll, tmxr_poll, tim_period); if (Q_ITS) { /* ITS? */ if (pi_act == 0) quant = (quant + TIM_ITS_QUANT) & DMASK; @@ -332,8 +360,10 @@ if (Q_ITS) { /* ITS? */ pcst = AOB (pcst); /* add 1,,1 */ } } /* end ITS */ -else if (t20_idlelock && PROB (100 - tim_t20_prob)) - t20_idlelock = 0; +else { + if (t20_idlelock && PROB (100 - tim_t20_prob)) + t20_idlelock = 0; + } return SCPE_OK; } @@ -350,6 +380,7 @@ return; static t_stat tim_reset (DEVICE *dptr) { +sim_debug (DEB_TRC, &tim_dev, "tim_reset()\n"); sim_register_clock_unit (&tim_unit); /* declare clock unit */ tim_base[0] = tim_base[1] = 0; /* clear timebase (HW does) */ @@ -366,6 +397,7 @@ tim_base[0] = tim_base[1] = 0; /* clear timebase (HW do */ tim_interval = 0; clk_tps = 60; +sim_debug (DEB_TPS, &tim_dev, "tim_reset() - clk_tps set to %d\n", clk_tps); update_interval(17*4096); apr_flg = apr_flg & ~APRF_TIM; /* clear interrupt */ @@ -411,6 +443,7 @@ static t_stat tcu_rd (int32 *data, int32 PA, int32 access) { time_t curtim; struct tm *tptr; +t_stat st = SCPE_OK; curtim = time (NULL); /* get time */ tptr = localtime (&curtim); /* decompose */ @@ -425,21 +458,23 @@ switch ((PA >> 1) & 03) { /* decode PA<3:1> */ *data = (((tptr->tm_year) & 0177) << 9) | (((tptr->tm_mon + 1) & 017) << 5) | ((tptr->tm_mday) & 037); - return SCPE_OK; + break; case 1: /* hour/minute */ *data = (((tptr->tm_hour) & 037) << 8) | ((tptr->tm_min) & 077); - return SCPE_OK; + break; case 2: /* second */ *data = (tptr->tm_sec) & 077; - return SCPE_OK; + break; case 3: /* status */ *data = CSR_DONE; - return SCPE_OK; + break; } -return SCPE_NXM; /* can't get here */ +sim_debug (DEB_RRD, &tim_dev, "tcu_rd() = %o\n", *data); + +return st; }