VAX, PDP11, PDP8, PDP1: Properly declare timer with clock unit
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2b61a9a92d
commit
da3f5359bb
10 changed files with 21 additions and 37 deletions
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@ -118,9 +118,8 @@ t_stat clk_reset (DEVICE *dptr)
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{
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if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit); /* disabled? */
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else {
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK);
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sim_activate_abs (&clk_unit, tmxr_poll); /* activate unit */
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tmxr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init timer */
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sim_activate_after (&clk_unit, 1000000/CLK_TPS); /* activate unit */
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}
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clk_cntr = 0; /* clear counter */
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return SCPE_OK;
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@ -471,7 +471,6 @@ return clk_dib.vec;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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if (CPUT (HAS_LTCR)) /* reg there? */
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clk_fie = clk_fnxm = 0;
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else {
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@ -481,8 +480,8 @@ else {
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clk_tps = clk_default; /* set default tps */
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clk_csr = CSR_DONE; /* set done */
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CLR_INT (CLK);
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sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init line clock */
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sim_activate (&clk_unit, clk_unit.wait); /* activate unit */
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tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init line clock */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate unit */
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tmr_poll = clk_unit.wait; /* set timer poll */
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tmxr_poll = clk_unit.wait; /* set mux poll */
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return SCPE_OK;
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@ -141,12 +141,9 @@ switch (IR & 07) { /* decode IR<9:11> */
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t_stat clk_svc (UNIT *uptr)
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{
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int32 t;
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dev_done = dev_done | INT_CLK; /* set done */
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int_req = INT_UPDATE; /* update interrupts */
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t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
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tmxr_poll = t; /* set mux poll */
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tmxr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
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sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
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return SCPE_OK;
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}
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@ -155,16 +152,12 @@ return SCPE_OK;
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t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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dev_done = dev_done & ~INT_CLK; /* clear done, int */
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int_req = int_req & ~INT_CLK;
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int_enable = int_enable & ~INT_CLK; /* clear enable */
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if (!sim_is_running) { /* RESET (not CAF)? */
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK);
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sim_activate (&clk_unit, t); /* activate unit */
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tmxr_poll = t;
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tmxr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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}
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return SCPE_OK;
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}
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@ -453,11 +453,10 @@ t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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clk_csr = 0;
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CLR_INT (CLK);
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
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sim_activate_abs (&clk_unit, t); /* activate unit */
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t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmr_poll = t; /* set tmr poll */
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tmxr_poll = t * TMXR_MULT; /* set mux poll */
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return SCPE_OK;
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@ -396,11 +396,10 @@ t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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clk_csr = 0;
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CLR_INT (CLK);
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
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sim_activate_abs (&clk_unit, t); /* activate unit */
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t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmr_poll = t; /* set tmr poll */
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tmxr_poll = t * TMXR_MULT; /* set mux poll */
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return SCPE_OK;
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@ -757,9 +757,8 @@ return;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
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clk_unit.filebuf = calloc(sizeof(TOY), 1);
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@ -792,9 +792,8 @@ return;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
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clk_unit.filebuf = calloc(sizeof(TOY), 1);
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@ -734,9 +734,8 @@ if (SCPE_OK == sim_activate_after (&tmr_unit, usecs))
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
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clk_unit.filebuf = calloc(sizeof(TOY), 1);
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@ -856,9 +856,8 @@ return;
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t_stat clk_reset (DEVICE *dptr)
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{
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sim_register_clock_unit (&clk_unit); /* declare clock unit */
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tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
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sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */
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tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
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if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
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clk_unit.filebuf = calloc(sizeof(TOY), 1);
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@ -556,12 +556,11 @@ t_stat clk_reset (DEVICE *dptr)
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{
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int32 t;
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sim_register_clock_unit (&clk_unit);
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clk_csr = 0;
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CLR_INT (CLK);
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if (!sim_is_running) { /* RESET (not IORESET)? */
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t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate unit */
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t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
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sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
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tmr_poll = t; /* set tmr poll */
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tmxr_poll = t * TMXR_MULT; /* set mux poll */
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}
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