VAX, PDP11, PDP8, PDP1: Properly declare timer with clock unit

This commit is contained in:
Mark Pizzolato 2016-09-26 15:55:50 -07:00
parent 2b61a9a92d
commit da3f5359bb
10 changed files with 21 additions and 37 deletions

View file

@ -118,9 +118,8 @@ t_stat clk_reset (DEVICE *dptr)
{
if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit); /* disabled? */
else {
sim_register_clock_unit (&clk_unit); /* declare clock unit */
tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK);
sim_activate_abs (&clk_unit, tmxr_poll); /* activate unit */
tmxr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init timer */
sim_activate_after (&clk_unit, 1000000/CLK_TPS); /* activate unit */
}
clk_cntr = 0; /* clear counter */
return SCPE_OK;

View file

@ -471,7 +471,6 @@ return clk_dib.vec;
t_stat clk_reset (DEVICE *dptr)
{
sim_register_clock_unit (&clk_unit); /* declare clock unit */
if (CPUT (HAS_LTCR)) /* reg there? */
clk_fie = clk_fnxm = 0;
else {
@ -481,8 +480,8 @@ else {
clk_tps = clk_default; /* set default tps */
clk_csr = CSR_DONE; /* set done */
CLR_INT (CLK);
sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init line clock */
sim_activate (&clk_unit, clk_unit.wait); /* activate unit */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init line clock */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate unit */
tmr_poll = clk_unit.wait; /* set timer poll */
tmxr_poll = clk_unit.wait; /* set mux poll */
return SCPE_OK;

View file

@ -141,12 +141,9 @@ switch (IR & 07) { /* decode IR<9:11> */
t_stat clk_svc (UNIT *uptr)
{
int32 t;
dev_done = dev_done | INT_CLK; /* set done */
int_req = INT_UPDATE; /* update interrupts */
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
tmxr_poll = t; /* set mux poll */
tmxr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
return SCPE_OK;
}
@ -155,16 +152,12 @@ return SCPE_OK;
t_stat clk_reset (DEVICE *dptr)
{
int32 t;
sim_register_clock_unit (&clk_unit); /* declare clock unit */
dev_done = dev_done & ~INT_CLK; /* clear done, int */
int_req = int_req & ~INT_CLK;
int_enable = int_enable & ~INT_CLK; /* clear enable */
if (!sim_is_running) { /* RESET (not CAF)? */
t = sim_rtcn_init (clk_unit.wait, TMR_CLK);
sim_activate (&clk_unit, t); /* activate unit */
tmxr_poll = t;
tmxr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
}
return SCPE_OK;
}

View file

@ -453,11 +453,10 @@ t_stat clk_reset (DEVICE *dptr)
{
int32 t;
sim_register_clock_unit (&clk_unit); /* declare clock unit */
clk_csr = 0;
CLR_INT (CLK);
t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
sim_activate_abs (&clk_unit, t); /* activate unit */
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
return SCPE_OK;

View file

@ -396,11 +396,10 @@ t_stat clk_reset (DEVICE *dptr)
{
int32 t;
sim_register_clock_unit (&clk_unit); /* declare clock unit */
clk_csr = 0;
CLR_INT (CLK);
t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
sim_activate_abs (&clk_unit, t); /* activate unit */
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
return SCPE_OK;

View file

@ -757,9 +757,8 @@ return;
t_stat clk_reset (DEVICE *dptr)
{
sim_register_clock_unit (&clk_unit); /* declare clock unit */
tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
clk_unit.filebuf = calloc(sizeof(TOY), 1);

View file

@ -792,9 +792,8 @@ return;
t_stat clk_reset (DEVICE *dptr)
{
sim_register_clock_unit (&clk_unit); /* declare clock unit */
tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
clk_unit.filebuf = calloc(sizeof(TOY), 1);

View file

@ -734,9 +734,8 @@ if (SCPE_OK == sim_activate_after (&tmr_unit, usecs))
t_stat clk_reset (DEVICE *dptr)
{
sim_register_clock_unit (&clk_unit); /* declare clock unit */
tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
clk_unit.filebuf = calloc(sizeof(TOY), 1);

View file

@ -856,9 +856,8 @@ return;
t_stat clk_reset (DEVICE *dptr)
{
sim_register_clock_unit (&clk_unit); /* declare clock unit */
tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (clk_unit.filebuf == NULL) { /* make sure the TODR is initialized */
clk_unit.filebuf = calloc(sizeof(TOY), 1);

View file

@ -556,12 +556,11 @@ t_stat clk_reset (DEVICE *dptr)
{
int32 t;
sim_register_clock_unit (&clk_unit);
clk_csr = 0;
CLR_INT (CLK);
if (!sim_is_running) { /* RESET (not IORESET)? */
t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate unit */
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
}