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Migrating scp and library global variables to be declared as extern in the appropriate library include file and remove repetitive declarations in referencing modules.

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This commit is contained in:
Mark Pizzolato 2013-01-10 13:29:15 -08:00
parent bc816ae871
commit dac73b9381
139 changed files with 37 additions and 373 deletions
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4
ALTAIR/altair_cpu.c
View file

@ -107,9 +107,6 @@ int32 chip = 0; /* 0 = 8080 chip, 1 = z8
int32 PCX; /* External view of PC */
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ;/* breakpoint info */
/* function prototypes */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
@ -302,7 +299,6 @@ DEVICE cpu_dev = {
int32 sim_instr (void)
{
extern int32 sim_interval;
int32 PC, IR, OP, DAR, reason, hi, lo, carry, i;
PC = saved_PC & ADDRMASK; /* load local PC */

7
AltairZ80/altairz80_cpu.c
View file

@ -128,7 +128,6 @@
} \
}
extern int32 sim_int_char;
extern int32 sio0s (const int32 port, const int32 io, const int32 data);
extern int32 sio0d (const int32 port, const int32 io, const int32 data);
extern int32 sio1s (const int32 port, const int32 io, const int32 data);
@ -147,8 +146,6 @@ extern void do_SIMH_sleep(void);
extern void prepareMemoryAccessMessage(const t_addr loc);
extern void prepareInstructionMessage(const t_addr loc, const uint32 op);
extern FILE *sim_deb;
extern t_stat sim_instr_nommu(void);
extern uint8 MOPT[MAXBANKSIZE];
extern t_stat sim_instr_8086(void);
@ -1882,15 +1879,12 @@ void setClockFrequency(const uint32 Value) {
}
static t_stat sim_instr_mmu (void) {
extern int32 sim_interval;
extern t_bool sim_brk_pend[SIM_BKPT_N_SPC];
extern int32 timerInterrupt;
extern int32 timerInterruptHandler;
extern int32 keyboardInterrupt;
extern uint32 keyboardInterruptHandler;
extern uint32 sim_os_msec(void);
extern const t_bool rtc_avail;
extern uint32 sim_brk_summ;
int32 reason = SCPE_OK;
register uint32 specialProcessing;
register uint32 AF;
@ -6287,7 +6281,6 @@ static t_stat sim_instr_mmu (void) {
/* reset routine */
static t_stat cpu_reset(DEVICE *dptr) {
extern uint32 sim_brk_types, sim_brk_dflt; /* breakpoint info */
int32 i;
AF_S = AF1_S = 0;
BC_S = DE_S = HL_S = 0;

2
AltairZ80/altairz80_cpu_nommu.c
View file

@ -985,8 +985,6 @@ static uint16 GET_WORD(register uint32 a) {
INOUTFLAGS((HIGH_REGISTER(BC) & 0xa8) | ((HIGH_REGISTER(BC) == 0) << 6), x)
t_stat sim_instr_nommu(void) {
extern int32 sim_interval;
extern uint32 sim_brk_summ;
int32 reason = SCPE_OK;
register uint32 AF;
register uint32 BC;

3
AltairZ80/altairz80_sio.c
View file

@ -166,12 +166,9 @@ extern void setClockFrequency(const uint32 Value);
extern int32 chiptype;
extern const t_bool rtc_avail;
extern uint32 PCX;
extern int32 sim_switches;
extern int32 sim_quiet;
extern int32 SR;
extern UNIT cpu_unit;
extern volatile int32 stop_cpu;
extern int32 sim_interval;
/* Debug Flags */
static DEBTAB generic_dt[] = {

2
AltairZ80/i86_decode.c
View file

@ -41,9 +41,7 @@ extern int32 SPX_S; /* SP register (8086) */
extern int32 IP_S; /* IP register (8086) */
extern int32 FLAGS_S; /* flags register (8086) */
extern int32 PCX_S; /* PC register (8086), 20 bit */
extern int32 sim_interval;
extern uint32 PCX; /* external view of PC */
extern uint32 sim_brk_summ;
extern UNIT cpu_unit;
void i86_intr_raise(PC_ENV *m,uint8 intrnum);

4
GRI/gri_cpu.c
View file

@ -187,10 +187,6 @@ int16 scq[SCQ_SIZE] = { 0 }; /* PC queue */
int32 scq_p = 0; /* PC queue ptr */
REG *scq_r = NULL; /* PC queue reg ptr */
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);

1
GRI/gri_sys.c
View file

@ -37,7 +37,6 @@ extern DEVICE hsr_dev, hsp_dev;
extern DEVICE rtc_dev;
extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
void fprint_addr (FILE *of, uint32 val, uint32 mod, uint32 dst);

6
H316/h316_cpu.c
View file

@ -276,12 +276,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
extern int32 sim_int_char;
extern int32 sim_interval;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern FILE *sim_log;
extern DEVICE *sim_devices[];
t_bool devtab_init (void);
int32 dmaio (int32 inst, int32 fnc, int32 dat, int32 dev);
int32 undio (int32 inst, int32 fnc, int32 dat, int32 dev);

1
H316/h316_dp.c
View file

@ -220,7 +220,6 @@ extern int32 dev_int, dev_enb;
extern uint32 chan_req;
extern int32 stop_inst;
extern uint32 dma_ad[DMA_MAX];
extern int32 sim_switches;
uint32 dp_cw1 = 0; /* cmd word 1 */
uint32 dp_cw2 = 0; /* cmd word 2 */

1
H316/h316_stddev.c
View file

@ -88,7 +88,6 @@ extern int32 PC;
extern int32 stop_inst;
extern int32 C, dp, ext, extoff_pending, sc;
extern int32 dev_int, dev_enb;
extern int32 sim_switches;
extern UNIT cpu_unit;
uint32 ptr_motion = 0; /* read motion */

1
H316/h316_sys.c
View file

@ -43,7 +43,6 @@ extern DEVICE fhd_dev;
extern DEVICE mt_dev;
extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
/* SCP data structures and interface routines

7
HP2100/hp2100_cpu.c
View file

@ -561,14 +561,7 @@ uint16 dms_map[MAP_NUM * MAP_LNT] = { 0 }; /* dms maps */
/* External data */
extern int32 sim_interval;
extern int32 sim_int_char;
extern int32 sim_brk_char;
extern int32 sim_del_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern DEVICE *sim_devices[];
extern char halt_msg[];
extern t_bool sim_idle_enab;
extern DIB clk_dib; /* CLK DIB for idle check */
/* CPU local routines */

7
I1401/i1401_cpu.c
View file

@ -197,11 +197,8 @@ int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
t_bool conv_old = 0; /* old conversions */
extern int32 sim_int_char;
extern int32 sim_emax;
extern t_value *sim_eval;
extern FILE *sim_deb;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
@ -229,8 +226,6 @@ extern t_stat inq_io (int32 flag, int32 mod);
extern t_stat mt_io (int32 unit, int32 flag, int32 mod);
extern t_stat dp_io (int32 fnc, int32 flag, int32 mod);
extern t_stat mt_func (int32 unit, int32 flag, int32 mod);
extern t_stat sim_activate (UNIT *uptr, int32 delay);
extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
/* CPU data structures
@ -1904,8 +1899,6 @@ char *cptr = (char *) desc;
t_value sim_eval[MAX_L + 1];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

2
I1401/i1401_mt.c
View file

@ -113,7 +113,6 @@ extern uint8 M[]; /* memory */
extern int32 ind[64];
extern int32 BS, iochk;
extern UNIT cpu_unit;
extern FILE *sim_deb;
t_stat mt_reset (DEVICE *dptr);
t_stat mt_boot (int32 unitno, DEVICE *dptr);
@ -469,7 +468,6 @@ return SCPE_OK;
t_stat mt_boot (int32 unitno, DEVICE *dptr)
{
extern int32 saved_IS;
extern int32 sim_switches;
if ((sim_switches & SWMASK ('N')) == 0) /* unless -n */
sim_tape_rewind (&mt_unit[unitno]); /* force rewind */

5
I1620/i1620_cpu.c
View file

@ -131,11 +131,6 @@ int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
uint8 ind[NUM_IND] = { 0 }; /* indicators */
extern int32 sim_int_char;
extern int32 sim_interval;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern FILE *sim_log;
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);

1
I7094/i7094_cd.c
View file

@ -88,7 +88,6 @@ t_stat cd_attach (UNIT *uptr, char *cptr);
t_stat cd_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);
char colbin_to_bcd (uint32 cb);
extern int32 sim_switches;
extern uint32 PC;
extern uint32 ind_ioc;
extern char bcd_to_ascii_a[64];

7
I7094/i7094_cpu.c
View file

@ -211,11 +211,6 @@ extern uint32 ch_sta[NUM_CHAN];
extern uint32 ch_flags[NUM_CHAN];
extern DEVICE mt_dev[NUM_CHAN];
extern DEVICE ch_dev[NUM_CHAN];
extern FILE *sim_deb;
extern int32 sim_int_char;
extern int32 sim_interval;
extern int32 sim_switches;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
/* Forward and external declarations */
@ -2406,8 +2401,6 @@ t_stat cpu_fprint_one_inst (FILE *st, uint32 pc, uint32 rpt, uint32 ea,
{
int32 ch;
t_value sim_eval;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
sim_eval = ir;
if (pc & HIST_PC) { /* instruction? */

2
I7094/i7094_io.c
View file

@ -88,7 +88,6 @@ extern DEVICE mt_dev[NUM_CHAN];
extern DEVICE drm_dev;
extern DEVICE dsk_dev;
extern DEVICE com_dev;
extern uint32 sim_brk_summ;
t_stat ch_reset (DEVICE *dptr);
t_stat ch6_svc (UNIT *uptr);
@ -111,7 +110,6 @@ t_stat ch9_wr_getw (uint32 ch);
void ch9_eval_int (uint32 ch, uint32 iflags);
DEVICE *ch_map_flags (uint32 ch, int32 fl);
extern CTAB *sim_vm_cmd;
extern t_stat ch_bkpt (uint32 ch, uint32 clc);
const uint32 col_masks[12] = { /* row 9,8,..,0,11,12 */

1
I7094/i7094_mt.c
View file

@ -72,7 +72,6 @@ static const char *tape_stat[] = {
extern uint32 PC;
extern uint32 cpu_model;
extern uint32 ind_ioc;
extern FILE *sim_deb;
extern const char *sel_name[];
t_stat mt_chsel (uint32 ch, uint32 sel, uint32 unit);

6
Ibm1130/ibm1130_cpu.c
View file

@ -222,9 +222,7 @@ t_stat cpu_set_type (UNIT *uptr, int32 value, char *cptr, void *desc);
void calc_ints (void);
extern t_stat ts_wr (int32 data, int32 addr, int32 access);
extern t_stat detach_cmd (int32 flags, char *cptr);
extern UNIT cr_unit;
extern int32 sim_switches;
#ifdef ENABLE_BACKTRACE
static void archive_backtrace(char *inst);
@ -466,8 +464,6 @@ static char *xio_funcs[] = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
extern UNIT *sim_clock_queue;
int32 i, eaddr, INDIR, IR, F, DSPLC, word2, oldval, newval, src, src2, dst, abit, xbit;
int32 iocc_addr, iocc_op, iocc_dev, iocc_func, iocc_mod;
char msg[50];
@ -516,7 +512,7 @@ t_stat sim_instr (void)
#endif /* ifdef GUI_SUPPORT */
if (sim_interval <= 0) { /* any events timed out? */
if (sim_clock_queue != NULL) {
if (sim_clock_queue != QUEUE_LIST_END) {
if ((status = sim_process_event()) != 0)
reason = simh_status_to_stopcode(status);

1
Ibm1130/ibm1130_cr.c
View file

@ -349,7 +349,6 @@ way to solve the problem, the other is to keep DSW up-to-date all the time).
#define ENABLE_PHYSICAL_CARD_READER_SUPPORT
extern int32 sim_switches;
extern UNIT cpu_unit;
static t_stat cr_svc (UNIT *uptr);

2
Ibm1130/ibm1130_disk.c
View file

@ -39,8 +39,6 @@ commands may NOT be accurate. This should probably be fixed.
#define TRACE_DMS_IO /* define to enable debug of DMS phase IO */
#ifdef TRACE_DMS_IO
extern int32 sim_switches;
extern int32 sim_quiet;
static int trace_dms = 0;
static void tracesector (int iswrite, int nwords, int addr, int sector);
static t_stat where_cmd (int32 flag, char *ptr);

1
Ibm1130/ibm1130_gui.c
View file

@ -93,7 +93,6 @@ DEVICE console_dev = {
/* reset for the "console" display device */
extern char *read_line (char *cptr, int size, FILE *stream);
extern FILE *sim_log;
extern DEVICE *find_unit (char *cptr, UNIT **uptr);
extern char *sim_prompt;

1
Ibm1130/ibm1130_plot.c
View file

@ -93,7 +93,6 @@ static void update_pen(void); /* will ensure pen action is correct
static t_stat plot_validate_change (UNIT *uptr, int32 val, char * ptr, void *desc); /* when set command issued */
static void process_cmd(void); /* does actual drawing for plotter */
extern int32 sim_switches; /* switches set on simh command */
static int16 plot_dsw = 0; /* device status word */
static int16 plot_cmd = 0; /* the command to process */
static int32 plot_wait = 1000; /* plotter movement wait */

2
Ibm1130/ibm1130_prt.c
View file

@ -202,8 +202,6 @@ cccgi[] = {
#include "ibm1130_prtwheel.h"
extern int32 sim_switches;
/* cc_format_1132 and cc_format_1403 - turn cctape bits into proper format for DSW or status read */
static int cc_format_1132 (int bits)

2
Ibm1130/ibm1130_sca.c
View file

@ -202,8 +202,6 @@ static int sca_rcvptr = 0; /* index of next byte to take from rcvbuf *
#define UNIT_AUTOANSWER (1u << UNIT_V_AUTOANSWER)
#define UNIT_LISTEN (1u << UNIT_V_LISTEN)
extern int sim_switches; /* variable that gets bits set for -x switches on command lines */
t_stat sca_set_baud (UNIT *uptr, int32 value, char *cptr, void *desc);
UNIT sca_unit = { /* default settings */

7
Ibm1130/ibm1130_stddev.c
View file

@ -112,7 +112,6 @@ typedef struct tag_os_map { /* os_map = overstrike mapping */
unsigned char inlist[MAX_OS_CHARS]; /* inlist = overstruck ASCII characters, sorted. NOT NULL TERMINATED */
} OS_MAP;
extern UNIT *sim_clock_queue;
extern int cgi;
static int32 tti_dsw = 0; /* device status words */
@ -152,10 +151,6 @@ static char * handle_map_input_definition(char **pc);
static char * handle_map_output_definition(char **pc);
static char * handle_map_overstrike_definition(char **pc);
extern t_stat sim_poll_kbd(void);
extern t_stat sim_wait_kbd(void);
extern t_stat sim_putchar(int32 out);
#define UNIT_V_CSET (UNIT_V_UF + 0) /* user flag: character set */
#define UNIT_V_LOCKED (UNIT_V_UF + 2) /* user flag: keyboard locked */
#define UNIT_V_ANSI (UNIT_V_UF + 3)
@ -356,7 +351,7 @@ static t_stat tti_svc (UNIT *uptr)
/* otherwise, so ^E can interrupt the simulator, */
sim_activate(&tti_unit, tti_unit.wait); /* always continue polling keyboard */
assert(sim_clock_queue != NULL);
assert(sim_clock_queue != QUEUE_LIST_END);
temp = sim_poll_kbd();

7
Interdata/id16_cpu.c
View file

@ -223,11 +223,6 @@ InstHistory *hst = NULL; /* instruction history *
struct BlockIO blk_io; /* block I/O status */
uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
uint32 ReadB (uint32 loc);
uint32 ReadH (uint32 loc);
void WriteB (uint32 loc, uint32 val);
@ -2011,8 +2006,6 @@ char *cptr = (char *) desc;
t_value sim_eval[2];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

8
Interdata/id32_cpu.c
View file

@ -253,12 +253,6 @@ jmp_buf save_env; /* abort handler */
struct BlockIO blk_io; /* block I/O status */
uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
extern FILE *sim_deb;
uint32 ReadB (uint32 loc, uint32 rel);
uint32 ReadH (uint32 loc, uint32 rel);
void WriteB (uint32 loc, uint32 val, uint32 rel);
@ -2400,8 +2394,6 @@ char *cptr = (char *) desc;
t_value sim_eval[3];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

1
Interdata/id32_dboot.c
View file

@ -288,7 +288,6 @@ t_stat id_dboot (int32 u, DEVICE *dptr)
{
extern DIB ttp_dib, sch_dib;
extern uint32 PC;
extern int32 sim_switches;
uint32 i, typ, ctlno, off, add, cap, sch_dev;
UNIT *uptr;

1
Interdata/id_dp.c
View file

@ -139,7 +139,6 @@ static struct drvtyp drv_tab[] = {
};
extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern FILE *sim_deb;
uint8 dpxb[DP_NUMBY]; /* xfer buffer */
uint32 dp_bptr = 0; /* buffer ptr */

2
Interdata/id_io.c
View file

@ -66,8 +66,6 @@ extern uint32 int_req[INTSZ], int_enb[INTSZ];
extern uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout);
extern uint32 pawidth;
extern UNIT cpu_unit;
extern FILE *sim_log;
extern DEVICE *sim_devices[];
uint32 sch_max = 2; /* sch count */
uint32 sch_sa[SCH_NUMCH] = { 0 }; /* start addr */

3
LGP/lgp_cpu.c
View file

@ -147,9 +147,6 @@ int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
int32 pcq_p = 0; /* PC queue ptr */
REG *pcq_r = NULL; /* PC queue reg ptr */
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern int32 sim_step;
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);

1
LGP/lgp_stddev.c
View file

@ -48,7 +48,6 @@ extern uint32 A;
extern uint32 inp_strt, inp_done;
extern uint32 out_strt, out_done;
extern UNIT cpu_unit;
extern int32 sim_switches;
t_stat tti_svc (UNIT *uptr);
t_stat ttr_svc (UNIT *uptr);

4
LGP/lgp_sys.c
View file

@ -40,12 +40,8 @@ extern REG cpu_reg[];
extern uint32 M[];
extern uint32 PC;
extern uint32 ts_flag;
extern int32 sim_switches;
extern int32 flex_to_ascii[128], ascii_to_flex[128];
extern void (*sim_vm_fprint_addr) (FILE *st, DEVICE *dptr, t_addr addr);
extern t_addr (*sim_vm_parse_addr) (DEVICE *dptr, char *cptr, char **tptr);
/* SCP data structures and interface routines
sim_name simulator name string

7
NOVA/eclipse_cpu.c
View file

@ -495,9 +495,6 @@ FILE *Trace;
t_stat reason;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern DEVICE *sim_devices[];
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
@ -516,9 +513,6 @@ int32 PutMap(int32 addr, int32 data);
int32 Debug_Entry(int32 PC, int32 inst, int32 inst2, int32 AC0, int32 AC1, int32 AC2, int32 AC3, int32 flags);
t_stat build_devtab (void);
extern t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
/* CPU data structures
cpu_dev CPU device descriptor
@ -699,7 +693,6 @@ DEVICE pit_dev = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
register int32 PC, IR, i, t, MA, j, k, tac;
register uint32 mddata, uAC0, uAC1, uAC2, uAC3;
int16 sAC0, sAC1, sAC2;

8
NOVA/nova_cpu.c
View file

@ -330,14 +330,6 @@ char * devBitNames( int32 flags, char * ptr, char * sepStr ) ;
void mask_out (int32 mask);
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern DEVICE * sim_devices[];
extern t_stat fprint_sym(FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 sw);
/* CPU data structures
cpu_dev CPU device descriptor

2
NOVA/nova_qty.c
View file

@ -105,8 +105,6 @@
extern int32 int_req, dev_busy, dev_done, dev_disable ;
extern int32 sim_switches ;
extern FILE * sim_log ;
extern int32 tmxr_poll ; /* calibrated delay */
t_stat qty_setnl ( UNIT * uptr, int32 val, char * cptr, void * desc ) ;

3
NOVA/nova_sys.c
View file

@ -79,9 +79,6 @@ extern int32 MapStat;
#endif
extern int32 sim_switches;
/* SCP data structures
sim_name simulator name string

7
PDP1/pdp1_cpu.c
View file

@ -335,10 +335,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* inst history */
extern UNIT *sim_clock_queue;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
@ -503,7 +499,6 @@ DEVICE cpu_dev = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
int32 IR, op, i, t, xct_count;
int32 sign, signd, v, sbs_lvl, byno;
int32 dev, pulse, io_data, sc, skip;
@ -1656,8 +1651,6 @@ char *cptr = (char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

3
PDP1/pdp1_dt.c
View file

@ -250,9 +250,6 @@
extern int32 M[];
extern int32 stop_inst;
extern UNIT cpu_unit;
extern int32 sim_switches;
extern int32 sim_is_running;
extern FILE *sim_deb;
int32 dtsa = 0; /* status A */
int32 dtsb = 0; /* status B */

1
PDP1/pdp1_sys.c
View file

@ -65,7 +65,6 @@ extern int32 M[];
extern int32 PC;
extern int32 ascii_to_fiodec[], fiodec_to_ascii[];
extern int32 sc_map[];
extern int32 sim_switches;
/* SCP data structures and interface routines

6
PDP10/pdp10_cpu.c
View file

@ -198,10 +198,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
extern int32 sim_int_char;
extern int32 sim_interval;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
/* Forward and external declarations */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
@ -2393,8 +2389,6 @@ char *cptr = (char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

2
PDP10/pdp10_ksio.c
View file

@ -120,9 +120,7 @@ extern d10 pager_word;
extern int32 flags;
extern const int32 pi_l2bit[8];
extern UNIT cpu_unit;
extern FILE *sim_log;
extern jmp_buf save_env;
extern DEVICE *sim_devices[];
extern int32 pi_eval (void);
extern int32 rp_inta (void);

1
PDP10/pdp10_rp.c
View file

@ -1155,7 +1155,6 @@ return SCPE_OK;
t_stat rp_detach (UNIT *uptr)
{
int32 drv;
extern int32 sim_is_running;
if (!(uptr->flags & UNIT_ATT)) /* attached? */
return SCPE_OK;

1
PDP10/pdp10_sys.c
View file

@ -338,7 +338,6 @@ t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
d10 data;
int32 wc, fmt;
extern int32 sim_switches;
fmt = 0; /* no fmt */
if (sim_switches & SWMASK ('R')) /* -r? */

2
PDP10/pdp10_tu.c
View file

@ -297,8 +297,6 @@ extern int32 int_req;
extern int32 ubmap[UBANUM][UMAP_MEMSIZE]; /* Unibus map */
extern int32 ubcs[UBANUM];
extern UNIT cpu_unit;
extern int32 sim_switches;
extern FILE *sim_deb;
int32 tucs1 = 0; /* control/status 1 */
int32 tuwc = 0; /* word count */

2
PDP11/pdp11_cis.c
View file

@ -175,9 +175,7 @@ static DSTR Dstr0 = { 0, {0, 0, 0, 0} };
extern int32 isenable, dsenable;
extern int32 N, Z, V, C, fpd, ipl;
extern int32 R[8], trap_req;
extern int32 sim_interval;
extern uint32 cpu_type;
extern FILE *sim_deb;
int32 ReadDstr (int32 *dscr, DSTR *dec, int32 flag);
void WriteDstr (int32 *dscr, DSTR *dec, int32 flag);

6
PDP11/pdp11_cpu.c
View file

@ -304,12 +304,6 @@ int32 dsmask[4] = { MMR3_KDS, MMR3_SDS, 0, MMR3_UDS }; /* dspace enables */
t_addr cpu_memsize = INIMEMSIZE; /* last mem addr */
extern int32 CPUERR, MAINT;
extern int32 sim_interval;
extern int32 sim_int_char;
extern int32 sim_switches;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
extern DEVICE *sim_devices[];
extern CPUTAB cpu_tab[];
/* Function declarations */

4
PDP11/pdp11_cpumod.c
View file

@ -84,13 +84,11 @@ static int32 clk_tps_map[4] = { 60, 60, 50, 800 };
extern uint16 *M;
extern int32 R[8];
extern DEVICE cpu_dev, *sim_devices[];
extern DEVICE cpu_dev;
extern UNIT cpu_unit;
extern FILE *sim_log;
extern int32 STKLIM, PIRQ;
extern uint32 cpu_model, cpu_type, cpu_opt;
extern int32 clk_fie, clk_fnxm, clk_tps, clk_default;
extern int32 sim_switches;
t_stat CPU24_rd (int32 *data, int32 addr, int32 access);
t_stat CPU24_wr (int32 data, int32 addr, int32 access);

3
PDP11/pdp11_cr.c
View file

@ -186,8 +186,6 @@ extern int32 int_req[IPL_HLVL];
#define DFLT_CPM 285
#endif
extern FILE *sim_deb; /* sim_console.c */
/* create a int32 constant from four characters */
#define I4C(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
#define I4C_CBN I4C ('C','B','N',' ')
@ -1102,7 +1100,6 @@ t_stat cr_attach ( UNIT *uptr,
char *cptr )
{
t_stat reason;
extern int32 sim_switches;
if (sim_switches & ~MASK)
return (SCPE_INVSW);

3
PDP11/pdp11_dz.c
View file

@ -164,8 +164,6 @@ char *dz_stopbits[] = {"1", "2", "1", "1.5"};
#define TDR_V_TBR 8 /* xmit break - NI */
extern int32 IREQ (HLVL);
extern int32 sim_switches;
extern FILE *sim_log;
extern int32 tmxr_poll; /* calibrated delay */
uint16 dz_csr[MAX_DZ_MUXES] = { 0 }; /* csr */
@ -674,7 +672,6 @@ t_stat dz_attach (UNIT *uptr, char *cptr)
{
int32 dz, muxln;
t_stat r;
extern int32 sim_switches;
if (sim_switches & SWMASK ('M')) /* modem control? */
tmxr_set_modem_control_passthru (&dz_desc);

3
PDP11/pdp11_io.c
View file

@ -60,8 +60,7 @@ extern int32 trap_req, ipl;
extern int32 cpu_log;
extern int32 autcon_enb;
extern int32 uba_last;
extern FILE *sim_log;
extern DEVICE *sim_devices[], cpu_dev;
extern DEVICE cpu_dev;
extern t_addr cpu_memsize;
int32 calc_ints (int32 nipl, int32 trq);

2
PDP11/pdp11_io_lib.c
View file

@ -36,8 +36,6 @@
#include "sim_sock.h"
#include "sim_tmxr.h"
extern FILE *sim_log;
extern DEVICE *sim_devices[];
extern int32 autcon_enb;
extern int32 int_vec[IPL_HLVL][32];
extern int32 (*int_ack[IPL_HLVL][32])(void);

1
PDP11/pdp11_kg.c
View file

@ -95,7 +95,6 @@
#endif
#include "pdp11_defs.h"
extern FILE *sim_deb;
extern REG cpu_reg[];
extern int32 R[];

1
PDP11/pdp11_rc.c
View file

@ -147,7 +147,6 @@
((double) RC_NUMWD)))
extern int32 int_req[IPL_HLVL];
extern FILE *sim_deb;
extern int32 R[];
static uint32 rc_la = 0; /* look-ahead */

1
PDP11/pdp11_rf.c
View file

@ -110,7 +110,6 @@
extern uint16 *M;
extern int32 int_req[IPL_HLVL];
extern FILE *sim_deb;
uint32 rf_cs = 0; /* status register */
uint32 rf_cma = 0;

3
PDP11/pdp11_rh.c
View file

@ -164,9 +164,6 @@ extern int32 cpu_bme;
extern uint16 *M;
extern int32 int_req[IPL_HLVL];
extern t_addr cpu_memsize;
extern FILE *sim_deb;
extern FILE *sim_log;
extern int32 sim_switches;
t_stat mba_reset (DEVICE *dptr);
t_stat mba_rd (int32 *val, int32 pa, int32 access);

1
PDP11/pdp11_rl.c
View file

@ -227,7 +227,6 @@ extern UNIT cpu_unit;
#define RLBAE_IMP (0000077) /* implemented */
extern int32 int_req[IPL_HLVL];
extern FILE *sim_deb;
uint16 *rlxb = NULL; /* xfer buffer */
int32 rlcs = 0; /* control/status */

1
PDP11/pdp11_rp.c
View file

@ -1393,7 +1393,6 @@ t_stat rp_detach (UNIT *uptr)
{
int32 drv;
DEVICE *dptr = find_dev_from_unit (uptr);
extern int32 sim_is_running;
if (!(uptr->flags & UNIT_ATT)) /* attached? */
return SCPE_OK;

2
PDP11/pdp11_rq.c
View file

@ -700,8 +700,6 @@ static struct ctlrtyp ctlr_tab[] = {
extern int32 int_req[IPL_HLVL];
extern int32 tmr_poll, clk_tps;
extern uint32 sim_taddr_64;
extern int32 sim_switches;
int32 rq_itime = 200; /* init time, except */
int32 rq_itime4 = 10; /* stage 4 */

1
PDP11/pdp11_ta.c
View file

@ -106,7 +106,6 @@
#define UST_GAP 01 /* last op hit gap */
extern int32 int_req[IPL_HLVL];
extern FILE *sim_deb;
uint32 ta_cs = 0; /* control/status */
uint32 ta_idb = 0; /* input data buf */

3
PDP11/pdp11_tc.c
View file

@ -274,8 +274,6 @@
extern uint16 *M; /* memory */
extern int32 int_req[IPL_HLVL];
extern UNIT cpu_unit;
extern int32 sim_switches;
extern FILE *sim_deb;
int32 tcst = 0; /* status */
int32 tccm = 0; /* command */
@ -308,7 +306,6 @@ void dt_stopunit (UNIT *uptr);
int32 dt_comobv (int32 val);
int32 dt_csum (UNIT *uptr, int32 blk);
int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos);
extern int32 sim_is_running;
/* DT data structures

2
PDP11/pdp11_tm.c
View file

@ -154,7 +154,6 @@
extern uint16 *M; /* memory */
extern int32 int_req[IPL_HLVL];
extern FILE *sim_deb;
uint8 *tmxb = NULL; /* xfer buffer */
int32 tm_sta = 0; /* status register */
@ -715,7 +714,6 @@ t_stat tm_boot (int32 unitno, DEVICE *dptr)
{
size_t i;
extern int32 saved_PC;
extern int32 sim_switches;
sim_tape_rewind (&tm_unit[unitno]);
if (sim_switches & SWMASK ('O')) {

2
PDP11/pdp11_tq.c
View file

@ -246,8 +246,6 @@ static struct drvtyp drv_tab[] = {
extern int32 int_req[IPL_HLVL];
extern int32 tmr_poll, clk_tps;
extern FILE *sim_deb;
extern uint32 sim_taddr_64;
uint32 tq_sa = 0; /* status, addr */
uint32 tq_saw = 0; /* written data */

1
PDP11/pdp11_ts.c
View file

@ -268,7 +268,6 @@ extern uint32 cpu_opt;
extern int32 int_req[IPL_HLVL];
extern UNIT cpu_unit;
extern FILE *sim_deb;
uint8 *tsxb = NULL; /* xfer buffer */
int32 tssr = 0; /* status register */

3
PDP11/pdp11_tu.c
View file

@ -239,9 +239,6 @@ static char *tu_fname[CS1_N_FNC] = {
"WRITE", "31", "32", "33", "READF", "35", "36" "READR"
};
extern int32 sim_switches;
extern FILE *sim_deb;
t_stat tu_mbrd (int32 *data, int32 PA, int32 fmtr);
t_stat tu_mbwr (int32 data, int32 PA, int32 fmtr);
t_stat tu_svc (UNIT *uptr);

4
PDP11/pdp11_xq.c
View file

@ -254,10 +254,6 @@
extern int32 tmxr_poll;
extern int32 tmr_poll, clk_tps;
extern t_bool sim_idle_enab;
extern FILE* sim_deb;
extern int32 sim_switches;
extern FILE *sim_log;
extern char* read_line (char *ptr, int32 size, FILE *stream);
/* forward declarations */

9
PDP18B/pdp18b_cpu.c
View file

@ -379,13 +379,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
extern int32 sim_int_char;
extern int32 sim_interval;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
extern DEVICE *sim_devices[];
extern FILE *sim_log;
t_bool build_dev_tab (void);
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
@ -2321,8 +2314,6 @@ char *cptr = (char *) desc;
t_value sim_eval[2];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

3
PDP18B/pdp18b_dt.c
View file

@ -327,9 +327,6 @@
extern int32 M[];
extern int32 int_hwre[API_HLVL+1];
extern UNIT cpu_unit;
extern int32 sim_switches;
extern int32 sim_is_running;
extern FILE *sim_deb;
int32 dtsa = 0; /* status A */
int32 dtsb = 0; /* status B */

1
PDP18B/pdp18b_mt.c
View file

@ -127,7 +127,6 @@
extern int32 M[];
extern int32 int_hwre[API_HLVL+1];
extern UNIT cpu_unit;
extern FILE *sim_deb;
int32 mt_cu = 0; /* command/unit */
int32 mt_sta = 0; /* status register */

3
PDP18B/pdp18b_stddev.c
View file

@ -85,8 +85,6 @@
extern int32 M[];
extern int32 int_hwre[API_HLVL+1], PC, ASW;
extern int32 sim_switches;
extern int32 sim_is_running;
extern UNIT cpu_unit;
int32 clk_state = 0;
@ -862,7 +860,6 @@ t_stat ptr_boot (int32 unitno, DEVICE *dptr)
{
size_t i;
int32 mask, wd;
extern int32 sim_switches;
#if defined (PDP7)
if (sim_switches & SWMASK ('H')) /* hardware RIM load? */

2
PDP18B/pdp18b_sys.c
View file

@ -345,8 +345,6 @@ return SCPE_OK;
t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
extern int32 sim_switches;
if (flag != 0)
return SCPE_NOFNC;
if (sim_switches & SWMASK ('S')) /* RIM format? */

2
PDP8/pdp8_clk.c
View file

@ -44,8 +44,6 @@ extern int32 int_req, int_enable, dev_done, stop_inst;
int32 clk_tps = 60; /* ticks/second */
int32 tmxr_poll = 16000; /* term mux poll */
extern int32 sim_is_running;
int32 clk (int32 IR, int32 AC);
t_stat clk_svc (UNIT *uptr);
t_stat clk_reset (DEVICE *dptr);

9
PDP8/pdp8_cpu.c
View file

@ -240,13 +240,6 @@ int32 hst_p = 0; /* history pointer */
int32 hst_lnt = 0; /* history length */
InstHistory *hst = NULL; /* instruction history */
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern DEVICE *sim_devices[];
extern FILE *sim_log;
extern t_bool sim_idle_enab;
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
@ -1543,8 +1536,6 @@ char *cptr = (char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;

1
PDP8/pdp8_ct.c
View file

@ -138,7 +138,6 @@
extern int32 int_req, stop_inst;
extern UNIT cpu_unit;
extern FILE *sim_deb;
uint32 ct_sra = 0; /* status reg A */
uint32 ct_srb = 0; /* status reg B */

2
PDP8/pdp8_df.c
View file

@ -335,7 +335,7 @@ static const uint16 dm4_rom[] = {
t_stat df_boot (int32 unitno, DEVICE *dptr)
{
size_t i;
extern int32 sim_switches, saved_PC;
extern int32 saved_PC;
if (sim_switches & SWMASK ('D')) {
for (i = 0; i < DM4_LEN; i = i + 2)

3
PDP8/pdp8_dt.c
View file

@ -265,8 +265,6 @@
extern uint16 M[];
extern int32 int_req;
extern UNIT cpu_unit;
extern int32 sim_switches;
extern FILE *sim_deb;
int32 dtsa = 0; /* status A */
int32 dtsb = 0; /* status B */
@ -293,7 +291,6 @@ void dt_seterr (UNIT *uptr, int32 e);
int32 dt_comobv (int32 val);
int32 dt_csum (UNIT *uptr, int32 blk);
int32 dt_gethdr (UNIT *uptr, int32 blk, int32 relpos, int32 dir);
extern int32 sim_is_running;
/* DT data structures

2
PDP8/pdp8_fpp.c
View file

@ -96,8 +96,6 @@
#include "pdp8_defs.h"
extern int32 int_req;
extern int32 sim_switches;
extern int32 sim_interval;
extern uint16 M[];
extern int32 stop_inst;
extern UNIT cpu_unit;

2
PDP8/pdp8_rf.c
View file

@ -399,7 +399,7 @@ static const uint16 dm4_rom[] = {
t_stat rf_boot (int32 unitno, DEVICE *dptr)
{
size_t i;
extern int32 sim_switches, saved_PC;
extern int32 saved_PC;
if (rf_dib.dev != DEV_RF) /* only std devno */
return STOP_NOTSTD;

1
PDP8/pdp8_sys.c
View file

@ -65,7 +65,6 @@ extern DEVICE mt_dev, ct_dev;
extern DEVICE ttix_dev, ttox_dev;
extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
t_stat fprint_sym_fpp (FILE *of, t_value *val);
t_stat parse_sym_fpp (char *cptr, t_value *val);

2
PDP8/pdp8_td.c
View file

@ -208,8 +208,6 @@ int32 td_set_mtk (int32 code, int32 u, int32 k);
t_stat td_show_pos (FILE *st, UNIT *uptr, int32 val, void *desc);
extern uint16 M[];
extern int32 sim_switches;
extern int32 sim_is_running;
/* TD data structures

2
PDP8/pdp8_tt.c
View file

@ -45,7 +45,7 @@
#include <ctype.h>
extern int32 int_req, int_enable, dev_done, stop_inst;
extern int32 tmxr_poll, sim_is_running;
extern int32 tmxr_poll;
int32 tti (int32 IR, int32 AC);
int32 tto (int32 IR, int32 AC);

2
PDP8/pdp8_ttx.c
View file

@ -61,7 +61,7 @@
#define TTX_GETLN(x) (((x) >> 4) & TTX_MASK)
extern int32 int_req, int_enable, dev_done, stop_inst;
extern int32 tmxr_poll, sim_is_running;
extern int32 tmxr_poll;
uint8 ttix_buf[TTX_LINES] = { 0 }; /* input buffers */
uint8 ttox_buf[TTX_LINES] = { 0 }; /* output buffers */

4
S3/s3_cpu.c
View file

@ -382,8 +382,6 @@ int32 saved_PC; /* Saved (old) PC) */
int32 debug_reg = 0; /* set for debug/trace */
int32 debug_flag = 0; /* 1 when trace.log open */
FILE *trace;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ;/* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
@ -396,7 +394,6 @@ extern int32 lpt (int32 op, int32 m, int32 n, int32 data);
extern int32 dsk1 (int32 op, int32 m, int32 n, int32 data);
extern int32 dsk2 (int32 op, int32 m, int32 n, int32 data);
extern int32 cpu (int32 op, int32 m, int32 n, int32 data);
extern t_stat sim_activate (UNIT *uptr, int32 delay);
int32 nulldev (int32 opcode, int32 m, int32 n, int32 data);
int32 add_zoned (int32 addr1, int32 len1, int32 addr2, int32 len2);
int32 subtract_zoned (int32 addr1, int32 len1, int32 addr2, int32 len2);
@ -505,7 +502,6 @@ DEVICE cpu_dev = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
register int32 PC, IR;
int32 i, j, carry, zero, op1, op2;
int32 opcode = 0, qbyte = 0, rbyte = 0;

2
S3/s3_pkb.c
View file

@ -35,8 +35,6 @@
extern int32 int_req, dev_busy, dev_done, dev_disable;
t_stat pkb_svc (UNIT *uptr);
t_stat pkb_reset (DEVICE *dptr);
extern t_stat sim_poll_kbd (void);
extern t_stat sim_putchar (int32 out);
extern int32 IAR[], level;
extern int32 debug_reg;

8
S3/s3_sys.c
View file

@ -44,9 +44,9 @@ extern REG cpu_reg[];
extern unsigned char M[];
extern int32 saved_PC, IAR[];
extern unsigned char ebcdic_to_ascii[];
char *parse_addr(char *cptr, char *gbuf, int32 *addr, int32 *addrtype);
char *parse_addr(char *cptr, char *gbuf, t_addr *addr, int32 *addrtype);
int32 printf_sym (FILE *of, char *strg, int32 addr, uint32 *val,
int32 printf_sym (FILE *of, char *strg, t_addr addr, uint32 *val,
UNIT *uptr, int32 sw);
/* SCP data structures
@ -267,7 +267,7 @@ int32 fprint_sym (FILE *of, t_addr addr, uint32 *val,
return (r);
}
int32 printf_sym (FILE *of, char *strg, int32 addr, uint32 *val,
int32 printf_sym (FILE *of, char *strg, t_addr addr, uint32 *val,
UNIT *uptr, int32 sw)
{
int32 c1, c2, group, len1, len2, inst, aaddr, baddr;
@ -923,7 +923,7 @@ switch (opcode[j].form) { /* Get operands based on
return (-(oplen-1));
}
char *parse_addr(char *cptr, char *gbuf, int32 *addr, int32 *addrtype)
char *parse_addr(char *cptr, char *gbuf, t_addr *addr, int32 *addrtype)
{
int32 nybble = 0;
char temp[32];

6
SDS/sds_cpu.c
View file

@ -194,9 +194,6 @@ InstHistory *hst = NULL; /* instruction history *
int32 rtc_pie = 0; /* rtc pulse ie */
int32 rtc_tps = 60; /* rtc ticks/sec */
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
@ -359,7 +356,6 @@ static const uint32 int_vec[32] = {
t_stat sim_instr (void)
{
extern int32 sim_interval;
uint32 inst, tinst, pa, save_P, save_mode;
t_stat reason, tr;
@ -1667,8 +1663,6 @@ char *cptr = (char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
static char *cyc[] = { " ", " ", "INT", "TRP" };
if (hst_lnt == 0) /* enabled? */

2
SDS/sds_io.c
View file

@ -86,8 +86,6 @@ extern int32 rtc_pie;
extern int32 stop_invins, stop_invdev, stop_inviop;
extern uint32 mon_usr_trap;
extern UNIT cpu_unit;
extern FILE *sim_log;
extern DEVICE *sim_devices[];
t_stat chan_reset (DEVICE *dptr);
t_stat chan_read (int32 ch);

1
SDS/sds_sys.c
View file

@ -217,7 +217,6 @@ t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
{
int32 i, wd, buf[8];
int32 ldr = 1;
extern int32 sim_switches;
extern uint32 P;
if ((*cptr != 0) || (flag != 0))

7
TX-0/tx0_cpu.c
View file

@ -282,10 +282,6 @@ int32 fpc_OP; /* shadow op for FPC acc
int32 addr_mask = YMASK;
extern UNIT *sim_clock_queue;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
t_stat cpu_reset (DEVICE *dptr);
@ -448,7 +444,6 @@ t_stat sim_opr_orig(int32 op);
t_stat sim_instr (void)
{
extern int32 sim_interval;
int32 IR, op, inst_class, y;
int32 tempLR; /* LR temporary storage in case both LMB and MBL are set (swap LR<->MBR) */
t_stat reason;
@ -1167,8 +1162,6 @@ char *cptr = (char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) return SCPE_NOFNC; /* enabled? */
if (cptr) {

1
VAX/vax610_io.c
View file

@ -37,7 +37,6 @@ int32 autcon_enb = 1; /* autoconfig enable */
extern int32 PSL, SISR, trpirq, mem_err, hlt_pin;
extern int32 p1;
extern jmp_buf save_env;
extern DEVICE *sim_devices[];
int32 eval_int (void);
t_stat qba_reset (DEVICE *dptr);

1
VAX/vax610_stddev.c
View file

@ -69,7 +69,6 @@
extern int32 int_req[IPL_HLVL];
extern int32 hlt_pin;
extern int32 sim_switches;
extern jmp_buf save_env;
extern int32 p1;

3
VAX/vax610_sysdev.c
View file

@ -54,9 +54,6 @@ extern int32 mchk_va, mchk_ref;
extern int32 int_req[IPL_HLVL];
extern jmp_buf save_env;
extern int32 p1;
extern int32 sim_switches;
extern FILE *sim_log;
extern CTAB *sim_vm_cmd;
extern int32 trpirq, mem_err;
int32 conisp, conpc, conpsl; /* console reg */

1
VAX/vax610_syslist.c
View file

@ -49,7 +49,6 @@ extern DEVICE dz_dev;
extern DEVICE xq_dev, xqb_dev;
extern DEVICE vh_dev;
extern int32 sim_switches;
extern void WriteB (uint32 pa, int32 val);
extern UNIT cpu_unit;

3
VAX/vax630_io.c
View file

@ -64,9 +64,6 @@ extern UNIT cpu_unit;
extern int32 PSL, SISR, trpirq, mem_err, hlt_pin;
extern int32 p1;
extern jmp_buf save_env;
extern int32 sim_switches;
extern DEVICE *sim_devices[];
extern FILE *sim_log;
extern int32 ka_mser; /* KA630 mem sys err */
t_stat dbl_rd (int32 *data, int32 addr, int32 access);

1
VAX/vax630_stddev.c
View file

@ -49,7 +49,6 @@
extern int32 int_req[IPL_HLVL];
extern int32 hlt_pin;
extern int32 sim_switches;
int32 tti_csr = 0; /* control/status */
int32 tto_csr = 0; /* control/status */

5
VAX/vax630_sysdev.c
View file

@ -54,8 +54,6 @@
#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */
#define UNIT_NODELAY (1u << UNIT_V_NODELAY)
extern CTAB *sim_vm_cmd;
t_stat vax630_boot (int32 flag, char *ptr);
/* Special boot command, overrides regular boot */
@ -139,7 +137,6 @@ extern UNIT cpu_unit;
extern UNIT clk_unit;
extern jmp_buf save_env;
extern int32 p1;
extern int32 sim_switches;
extern int32 tmr_poll;
uint32 *rom = NULL; /* boot ROM */
@ -192,7 +189,6 @@ extern void rxcs_wr (int32 dat);
extern void txcs_wr (int32 dat);
extern void txdb_wr (int32 dat);
extern void ioreset_wr (int32 dat);
extern uint32 sim_os_msec();
/* ROM data structures
@ -830,7 +826,6 @@ return run_cmd (flag, "CPU");
t_stat cpu_boot (int32 unitno, DEVICE *dptr)
{
extern t_stat load_cmd (int32 flag, char *cptr);
t_stat r;
PC = ROMBASE;

1
VAX/vax630_syslist.c
View file

@ -55,7 +55,6 @@ extern DEVICE dz_dev;
extern DEVICE xq_dev, xqb_dev;
extern DEVICE vh_dev;
extern int32 sim_switches;
extern void WriteB (uint32 pa, int32 val);
extern void rom_wr_B (int32 pa, int32 val);
extern UNIT cpu_unit;

1
VAX/vax730_mem.c
View file

@ -66,7 +66,6 @@
#define MEM_BOARD_MASK(x,y) ((1u << (uint32)(x/y)) - 1)
extern UNIT cpu_unit;
extern FILE *sim_log, *sim_deb;
uint32 mcsr0 = 0;
uint32 mcsr1 = 0;

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