From dc871fa631dd55bf9de67c6b0d33257f5874a294 Mon Sep 17 00:00:00 2001 From: Bob Supnik Date: Sat, 27 May 2006 11:34:00 -0700 Subject: [PATCH] Notes For V3.6-0 The save/restore format has been updated to improve its reliability. As a result, save files prior to release 3.0 are no longer supported. The text documentation files are obsolete and are no longer included with the distribution. Up-to-date PDF documentation files are available on the SimH web site. 1. New Features 1.1 3.6-0 1.1.1 Most magnetic tapes - Added support for limiting tape capacity to a particular size in MB 1.1.2 IBM 7090/7094 - First release 1.1.3 VAX-11/780 - Added FLOAD command, loads system file from console floppy disk 1.1.4 VAX, VAX-11/780, and PDP-11 - Added card reader support (from John Dundas) 1.1.5 PDP-11 - Added instruction history 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h. --- 0readme_35.txt | 148 --- 0readme_36.txt | 39 + AltairZ80/altairZ80_cpu.c | 845 +++++++------- AltairZ80/altairZ80_defs.h | 13 +- AltairZ80/altairZ80_dsk.c | 4 +- AltairZ80/altairZ80_sio.c | 8 +- AltairZ80/altairZ80_sys.c | 4 +- AltairZ80/altairz80_hdsk.c | 10 +- GRI/gri_doc.txt | 338 ------ H316/h316_cpu.c | 49 +- H316/h316_doc.txt | 672 ----------- H316/h316_fhd.c | 13 +- H316/h316_lp.c | 5 +- H316/h316_mt.c | 13 +- H316/h316_stddev.c | 7 +- HP2100/hp2100_doc.txt | 1381 ---------------------- HP2100/hp2100_ms.c | 14 +- I1401/i1401_cpu.c | 20 +- I1401/i1401_doc.txt | 579 ---------- I1401/i1401_mt.c | 9 +- I1620/i1620_doc.txt | 533 --------- I7094/i7094_bugs.txt | 72 ++ I7094/i7094_cd.c | 495 ++++++++ I7094/i7094_clk.c | 124 ++ I7094/i7094_com.c | 1149 ++++++++++++++++++ I7094/i7094_cpu.c | 2239 ++++++++++++++++++++++++++++++++++++ I7094/i7094_cpu1.c | 837 ++++++++++++++ I7094/i7094_dat.h | 152 +++ I7094/i7094_defs.h | 474 ++++++++ I7094/i7094_drm.c | 286 +++++ I7094/i7094_dsk.c | 1172 +++++++++++++++++++ I7094/i7094_io.c | 1789 ++++++++++++++++++++++++++++ I7094/i7094_lp.c | 365 ++++++ I7094/i7094_mt.c | 826 +++++++++++++ I7094/i7094_sys.c | 718 ++++++++++++ Interdata/id16_cpu.c | 6 +- Interdata/id32_cpu.c | 22 +- Interdata/id_defs.h | 11 +- Interdata/id_diag.txt | 6 +- Interdata/id_doc.txt | 1054 ----------------- Interdata/id_fp.c | 4 +- Interdata/id_idc.c | 73 +- Interdata/id_io.c | 5 +- Interdata/id_mt.c | 11 +- LGP/lgp_doc.txt | 465 -------- NOVA/eclipse_cpu.c | 5 +- NOVA/nova_cpu.c | 5 +- NOVA/nova_doc.txt | 682 ----------- NOVA/nova_dsk.c | 10 +- PDP1/pdp1_doc.txt | 572 --------- PDP10/pdp10_doc.txt | 660 ----------- PDP10/pdp10_tu.c | 28 +- PDP11/pdp11_cis.c | 41 +- PDP11/pdp11_cpu.c | 150 ++- PDP11/pdp11_cr.c | 1272 ++++++++++++++++++++ PDP11/pdp11_cr_dat.h | 622 ++++++++++ PDP11/pdp11_defs.h | 16 +- PDP11/pdp11_doc.txt | 1624 -------------------------- PDP11/pdp11_ry.c | 10 +- PDP11/pdp11_sys.c | 5 +- PDP11/pdp11_tc.c | 4 +- PDP11/pdp11_tm.c | 10 +- PDP11/pdp11_tq.c | 23 +- PDP11/pdp11_ts.c | 19 +- PDP11/pdp11_tu.c | 30 +- PDP11/pdp11_xq.c | 23 +- PDP11/txt2cbn.c | 49 + PDP18B/pdp18b_doc.txt | 1037 ----------------- PDP18B/pdp18b_mt.c | 11 +- PDP18B/pdp18b_rf.c | 10 +- PDP8/pdp8_df.c | 8 +- PDP8/pdp8_doc.txt | 886 -------------- PDP8/pdp8_mt.c | 11 +- PDP8/pdp8_rf.c | 8 +- PDP8/pdp8_rx.c | 16 +- SDS/sds_doc.txt | 559 --------- SDS/sds_mt.c | 15 +- VAX/vax780_bugs.txt | 43 + VAX/vax780_defs.h | 25 +- VAX/vax780_doc.txt | 1093 ------------------ VAX/vax780_fload.c | 250 ++++ VAX/vax780_sbi.c | 12 +- VAX/vax780_stddev.c | 53 +- VAX/vax780_syslist.c | 7 +- VAX/vax_cis.c | 141 ++- VAX/vax_cmode.c | 81 +- VAX/vax_cpu.c | 551 +++++++-- VAX/vax_cpu1.c | 46 +- VAX/vax_defs.h | 12 +- VAX/vax_doc.txt | 1133 ------------------ VAX/vax_fpa.c | 142 ++- VAX/vax_mmu.c | 15 +- VAX/vax_octa.c | 164 ++- VAX/vax_syslist.c | 5 +- VAX/vaxmod_defs.h | 19 +- descrip.mms | 433 ++++--- makefile | 28 +- scp.c | 176 +-- sim_fio.c | 17 +- sim_fio.h | 4 +- sim_rev.h | 120 +- sim_tape.c | 42 +- sim_tape.h | 7 +- simh_doc.txt | 1466 ----------------------- simh_faq.txt | 682 ----------- simh_swre.txt | 709 ------------ 106 files changed, 15439 insertions(+), 17517 deletions(-) delete mode 100644 0readme_35.txt create mode 100644 0readme_36.txt delete mode 100644 GRI/gri_doc.txt delete mode 100644 H316/h316_doc.txt delete mode 100644 HP2100/hp2100_doc.txt delete mode 100644 I1401/i1401_doc.txt delete mode 100644 I1620/i1620_doc.txt create mode 100644 I7094/i7094_bugs.txt create mode 100644 I7094/i7094_cd.c create mode 100644 I7094/i7094_clk.c create mode 100644 I7094/i7094_com.c create mode 100644 I7094/i7094_cpu.c create mode 100644 I7094/i7094_cpu1.c create mode 100644 I7094/i7094_dat.h create mode 100644 I7094/i7094_defs.h create mode 100644 I7094/i7094_drm.c create mode 100644 I7094/i7094_dsk.c create mode 100644 I7094/i7094_io.c create mode 100644 I7094/i7094_lp.c create mode 100644 I7094/i7094_mt.c create mode 100644 I7094/i7094_sys.c delete mode 100644 Interdata/id_doc.txt delete mode 100644 LGP/lgp_doc.txt delete mode 100644 NOVA/nova_doc.txt delete mode 100644 PDP1/pdp1_doc.txt delete mode 100644 PDP10/pdp10_doc.txt create mode 100644 PDP11/pdp11_cr.c create mode 100644 PDP11/pdp11_cr_dat.h delete mode 100644 PDP11/pdp11_doc.txt create mode 100644 PDP11/txt2cbn.c delete mode 100644 PDP18B/pdp18b_doc.txt delete mode 100644 PDP8/pdp8_doc.txt delete mode 100644 SDS/sds_doc.txt delete mode 100644 VAX/vax780_doc.txt create mode 100644 VAX/vax780_fload.c delete mode 100644 VAX/vax_doc.txt delete mode 100644 simh_doc.txt delete mode 100644 simh_faq.txt delete mode 100644 simh_swre.txt diff --git a/0readme_35.txt b/0readme_35.txt deleted file mode 100644 index 08780619..00000000 --- a/0readme_35.txt +++ /dev/null @@ -1,148 +0,0 @@ -Notes For V3.5-1 - -The source set has been extensively overhauled. For correct -viewing, set Visual C++ or Emacs to have tab stops every 4 -characters. - -1. New Features - -1.1 3.5-0 - -1.1.1 All Ethernet devices - -- Added Windows user-defined adapter names (from Timothe Litt) - -1.1.2 Interdata, SDS, HP, PDP-8, PDP-18b terminal multiplexors - -- Added support for SET n DISCONNECT - -1.1.3 VAX - -- Added latent QDSS support -- Revised autoconfigure to handle QDSS - -1.1.4 PDP-11 - -- Revised autoconfigure to handle more cases - -1.2 3.5-1 - -No new features - -1.3 3.5-2 - -1.3.1 All ASCII terminals - -- Most ASCII terminal emulators have supported 7-bit and 8-bit - operation; where required, they have also supported an upper- - case only or KSR-emulation mode. This release adds a new mode, - 7P, for 7-bit printing characters. In 7P mode, non-printing - characters in the range 0-31 (decimal), and 127 (decimal), are - automatically suppressed. This prevents printing of fill - characters under Windows. - - The printable character set for ASCII code values 0-31 can be - changed with the SET CONSOLE PCHAR command. Code value 127 - (DELETE) is always suppressed. - -1.3.2 VAX-11/780 - -- First release. The VAX-11/780 has successfully run VMS V7.2. The - commercial instructions and compatability mode have not been - extensively tested. The Ethernet controller is not working yet - and is disabled. - -2. Bugs Fixed - -2.1 3.5-0 - -2.1.1 SCP and libraries - -- Trim trailing spaces on all input (for example, attach file names) -- Fixed sim_sock spurious SIGPIPE error in Unix/Linux -- Fixed sim_tape misallocation of TPC map array for 64b simulators - -2.1.2 1401 - -- Fixed bug, CPU reset was clearing SSB through SSG - -2.1.3 PDP-11 - -- Fixed bug in VH vector display routine -- Fixed XU runt packet processing (found by Tim Chapman) - -2.1.4 Interdata - -- Fixed bug in SHOW PAS CONN/STATS -- Fixed potential integer overflow exception in divide - -2.1.5 SDS - -- Fixed bug in SHOW MUX CONN/STATS - -2.1.6 HP - -- Fixed bug in SHOW MUX CONN/STATS - -2.1.7 PDP-8 - -- Fixed bug in SHOW TTIX CONN/STATS -- Fixed bug in SET/SHOW TTOXn LOG - -2.1.8 PDP-18b - -- Fixed bug in SHOW TTIX CONN/STATS -- Fixed bug in SET/SHOW TTOXn LOG - -2.1.9 Nova, Eclipse - -- Fixed potential integer overflow exception in divide - -2.2 3.5-1 - -2.2.1 1401 - -- Changed character encodings to be compatible with Pierce 709X simulator -- Added mode for old/new character encodings - -2.2.2 1620 - -- Changed character encodings to be compatible with Pierce 709X simulator - -2.2.3 PDP-10 - -- Changed MOVNI to eliminate GCC warning - -2.2.4 VAX - -- Fixed bug in structure definitions with 32b compilation options -- Fixed bug in autoconfiguration table - -2.2.5 PDP-11 - -- Fixed bug in autoconfiguration table - -2.3 3.5-2 - -2.3.1 PDP-10 - -- RP: fixed drive clear not to clear disk address - -2.3.2 PDP-11 (VAX, VAX-11/780, for shared peripherals) - -- HK: fixed overlap seek interaction with drive select, drive clear, etc -- RQ, TM, TQ, TS, TU: widened address display to 64b when USE_ADDR64 option selected -- TU: changed default adapter from TM02 to TM03 (required by VMS) -- RP: fixed drive clear not to clear disk address -- RP, TU: fixed device enable/disable to enabled/disable Massbus adapter as well -- XQ: fixed register access alignment bug (found by Doug Carman) - -2.3.3 PDP-8 - -- RL: fixed IOT 61 decoding bug (found by David Gesswein) -- DF, DT, RF: fixed register access alignment bug (found by Doug Carman) - -2.3.4 VAX - -- Fixed CVTfi to trap on integer overflow if PSW is set -- Fixed breakpoint detection when USE_ADDR64 option selected diff --git a/0readme_36.txt b/0readme_36.txt new file mode 100644 index 00000000..307e7846 --- /dev/null +++ b/0readme_36.txt @@ -0,0 +1,39 @@ +Notes For V3.6-0 + +The save/restore format has been updated to improve its reliability. +As a result, save files prior to release 3.0 are no longer supported. + +The text documentation files are obsolete and are no longer included +with the distribution. Up-to-date PDF documentation files are +available on the SimH web site. + + +1. New Features + +1.1 3.6-0 + +1.1.1 Most magnetic tapes + +- Added support for limiting tape capacity to a particular size in MB + +1.1.2 IBM 7090/7094 + +- First release + +1.1.3 VAX-11/780 + +- Added FLOAD command, loads system file from console floppy disk + +1.1.4 VAX, VAX-11/780, and PDP-11 + +- Added card reader support (from John Dundas) + +1.1.5 PDP-11 + +- Added instruction history + + +2. Bugs Fixed + +Please see the revision history on http://simh.trailing-edge.com or +in the source module sim_rev.h. diff --git a/AltairZ80/altairZ80_cpu.c b/AltairZ80/altairZ80_cpu.c index bec5cc67..0254dcae 100644 --- a/AltairZ80/altairZ80_cpu.c +++ b/AltairZ80/altairZ80_cpu.c @@ -1,6 +1,6 @@ /* altairz80_cpu.c: MITS Altair CPU (8080 and Z80) - Copyright (c) 2002-2005, Peter Schorn + Copyright (c) 2002-2006, Peter Schorn Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -82,7 +82,7 @@ goto end_decode; \ } \ else { \ - sim_brk_pend = FALSE; \ + sim_brk_pend[0] = FALSE; \ continue; \ } \ } @@ -120,7 +120,7 @@ tStates += 17; \ } \ else { \ - sim_brk_pend = FALSE; \ + sim_brk_pend[0] = FALSE; \ PC += 2; \ tStates += 10; \ } \ @@ -148,19 +148,18 @@ t_stat cpu_reset(DEVICE *dptr); t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int32 flag); void PutBYTEBasic(const uint32 Addr, const uint32 Bank, const uint32 Value); -void PutBYTEForced(register uint32 Addr, register uint32 Value); -int32 addressIsInROM(const uint32 Addr); -int32 addressExists(const uint32 Addr); t_stat sim_instr(void); int32 install_bootrom(void); void protect(const int32 l, const int32 h); -void printROMMessage(const uint32 cntROM); -uint8 GetBYTEWrapper(register uint32 Addr); -void PutBYTEWrapper(register uint32 Addr, register uint32 Value); +uint8 GetBYTEWrapper(const uint32 Addr); +void PutBYTEWrapper(const uint32 Addr, const uint32 Value); int32 getBankSelect(void); -void setBankSelect(int32 b); +void setBankSelect(const int32 b); uint32 getCommon(void); -void setCommon(uint32 c); +static void PutBYTEForced(uint32 Addr, const uint32 Value); +static int32 addressIsInROM(const uint32 Addr); +static int32 addressExists(const uint32 Addr); +static void printROMMessage(const uint32 cntROM); static void warnUnsuccessfulWriteAttempt(const uint32 Addr); static uint8 warnUnsuccessfulReadAttempt(const uint32 Addr); static t_stat cpu_set_rom (UNIT *uptr, int32 value, char *cptr, void *desc); @@ -175,9 +174,7 @@ static void checkROMBoundaries(void); static void reset_memory(void); static uint32 in(const uint32 Port); static void out(const uint32 Port, const uint32 Value); -static uint8 GetBYTE(register uint32 Addr); static void PutBYTE(register uint32 Addr, register uint32 Value); -static uint16 GetWORD(register uint32 a); static void PutWORD(register uint32 a, register uint32 v); static t_bool sim_brk_lookup (const t_addr bloc, const int32 btyp); static void resetCell(const int32 address, const int32 bank); @@ -374,11 +371,11 @@ static const struct idev dev_table[256] = { {&nulldev}, {&hdsk_io}, {&simh_dev}, {&sr_dev} /* FC */ }; -static INLINE void out(const uint32 Port, const uint32 Value) { +static void out(const uint32 Port, const uint32 Value) { dev_table[Port].routine(Port, 1, Value); } -static INLINE uint32 in(const uint32 Port) { +static uint32 in(const uint32 Port) { return dev_table[Port].routine(Port, 0, 0); } @@ -1502,20 +1499,7 @@ int32 addressExists(const uint32 Addr) { && (ROMLow <= addr) && (addr <= ROMHigh) ); } -static INLINE uint8 GetBYTE(register uint32 Addr) { - Addr &= ADDRMASK; /* registers are NOT guaranteed to be always 16-bit values */ - if (cpu_unit.flags & UNIT_BANKED) { /* banked memory case */ - /* if Addr below "common" take from selected bank, otherwise from bank 0 */ - return Addr < common ? M[Addr][bankSelect] : M[Addr][0]; - } - else { /* non-banked memory case */ - return ((Addr < MEMSIZE) || - ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= Addr) && (Addr <= ROMHigh) )) ? - M[Addr][0] : warnUnsuccessfulReadAttempt(Addr); - } -} - -static INLINE void PutBYTE(register uint32 Addr, register uint32 Value) { +static void PutBYTE(register uint32 Addr, const register uint32 Value) { Addr &= ADDRMASK; /* registers are NOT guaranteed to be always 16-bit values */ if (cpu_unit.flags & UNIT_BANKED) { if (Addr < common) { @@ -1538,7 +1522,7 @@ static INLINE void PutBYTE(register uint32 Addr, register uint32 Value) { } } -static INLINE void PutWORD(register uint32 Addr, register uint32 Value) { +static void PutWORD(register uint32 Addr, const register uint32 Value) { Addr &= ADDRMASK; /* registers are NOT guaranteed to be always 16-bit values */ if (cpu_unit.flags & UNIT_BANKED) { if (Addr < common) { @@ -1578,7 +1562,7 @@ static INLINE void PutWORD(register uint32 Addr, register uint32 Value) { } } -void PutBYTEForced(register uint32 Addr, register uint32 Value) { +static void PutBYTEForced(uint32 Addr, const uint32 Value) { Addr &= ADDRMASK; /* registers are NOT guaranteed to be always 16-bit values */ if ((cpu_unit.flags & UNIT_BANKED) && (Addr < common)) { M[Addr][bankSelect] = Value; @@ -1626,7 +1610,7 @@ int32 getBankSelect(void) { return bankSelect; } -void setBankSelect(int32 b) { +void setBankSelect(const int32 b) { bankSelect = b; } @@ -1634,51 +1618,80 @@ uint32 getCommon(void) { return common; } -void setCommon(uint32 c) { - common = c; -} +#define Reduce(Addr) ((Addr) & ADDRMASK) -uint8 GetBYTEWrapper(register uint32 Addr) { /* make sure that non-inlined version exists */ +#define GetBYTE(Addr) \ + ((cpu_unit.flags & UNIT_BANKED) ? \ + (Reduce(Addr) < common ? \ + M[Reduce(Addr)][bankSelect] \ + : \ + M[Reduce(Addr)][0]) \ + : \ + (((Reduce(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= Reduce(Addr)) && (Reduce(Addr) <= ROMHigh) )) ? \ + M[Reduce(Addr)][0] \ + : \ + warnUnsuccessfulReadAttempt(Reduce(Addr)))) + +#define RAM_pp(Addr) \ + ((cpu_unit.flags & UNIT_BANKED) ? \ + (Reduce(Addr) < common ? \ + M[Reduce(Addr++)][bankSelect] \ + : \ + M[Reduce(Addr++)][0]) \ + : \ + (((Reduce(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= Reduce(Addr)) && (Reduce(Addr) <= ROMHigh) )) ? \ + M[Reduce(Addr++)][0] \ + : \ + warnUnsuccessfulReadAttempt(Reduce(Addr++)))) + +#define RAM_mm(Addr) \ + ((cpu_unit.flags & UNIT_BANKED) ? \ + (Reduce(Addr) < common ? \ + M[Reduce(Addr--)][bankSelect] \ + : \ + M[Reduce(Addr--)][0]) \ + : \ + (((Reduce(Addr) < MEMSIZE) || ( (cpu_unit.flags & UNIT_ROM) && (ROMLow <= Reduce(Addr)) && (Reduce(Addr) <= ROMHigh) )) ? \ + M[Reduce(Addr--)][0] \ + : \ + warnUnsuccessfulReadAttempt(Reduce(Addr--)))) + +#define GetWORD(Addr) (GetBYTE(Addr) | (GetBYTE(Addr + 1) << 8)) + +uint8 GetBYTEWrapper(const uint32 Addr) { return GetBYTE(Addr); } -void PutBYTEWrapper(register uint32 Addr, register uint32 Value) { +void PutBYTEWrapper(const uint32 Addr, const uint32 Value) { PutBYTE(Addr, Value); } -#define RAM_mm(a) GetBYTE(a--) -#define RAM_pp(a) GetBYTE(a++) - #define PutBYTE_pp(a,v) PutBYTE(a++, v) #define PutBYTE_mm(a,v) PutBYTE(a--, v) #define mm_PutBYTE(a,v) PutBYTE(--a, v) -static INLINE uint16 GetWORD(register uint32 a) { - return GetBYTE(a) | (GetBYTE(a + 1) << 8); -} - #define MASK_BRK (TRUE + 1) /* this is a modified version of sim_brk_test with two differences: - 1) is does not set sim_brk_pend to FALSE (this if left to the instruction decode) + 1) is does not set sim_brk_pend to FALSE (this is left to the instruction decode) 2) it returns MASK_BRK if a breakpoint is found but should be ignored */ static int32 sim_brk_lookup (const t_addr loc, const int32 btyp) { - extern t_bool sim_brk_pend; - extern t_addr sim_brk_ploc; + extern t_bool sim_brk_pend[SIM_BKPT_N_SPC]; + extern t_addr sim_brk_ploc[SIM_BKPT_N_SPC]; extern char *sim_brk_act; BRKTAB *bp; - if ((bp = sim_brk_fnd (loc)) && /* entry in table? */ - (btyp & bp -> typ) && /* type match? */ - (!sim_brk_pend || (loc != sim_brk_ploc)) && /* new location? */ - (--(bp -> cnt) <= 0)) { /* count reach 0? */ - bp -> cnt = 0; /* reset count */ - sim_brk_ploc = loc; /* save location */ - sim_brk_act = bp -> act; /* set up actions */ - sim_brk_pend = TRUE; /* don't do twice */ + if ((bp = sim_brk_fnd (loc)) && /* entry in table? */ + (btyp & bp -> typ) && /* type match? */ + (!sim_brk_pend[0] || (loc != sim_brk_ploc[0])) && /* new location? */ + (--(bp -> cnt) <= 0)) { /* count reach 0? */ + bp -> cnt = 0; /* reset count */ + sim_brk_ploc[0] = loc; /* save location */ + sim_brk_act = bp -> act; /* set up actions */ + sim_brk_pend[0] = TRUE; /* don't do twice */ return TRUE; } - return (sim_brk_pend && (loc == sim_brk_ploc)) ? MASK_BRK : FALSE; + return (sim_brk_pend[0] && (loc == sim_brk_ploc[0])) ? MASK_BRK : FALSE; } static void prepareMemoryAccessMessage(t_addr loc) { @@ -1703,7 +1716,7 @@ static void prepareMemoryAccessMessage(t_addr loc) { br1 = sim_brk_lookup(a1, SWMASK('M')); \ br2 = br1 ? FALSE : sim_brk_lookup(a2, SWMASK('M')); \ if ((br1 == MASK_BRK) || (br2 == MASK_BRK)) { \ - sim_brk_pend = FALSE; \ + sim_brk_pend[0] = FALSE; \ } \ else if (br1 || br2) { \ reason = STOP_MEM; \ @@ -1717,7 +1730,7 @@ static void prepareMemoryAccessMessage(t_addr loc) { goto end_decode; \ } \ else { \ - sim_brk_pend = FALSE; \ + sim_brk_pend[0] = FALSE; \ } \ } @@ -1727,7 +1740,7 @@ static void prepareMemoryAccessMessage(t_addr loc) { t_stat sim_instr (void) { extern int32 sim_interval; - extern t_bool sim_brk_pend; + extern t_bool sim_brk_pend[SIM_BKPT_N_SPC]; extern int32 timerInterrupt; extern int32 timerInterruptHandler; extern uint32 sim_os_msec(void); @@ -1829,12 +1842,12 @@ t_stat sim_instr (void) { case 0x00: /* NOP */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; break; case 0x01: /* LD BC,nnnn */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = GetWORD(PC); PC += 2; break; @@ -1847,13 +1860,13 @@ t_stat sim_instr (void) { case 0x03: /* INC BC */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++BC; break; case 0x04: /* INC B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC += 0x100; temp = hreg(BC); AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */ @@ -1861,7 +1874,7 @@ t_stat sim_instr (void) { case 0x05: /* DEC B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC -= 0x100; temp = hreg(BC); AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */ @@ -1869,20 +1882,20 @@ t_stat sim_instr (void) { case 0x06: /* LD B,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(BC, RAM_pp(PC)); break; case 0x07: /* RLCA */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = ((AF >> 7) & 0x0128) | ((AF << 1) & ~0x1ff) | (AF & 0xc4) | ((AF >> 15) & 1); break; case 0x08: /* EX AF,AF' */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; temp = AF; AF = AF1_S; @@ -1891,7 +1904,7 @@ t_stat sim_instr (void) { case 0x09: /* ADD HL,BC */ tStates += 11; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; BC &= ADDRMASK; sum = HL + BC; @@ -1907,13 +1920,13 @@ t_stat sim_instr (void) { case 0x0b: /* DEC BC */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; --BC; break; case 0x0c: /* INC C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(BC) + 1; Setlreg(BC, temp); AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); @@ -1921,7 +1934,7 @@ t_stat sim_instr (void) { case 0x0d: /* DEC C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(BC) - 1; Setlreg(BC, temp); AF = (AF & ~0xfe) | decTable[temp & 0xff] | SetPV2(0x7f); @@ -1929,18 +1942,18 @@ t_stat sim_instr (void) { case 0x0e: /* LD C,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(BC, RAM_pp(PC)); break; case 0x0f: /* RRCA */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0xc4) | rrcaTable[hreg(AF)]; break; case 0x10: /* DJNZ dd */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; if ((BC -= 0x100) & 0xff00) { PCQ_ENTRY(PC - 1); @@ -1955,7 +1968,7 @@ t_stat sim_instr (void) { case 0x11: /* LD DE,nnnn */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = GetWORD(PC); PC += 2; break; @@ -1968,13 +1981,13 @@ t_stat sim_instr (void) { case 0x13: /* INC DE */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++DE; break; case 0x14: /* INC D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE += 0x100; temp = hreg(DE); AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */ @@ -1982,7 +1995,7 @@ t_stat sim_instr (void) { case 0x15: /* DEC D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE -= 0x100; temp = hreg(DE); AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */ @@ -1990,20 +2003,20 @@ t_stat sim_instr (void) { case 0x16: /* LD D,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(DE, RAM_pp(PC)); break; case 0x17: /* RLA */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = ((AF << 8) & 0x0100) | ((AF >> 7) & 0x28) | ((AF << 1) & ~0x01ff) | (AF & 0xc4) | ((AF >> 15) & 1); break; case 0x18: /* JR dd */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; PCQ_ENTRY(PC - 1); PC += (int8) GetBYTE(PC) + 1; @@ -2011,7 +2024,7 @@ t_stat sim_instr (void) { case 0x19: /* ADD HL,DE */ tStates += 11; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; DE &= ADDRMASK; sum = HL + DE; @@ -2027,13 +2040,13 @@ t_stat sim_instr (void) { case 0x1b: /* DEC DE */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; --DE; break; case 0x1c: /* INC E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(DE) + 1; Setlreg(DE, temp); AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); @@ -2041,7 +2054,7 @@ t_stat sim_instr (void) { case 0x1d: /* DEC E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(DE) - 1; Setlreg(DE, temp); AF = (AF & ~0xfe) | decTable[temp & 0xff] | SetPV2(0x7f); @@ -2049,18 +2062,18 @@ t_stat sim_instr (void) { case 0x1e: /* LD E,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(DE, RAM_pp(PC)); break; case 0x1f: /* RRA */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = ((AF & 1) << 15) | (AF & 0xc4) | rraTable[hreg(AF)]; break; case 0x20: /* JR NZ,dd */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; if (TSTFLAG(Z)) { PC++; @@ -2075,7 +2088,7 @@ t_stat sim_instr (void) { case 0x21: /* LD HL,nnnn */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = GetWORD(PC); PC += 2; break; @@ -2090,13 +2103,13 @@ t_stat sim_instr (void) { case 0x23: /* INC HL */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++HL; break; case 0x24: /* INC H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL += 0x100; temp = hreg(HL); AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */ @@ -2104,7 +2117,7 @@ t_stat sim_instr (void) { case 0x25: /* DEC H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL -= 0x100; temp = hreg(HL); AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */ @@ -2112,13 +2125,13 @@ t_stat sim_instr (void) { case 0x26: /* LD H,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(HL, RAM_pp(PC)); break; case 0x27: /* DAA */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; acu = hreg(AF); temp = ldig(acu); cbits = TSTFLAG(C); @@ -2148,7 +2161,7 @@ t_stat sim_instr (void) { break; case 0x28: /* JR Z,dd */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; if (TSTFLAG(Z)) { PCQ_ENTRY(PC - 1); @@ -2163,7 +2176,7 @@ t_stat sim_instr (void) { case 0x29: /* ADD HL,HL */ tStates += 11; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; sum = HL + HL; AF = (AF & ~0x3b) | cbitsDup16Table[sum >> 8]; @@ -2180,13 +2193,13 @@ t_stat sim_instr (void) { case 0x2b: /* DEC HL */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; --HL; break; case 0x2c: /* INC L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(HL) + 1; Setlreg(HL, temp); AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); @@ -2194,7 +2207,7 @@ t_stat sim_instr (void) { case 0x2d: /* DEC L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(HL) - 1; Setlreg(HL, temp); AF = (AF & ~0xfe) | decTable[temp & 0xff] | SetPV2(0x7f); @@ -2202,18 +2215,18 @@ t_stat sim_instr (void) { case 0x2e: /* LD L,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(HL, RAM_pp(PC)); break; case 0x2f: /* CPL */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (~AF & ~0xff) | (AF & 0xc5) | ((~AF >> 8) & 0x28) | 0x12; break; case 0x30: /* JR NC,dd */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; if (TSTFLAG(C)) { PC++; @@ -2228,7 +2241,7 @@ t_stat sim_instr (void) { case 0x31: /* LD SP,nnnn */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; SP = GetWORD(PC); PC += 2; break; @@ -2243,7 +2256,7 @@ t_stat sim_instr (void) { case 0x33: /* INC SP */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++SP; break; @@ -2271,12 +2284,12 @@ t_stat sim_instr (void) { case 0x37: /* SCF */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & ~0x3b) | ((AF >> 8) & 0x28) | 1; break; case 0x38: /* JR C,dd */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; if (TSTFLAG(C)) { PCQ_ENTRY(PC - 1); @@ -2291,7 +2304,7 @@ t_stat sim_instr (void) { case 0x39: /* ADD HL,SP */ tStates += 11; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; SP &= ADDRMASK; sum = HL + SP; @@ -2309,13 +2322,13 @@ t_stat sim_instr (void) { case 0x3b: /* DEC SP */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; --SP; break; case 0x3c: /* INC A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF += 0x100; temp = hreg(AF); AF = (AF & ~0xfe) | incTable[temp] | SetPV2(0x80); /* SetPV2 uses temp */ @@ -2323,7 +2336,7 @@ t_stat sim_instr (void) { case 0x3d: /* DEC A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF -= 0x100; temp = hreg(AF); AF = (AF & ~0xfe) | decTable[temp] | SetPV2(0x7f); /* SetPV2 uses temp */ @@ -2331,48 +2344,48 @@ t_stat sim_instr (void) { case 0x3e: /* LD A,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(AF, RAM_pp(PC)); break; case 0x3f: /* CCF */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & ~0x3b) | ((AF >> 8) & 0x28) | ((AF & 1) << 4) | (~AF & 1); break; case 0x40: /* LD B,B */ tStates += 4; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x41: /* LD B,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & 0xff) | ((BC & 0xff) << 8); break; case 0x42: /* LD B,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & 0xff) | (DE & ~0xff); break; case 0x43: /* LD B,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & 0xff) | ((DE & 0xff) << 8); break; case 0x44: /* LD B,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & 0xff) | (HL & ~0xff); break; case 0x45: /* LD B,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & 0xff) | ((HL & 0xff) << 8); break; @@ -2384,42 +2397,42 @@ t_stat sim_instr (void) { case 0x47: /* LD B,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & 0xff) | (AF & ~0xff); break; case 0x48: /* LD C,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & ~0xff) | ((BC >> 8) & 0xff); break; case 0x49: /* LD C,C */ tStates += 4; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x4a: /* LD C,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & ~0xff) | ((DE >> 8) & 0xff); break; case 0x4b: /* LD C,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & ~0xff) | (DE & 0xff); break; case 0x4c: /* LD C,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & ~0xff) | ((HL >> 8) & 0xff); break; case 0x4d: /* LD C,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & ~0xff) | (HL & 0xff); break; @@ -2431,42 +2444,42 @@ t_stat sim_instr (void) { case 0x4f: /* LD C,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; BC = (BC & ~0xff) | ((AF >> 8) & 0xff); break; case 0x50: /* LD D,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & 0xff) | (BC & ~0xff); break; case 0x51: /* LD D,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & 0xff) | ((BC & 0xff) << 8); break; case 0x52: /* LD D,D */ tStates += 4; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x53: /* LD D,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & 0xff) | ((DE & 0xff) << 8); break; case 0x54: /* LD D,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & 0xff) | (HL & ~0xff); break; case 0x55: /* LD D,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & 0xff) | ((HL & 0xff) << 8); break; @@ -2478,42 +2491,42 @@ t_stat sim_instr (void) { case 0x57: /* LD D,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & 0xff) | (AF & ~0xff); break; case 0x58: /* LD E,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & ~0xff) | ((BC >> 8) & 0xff); break; case 0x59: /* LD E,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & ~0xff) | (BC & 0xff); break; case 0x5a: /* LD E,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & ~0xff) | ((DE >> 8) & 0xff); break; case 0x5b: /* LD E,E */ tStates += 4; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x5c: /* LD E,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & ~0xff) | ((HL >> 8) & 0xff); break; case 0x5d: /* LD E,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & ~0xff) | (HL & 0xff); break; @@ -2525,42 +2538,42 @@ t_stat sim_instr (void) { case 0x5f: /* LD E,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; DE = (DE & ~0xff) | ((AF >> 8) & 0xff); break; case 0x60: /* LD H,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & 0xff) | (BC & ~0xff); break; case 0x61: /* LD H,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & 0xff) | ((BC & 0xff) << 8); break; case 0x62: /* LD H,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & 0xff) | (DE & ~0xff); break; case 0x63: /* LD H,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & 0xff) | ((DE & 0xff) << 8); break; case 0x64: /* LD H,H */ tStates += 4; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x65: /* LD H,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & 0xff) | ((HL & 0xff) << 8); break; @@ -2572,43 +2585,43 @@ t_stat sim_instr (void) { case 0x67: /* LD H,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & 0xff) | (AF & ~0xff); break; case 0x68: /* LD L,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & ~0xff) | ((BC >> 8) & 0xff); break; case 0x69: /* LD L,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & ~0xff) | (BC & 0xff); break; case 0x6a: /* LD L,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & ~0xff) | ((DE >> 8) & 0xff); break; case 0x6b: /* LD L,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & ~0xff) | (DE & 0xff); break; case 0x6c: /* LD L,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & ~0xff) | ((HL >> 8) & 0xff); break; case 0x6d: /* LD L,L */ tStates += 4; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x6e: /* LD L,(HL) */ @@ -2619,7 +2632,7 @@ t_stat sim_instr (void) { case 0x6f: /* LD L,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL = (HL & ~0xff) | ((AF >> 8) & 0xff); break; @@ -2661,7 +2674,7 @@ t_stat sim_instr (void) { case 0x76: /* HALT */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; reason = STOP_HALT; PC--; goto end_decode; @@ -2674,37 +2687,37 @@ t_stat sim_instr (void) { case 0x78: /* LD A,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0xff) | (BC & ~0xff); break; case 0x79: /* LD A,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0xff) | ((BC & 0xff) << 8); break; case 0x7a: /* LD A,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0xff) | (DE & ~0xff); break; case 0x7b: /* LD A,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0xff) | ((DE & 0xff) << 8); break; case 0x7c: /* LD A,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0xff) | (HL & ~0xff); break; case 0x7d: /* LD A,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0xff) | ((HL & 0xff) << 8); break; @@ -2716,12 +2729,12 @@ t_stat sim_instr (void) { case 0x7f: /* LD A,A */ tStates += 4; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x80: /* ADD A,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(BC); acu = hreg(AF); sum = acu + temp; @@ -2731,7 +2744,7 @@ t_stat sim_instr (void) { case 0x81: /* ADD A,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(BC); acu = hreg(AF); sum = acu + temp; @@ -2741,7 +2754,7 @@ t_stat sim_instr (void) { case 0x82: /* ADD A,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(DE); acu = hreg(AF); sum = acu + temp; @@ -2751,7 +2764,7 @@ t_stat sim_instr (void) { case 0x83: /* ADD A,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(DE); acu = hreg(AF); sum = acu + temp; @@ -2761,7 +2774,7 @@ t_stat sim_instr (void) { case 0x84: /* ADD A,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(HL); acu = hreg(AF); sum = acu + temp; @@ -2771,7 +2784,7 @@ t_stat sim_instr (void) { case 0x85: /* ADD A,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(HL); acu = hreg(AF); sum = acu + temp; @@ -2791,14 +2804,14 @@ t_stat sim_instr (void) { case 0x87: /* ADD A,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; cbits = 2 * hreg(AF); AF = cbitsDup8Table[cbits] | (SetPVS(cbits)); break; case 0x88: /* ADC A,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(BC); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -2808,7 +2821,7 @@ t_stat sim_instr (void) { case 0x89: /* ADC A,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(BC); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -2818,7 +2831,7 @@ t_stat sim_instr (void) { case 0x8a: /* ADC A,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(DE); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -2828,7 +2841,7 @@ t_stat sim_instr (void) { case 0x8b: /* ADC A,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(DE); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -2838,7 +2851,7 @@ t_stat sim_instr (void) { case 0x8c: /* ADC A,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(HL); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -2848,7 +2861,7 @@ t_stat sim_instr (void) { case 0x8d: /* ADC A,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(HL); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -2868,14 +2881,14 @@ t_stat sim_instr (void) { case 0x8f: /* ADC A,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; cbits = 2 * hreg(AF) + TSTFLAG(C); AF = cbitsDup8Table[cbits] | (SetPVS(cbits)); break; case 0x90: /* SUB B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(BC); acu = hreg(AF); sum = acu - temp; @@ -2885,7 +2898,7 @@ t_stat sim_instr (void) { case 0x91: /* SUB C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(BC); acu = hreg(AF); sum = acu - temp; @@ -2895,7 +2908,7 @@ t_stat sim_instr (void) { case 0x92: /* SUB D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(DE); acu = hreg(AF); sum = acu - temp; @@ -2905,7 +2918,7 @@ t_stat sim_instr (void) { case 0x93: /* SUB E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(DE); acu = hreg(AF); sum = acu - temp; @@ -2915,7 +2928,7 @@ t_stat sim_instr (void) { case 0x94: /* SUB H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(HL); acu = hreg(AF); sum = acu - temp; @@ -2925,7 +2938,7 @@ t_stat sim_instr (void) { case 0x95: /* SUB L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(HL); acu = hreg(AF); sum = acu - temp; @@ -2945,13 +2958,13 @@ t_stat sim_instr (void) { case 0x97: /* SUB A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = cpu_unit.flags & UNIT_CHIP ? 0x42 : 0x46; break; case 0x98: /* SBC A,B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(BC); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -2961,7 +2974,7 @@ t_stat sim_instr (void) { case 0x99: /* SBC A,C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(BC); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -2971,7 +2984,7 @@ t_stat sim_instr (void) { case 0x9a: /* SBC A,D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(DE); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -2981,7 +2994,7 @@ t_stat sim_instr (void) { case 0x9b: /* SBC A,E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(DE); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -2991,7 +3004,7 @@ t_stat sim_instr (void) { case 0x9c: /* SBC A,H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(HL); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -3001,7 +3014,7 @@ t_stat sim_instr (void) { case 0x9d: /* SBC A,L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(HL); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -3021,44 +3034,44 @@ t_stat sim_instr (void) { case 0x9f: /* SBC A,A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; cbits = -TSTFLAG(C); AF = subTable[cbits & 0xff] | cbitsTable[cbits & 0x1ff] | (SetPVS(cbits)); break; case 0xa0: /* AND B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF & BC) >> 8) & 0xff]; break; case 0xa1: /* AND C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF >> 8) & BC) & 0xff]; break; case 0xa2: /* AND D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF & DE) >> 8) & 0xff]; break; case 0xa3: /* AND E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF >> 8) & DE) & 0xff]; break; case 0xa4: /* AND H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF & HL) >> 8) & 0xff]; break; case 0xa5: /* AND L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF >> 8) & HL) & 0xff]; break; @@ -3070,43 +3083,43 @@ t_stat sim_instr (void) { case 0xa7: /* AND A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[(AF >> 8) & 0xff]; break; case 0xa8: /* XOR B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF ^ BC) >> 8) & 0xff]; break; case 0xa9: /* XOR C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) ^ BC) & 0xff]; break; case 0xaa: /* XOR D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF ^ DE) >> 8) & 0xff]; break; case 0xab: /* XOR E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) ^ DE) & 0xff]; break; case 0xac: /* XOR H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF ^ HL) >> 8) & 0xff]; break; case 0xad: /* XOR L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) ^ HL) & 0xff]; break; @@ -3118,43 +3131,43 @@ t_stat sim_instr (void) { case 0xaf: /* XOR A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = 0x44; break; case 0xb0: /* OR B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF | BC) >> 8) & 0xff]; break; case 0xb1: /* OR C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) | BC) & 0xff]; break; case 0xb2: /* OR D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF | DE) >> 8) & 0xff]; break; case 0xb3: /* OR E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) | DE) & 0xff]; break; case 0xb4: /* OR H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF | HL) >> 8) & 0xff]; break; case 0xb5: /* OR L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) | HL) & 0xff]; break; @@ -3166,13 +3179,13 @@ t_stat sim_instr (void) { case 0xb7: /* OR A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[(AF >> 8) & 0xff]; break; case 0xb8: /* CP B */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(BC); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -3184,7 +3197,7 @@ t_stat sim_instr (void) { case 0xb9: /* CP C */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(BC); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -3196,7 +3209,7 @@ t_stat sim_instr (void) { case 0xba: /* CP D */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(DE); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -3208,7 +3221,7 @@ t_stat sim_instr (void) { case 0xbb: /* CP E */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(DE); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -3220,7 +3233,7 @@ t_stat sim_instr (void) { case 0xbc: /* CP H */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(HL); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -3232,7 +3245,7 @@ t_stat sim_instr (void) { case 0xbd: /* CP L */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(HL); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -3256,13 +3269,13 @@ t_stat sim_instr (void) { case 0xbf: /* CP A */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(AF, (hreg(AF) & 0x28) | (cpu_unit.flags & UNIT_CHIP ? 0x42 : 0x46)); break; case 0xc0: /* RET NZ */ if (TSTFLAG(Z)) { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } else { @@ -3280,12 +3293,12 @@ t_stat sim_instr (void) { break; case 0xc2: /* JP NZ,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(!TSTFLAG(Z)); /* also updates tStates */ break; case 0xc3: /* JP nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(1); /* also updates tStates */ break; @@ -3301,7 +3314,7 @@ t_stat sim_instr (void) { case 0xc6: /* ADD A,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = RAM_pp(PC); acu = hreg(AF); sum = acu + temp; @@ -3325,7 +3338,7 @@ t_stat sim_instr (void) { tStates += 11; } else { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } break; @@ -3338,7 +3351,7 @@ t_stat sim_instr (void) { break; case 0xca: /* JP Z,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(TSTFLAG(Z)); /* also updates tStates */ break; @@ -3348,42 +3361,42 @@ t_stat sim_instr (void) { switch ((op = GetBYTE(PC)) & 7) { case 0: - sim_brk_pend = tStateModifier = FALSE; + sim_brk_pend[0] = tStateModifier = FALSE; ++PC; acu = hreg(BC); tStates += 8; break; case 1: - sim_brk_pend = tStateModifier = FALSE; + sim_brk_pend[0] = tStateModifier = FALSE; ++PC; acu = lreg(BC); tStates += 8; break; case 2: - sim_brk_pend = tStateModifier = FALSE; + sim_brk_pend[0] = tStateModifier = FALSE; ++PC; acu = hreg(DE); tStates += 8; break; case 3: - sim_brk_pend = tStateModifier = FALSE; + sim_brk_pend[0] = tStateModifier = FALSE; ++PC; acu = lreg(DE); tStates += 8; break; case 4: - sim_brk_pend = tStateModifier = FALSE; + sim_brk_pend[0] = tStateModifier = FALSE; ++PC; acu = hreg(HL); tStates += 8; break; case 5: - sim_brk_pend = tStateModifier = FALSE; + sim_brk_pend[0] = tStateModifier = FALSE; ++PC; acu = lreg(HL); tStates += 8; @@ -3398,7 +3411,7 @@ t_stat sim_instr (void) { break; case 7: - sim_brk_pend = tStateModifier = FALSE; + sim_brk_pend[0] = tStateModifier = FALSE; ++PC; acu = hreg(AF); tStates += 8; @@ -3523,7 +3536,7 @@ t_stat sim_instr (void) { case 0xce: /* ADC A,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = RAM_pp(PC); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -3541,7 +3554,7 @@ t_stat sim_instr (void) { case 0xd0: /* RET NC */ if (TSTFLAG(C)) { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } else { @@ -3559,13 +3572,13 @@ t_stat sim_instr (void) { break; case 0xd2: /* JP NC,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(!TSTFLAG(C)); /* also updates tStates */ break; case 0xd3: /* OUT (nn),A */ tStates += 11; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(RAM_pp(PC), hreg(AF)); break; @@ -3581,7 +3594,7 @@ t_stat sim_instr (void) { case 0xd6: /* SUB nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = RAM_pp(PC); acu = hreg(AF); sum = acu - temp; @@ -3605,14 +3618,14 @@ t_stat sim_instr (void) { tStates += 11; } else { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } break; case 0xd9: /* EXX */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPU8080; temp = BC; BC = BC1_S; @@ -3626,13 +3639,13 @@ t_stat sim_instr (void) { break; case 0xda: /* JP C,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(TSTFLAG(C)); /* also updates tStates */ break; case 0xdb: /* IN A,(nn) */ tStates += 11; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(AF, in(RAM_pp(PC))); break; @@ -3646,7 +3659,7 @@ t_stat sim_instr (void) { case 0x09: /* ADD IX,BC */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IX &= ADDRMASK; BC &= ADDRMASK; sum = IX + BC; @@ -3656,7 +3669,7 @@ t_stat sim_instr (void) { case 0x19: /* ADD IX,DE */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IX &= ADDRMASK; DE &= ADDRMASK; sum = IX + DE; @@ -3666,7 +3679,7 @@ t_stat sim_instr (void) { case 0x21: /* LD IX,nnnn */ tStates += 14; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IX = GetWORD(PC); PC += 2; break; @@ -3681,33 +3694,33 @@ t_stat sim_instr (void) { case 0x23: /* INC IX */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++IX; break; case 0x24: /* INC IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IX += 0x100; AF = (AF & ~0xfe) | incZ80Table[hreg(IX)]; break; case 0x25: /* DEC IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IX -= 0x100; AF = (AF & ~0xfe) | decZ80Table[hreg(IX)]; break; case 0x26: /* LD IXH,nn */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IX, RAM_pp(PC)); break; case 0x29: /* ADD IX,IX */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IX &= ADDRMASK; sum = IX + IX; AF = (AF & ~0x3b) | cbitsDup16Table[sum >> 8]; @@ -3724,13 +3737,13 @@ t_stat sim_instr (void) { case 0x2b: /* DEC IX */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; --IX; break; case 0x2c: /* INC IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IX) + 1; Setlreg(IX, temp); AF = (AF & ~0xfe) | incZ80Table[temp]; @@ -3738,7 +3751,7 @@ t_stat sim_instr (void) { case 0x2d: /* DEC IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IX) - 1; Setlreg(IX, temp); AF = (AF & ~0xfe) | decZ80Table[temp & 0xff]; @@ -3746,7 +3759,7 @@ t_stat sim_instr (void) { case 0x2e: /* LD IXL,nn */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IX, RAM_pp(PC)); break; @@ -3777,7 +3790,7 @@ t_stat sim_instr (void) { case 0x39: /* ADD IX,SP */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IX &= ADDRMASK; SP &= ADDRMASK; sum = IX + SP; @@ -3787,13 +3800,13 @@ t_stat sim_instr (void) { case 0x44: /* LD B,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(BC, hreg(IX)); break; case 0x45: /* LD B,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(BC, lreg(IX)); break; @@ -3806,13 +3819,13 @@ t_stat sim_instr (void) { case 0x4c: /* LD C,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(BC, hreg(IX)); break; case 0x4d: /* LD C,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(BC, lreg(IX)); break; @@ -3825,13 +3838,13 @@ t_stat sim_instr (void) { case 0x54: /* LD D,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(DE, hreg(IX)); break; case 0x55: /* LD D,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(DE, lreg(IX)); break; @@ -3844,13 +3857,13 @@ t_stat sim_instr (void) { case 0x5c: /* LD E,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(DE, hreg(IX)); break; case 0x5d: /* LD E,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(DE, lreg(IX)); break; @@ -3863,36 +3876,36 @@ t_stat sim_instr (void) { case 0x60: /* LD IXH,B */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IX, hreg(BC)); break; case 0x61: /* LD IXH,C */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IX, lreg(BC)); break; case 0x62: /* LD IXH,D */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IX, hreg(DE)); break; case 0x63: /* LD IXH,E */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IX, lreg(DE)); break; case 0x64: /* LD IXH,IXH */ tStates += 9; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x65: /* LD IXH,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IX, lreg(IX)); break; @@ -3905,43 +3918,43 @@ t_stat sim_instr (void) { case 0x67: /* LD IXH,A */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IX, hreg(AF)); break; case 0x68: /* LD IXL,B */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IX, hreg(BC)); break; case 0x69: /* LD IXL,C */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IX, lreg(BC)); break; case 0x6a: /* LD IXL,D */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IX, hreg(DE)); break; case 0x6b: /* LD IXL,E */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IX, lreg(DE)); break; case 0x6c: /* LD IXL,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IX, hreg(IX)); break; case 0x6d: /* LD IXL,IXL */ tStates += 9; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x6e: /* LD L,(IX+dd) */ @@ -3953,7 +3966,7 @@ t_stat sim_instr (void) { case 0x6f: /* LD IXL,A */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IX, hreg(AF)); break; @@ -4008,13 +4021,13 @@ t_stat sim_instr (void) { case 0x7c: /* LD A,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(AF, hreg(IX)); break; case 0x7d: /* LD A,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(AF, lreg(IX)); break; @@ -4027,7 +4040,7 @@ t_stat sim_instr (void) { case 0x84: /* ADD A,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IX); acu = hreg(AF); sum = acu + temp; @@ -4036,7 +4049,7 @@ t_stat sim_instr (void) { case 0x85: /* ADD A,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IX); acu = hreg(AF); sum = acu + temp; @@ -4055,7 +4068,7 @@ t_stat sim_instr (void) { case 0x8c: /* ADC A,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IX); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -4064,7 +4077,7 @@ t_stat sim_instr (void) { case 0x8d: /* ADC A,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IX); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -4096,7 +4109,7 @@ t_stat sim_instr (void) { case 0x9c: /* SBC A,IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IX); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -4108,7 +4121,7 @@ t_stat sim_instr (void) { case 0x9d: /* SBC A,IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IX); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -4127,13 +4140,13 @@ t_stat sim_instr (void) { case 0xa4: /* AND IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF & IX) >> 8) & 0xff]; break; case 0xa5: /* AND IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF >> 8) & IX) & 0xff]; break; @@ -4146,13 +4159,13 @@ t_stat sim_instr (void) { case 0xac: /* XOR IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF ^ IX) >> 8) & 0xff]; break; case 0xad: /* XOR IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) ^ IX) & 0xff]; break; @@ -4165,13 +4178,13 @@ t_stat sim_instr (void) { case 0xb4: /* OR IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF | IX) >> 8) & 0xff]; break; case 0xb5: /* OR IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) | IX) & 0xff]; break; @@ -4184,7 +4197,7 @@ t_stat sim_instr (void) { case 0xbc: /* CP IXH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IX); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -4195,7 +4208,7 @@ t_stat sim_instr (void) { case 0xbd: /* CP IXL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IX); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -4221,37 +4234,37 @@ t_stat sim_instr (void) { switch ((op = GetBYTE(PC)) & 7) { case 0: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(BC); break; case 1: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = lreg(BC); break; case 2: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(DE); break; case 3: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = lreg(DE); break; case 4: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(HL); break; case 5: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = lreg(HL); break; @@ -4263,7 +4276,7 @@ t_stat sim_instr (void) { break; case 7: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(AF); break; @@ -4399,19 +4412,19 @@ t_stat sim_instr (void) { case 0xe9: /* JP (IX) */ tStates += 8; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; PCQ_ENTRY(PC - 2); PC = IX; break; case 0xf9: /* LD SP,IX */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; SP = IX; break; default: /* ignore DD */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPUZ80; PC--; } @@ -4419,7 +4432,7 @@ t_stat sim_instr (void) { case 0xde: /* SBC A,nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = RAM_pp(PC); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -4437,7 +4450,7 @@ t_stat sim_instr (void) { case 0xe0: /* RET PO */ if (TSTFLAG(P)) { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } else { @@ -4455,7 +4468,7 @@ t_stat sim_instr (void) { break; case 0xe2: /* JP PO,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(!TSTFLAG(P)); /* also updates tStates */ break; @@ -4479,7 +4492,7 @@ t_stat sim_instr (void) { case 0xe6: /* AND nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF >> 8) & RAM_pp(PC)) & 0xff]; break; @@ -4499,26 +4512,26 @@ t_stat sim_instr (void) { tStates += 11; } else { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } break; case 0xe9: /* JP (HL) */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; PCQ_ENTRY(PC - 1); PC = HL; break; case 0xea: /* JP PE,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(TSTFLAG(P)); /* also updates tStates */ break; case 0xeb: /* EX DE,HL */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = HL; HL = DE; DE = temp; @@ -4534,7 +4547,7 @@ t_stat sim_instr (void) { case 0x40: /* IN B,(C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Sethreg(BC, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4542,13 +4555,13 @@ t_stat sim_instr (void) { case 0x41: /* OUT (C),B */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), hreg(BC)); break; case 0x42: /* SBC HL,BC */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; BC &= ADDRMASK; sum = HL - BC - TSTFLAG(C); @@ -4581,7 +4594,7 @@ t_stat sim_instr (void) { case 0x7C: /* NEG, unofficial */ tStates += 8; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(AF); AF = ((~(AF & 0xff00) + 1) & 0xff00); /* AF = (-(AF & 0xff00) & 0xff00); */ AF |= ((AF >> 8) & 0xa8) | (((AF & 0xff00) == 0) << 6) | negTable[temp]; @@ -4609,19 +4622,19 @@ t_stat sim_instr (void) { case 0x46: /* IM 0 */ tStates += 8; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; /* interrupt mode 0 */ break; case 0x47: /* LD I,A */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IR_S = (IR_S & 0xff) | (AF & ~0xff); break; case 0x48: /* IN C,(C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Setlreg(BC, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4629,13 +4642,13 @@ t_stat sim_instr (void) { case 0x49: /* OUT (C),C */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), lreg(BC)); break; case 0x4a: /* ADC HL,BC */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; BC &= ADDRMASK; sum = HL + BC + TSTFLAG(C); @@ -4662,13 +4675,13 @@ t_stat sim_instr (void) { case 0x4f: /* LD R,A */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IR_S = (IR_S & ~0xff) | ((AF >> 8) & 0xff); break; case 0x50: /* IN D,(C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Sethreg(DE, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4676,13 +4689,13 @@ t_stat sim_instr (void) { case 0x51: /* OUT (C),D */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), hreg(DE)); break; case 0x52: /* SBC HL,DE */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; DE &= ADDRMASK; sum = HL - DE - TSTFLAG(C); @@ -4701,19 +4714,19 @@ t_stat sim_instr (void) { case 0x56: /* IM 1 */ tStates += 8; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; /* interrupt mode 1 */ break; case 0x57: /* LD A,I */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0x29) | (IR_S & ~0xff) | ((IR_S >> 8) & 0x80) | (((IR_S & ~0xff) == 0) << 6) | ((IFF_S & 2) << 1); break; case 0x58: /* IN E,(C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Setlreg(DE, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4721,13 +4734,13 @@ t_stat sim_instr (void) { case 0x59: /* OUT (C),E */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), lreg(DE)); break; case 0x5a: /* ADC HL,DE */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; DE &= ADDRMASK; sum = HL + DE + TSTFLAG(C); @@ -4746,20 +4759,20 @@ t_stat sim_instr (void) { case 0x5e: /* IM 2 */ tStates += 8; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; /* interrupt mode 2 */ break; case 0x5f: /* LD A,R */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = (AF & 0x29) | ((IR_S & 0xff) << 8) | (IR_S & 0x80) | (((IR_S & 0xff) == 0) << 6) | ((IFF_S & 2) << 1); break; case 0x60: /* IN H,(C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Sethreg(HL, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4767,13 +4780,13 @@ t_stat sim_instr (void) { case 0x61: /* OUT (C),H */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), hreg(HL)); break; case 0x62: /* SBC HL,HL */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; sum = HL - HL - TSTFLAG(C); AF = (AF & ~0xff) | (((sum & ADDRMASK) == 0) << 6) | @@ -4791,7 +4804,7 @@ t_stat sim_instr (void) { case 0x67: /* RRD */ tStates += 18; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = GetBYTE(HL); acu = hreg(AF); PutBYTE(HL, hdig(temp) | (ldig(acu) << 4)); @@ -4800,7 +4813,7 @@ t_stat sim_instr (void) { case 0x68: /* IN L,(C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Setlreg(HL, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4808,13 +4821,13 @@ t_stat sim_instr (void) { case 0x69: /* OUT (C),L */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), lreg(HL)); break; case 0x6a: /* ADC HL,HL */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; sum = HL + HL + TSTFLAG(C); AF = (AF & ~0xff) | (((sum & ADDRMASK) == 0) << 6) | @@ -4832,7 +4845,7 @@ t_stat sim_instr (void) { case 0x6f: /* RLD */ tStates += 18; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = GetBYTE(HL); acu = hreg(AF); PutBYTE(HL, (ldig(temp) << 4) | ldig(acu)); @@ -4841,7 +4854,7 @@ t_stat sim_instr (void) { case 0x70: /* IN (C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Setlreg(temp, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4849,13 +4862,13 @@ t_stat sim_instr (void) { case 0x71: /* OUT (C),0 */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), 0); break; case 0x72: /* SBC HL,SP */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; SP &= ADDRMASK; sum = HL - SP - TSTFLAG(C); @@ -4874,7 +4887,7 @@ t_stat sim_instr (void) { case 0x78: /* IN A,(C) */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = in(lreg(BC)); Sethreg(AF, temp); AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff]; @@ -4882,13 +4895,13 @@ t_stat sim_instr (void) { case 0x79: /* OUT (C),A */ tStates += 12; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; out(lreg(BC), hreg(AF)); break; case 0x7a: /* ADC HL,SP */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; HL &= ADDRMASK; SP &= ADDRMASK; sum = HL + SP + TSTFLAG(C); @@ -5122,14 +5135,14 @@ t_stat sim_instr (void) { break; default: /* ignore ED and following byte */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPUZ80; } break; case 0xee: /* XOR nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) ^ RAM_pp(PC)) & 0xff]; break; @@ -5143,7 +5156,7 @@ t_stat sim_instr (void) { case 0xf0: /* RET P */ if (TSTFLAG(S)) { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } else { @@ -5161,13 +5174,13 @@ t_stat sim_instr (void) { break; case 0xf2: /* JP P,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(!TSTFLAG(S)); /* also updates tStates */ break; case 0xf3: /* DI */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IFF_S = 0; break; @@ -5183,7 +5196,7 @@ t_stat sim_instr (void) { case 0xf6: /* OR nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) | RAM_pp(PC)) & 0xff]; break; @@ -5203,25 +5216,25 @@ t_stat sim_instr (void) { tStates += 11; } else { - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; tStates += 5; } break; case 0xf9: /* LD SP,HL */ tStates += 6; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; SP = HL; break; case 0xfa: /* JP M,nnnn */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; JPC(TSTFLAG(S)); /* also updates tStates */ break; case 0xfb: /* EI */ tStates += 4; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IFF_S = 3; break; @@ -5235,7 +5248,7 @@ t_stat sim_instr (void) { case 0x09: /* ADD IY,BC */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IY &= ADDRMASK; BC &= ADDRMASK; sum = IY + BC; @@ -5245,7 +5258,7 @@ t_stat sim_instr (void) { case 0x19: /* ADD IY,DE */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IY &= ADDRMASK; DE &= ADDRMASK; sum = IY + DE; @@ -5255,7 +5268,7 @@ t_stat sim_instr (void) { case 0x21: /* LD IY,nnnn */ tStates += 14; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IY = GetWORD(PC); PC += 2; break; @@ -5270,33 +5283,33 @@ t_stat sim_instr (void) { case 0x23: /* INC IY */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++IY; break; case 0x24: /* INC IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IY += 0x100; AF = (AF & ~0xfe) | incZ80Table[hreg(IY)]; break; case 0x25: /* DEC IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IY -= 0x100; AF = (AF & ~0xfe) | decZ80Table[hreg(IY)]; break; case 0x26: /* LD IYH,nn */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IY, RAM_pp(PC)); break; case 0x29: /* ADD IY,IY */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IY &= ADDRMASK; sum = IY + IY; AF = (AF & ~0x3b) | cbitsDup16Table[sum >> 8]; @@ -5313,13 +5326,13 @@ t_stat sim_instr (void) { case 0x2b: /* DEC IY */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; --IY; break; case 0x2c: /* INC IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IY) + 1; Setlreg(IY, temp); AF = (AF & ~0xfe) | incZ80Table[temp]; @@ -5327,7 +5340,7 @@ t_stat sim_instr (void) { case 0x2d: /* DEC IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IY) - 1; Setlreg(IY, temp); AF = (AF & ~0xfe) | decZ80Table[temp & 0xff]; @@ -5335,7 +5348,7 @@ t_stat sim_instr (void) { case 0x2e: /* LD IYL,nn */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IY, RAM_pp(PC)); break; @@ -5366,7 +5379,7 @@ t_stat sim_instr (void) { case 0x39: /* ADD IY,SP */ tStates += 15; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; IY &= ADDRMASK; SP &= ADDRMASK; sum = IY + SP; @@ -5376,13 +5389,13 @@ t_stat sim_instr (void) { case 0x44: /* LD B,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(BC, hreg(IY)); break; case 0x45: /* LD B,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(BC, lreg(IY)); break; @@ -5395,13 +5408,13 @@ t_stat sim_instr (void) { case 0x4c: /* LD C,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(BC, hreg(IY)); break; case 0x4d: /* LD C,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(BC, lreg(IY)); break; @@ -5414,13 +5427,13 @@ t_stat sim_instr (void) { case 0x54: /* LD D,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(DE, hreg(IY)); break; case 0x55: /* LD D,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(DE, lreg(IY)); break; @@ -5433,13 +5446,13 @@ t_stat sim_instr (void) { case 0x5c: /* LD E,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(DE, hreg(IY)); break; case 0x5d: /* LD E,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(DE, lreg(IY)); break; @@ -5452,36 +5465,36 @@ t_stat sim_instr (void) { case 0x60: /* LD IYH,B */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IY, hreg(BC)); break; case 0x61: /* LD IYH,C */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IY, lreg(BC)); break; case 0x62: /* LD IYH,D */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IY, hreg(DE)); break; case 0x63: /* LD IYH,E */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IY, lreg(DE)); break; case 0x64: /* LD IYH,IYH */ tStates += 9; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x65: /* LD IYH,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IY, lreg(IY)); break; @@ -5494,43 +5507,43 @@ t_stat sim_instr (void) { case 0x67: /* LD IYH,A */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(IY, hreg(AF)); break; case 0x68: /* LD IYL,B */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IY, hreg(BC)); break; case 0x69: /* LD IYL,C */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IY, lreg(BC)); break; case 0x6a: /* LD IYL,D */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IY, hreg(DE)); break; case 0x6b: /* LD IYL,E */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IY, lreg(DE)); break; case 0x6c: /* LD IYL,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IY, hreg(IY)); break; case 0x6d: /* LD IYL,IYL */ tStates += 9; - sim_brk_pend = FALSE; /* nop */ + sim_brk_pend[0] = FALSE; /* nop */ break; case 0x6e: /* LD L,(IY+dd) */ @@ -5542,7 +5555,7 @@ t_stat sim_instr (void) { case 0x6f: /* LD IYL,A */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Setlreg(IY, hreg(AF)); break; @@ -5597,13 +5610,13 @@ t_stat sim_instr (void) { case 0x7c: /* LD A,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(AF, hreg(IY)); break; case 0x7d: /* LD A,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; Sethreg(AF, lreg(IY)); break; @@ -5616,7 +5629,7 @@ t_stat sim_instr (void) { case 0x84: /* ADD A,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IY); acu = hreg(AF); sum = acu + temp; @@ -5625,7 +5638,7 @@ t_stat sim_instr (void) { case 0x85: /* ADD A,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IY); acu = hreg(AF); sum = acu + temp; @@ -5644,7 +5657,7 @@ t_stat sim_instr (void) { case 0x8c: /* ADC A,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IY); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -5653,7 +5666,7 @@ t_stat sim_instr (void) { case 0x8d: /* ADC A,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IY); acu = hreg(AF); sum = acu + temp + TSTFLAG(C); @@ -5685,7 +5698,7 @@ t_stat sim_instr (void) { case 0x9c: /* SBC A,IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IY); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -5697,7 +5710,7 @@ t_stat sim_instr (void) { case 0x9d: /* SBC A,IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IY); acu = hreg(AF); sum = acu - temp - TSTFLAG(C); @@ -5716,13 +5729,13 @@ t_stat sim_instr (void) { case 0xa4: /* AND IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF & IY) >> 8) & 0xff]; break; case 0xa5: /* AND IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = andTable[((AF >> 8) & IY) & 0xff]; break; @@ -5735,13 +5748,13 @@ t_stat sim_instr (void) { case 0xac: /* XOR IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF ^ IY) >> 8) & 0xff]; break; case 0xad: /* XOR IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) ^ IY) & 0xff]; break; @@ -5754,13 +5767,13 @@ t_stat sim_instr (void) { case 0xb4: /* OR IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF | IY) >> 8) & 0xff]; break; case 0xb5: /* OR IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; AF = xororTable[((AF >> 8) | IY) & 0xff]; break; @@ -5773,7 +5786,7 @@ t_stat sim_instr (void) { case 0xbc: /* CP IYH */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = hreg(IY); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -5784,7 +5797,7 @@ t_stat sim_instr (void) { case 0xbd: /* CP IYL */ tStates += 9; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = lreg(IY); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -5810,37 +5823,37 @@ t_stat sim_instr (void) { switch ((op = GetBYTE(PC)) & 7) { case 0: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(BC); break; case 1: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = lreg(BC); break; case 2: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(DE); break; case 3: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = lreg(DE); break; case 4: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(HL); break; case 5: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = lreg(HL); break; @@ -5852,7 +5865,7 @@ t_stat sim_instr (void) { break; case 7: - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; ++PC; acu = hreg(AF); break; @@ -5988,19 +6001,19 @@ t_stat sim_instr (void) { case 0xe9: /* JP (IY) */ tStates += 8; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; PCQ_ENTRY(PC - 2); PC = IY; break; case 0xf9: /* LD SP,IY */ tStates += 10; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; SP = IY; break; default: /* ignore FD */ - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; checkCPUZ80; PC--; } @@ -6008,7 +6021,7 @@ t_stat sim_instr (void) { case 0xfe: /* CP nn */ tStates += 7; - sim_brk_pend = FALSE; + sim_brk_pend[0] = FALSE; temp = RAM_pp(PC); AF = (AF & ~0x28) | (temp & 0x28); acu = hreg(AF); @@ -6080,7 +6093,7 @@ void printROMMessage(const uint32 cntROM) { /* reset routine */ t_stat cpu_reset(DEVICE *dptr) { - extern int32 sim_brk_types, sim_brk_dflt; /* breakpoint info */ + extern uint32 sim_brk_types, sim_brk_dflt; /* breakpoint info */ int32 i; AF_S = AF1_S = 0; BC_S = DE_S = HL_S = 0; diff --git a/AltairZ80/altairZ80_defs.h b/AltairZ80/altairZ80_defs.h index e3c58970..6b9f3814 100644 --- a/AltairZ80/altairZ80_defs.h +++ b/AltairZ80/altairZ80_defs.h @@ -1,6 +1,6 @@ /* altairz80_defs.h: MITS Altair simulator definitions - Copyright (c) 2002-2005, Peter Schorn + Copyright (c) 2002-2006, Peter Schorn Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -73,14 +73,3 @@ sprintf(messageBuffer,PCformat p1,PCX,p2,p3,p4,p5); printMessage() #define message6(p1,p2,p3,p4,p5,p6) \ sprintf(messageBuffer,PCformat p1,PCX,p2,p3,p4,p5,p6); printMessage() - -/* The default is to use "inline". */ -#if defined(NO_INLINE) -#define INLINE -#else -#if defined(__DECC) && defined(VMS) -#define INLINE __inline -#else -#define INLINE inline -#endif -#endif diff --git a/AltairZ80/altairZ80_dsk.c b/AltairZ80/altairZ80_dsk.c index f5ae4409..f3613c1a 100644 --- a/AltairZ80/altairZ80_dsk.c +++ b/AltairZ80/altairZ80_dsk.c @@ -1,6 +1,6 @@ /* altairz80_dsk.c: MITS Altair 88-DISK Simulator - Copyright (c) 2002-2005, Peter Schorn + Copyright (c) 2002-2006, Peter Schorn Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -494,7 +494,7 @@ int32 dsk11(const int32 port, const int32 io, const int32 data) { /* Disk Data In/Out */ -static INLINE int32 dskseek(const UNIT *xptr) { +static int32 dskseek(const UNIT *xptr) { return fseek(xptr -> fileref, DSK_TRACSIZE * current_track[current_disk] + DSK_SECTSIZE * current_sector[current_disk], SEEK_SET); } diff --git a/AltairZ80/altairZ80_sio.c b/AltairZ80/altairZ80_sio.c index 6967c518..474646b8 100644 --- a/AltairZ80/altairZ80_sio.c +++ b/AltairZ80/altairZ80_sio.c @@ -1,6 +1,6 @@ -/* altairz80_sio: MITS Altair serial I/O card +/* altairz80_sio.c: MITS Altair serial I/O card - Copyright (c) 2002-2005, Peter Schorn + Copyright (c) 2002-2006, Peter Schorn Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -115,7 +115,7 @@ extern t_stat sim_poll_kbd(void); extern t_stat sim_putchar(int32 out); extern t_stat attach_unit(UNIT *uptr, char *cptr); extern int32 getBankSelect(void); -extern void setBankSelect(int32 b); +extern void setBankSelect(const int32 b); extern uint32 getCommon(void); extern t_bool rtc_avail; extern FILE *sim_log; @@ -124,7 +124,7 @@ extern int32 sim_switches; extern uint32 sim_os_msec(void); extern const char *scp_error_messages[]; extern int32 SR; -extern uint8 GetBYTEWrapper(register uint32 Addr); +extern uint8 GetBYTEWrapper(const uint32 Addr); extern UNIT cpu_unit; /* SIMH pseudo device status registers */ diff --git a/AltairZ80/altairZ80_sys.c b/AltairZ80/altairZ80_sys.c index 7b8b4b35..84a3837a 100644 --- a/AltairZ80/altairZ80_sys.c +++ b/AltairZ80/altairZ80_sys.c @@ -1,6 +1,6 @@ /* altairz80_sys.c: MITS Altair system interface - Copyright (c) 2002-2005, Peter Schorn + Copyright (c) 2002-2006, Peter Schorn Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -584,7 +584,7 @@ static int32 match(const char *pattern, const char *input, char *xyFirst, char * return (pat == 0) && (inp == 0); } -static INLINE int32 checkXY(const char xy) { +static int32 checkXY(const char xy) { return xy == 'X' ? 0xdd : 0xfd; /* else is 'Y' */ } diff --git a/AltairZ80/altairz80_hdsk.c b/AltairZ80/altairz80_hdsk.c index 0da8a34b..61a9be46 100644 --- a/AltairZ80/altairz80_hdsk.c +++ b/AltairZ80/altairz80_hdsk.c @@ -1,6 +1,6 @@ /* altairz80_hdsk.c: simulated hard disk device to increase capacity - Copyright (c) 2002-2005, Peter Schorn + Copyright (c) 2002-2006, Peter Schorn Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -54,9 +54,9 @@ extern int32 saved_PC; extern int32 install_bootrom(void); extern void printMessage(void); extern void PutBYTEBasic(const uint32 Addr, const uint32 Bank, const uint32 Value); -extern void PutBYTEWrapper(register uint32 Addr, register uint32 Value); +extern void PutBYTEWrapper(const uint32 Addr, const uint32 Value); extern void protect(const int32 l, const int32 h); -extern uint8 GetBYTEWrapper(register uint32 Addr); +extern uint8 GetBYTEWrapper(const uint32 Addr); extern int32 bootrom[bootrom_size]; static t_stat hdsk_svc(UNIT *uptr); @@ -204,7 +204,7 @@ static int32 hdsk_hasVerbose(void) { l: out (0fdh),a dec b jp nz,l - + 2. Read / write ; parameter block cmd: db hdsk_read or hdsk_write @@ -212,7 +212,7 @@ static int32 hdsk_hasVerbose(void) { sector: db 0 ; 0 .. 31, defines sector track: dw 0 ; 0 .. 2047, defines track dma: dw 0 ; defines where result is placed in memory - + ; routine to execute ld b,7 ; size of parameter block ld hl,cmd ; start address of parameter block diff --git a/GRI/gri_doc.txt b/GRI/gri_doc.txt deleted file mode 100644 index 80b2b06b..00000000 --- a/GRI/gri_doc.txt +++ /dev/null @@ -1,338 +0,0 @@ -To: Users -From: Bob Supnik -Subj: GRI-909 Simulator Usage -Date: 01-Dec-2005 - - COPYRIGHT NOTICE - -The following copyright notice applies to both the SIMH source and binary: - - Original code published in 1993-2005, written by Robert M Supnik - Copyright (c) 1993-2005, Robert M Supnik - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of Robert M Supnik shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from Robert M Supnik. - -This memorandum documents the GRI-909 simulator. - - -1. Simulator Files - -sim/ scp.h - sim_console.h - sim_defs.h - sim_fio.h - sim_rev.h - sim_sock.h - sim_timer.h - sim_tmxr.h - scp.c - sim_console.c - sim_fio.c - sim_sock.c - sim_timer.c - sim_tmxr.c - -sim/gri/ gri_defs.h - gri_cpu.c - gri_stddev.c - gri_sys.c - -2. GRI-909 Features - -The GRI-909 is configured as follows: - -device simulates -name(s) - -CPU GRI-909 CPU with up to 32KW of memory -HSR S42-004 high speed reader -HSP S42-004 high speed punch -TTI S42-001 Teletype input -TTO S42-002 Teletype output -RTC real-time clock - -The GRI-909 simulator implements the following unique stop conditions: - - - an unimplemented operator is referenced, and register - STOP_OPR is set - - an invalid interrupt request is made - -The LOAD commands has an optional argument to specify the load address: - - LOAD {} - -The LOAD command loads a paper-tape bootstrap format file at the specified -address. If no address is specified, loading starts at location 200. The -DUMP command is not supported. - -2.1 CPU - -The only CPU options are the presence of the extended arithmetic operator -and the size of main memory. - - SET CPU EAO enable extended arithmetic operator - SET CPU NOEAO disable extended arithmetic operator - SET CPU 4K set memory size = 4K - SET CPU 8K set memory size = 8K - SET CPU 12K set memory size = 12K - SET CPU 16K set memory size = 16K - SET CPU 20K set memory size = 20K - SET CPU 24K set memory size = 24K - SET CPU 28K set memory size = 28K - SET CPU 32K set memory size = 32K - -If memory size is being reduced, and the memory being truncated contains -non-zero data, the simulator asks for confirmation. Data in the truncated -portion of memory is lost. Initial memory size is 32K. - -CPU registers include the visible state of the processor as well as the -control registers for the interrupt system. - - name size comments - - SC 15 sequence counter - AX 16 arithmetic operator input register 1 - AY 16 arithmetic operator input register 2 - AO 16 arithmetic operator output register - TRP 16 TRP register - MSR 16 machine status register - ISR 16 interrupt status register - BSW 16 byte swapper buffer - BPK 16 byte packer buffer - GR1..GR6 16 general registers 1 to 6 - BOV 1 bus overflow (MSR<15>) - L 1 link (MSR<14>) - FOA 2 arithmetic operator function (MSR<9:8>) - AOV 1 arithmetic overflow (MSR<0>) - IR 16 instruction register (read only) - MA 16 memory address register (read only) - SWR 16 switch register - DR 16 display register - THW 6 thumbwheels (selects operator displayed in DR) - IREQ 16 interrupt requests - ION 1 interrupts enabled - INODEF 1 interrupts not deferred - BKP 1 breakpoint request - SCQ[0:63] 15 SC prior to last jump or interrupt; - most recent SC change first - STOP_OPR 1 stop on undefined operator - WRU 8 interrupt character - -2.2 Programmed I/O Devices - -2.2.1 S42-004 High Speed Reader (HSR) - -The paper tape reader (HSR) reads data from or a disk file. The POS -register specifies the number of the next data item to be read. -Thus, by changing POS, the user can backspace or advance the reader. - -The paper tape reader implements these registers: - - name size comments - - BUF 8 last data item processed - IRDY 1 device ready flag - IENB 1 device interrupt enable flag - POS 32 position in the input file - TIME 24 time from I/O initiation to interrupt - STOP_IOE 1 stop on I/O error - -Error handling is as follows: - - error STOP_IOE processed as - - not attached 1 report error and stop - 0 out of tape - - end of file 1 report error and stop - 0 out of tape - - OS I/O error x report error and stop - -2.2.2 S42-006 High Speed Punch (HSP) - -The paper tape punch (HSP) writes data to a disk file. The POS -register specifies the number of the next data item to be written. -Thus, by changing POS, the user can backspace or advance the punch. - -The paper tape punch implements these registers: - - name size comments - - BUF 8 last data item processed - ORDY 1 device ready flag - IENB 1 device interrupt enable flag - POS 32 position in the output file - TIME 24 time from I/O initiation to interrupt - STOP_IOE 1 stop on I/O error - -Error handling is as follows: - - error STOP_IOE processed as - - not attached 1 report error and stop - 0 out of tape - - OS I/O error x report error and stop - -2.2.3 S42-001 Teletype Input (TTI) - -The Teletype interfaces (TTI, TTO) can be set to one of four modes, -KSR, 7P, 7B, or 8B: - - mode input characters output characters - - KSR lower case converted lower case converted - to upper case, to upper case, - high-order bit set high-order bit cleared, - non-printing characters - suppressed - 7P high-order bit cleared high-order bit cleared, - non-printing characters - suppressed - 7B high-order bit cleared high-order bit cleared - 8B no changes no changes - -The default mode is KSR. - -The Teletype input (TTI) polls the console keyboard for input. It -implements these registers: - - name size comments - - BUF 8 last data item processed - IRDY 1 device ready flag - IENB 1 device interrupt enable flag - POS 32 position in the output file - TIME 24 keyboard polling interval - -2.2.4 S42-002 Teletype Output (TTO) - -The Teletype output (TTO) writes to the simulator console window. It -implements these registers: - - name size comments - - BUF 8 last data item processed - ORDY 1 device ready flag - IENB 1 device interrupt enable flag - POS 32 number of characters output - TIME 24 time from I/O initiation to interrupt - -2.2.5 Real-Time Clock (RTC) - -The real-time clock (CLK) implements these registers: - - name size comments - - RDY 1 device ready flag - IENB 1 interrupt enable flag - TIME 24 clock interval - -The real-time clock autocalibrates; the clock interval is adjusted up or -down so that the clock tracks actual elapsed time. - -2.3 Symbolic Display and Input - -The GRI-909 simulator implements symbolic display and input. Display is -controlled by command line switches: - - -a display as ASCII character - -c display as packed ASCII characters - -m display instruction mnemonics - -Input parsing is controlled by the first character typed in or by command -line switches: - - ' or -a ASCII character - " or -c two packed ASCII characters - alphabetic instruction mnemonic - numeric octal number - -Instruction input uses modified GRI-909 basic assembler syntax. There are -thirteen different instruction formats. Operators, functions, and tests may -be octal or symbolic; jump conditions and bus operators are always symbolic. - -Function out, general - Syntax: FO function,operator - Function symbols: INP, IRDY, ORDY, STRT - Example: FO ORDY,TTO - -Function out, named - Syntax: FO{M|I|A} function - Function symbols: M: CLL, CML, STL, HLT; I: ICF, ICO; - A: ADD, AND, XOR, OR - Example: FOA XOR - -Sense function, general - Syntax: SF operator,{NOT} tests - Test symbols: IRDY, ORDY - Example: SF HSR,IRDY - -Sense function, named - Syntax: SF{M|A} {NOT} tests - Test symbols: M: POK BOV LNK; A: SOV AOV - Example: SFM NOT BOV - -Register to register - Syntax: RR{C} src,{bus op,}dst - Bus op symbols: P1, L1, R1 - Example: RRC AX,P1,AY - -Zero to register - Syntax: ZR{C} {bus op,}dst - Bus op symbols: P1, L1, R1 - Example: ZR P1,GR1 - -Register to self - Syntax: RS{C} dst{,bus op} - Bus op symbols: P1, L1, R1 - Example: RS AX,L1 - -Jump unconditional or named condition - Syntax: J{U|O|N}{D} address - Example: JUD 1400 - -Jump conditional - Syntax: JC{D} src,cond,address - Cond symbols: NEVER,ALWAYS,ETZ,NEZ,LTZ,GEZ,LEZ,GTZ - Example: JC AX,LEZ,200 - -Register to memory - syntax: RM{I|D|ID} src,{bus op,}address - Bus op symbols: P1, L1, R1 - Example: RMD AX,P1,1315 - -Zero to memory - Syntax: ZM{I|D|ID} {bus op,}address - Bus op symbols: P1, L1, R1 - Example: ZM P1,5502 - -Memory to register - Syntax: MR{I|D|ID} address,{bus op,}dst - Bus op symbols: P1, L1, R1 - Example: MRI 1405,GR6 - -Memory to self: - Syntax: MS{I|D|ID} address{,bus op} - Bus op symbols: P1, L1, R1 - Example: MS 3333,P1 diff --git a/H316/h316_cpu.c b/H316/h316_cpu.c index 4bfd98b8..92be3e37 100644 --- a/H316/h316_cpu.c +++ b/H316/h316_cpu.c @@ -1,6 +1,6 @@ /* h316_cpu.c: Honeywell 316/516 CPU simulator - Copyright (c) 1999-2005, Robert M. Supnik + Copyright (c) 1999-2006, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ cpu H316/H516 CPU + 03-Apr-06 RMS Fixed bugs in LLL, LRL (from Theo Engel) 22-Sep-05 RMS Fixed declarations (from Sterling Garwood) 16-Aug-05 RMS Fixed C++ declaration and cast problems 15-Feb-05 RMS Added start button interrupt @@ -427,7 +428,7 @@ if (chan_req) { /* channel request? */ if (st & DMA_IN) { /* input? */ t = iotab[dev] (ioINA, 0, 0, dev); /* input word */ if ((t & IOT_SKIP) == 0) return STOP_DMAER; - if (r = (t >> IOT_V_REASON)) return r; + if ((r = t >> IOT_V_REASON) != 0) return r; Write (ad, t & DMASK); /* write to mem */ } else { /* no, output */ @@ -441,7 +442,7 @@ if (chan_req) { /* channel request? */ if (dma_wc[i] == 0) { /* done? */ dma_eor[i] = 1; /* set end of range */ t = iotab[dev] (ioEND, 0, 0, dev); /* send end range */ - if (r = (t >> IOT_V_REASON)) return r; + if ((r = t >> IOT_V_REASON) != 0) return r; } } else { /* DMC */ @@ -450,7 +451,7 @@ if (chan_req) { /* channel request? */ end = Read (dmcad + 1); /* get end */ if (((ad ^ end) & X_AMASK) == 0) { /* start == end? */ t = iotab[dev] (ioEND, 0, 0, dev); /* send end range */ - if (r = (t >> IOT_V_REASON)) return r; + if ((r = t >> IOT_V_REASON) != 0) return r; } /* end if end range */ } /* end else DMC */ } /* end if chan i */ @@ -659,6 +660,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */ case 000: if ((MB & 1) == 0) { /* HLT */ + if ((reason = sim_process_event ()) != SCPE_OK) break; reason = STOP_HALT; break; } @@ -739,7 +741,8 @@ switch (I_GETOP (MB)) { /* case on <1:6> */ else { ut = GETDBL_U (AR, BR); /* get A'B */ C = (ut >> (t1 - 1)) & 1; /* C = last out */ - ut = ut >> t1; /* log right */ + if (t1 == 32) ut = 0; /* =32? all 0 */ + else ut = ut >> t1; /* log right */ } PUTDBL_U (ut); /* store A,B */ break; @@ -803,7 +806,8 @@ switch (I_GETOP (MB)) { /* case on <1:6> */ else { ut = GETDBL_U (AR, BR); /* get A'B */ C = (ut >> (32 - t1)) & 1; /* C = last out */ - ut = ut << t1; /* log left */ + if (t1 == 32) ut = 0; /* =32? all 0 */ + else ut = ut << t1; /* log left */ } PUTDBL_U (ut); /* store A,B */ break; @@ -879,7 +883,7 @@ switch (I_GETOP (MB)) { /* case on <1:6> */ ((MB & 000020) && ss[0]) || /* SS1 */ ((MB & 000040) && AR) || /* SNZ */ ((MB & 000100) && (AR & 1)) || /* SLN */ - ((MB & 000200) && (TST_INTREQ (INT_MPE))) || /* SPS */ + ((MB & 000200) && (TST_INTREQ (INT_MPE))) || /* SPS */ ((MB & 000400) && (AR & SIGN))) skip = 1; /* SMI */ if ((MB & 001000) == 0) skip = skip ^ 1; /* reverse? */ PC = NEWA (PC, PC + skip); @@ -895,12 +899,12 @@ switch (I_GETOP (MB)) { /* case on <1:6> */ else if (MB == 0140320) { /* CSA */ C = (AR & SIGN) >> 15; AR = AR & ~SIGN; - } + } else if (MB == 0140401) AR = AR ^ DMASK; /* CMA */ else if (MB == 0140407) { /* TCA */ AR = (-AR) & DMASK; sc = 0; - } + } else if (MB == 0140500) AR = AR | SIGN; /* SSM */ else if (MB == 0140600) C = 1; /* SCB */ else if (MB == 0141044) AR = AR & 0177400; /* CAR */ @@ -1369,9 +1373,11 @@ for (i = 0; dptr = sim_devices[i]; i++) { /* loop thru devices */ dno = dibp->dev; /* device number */ for (j = 0; j < dibp->num; j++) { /* repeat for slots */ if (iotab[dno + j]) { /* conflict? */ - printf ("%s device number conflict, devno = %02o\n", sim_dname (dptr), dno + j); + printf ("%s device number conflict, devno = %02o\n", + sim_dname (dptr), dno + j); if (sim_log) fprintf (sim_log, - "%s device number conflict, devno = %02o\n", sim_dname (dptr), dno + j); + "%s device number conflict, devno = %02o\n", + sim_dname (dptr), dno + j); return TRUE; } iotab[dno + j] = dibp->io; /* set I/O routine */ @@ -1379,21 +1385,27 @@ for (i = 0; dptr = sim_devices[i]; i++) { /* loop thru devices */ if (dibp->chan) { /* DMA/DMC? */ chan = dibp->chan - 1; if ((chan < DMC_V_DMC1) && (chan >= dma_nch)) { - printf ("%s configured for DMA channel %d\n", sim_dname (dptr), chan + 1); + printf ("%s configured for DMA channel %d\n", + sim_dname (dptr), chan + 1); if (sim_log) fprintf (sim_log, - "%s configured for DMA channel %d\n", sim_dname (dptr), chan + 1); + "%s configured for DMA channel %d\n", + sim_dname (dptr), chan + 1); return TRUE; } if ((chan >= DMC_V_DMC1) && !(cpu_unit.flags & UNIT_DMC)) { - printf ("%s configured for DMC, option disabled\n", sim_dname (dptr)); + printf ("%s configured for DMC, option disabled\n", + sim_dname (dptr)); if (sim_log) fprintf (sim_log, - "%s configured for DMC, option disabled\n", sim_dname (dptr)); + "%s configured for DMC, option disabled\n", + sim_dname (dptr)); return TRUE; } if (chan_map[chan]) { /* channel conflict? */ - printf ("%s DMA/DMC channel conflict, devno = %02o\n", sim_dname (dptr), dno); + printf ("%s DMA/DMC channel conflict, devno = %02o\n", + sim_dname (dptr), dno); if (sim_log) fprintf (sim_log, - "%s DMA/DMC channel conflict, devno = %02o\n", sim_dname (dptr), dno); + "%s DMA/DMC channel conflict, devno = %02o\n", + sim_dname (dptr), dno); return TRUE; } chan_map[chan] = dno; /* channel back map */ @@ -1466,7 +1478,8 @@ for (k = 0; k < lnt; k++) { /* print specified */ if (h->pc & HIST_EA) fprintf (st, "%05o ", h->ea); else fprintf (st, " "); sim_eval = h->ir; - if ((fprint_sym (st, h->pc & X_AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) + if ((fprint_sym (st, h->pc & X_AMASK, &sim_eval, + &cpu_unit, SWMASK ('M'))) > 0) fprintf (st, "(undefined) %06o", h->ir); op = I_GETOP (h->ir) & 017; /* base op */ if (has_opnd[op]) fprintf (st, " [%06o]", h->opnd); diff --git a/H316/h316_doc.txt b/H316/h316_doc.txt deleted file mode 100644 index a2c397ea..00000000 --- a/H316/h316_doc.txt +++ /dev/null @@ -1,672 +0,0 @@ -To: Users -From: Bob Supnik -Subj: H316 Simulator Usage -Date: 01-Dec-2005 - - COPYRIGHT NOTICE - -The following copyright notice applies to both the SIMH source and binary: - - Original code published in 1993-2005, written by Robert M Supnik - Copyright (c) 1993-2005, Robert M Supnik - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of Robert M Supnik shall not be - used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from Robert M Supnik. - -This memorandum documents the Honeywell 316/516 simulator. - - -1. Simulator Files - -The H316 requires the following files: - -sim/ scp.h - sim_console.h - sim_defs.h - sim_fio.h - sim_rev.h - sim_sock.h - sim_tape.h - sim_timer.h - sim_tmxr.h - scp.c - sim_console.c - sim_fio.c - sim_sock.c - sim_tape.c - sim_timer.c - sim_tmxr.c - -sim/h316/ h316_defs.h - h316_cpu.c - h316_fhd.c - h316_lp.c - h316_mt.c - h316_dp.c - h316_stddev.c - h316_sys.c - -2. H316/H516 Features - -The Honeywell 316/516 simulator is configured as follows: - -device simulates -name(s) - -CPU H316/H516 CPU with 16/32KW memory -PTR 316/516-50 paper tape reader -PTP 316/516-52 paper tape punch -TTY 316/516-33 console terminal -CLK 316/516-12 real time clock -LPT 316/516 line printer -FHD 4400 fixed head disk -DP 4623/4653/4720 disk pack controller with eight drives -MT 4100 seven track magtape with four drives - -The H316/H516 simulator implements several unique stop conditions: - - - decode of an undefined instruction, and STOP_INST is et - - reference to an undefined I/O device, and STOP_DEV is set - - more than INDMAX indirect references are detected during - memory reference address decoding - - DMA/DMC direction does not agree with I/O device operation - - a write operation is initiated on a write locked magtape - unit (hangs the real system) - - a disk write overruns the specified record size (destroys - the rest of the track on the real system) - - a disk track has an illegal format - -The H316/H516 loader is not implemented. - -2.1 CPU - -CPU options include choice of instruction set, memory size, DMC option, -and number of DMA channels. - - SET CPU HSA high speed arithmetic instructions - SET CPU NOHSA no high speed arithmetic instructions - SET CPU 4K set memory size = 4K - SET CPU 8K set memory size = 8K - SET CPU 12K set memory size = 12K - SET CPU 16K set memory size = 16K - SET CPU 24K set memory size = 24K - SET CPU 32K set memory size = 32K - SET CPU DMC enable DMC option - SET CPU NODMC disable DMC option - SET CPU DMA=n set number of DMA channels to n (0-4) - -If memory size is being reduced, and the memory being truncated contains -non-zero data, the simulator asks for confirmation. Data in the truncated -portion of memory is lost. Initial memory size is 32K. The HSA and DMC -options are enabled, and four DMA channels are configured. - -The CPU includes special show commands to display the state of the DMA -channels: - - SHOW CPU DMAn show DMA channel n - -CPU registers include the visible state of the processor as well as the -control registers for the interrupt system. - - name size comments - - P 15 program counter - A 16 A register - B 16 B register - X 16 index register - SC 16 shift count - C 1 carry flag - EXT 1 extend flag - PME 1 previous mode extend flag - EXT_OFF 1 extend off pending flag - DP 1 double precision flag - SS1..4 1 sense switches 1..4 - ION 1 interrupts enabled - INODEF 1 interrupts not deferred - INTREQ 16 interrupt requests - DEVRDY 16 device ready flags (read only) - DEVENB 16 device interrupt enable flags (read only) - CHREQ 20 DMA/DMC channel requests - DMAAD[0:3] 16 DMA channel current address, channels 1-4 - DMAWC[0:3] 15 DMA channel word count, channels 1-4 - DMAEOR[0:3] 1 DMA end of range flag, channels 1-4 - STOP_INST 1 stop on undefined instruction - STOP_DEV 1 stop on undefined device - INDMAX 1 indirect address limit - PCQ[0:63] 15 PC prior to last JMP, JSB, or interrupt; - most recent PC change first - WRU 8 interrupt character - -The CPU can maintain a history of the most recently executed instructions. -This is controlled by the SET CPU HISTORY and SHOW CPU HISTORY commands: - - SET CPU HISTORY clear history buffer - SET CPU HISTORY=0 disable history - SET CPU HISTORY=n enable history, length = n - SHOW CPU HISTORY print CPU history - SHOW CPU HISTORY=n print first n entries of CPU history - -The maximum length for the history is 65536 entries. - -2.2 Programmed I/O Devices - -2.2.1 316/516-50 Paper Tape Reader (PTR) - -The paper tape reader (PTR) reads data from a disk file. The POS -register specifies the number of the next data item to be read. -Thus, by changing POS, the user can backspace or advance the reader. - -The paper tape reader can bet set to operate in binary, ASCII, or -Unix ASCII mode: - - sim> set ptr binary -- binary mode - sim> set ptr ascii -- ASCII mode - sim> set ptr uascii -- Unix ASCII mode - -The mode can also be set by a switch setting in the attach command: - - sim> att -b ptr -- binary mode - sim> att -a ptr -- ASCII mode - sim> att -u ptr -- Unix ASCII mode - -In ASCII or Unix ASCII mode, all non-zero characters have the high -order bit forced on. In Unix ASCII mode, newline is converted to -CR, and LF in inserted as the following character. - -The paper tape reader supports the BOOT command. BOOT PTR copies the -absolute binary loader into memory and starts it running. - -The paper tape reader implements these registers: - - name size comments - - BUF 8 last data item processed - INTREQ 1 device interrupt request - READY 1 device ready - ENABLE 1 device interrupts enabled - POS 32 position in the input or output file - TIME 24 time from I/O initiation to interrupt - STOP_IOE 1 stop on I/O error - -Error handling is as follows: - - error STOP_IOE processed as - - not attached 1 report error and stop - 0 out of tape - - end of file 1 report error and stop - 0 out of tape or paper - - OS I/O error x report error and stop - -2.2.2 316/516-52 Paper Tape Punch (PTP) - -The paper tape punch (PTP) writes data to a disk file. The POS -register specifies the number of the next data item to be written. -Thus, by changing POS, the user can backspace or advance the punch. - -The paper tape punch can bet set to operate in binary, ASCII, or -Unix ASCII mode: - - sim> set ptp binary -- binary mode - sim> set ptp ascii -- ASCII mode - sim> set ptp uascii -- Unix ASCII mode - -The mode can also be set by a switch setting in the attach command: - - sim> att -b ptp -- binary mode - sim> att -a ptp -- ASCII mode - sim> att -u ptp -- Unix ASCII mode - -In ASCII or Unix ASCII mode, all characters are masked to 7b -before being written to the output file. In Unix ASCII mode, LF -is converted to newline, and CR is discarded. - -The paper tape punch implements these registers: - - name size comments - - BUF 8 last data item processed - INTREQ 1 device interrupt request - READY 1 device ready - ENABLE 1 device interrupts enabled - POWER 1 device powered up - POS 32 position in the input or output file - TIME 24 time from I/O initiation to interrupt - PWRTIME 24 time from I/O request to power up - STOP_IOE 1 stop on I/O error - -Error handling is as follows: - - error STOP_IOE processed as - - not attached 1 report error and stop - 0 out of tape - - OS I/O error x report error and stop - -2.2.3 316/516-33 Console Teletype (TTY) - -The console Teletype (TTY) consists of four separate units: - - TTY0 keyboard - TTY1 printer - TTY2 paper tape reader - TTY3 paper tape punch - -The keyboard and printer (TTY0, TTY1) can be set to one of four modes, -KSR, 7P, 7B, or 8B: - - mode input characters output characters - - KSR lower case converted lower case converted - to upper case, to upper case, - high-order bit set high-order bit cleared, - non-printing characters - suppressed - 7P high-order bit cleared high-order bit cleared, - non-printing characters - suppressed - 7B high-order bit cleared high-order bit cleared - 8B no changes no changes - -The default mode is KSR. The Teletype keyboard reads from the console -keyboard, and the printer writes to the simulator console window. - -The paper tape reader (TTY2) can bet set to operate in binary, ASCII, or -Unix ASCII mode: - - sim> set tty2 binary -- binary mode - sim> set tty2 ascii -- ASCII mode - sim> set tty2 uascii -- Unix ASCII mode - -The mode can also be set by a switch setting in the attach command: - - sim> att -b tty2 -- binary mode - sim> att -a tty2 -- ASCII mode - sim> att -u tty2 -- Unix ASCII mode - -In ASCII or Unix ASCII mode, all non-zero characters have the high -order bit forced on. In Unix ASCII mode, newline is converted to -CR, and LF in inserted as the following character. - -The paper tape reader is started by program output of XON or by -the command SET TTY2 START. The paper tape reader is stopped by -reader input of XOFF or by the command SET TTY2 STOP. - -The paper tape punch (TTY3) can bet set to operate in binary, ASCII, or -Unix ASCII mode: - - sim> set tty3 binary -- binary mode - sim> set tty3 ascii -- ASCII mode - sim> set tty3 uascii -- Unix ASCII mode - -The mode can also be set by a switch setting in the attach command: - - sim> att -b tty3 -- binary mode - sim> att -a tty3 -- ASCII mode - sim> att -u tty3 -- Unix ASCII mode - -In ASCII or Unix ASCII mode, all characters are masked to 7b -before being written to the output file. In Unix ASCII mode, LF -is converted to newline, and CR is discarded. - -The paper tape punch is started by program output of TAPE or by -the command SET TTY3 START. The paper tape punch is stopped by -program output of XOFF or by the command SET TTY3 STOP. - -It implements these registers: - - name size comments - - BUF 8 last data item processed - MODE 1 read/write mode - INTREQ 1 device interrupt request - READY 1 device ready - ENABLE 1 device interrupts enabled - KPOS 32 number of keyboard characters input - KTIME 24 keyboard polling interval - TPOS 32 number of printer characters output - TTIME 24 time from I/O initiation to interrupt - RPOS 32 current reader character position - PPOS 32 current punch character position - -2.2.4 316/516-12 Real Time Clock (CLK) - -The real time clock (CLK) frequency can be adjusted as follows: - - SET CLK 60HZ set frequency to 60Hz - SET CLK 50HZ set frequency to 50Hz - -The default is 60Hz. - -The clock implements these registers: - - name size comments - - INTREQ 1 device interrupt request - READY 1 device ready - ENABLE 1 device interrupts enabled - TIME 24 clock interval - -The real-time clock autocalibrates; the clock interval is adjusted up or -down so that the clock tracks actual elapsed time. - -2.3 316/516 Line Printer (LPT) - -The line printer (LPT) writes data to a disk file. The POS register -specifies the number of the next data item to be written. Thus, -by changing POS, the user can backspace or advance the printer. - -The line printer can be connected to the IO bus, a DMC channel, or -a DMA channel: - - SET LPT IOBUS connect to IO bus - SET LPT DMC=n connect to DMC channel n (1-16) - SET LPT DMA=n connect to DMA channel n (1-4) - -By default, the line printer is connected to the IO bus. - -The line printer implements these registers: - - name size comments - - WDPOS 6 word position in current scan - DRPOS 6 drum position - CRPOS 1 carriage position - PRDN 1 print done flag - RDY 1 ready flag - EOR 1 (DMA/DMC) end of range flag - DMA 1 transfer using DMA/DMC - INTREQ 1 device interrupt request - ENABLE 1 device interrupt enable - SVCST 2 service state - SVCCH 2 service channel - BUF 8 buffer - POS 32 number of characters output - XTIME 24 delay between transfers - ETIME 24 delay at end of scan - PTIME 24 delay for shuttle/line advance - STOP_IOE 1 stop on I/O error - -Error handling is as follows: - - error STOP_IOE processed as - - not attached 1 report error and stop - 0 out of paper - - OS I/O error x report error and stop - -2.4 4400 Fixed Head Disk (FHD) - -Fixed head disk options include the ability to set the number of -surfaces to a fixed value between 1 and 16, or to autosize the number -of surfaces from the attached file: - - SET FHD 1S one surface (98K) - SET FHD 2S two platters (196K) - : - SET FHD 16S sixteen surfaces (1568K) - SET FHD AUTOSIZE autosized on attach - -The default is one surface. - -The fixed head disk can be connected to the IO bus, a DMC channel, or -a DMA channel: - - SET FHD IOBUS connect to IO bus - SET FHD DMC=n connect to DMC channel n (1-16) - SET FHD DMA=n connect to DMA channel n (1-4) - -By default, the fixed head disk is connected to the IO bus. - - -The fixed head disk implements these registers: - - name size comments - - CW1 16 control word 1 (read write, surface, track) - CW2 16 control word 2 (character address) - BUF 16 data buffer - BUSY 1 controller busy flag - RDY 1 transfer ready flag - DTE 1 data transfer error flag - ACE 1 access error flag - EOR 1 (DMA/DMC) end of range - DMA 1 transfer using DMA/DMC - CSUM 1 transfer parity checksum - INTREQ 1 device interrupt request - ENABLE 1 device interrupt enable - TIME 24 delay between words - STOP_IOE 1 stop on I/O error - -The fixed head disk does not support the BOOT command. - -Error handling is as follows: - - error STOP_IOE processed as - - not attached 1 report error and stop - 0 disk not ready - -Fixed head disk data files are buffered in memory; therefore, end of file -and OS I/O errors cannot occur. - -2.5 4100 7-track Magnetic Tape (MT) - -Magnetic tape options include the ability to make units write enabled or -or write locked. - - SET MTn LOCKED set unit n write locked - SET MTn WRITEENABLED set unit n write enabled - -Units can also be set ENABLED or DISABLED. - -The magtape controller can be connected to the IO bus, a DMC channel, or -a DMA channel: - - SET MT IOBUS connect to IO bus - SET MT DMC=n connect to DMC channel n (1-16) - SET MT DMA=n connect to DMA channel n (1-4) - -By default, the magtape controller is connected to the IO bus. - -The magnetic tape controller implements these registers: - - name size comments - - BUF 16 data buffer - USEL 2 unit select - BUSY 1 controller busy flag - RDY 1 transfer ready flag - ERR 1 error flag - EOF 1 end of file flag - EOR 1 (DMA/DMC) end of range - DMA 1 transfer using DMA/DMC - MDIRQ 1 motion done interrupt request - INTREQ 1 device interrupt request - ENABLE 1 device interrupt enable - DBUF[0:65535] 8 transfer buffer - BPTR 17 transfer buffer pointer - BMAX 17 transfer size (reads) - CTIME 24 start/stop time - XTIME 24 delay between words - POS[0:3] 32 position, units 0-3 - STOP_IOE 1 stop on I/O error - -Error handling is as follows: - - error processed as - - not attached tape not ready; if STOP_IOE, stop - - end of file bad tape - - OS I/O error parity error; if STOP_IOE, stop - -2.6 4623/4651/4720 Disk Packs (DP) - -The disk controller can be configured as a 4623, supporting 10 surface -disk packs; a 4651, supporting 2 surface disk packs; or a 4720, supporting -20 surface disk packs: - - SET DP 4623 controller is 4623 - SET DP 4651 controller is 4651 - SET DP 4720 controller is 4720 - -The default is 4651. All disk packs on the controller must be of the -same type. Units can be set ENABLED or DISABLED, and WRITEENABLED or -write LOCKED. - -The disk pack controller can be connected to a DMC channel or a DMA -channel; it cannot be connected to the IO bus: - - SET DP DMC=n connect to DMC channel n (1-16) - SET DP DMA=n connect to DMA channel n (1-4) - -The disk pack controller supports variable track formatting. Each track -can contain between 1 and 103 records, with a minimum size of 1 word and -a maximum size of 1893 words. Record addresses are unconstrained. The -simulator provides a command to perform a simple, fixed record size format -of a new disk: - - SET DPn FORMAT=k format unit n with k words per record - SET -R DPn FORMAT=k format unit n with k records per track - -Record addresses can either be geometric (cylinder/track/sector) or simple -sequential starting from 0: - - SET DPn FORMAT=k format with geometric record addresses - SET -S DPn FORMAT=k format with sequential record addresses - -Geometric address have the cylinder number in bits<1:8>, the head number in -bits<9:13>, and the sector number in bits <14:16>. - -A summary of the current format, and its validity, can be obtained with -the command: - - SHOW DPn FORMAT display format of unit n - -To accomodate the variable formatting, each track is allocated 2048 words -in the data file. A record consists of a three word header, the data, and -a five word trailer: - - word 0 record length in words, not including header/trailer - word 1 record address - word 2 number of extension words used (0-4) - word 3 start of data record - word 3+n-1 end of data record - word 3+n..7+n record trailer: up to four extension words, - plus checksum - -A record can "grow" by up to four words without disrupting the track formatting; -writing more than four extra words destroys the formatting of the rest of the -track and causes a simulator error. - -The disk pack controller implements these registers: - - name size comments - - STA 16 status - BUF 16 data buffer - FNC 4 controller function - CW1 16 command word 1 - CW2 16 command word 2 - CSUM 16 record checksum - BUSY 1 controller busy - RDY 1 transfer ready - EOR 1 (DMA/DMC) end of range - DEFINT 1 seek deferred interrupt pending - INTREQ 1 interrupt request - ENABLE 1 interrupt enable - TBUF[0:2047] 16 track buffer - RPTR 11 pointer to start of record in track buffer - WPTR 11 pointer to current word in record - BCTR 15 bit counter for formatting - STIME 24 seek time, per cylinder - XTIME 24 transfer time, per word - BTIME 24 controller busy time - -Error handling is as follows: - - error processed as - - not attached pack off line; if STOP_IOE, stop - - end of file ignored - - OS I/O error data error; if STOP_IOE, stop - -2.7 Symbolic Display and Input - -The H316/H516 simulator implements symbolic display and input. Display is -controlled by command line switches: - - -a display as ASCII character - -c display as two character string - -m display instruction mnemonics - -Input parsing is controlled by the first character typed in or by command -line switches: - - ' or -a ASCII character - " or -c two character sixbit string - alphabetic instruction mnemonic - numeric octal number - -Instruction input uses standard H316/H516 assembler syntax. There are six -instruction classes: memory reference, I/O, control, shift, skip, and -operate. - -Memory reference instructions have the format - - memref{*} {C/Z} address{,1} - -where * signifies indirect, C a current sector reference, Z a sector zero -reference, and 1 indexed. The address is an octal number in the range 0 - -077777; if C or Z is specified, the address is a page offset in the range -0 - 0777. Normally, C is not needed; the simulator figures out from the -address what mode to use. However, when referencing memory outside the CPU, -there is no valid PC, and C must be used to specify current sector addressing. - -I/O instructions have the format - - io pulse+device - -The pulse+device is an octal number in the range 0 - 01777. - -Control and operate instructions consist of a single opcode - - opcode - -Shift instructions have the format - - shift n - -where n is an octal number in the range 0-77. - -Skip instructions have the format - - sub-op sub-op sub-op... - -The simulator checks that the combination of sub-opcodes is legal. diff --git a/H316/h316_fhd.c b/H316/h316_fhd.c index c4d36c80..f27061a5 100644 --- a/H316/h316_fhd.c +++ b/H316/h316_fhd.c @@ -1,6 +1,6 @@ /* h316_fhd.c: H316/516 fixed head simulator - Copyright (c) 2003-2005, Robert M. Supnik + Copyright (c) 2003-2006, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ fhd 516-4400 fixed head disk + 15-May-06 RMS Fixed bug in autosize attach (reported by David Gesswein) 04-Jan-04 RMS Changed sim_fsize calling sequence These head-per-track devices are buffered in memory, to minimize overhead. @@ -63,7 +64,7 @@ #define CW2_GETCA(x) (((x) >> CW2_V_CA) & CW2_M_CA) #define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \ - ((double) FH_NUMWD))) + ((double) FH_NUMWD))) /* OTA states */ @@ -93,7 +94,6 @@ int32 fhdio (int32 inst, int32 fnc, int32 dat, int32 dev); t_stat fhd_svc (UNIT *uptr); t_stat fhd_reset (DEVICE *dptr); t_stat fhd_attach (UNIT *uptr, char *cptr); -t_stat fhd_boot (int32 unitno, DEVICE *dptr); t_stat fhd_set_size (UNIT *uptr, int32 val, char *cptr, void *desc); void fhd_go (uint32 dma); void fhd_go1 (uint32 dat); @@ -433,18 +433,15 @@ t_stat fhd_attach (UNIT *uptr, char *cptr) { uint32 sz, sf; uint32 ds_bytes = FH_WDPSF * sizeof (int16); -t_stat r; -r = attach_unit (uptr, cptr); -if (r != SCPE_OK) return r; -if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize (uptr->fileref))) { +if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) { sf = (sz + ds_bytes - 1) / ds_bytes; if (sf >= FH_NUMSF) sf = FH_NUMSF - 1; uptr->flags = (uptr->flags & ~UNIT_SF) | (sf << UNIT_V_SF); } uptr->capac = UNIT_GETSF (uptr->flags) * FH_WDPSF; -return SCPE_OK; +return attach_unit (uptr, cptr); } /* Set size routine */ diff --git a/H316/h316_lp.c b/H316/h316_lp.c index 81834897..59d18784 100644 --- a/H316/h316_lp.c +++ b/H316/h316_lp.c @@ -1,6 +1,6 @@ /* h316_lp.c: Honeywell 316/516 line printer - Copyright (c) 1999-2005, Robert M. Supnik + Copyright (c) 1999-2006, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ lpt line printer + 03-Apr-06 RMS Fixed bug in blanks backscanning (from Theo Engel) 01-Dec-04 RMS Fixed bug in DMA/DMC support 24-Oct-03 RMS Added DMA/DMC support 25-Apr-03 RMS Revised for extended file support @@ -298,7 +299,7 @@ if (lpt_svcst & LPT_SVCSH) { /* shuttling */ } if (lpt_svcst & LPT_SVCPA) { /* paper advance */ SET_INT (INT_LPT); /* interrupt */ - for (i = LPT_WIDTH - 1; i >= 0; i++) { + for (i = LPT_WIDTH - 1; i >= 0; i--) { /* backscan for blanks */ if (lpt_buf[i] != ' ') break; } lpt_buf[i + 1] = 0; diff --git a/H316/h316_mt.c b/H316/h316_mt.c index 324f2433..ece08561 100644 --- a/H316/h316_mt.c +++ b/H316/h316_mt.c @@ -1,6 +1,6 @@ /* h316_mt.c: H316/516 magnetic tape simulator - Copyright (c) 2003-2005, Robert M. Supnik + Copyright (c) 2003-2006, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -25,6 +25,7 @@ mt 516-4100 seven track magnetic tape + 16-Feb-06 RMS Added tape capacity checking 26-Aug-05 RMS Revised to use API for write lock check 08-Feb-05 RMS Fixed error reporting from OCP (found by Philipp Hachtmann) 01-Dec-04 RMS Fixed bug in DMA/DMC support @@ -154,6 +155,8 @@ MTAB mt_mod[] = { { MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL }, { MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT", &sim_tape_set_fmt, &sim_tape_show_fmt, NULL }, + { MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY", + &sim_tape_set_capac, &sim_tape_show_capac, NULL }, { MTAB_XTD|MTAB_VDV, 0, NULL, "IOBUS", &io_set_iobus, NULL, NULL }, { MTAB_XTD|MTAB_VDV, 0, NULL, "DMC", @@ -177,7 +180,7 @@ DEVICE mt_dev = { int32 mtio (int32 inst, int32 fnc, int32 dat, int32 dev) { -uint32 u = dev & 03; +uint32 i, u = dev & 03; UNIT *uptr = mt_dev.units + u; static uint8 wrt_fnc[16] = { /* >0 = wr, 1 = chan op */ 0, 0, 0, 0, 1, 1, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0 @@ -222,6 +225,8 @@ switch (inst) { /* case on opcode */ uptr->FNC = fnc; uptr->UST = 0; mt_busy = 1; + for (i = 0; i < MT_NUMDR; i++) /* clear all EOT flags */ + mt_unit[i].UST = mt_unit[i].UST & ~STA_EOT; sim_activate (uptr, mt_ctime); /* schedule */ break; } @@ -319,6 +324,7 @@ t_stat mt_svc (UNIT *uptr) int32 ch = mt_dib.chan - 1; /* DMA/DMC ch */ uint32 i, c1, c2, c3; t_mtrlnt tbc; +t_bool passed_eot; t_stat st, r = SCPE_OK; if ((uptr->flags & UNIT_ATT) == 0) { /* offline? */ @@ -328,6 +334,7 @@ if ((uptr->flags & UNIT_ATT) == 0) { /* offline? */ return IORETURN (mt_stopioe, SCPE_UNATT); } +passed_eot = sim_tape_eot (uptr); /* passed EOT? */ switch (uptr->FNC) { /* case on function */ case FNC_REW: /* rewind (initial) */ @@ -442,6 +449,8 @@ switch (uptr->FNC) { /* case on function */ /* End of command, process error or schedule end of motion */ +if (!passed_eot && sim_tape_eot (uptr)) /* just passed EOT? */ + uptr->UST = uptr->UST | STA_EOT; if (r != SCPE_OK) { uptr->FNC = FNC_NOP; /* nop function */ mt_busy = 0; /* not busy */ diff --git a/H316/h316_stddev.c b/H316/h316_stddev.c index 9e3cf547..89985214 100644 --- a/H316/h316_stddev.c +++ b/H316/h316_stddev.c @@ -1,6 +1,6 @@ /* h316_stddev.c: Honeywell 316/516 standard devices - Copyright (c) 1999-2005, Robert M. Supnik + Copyright (c) 1999-2006, Robert M. Supnik Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), @@ -28,6 +28,7 @@ tty 316/516-33 teleprinter clk/options 316/516-12 real time clocks/internal options + 03-Apr-06 RMS Fixed bugs in punch state handling (from Theo Engel) 22-Nov-05 RMS Revised for new terminal processing routines 05-Feb-05 RMS Fixed bug in OCP '0001 (found by Philipp Hachtmann) 31-Jan-05 RMS Fixed bug in TTY print (found by Philipp Hachtmann) @@ -608,7 +609,7 @@ else if ((ruptr->flags & UNIT_ATT) && /* TTR attached */ (ruptr->STA & RUNNING)) { /* and running? */ if (ruptr->STA & LF_PEND) { /* lf pending? */ c = 0212; /* char is lf */ - ruptr->STA &= LF_PEND; /* clear flag */ + ruptr->STA &= ~LF_PEND; /* clear flag */ } else { /* normal read */ if ((c = getc (ruptr->fileref)) == EOF) { /* read byte */ @@ -665,7 +666,7 @@ if (ttp_tape_rcvd != 0) { /* prev = tape? */ else if (c7b == TAPE) ttp_tape_rcvd = 2; /* char = TAPE? */ if (ttp_xoff_rcvd != 0) { /* prev = XOFF? */ ttp_xoff_rcvd--; /* decrement state */ - if (ttp_xoff_rcvd == 0) puptr->STA &= RUNNING; /* stop after delay */ + if (ttp_xoff_rcvd == 0) puptr->STA &= ~RUNNING; /* stop after delay */ } else if (c7b == XOFF) ttp_xoff_rcvd = 2; /* char = XOFF? */ if ((c7b == XON) && (ruptr->flags & UNIT_ATT)) { /* char = XON? */ diff --git a/HP2100/hp2100_doc.txt b/HP2100/hp2100_doc.txt deleted file mode 100644 index 59b89f62..00000000 --- a/HP2100/hp2100_doc.txt +++ /dev/null @@ -1,1381 +0,0 @@ -To: Users -From: Bob Supnik -Subj: HP2100 Simulator Usage -Date: 01-Dec-2005 - - COPYRIGHT NOTICE - -The following copyright notice applies to both the SIMH source and binary: - - Original code published in 1993-2005, written by Robert M Supnik - Copyright (c) 1993-2005, Robert M Supnik - - Permission is hereby granted, free of charge, to any person obtaining a - copy of this software and associated documentation files (the "Software"), - to deal in the Software without restriction, including without limitation - the rights to use, copy, modify, merge, publish, distribute, sublicense, - and/or sell copies of the Software, and to permit persons to whom the - Software is furnished to do so, subject to the following conditions: - - The above copyright notice and this permission notice shall be included in - all copies or substantial portions of the Software. - - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - - Except as contained in this notice, the name of Robert M Supnik shall not - be used in advertising or otherwise to promote the sale, use or other dealings - in this Software without prior written authorization from Robert M Supnik. - -This memorandum documents the HP 2100 simulator. - - -1. Simulator Files - -sim/ scp.h - sim_console.h - sim_defs.h - sim_fio.h - sim_rev.h - sim_sock.h - sim_tape.h - sim_timer.h - sim_tmxr.h - scp.c - sim_console.c - sim_fio.c - sim_sock.c - sim_tape.c - sim_timer.c - sim_tmxr.c - -sim/hp2100/ hp2100_cpu.h - hp2100_defs.h - hp2100_fp1.h - hp2100_cpu.c - hp2100_cpu1.c - hp2100_fp.c - hp2100_fp1.c - hp2100_dp.c - hp2100_dq.c - hp2100_dr.c - hp2100_ds.c - hp2100_ipl.c - hp2100_lps.c - hp2100_lpt.c - hp2100_mt.c - hp2100_ms.c - hp2100_mux.c - hp2100_stddev.c - hp2100_sys.c - -2. HP2100 Features - -The HP2100 simulator is configured as follows: - -device simulates -name(s) - -CPU 2116 CPU with up to 32KW of memory - 2100 CPU with up to 32KW of memory - 21MX-M or -E CPU with up to 1024KW of memory - EAU, FP, FFP, IOP, and/or DMS microcode extensions -MP 12892B memory protect -DMA0, DMA1 12895A/12897B direct memory access/dual channel port controller -PTR 12597A duplex register interface with 2748 paper tape reader -PTP 12597A duplex register interface with 2895 paper tape punch -TTY 12531C buffered teleprinter interface with 2752 teleprinter -LPS 12653A printer controller with 2767 line printer - 12566B microcircuit interface with loopback connector -LPT 12845B printer controller with 2607 line printer -CLK 12539C time base generator -MUX,MUXL,MUXM 12920A terminal multiplexor -DP 12557A disk controller with four 2871 drives - 13210A disk controller with four 7900 drives -DQ 12565A disk controller with two 2883 drives -DR 12606B fixed head disk controller with 2770/2771 disk - 12610B drum controller with 2773/2774/2775 drum -DS 13037 disk controller with eight 7905/7906/7920/7925 drives -MT 12559C magnetic tape controller with one 3030 drive -MS 13181A magnetic tape controller with four 7970B drives - 13183A magnetic tape controller with four 7970E drives -IPLI 12566B interprocessor link, input side -IPLO 12566B interprocessor link, output side - -The HP2100 simulator implements several unique stop conditions: - - - decode of an undefined instruction, and STOP_INST is set - - reference to an undefined I/O device, and STOP_DEV is set - - more than INDMAX indirect references are detected during - memory reference address decoding - -The HP2100 LOAD command supports standard absolute binary format. The DUMP -command is not implemented. - -2.1 CPU - -CPU options include choice of model, memory size, and instruction sets. -Several microcode options are simulated: - - EAU Extended Arithmetic Unit - FP Single-Precision Floating Point - FFP Fast FORTRAN Processor - IOP 2000/Access I/O Processor - DMS Dynamic Mapping System - -The general command form is: - - SET {-F} CPU