Added support for changing rq controller type to one of RQDX3, UDA50, RUX50 or KLESI. (from Mike Burke)
This commit is contained in:
Mark Pizzolato
parent
f3bc30aa39
commit
e0bb8fed91
1 changed files with 86 additions and 10 deletions
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@ -24,8 +24,9 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rq RQDX3 disk controller
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rq MSCP disk controller
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09-Dec-12 MB Added support for changing controller type.
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24-Oct-12 MB Added mapped transfers for VAX
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29-Jan-11 HUH Added RC25, RCF25 and RA80 disks
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Not all disk parameters set yet
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@ -140,8 +141,8 @@ extern uint32 cpu_opt;
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#define RQU_UQPM 6 /* UB port model */
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#define RQQ_UQPM 19 /* QB port model */
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#define RQ_UQPM (UNIBUS? RQU_UQPM: RQQ_UQPM)
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#define RQU_MODEL 6 /* UB MSCP ctrl model */
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#define RQQ_MODEL 19 /* QB MSCP ctrl model */
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#define RQU_MODEL 6 /* UB MSCP ctrl model (UDA50A) */
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#define RQQ_MODEL 19 /* QB MSCP ctrl model (RQDX3) */
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#define RQ_MODEL (UNIBUS? RQU_MODEL: RQQ_MODEL)
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#define RQ_HVER 1 /* hardware version */
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#define RQ_SVER 3 /* software version */
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@ -597,12 +598,12 @@ x RA73 70(+1) 21 2667+ 21 1 ? 3920490
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#define RA80_DTYPE 19 /* SDI drive */
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#define RA80_SECT 31 /* +1 spare/track */
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#define RA80_SURF 14
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#define RA80_CYL 546 /* */
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#define RA80_CYL 546 /* */
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#define RA80_TPG RA80_SURF
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#define RA80_GPC 1
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#define RA80_XBN 0 /* */
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#define RA80_DBN 0 /* */
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#define RA80_LBN 237212 /* 31*7*1092 */
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#define RA80_LBN 237212 /* 31*14*546 */
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#define RA80_RCTS 0 /* */
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#define RA80_RCTC 1
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#define RA80_RBN 0 /* */
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@ -610,6 +611,26 @@ x RA73 70(+1) 21 2667+ 21 1 ? 3920490
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#define RA80_MED 0x25641050
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#define RA80_FLGS RQDF_SDI
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/* Controller parameters */
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#define DEFAULT_CTYPE 0
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#define KLESI_CTYPE 1
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#define KLESI_UQPM 1
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#define KLESI_MODEL 1
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#define RUX50_CTYPE 2
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#define RUX50_UQPM 2
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#define RUX50_MODEL 2
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#define UDA50_CTYPE 3
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#define UDA50_UQPM 6
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#define UDA50_MODEL 6
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#define RQDX3_CTYPE 4
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#define RQDX3_UQPM 19
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#define RQDX3_MODEL 19
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struct drvtyp {
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int32 sect; /* sectors */
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int32 surf; /* surfaces */
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@ -659,6 +680,24 @@ static struct drvtyp drv_tab[] = {
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{ 0 }
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};
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struct ctlrtyp {
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uint32 uqpm; /* port model */
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uint32 model; /* controller model */
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char *name; /* name */
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};
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#define RQ_CTLR(d) \
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d##_UQPM, d##_MODEL
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static struct ctlrtyp ctlr_tab[] = {
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{ 0, 0, "DEFAULT" },
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{ RQ_CTLR (KLESI), "KLESI" },
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{ RQ_CTLR (RUX50), "RUX50" },
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{ RQ_CTLR (UDA50), "UDA50" },
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{ RQ_CTLR (RQDX3), "RQDX3" },
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{ 0 }
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};
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extern int32 int_req[IPL_HLVL];
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extern int32 tmr_poll, clk_tps;
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extern uint32 sim_taddr_64;
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@ -688,6 +727,7 @@ typedef struct {
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uint32 credits; /* credits */
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uint32 hat; /* host timer */
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uint32 htmo; /* host timeout */
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uint32 ctype; /* controller type */
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struct uq_ring cq; /* cmd ring */
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struct uq_ring rq; /* rsp ring */
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struct rqpkt pak[RQ_NPKTS]; /* packet queue */
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@ -755,7 +795,9 @@ t_stat rq_detach (UNIT *uptr);
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t_stat rq_boot (int32 unitno, DEVICE *dptr);
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t_stat rq_set_wlk (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat rq_set_type (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat rq_set_ctype (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat rq_show_type (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat rq_show_ctype (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat rq_show_wlk (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat rq_show_ctrl (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat rq_show_unitq (FILE *st, UNIT *uptr, int32 val, void *desc);
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@ -883,6 +925,14 @@ MTAB rq_mod[] = {
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NULL, &rq_show_ctrl, 0 },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, RQ_SH_ALL, "ALL", NULL,
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NULL, &rq_show_ctrl, 0 },
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{ MTAB_XTD | MTAB_VDV, KLESI_CTYPE, NULL, "KLESI",
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&rq_set_ctype, NULL, NULL },
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{ MTAB_XTD | MTAB_VDV, RUX50_CTYPE, NULL, "RUX50",
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&rq_set_ctype, NULL, NULL },
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{ MTAB_XTD | MTAB_VDV, UDA50_CTYPE, NULL, "UDA50",
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&rq_set_ctype, NULL, NULL },
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{ MTAB_XTD | MTAB_VDV, RQDX3_CTYPE, NULL, "RQDX3",
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&rq_set_ctype, NULL, NULL },
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{ MTAB_XTD | MTAB_VUN | MTAB_NMO, 0, "UNITQ", NULL,
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NULL, &rq_show_unitq, 0 },
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{ MTAB_XTD | MTAB_VUN, 0, "WRITE", NULL,
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@ -946,6 +996,8 @@ MTAB rq_mod[] = {
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#endif
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ MTAB_XTD | MTAB_VDV, 0, "TYPE", NULL,
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NULL, &rq_show_ctype, NULL },
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{ 0 }
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};
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@ -1291,7 +1343,8 @@ for (i = 0; i < (lnt >> 1); i++) /* clr buffer */
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zero[i] = 0;
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if (Map_WriteW (base, lnt, zero)) /* zero comm area */
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return rq_fatal (cp, PE_QWE); /* error? */
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cp->sa = SA_S4 | (RQ_UQPM << SA_S4C_V_MOD) | /* send step 4 */
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cp->sa = SA_S4 | /* send step 4 */
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(ctlr_tab[cp->ctype].uqpm << SA_S4C_V_MOD) |
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(RQ_SVER << SA_S4C_V_VER);
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cp->csta = CST_S4; /* set step 4 */
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rq_init_int (cp); /* poke host */
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@ -1724,7 +1777,7 @@ else {
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cp->pak[pkt].d[SCC_CIDB] = 0;
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cp->pak[pkt].d[SCC_CIDC] = 0;
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cp->pak[pkt].d[SCC_CIDD] = (RQ_CLASS << SCC_CIDD_V_CLS) |
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(RQ_MODEL << SCC_CIDD_V_MOD);
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(ctlr_tab[cp->ctype].model << SCC_CIDD_V_MOD);
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cp->pak[pkt].d[SCC_MBCL] = 0; /* max bc */
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cp->pak[pkt].d[SCC_MBCH] = 0;
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}
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@ -2186,7 +2239,7 @@ cp->pak[pkt].d[DTE_CIDA] = 0; /* ctrl ID */
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cp->pak[pkt].d[DTE_CIDB] = 0;
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cp->pak[pkt].d[DTE_CIDC] = 0;
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cp->pak[pkt].d[DTE_CIDD] = (RQ_CLASS << DTE_CIDD_V_CLS) |
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(RQ_MODEL << DTE_CIDD_V_MOD);
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(ctlr_tab[cp->ctype].model << DTE_CIDD_V_MOD);
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cp->pak[pkt].d[DTE_VER] = (RQ_HVER << DTE_VER_V_HVER) |
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(RQ_SVER << DTE_VER_V_SVER);
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cp->pak[pkt].d[DTE_MLUN] = lu; /* MLUN */
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@ -2228,7 +2281,7 @@ cp->pak[pkt].d[HBE_CIDA] = 0; /* ctrl ID */
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cp->pak[pkt].d[HBE_CIDB] = 0;
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cp->pak[pkt].d[HBE_CIDC] = 0;
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cp->pak[pkt].d[HBE_CIDD] = (RQ_CLASS << DTE_CIDD_V_CLS) |
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(RQ_MODEL << DTE_CIDD_V_MOD);
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(ctlr_tab[cp->ctype].model << DTE_CIDD_V_MOD);
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cp->pak[pkt].d[HBE_VER] = (RQ_HVER << HBE_VER_V_HVER) | /* versions */
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(RQ_SVER << HBE_VER_V_SVER);
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cp->pak[pkt].d[HBE_RSV] = 0;
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@ -2256,7 +2309,7 @@ cp->pak[pkt].d[PLF_CIDA] = 0; /* cntl ID */
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cp->pak[pkt].d[PLF_CIDB] = 0;
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cp->pak[pkt].d[PLF_CIDC] = 0;
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cp->pak[pkt].d[PLF_CIDD] = (RQ_CLASS << PLF_CIDD_V_CLS) |
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(RQ_MODEL << PLF_CIDD_V_MOD);
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(ctlr_tab[cp->ctype].model << PLF_CIDD_V_MOD);
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cp->pak[pkt].d[PLF_VER] = (RQ_SVER << PLF_VER_V_SVER) |
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(RQ_HVER << PLF_VER_V_HVER);
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cp->pak[pkt].d[PLF_ERR] = err;
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@ -2667,6 +2720,27 @@ fprintf (st, "%s", drv_tab[GET_DTYPE (uptr->flags)].name);
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return SCPE_OK;
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}
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/* Set controller type */
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t_stat rq_set_ctype (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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MSC *cp = rq_ctxmap[uptr->cnum];
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if (val < 0)
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return SCPE_ARG;
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cp->ctype = val;
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return SCPE_OK;
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}
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/* Show controller type */
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t_stat rq_show_ctype (FILE *st, UNIT *uptr, int32 val, void *desc)
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{
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MSC *cp = rq_ctxmap[uptr->cnum];
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fprintf (st, "%s", ctlr_tab[cp->ctype].name);
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return SCPE_OK;
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}
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/* Device attach */
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t_stat rq_attach (UNIT *uptr, char *cptr)
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@ -2716,6 +2790,8 @@ if (cidx < 0) /* not found??? */
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return SCPE_IERR;
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cp = rq_ctxmap[cidx]; /* get context */
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cp->cnum = cidx; /* init index */
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if (cp->ctype == DEFAULT_CTYPE)
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cp->ctype = (UNIBUS? UDA50_CTYPE : RQDX3_CTYPE);
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#if defined (VM_VAX) /* VAX */
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cp->ubase = 0; /* unit base = 0 */
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