PDP8, VAX750: Fix compiler detected errors in REG initializers

This commit is contained in:
Mark Pizzolato 2016-03-18 15:43:30 -07:00
parent 80321577f9
commit e153b7f224
2 changed files with 2 additions and 3 deletions

View file

@ -201,8 +201,8 @@ REG ct_reg[] = {
{ DRDATA (STIME, ct_stime, 24), PV_LEFT + REG_NZ },
{ DRDATA (CTIME, ct_ctime, 24), PV_LEFT + REG_NZ },
{ FLDATA (STOP_IOE, ct_stopioe, 0) },
{ URDATA (UFNC, ct_unit[0].FNC, 8, 4, 0, CT_NUMDR, 0), REG_HRO },
{ URDATA (UST, ct_unit[0].UST, 8, 2, 0, CT_NUMDR, 0), REG_HRO },
{ URDATA (UFNC, ct_unit[0].FNC, 8, 4, 0, CT_NUMDR, REG_HRO) },
{ URDATA (UST, ct_unit[0].UST, 8, 2, 0, CT_NUMDR, REG_HRO) },
{ URDATA (POS, ct_unit[0].pos, 10, T_ADDR_W, 0,
CT_NUMDR, PV_LEFT | REG_RO) },
{ FLDATA (DEVNUM, ct_dib.dev, 6), REG_HRO },

View file

@ -219,7 +219,6 @@ REG tti_reg[] = {
{ FLDATAD (IE, tti_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") },
{ DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATAD (TIME, tti_unit.wait, 24, "input polling interval"), PV_LEFT },
{ URDATAD (TIMEX, tti_unit, 10, 24, offsetof(UNIT, wait), 5, 0, "input polling interval"), PV_LEFT },
{ NULL }
};