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PDP-4/7/9/15: Added register descriptions to all devices

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This commit is contained in:
Ray Jewhurst 2016-04-07 16:07:57 -04:00 • committed by Mark Pizzolato
parent 54b3ca04a1
commit e67a180518
10 changed files with 195 additions and 195 deletions
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112
PDP18B/pdp18b_cpu.c
View file

@ -457,69 +457,69 @@ UNIT cpu_unit = {
}; };
REG cpu_reg[] = { REG cpu_reg[] = {
{ ORDATA (PC, PC, ADDRSIZE) }, { ORDATAD (PC, PC, ADDRSIZE, "program counter") },
{ ORDATA (AC, LAC, 18) }, { ORDATAD (AC, LAC, 18, "accumulator") },
{ FLDATA (L, LAC, 18) }, { FLDATAD (L, LAC, 18, "link") },
{ ORDATA (MQ, MQ, 18) }, { ORDATAD (MQ, MQ, 18, "multiplier-quotient") },
{ ORDATA (SC, SC, 6) }, { ORDATAD (SC, SC, 6, "shift counter") },
{ FLDATA (EAE_AC_SIGN, eae_ac_sign, 18) }, { FLDATAD (EAE_AC_SIGN, eae_ac_sign, 18, "EAE AC sign") },
{ ORDATA (SR, SR, 18) }, { ORDATAD (SR, SR, 18, "front panel switches") },
{ ORDATA (ASW, ASW, ADDRSIZE) }, { ORDATAD (ASW, ASW, ADDRSIZE, "address switches for RIM load") },
{ ORDATA (IORS, iors, 18), REG_RO }, { ORDATAD (IORS, iors, 18, "IORS register"), REG_RO },
{ BRDATA (INT, int_hwre, 8, 32, API_HLVL+1), REG_RO }, { BRDATAD (INT, int_hwre, 8, 32, API_HLVL+1, "interrupt requests, 0:3 = API levels 0 to 3, 4 = PI level"), REG_RO },
{ FLDATA (INT_PEND, int_pend, 0), REG_RO }, { FLDATAD (INT_PEND, int_pend, 0, "interrupt pending"), REG_RO },
{ FLDATA (ION, ion, 0) }, { FLDATAD (ION, ion, 0, "interrupt enable") },
{ ORDATA (ION_DELAY, ion_defer, 2) }, { ORDATAD (ION_DELAY, ion_defer, 2, "interrupt enable delay") },
#if defined (PDP7) #if defined (PDP7)
{ FLDATA (TRAPM, usmd, 0) }, { FLDATAD (TRAPM, usmd, 0, "trap mode") },
{ FLDATA (TRAPP, trap_pending, 0) }, { FLDATAD (TRAPP, trap_pending, 0, "trap pending") },
{ FLDATA (EXTM, memm, 0) }, { FLDATAD (EXTM, memm, 0, "extend mode") },
{ FLDATA (EXTM_INIT, memm_init, 0) }, { FLDATAD (EXTM_INIT, memm_init, 0, "exit mode value after reset") },
{ FLDATA (EMIRP, emir_pending, 0) }, { FLDATAD (EMIRP, emir_pending, 0, "EMIR instruction pending") },
#endif #endif
#if defined (PDP9) #if defined (PDP9)
{ FLDATA (APIENB, api_enb, 0) }, { FLDATAD (APIENB, api_enb, 0, "api enable") },
{ ORDATA (APIREQ, api_req, 8) }, { ORDATAD (APIREQ, api_req, 8, "api requesting levels") },
{ ORDATA (APIACT, api_act, 8) }, { ORDATAD (APIACT, api_act, 8, "api active levels") },
{ ORDATA (BR, BR, ADDRSIZE) }, { ORDATAD (BR, BR, ADDRSIZE, "memory protection bounds") },
{ FLDATA (USMD, usmd, 0) }, { FLDATAD (USMD, usmd, 0, "user mode") },
{ FLDATA (USMDBUF, usmd_buf, 0) }, { FLDATAD (USMDBUF, usmd_buf, 0, "user mode buffer") },
{ FLDATA (USMDDEF, usmd_defer, 0) }, { FLDATAD (USMDDEF, usmd_defer, 0, "user mode load defer") },
{ FLDATA (NEXM, nexm, 0) }, { FLDATAD (NEXM, nexm, 0, "non-existent memory violation") },
{ FLDATA (PRVN, prvn, 0) }, { FLDATAD (PRVN, prvn, 0, "privilege violation") },
{ FLDATA (TRAPP, trap_pending, 0) }, { FLDATAD (TRAPP, trap_pending, 0, "trap pending") },
{ FLDATA (EXTM, memm, 0) }, { FLDATAD (EXTM, memm, 0, "extend mode") },
{ FLDATA (EXTM_INIT, memm_init, 0) }, { FLDATAD (EXTM_INIT, memm_init, 0, "extend mode value after reset") },
{ FLDATA (EMIRP, emir_pending, 0) }, { FLDATAD (EMIRP, emir_pending, 0, "EMIR instruction pending") },
{ FLDATA (RESTP, rest_pending, 0) }, { FLDATAD (RESTP, rest_pending, 0, "DBR or RES instruction pending") },
{ FLDATA (PWRFL, int_hwre[API_PWRFL], INT_V_PWRFL) }, { FLDATAD (PWRFL, int_hwre[API_PWRFL], INT_V_PWRFL, "power fail pending") },
#endif #endif
#if defined (PDP15) #if defined (PDP15)
{ FLDATA (ION_INH, ion_inh, 0) }, { FLDATAD (ION_INH, ion_inh, 0, "interrupt inhibit") },
{ FLDATA (APIENB, api_enb, 0) }, { FLDATAD (APIENB, api_enb, 0, "API enable") },
{ ORDATA (APIREQ, api_req, 8) }, { ORDATAD (APIREQ, api_req, 8, "API requesting levels") },
{ ORDATA (APIACT, api_act, 8) }, { ORDATAD (APIACT, api_act, 8, "API active levels") },
{ ORDATA (XR, XR, 18) }, { ORDATAD (XR, XR, 18, "index register") },
{ ORDATA (LR, LR, 18) }, { ORDATAD (LR, LR, 18, "limit register") },
{ ORDATA (BR, BR, 18) }, { ORDATAD (BR, BR, 18, "memory protection bounds") },
{ ORDATA (RR, RR, 18) }, { ORDATAD (RR, RR, 18, "memory protection relocation") },
{ ORDATA (MMR, MMR, 18) }, { ORDATAD (MMR, MMR, 18, "memory protection control") },
{ FLDATA (USMD, usmd, 0) }, { FLDATAD (USMD, usmd, 0, "user mode") },
{ FLDATA (USMDBUF, usmd_buf, 0) }, { FLDATAD (USMDBUF, usmd_buf, 0, "user mode buffer") },
{ FLDATA (USMDDEF, usmd_defer, 0) }, { FLDATAD (USMDDEF, usmd_defer, 0, "user mode load defer") },
{ FLDATA (NEXM, nexm, 0) }, { FLDATAD (NEXM, nexm, 0, "non-existent memory violation") },
{ FLDATA (PRVN, prvn, 0) }, { FLDATAD (PRVN, prvn, 0, "privilege violation") },
{ FLDATA (TRAPP, trap_pending, 0) }, { FLDATAD (TRAPP, trap_pending, 0, "trap pending") },
{ FLDATA (BANKM, memm, 0) }, { FLDATAD (BANKM, memm, 0, "bank mode") },
{ FLDATA (BANKM_INIT, memm_init, 0) }, { FLDATAD (BANKM_INIT, memm_init, 0, "bank mode value after reset") },
{ FLDATA (RESTP, rest_pending, 0) }, { FLDATAD (RESTP, rest_pending, 0, "DBR or RES instruction pending") },
{ FLDATA (PWRFL, int_hwre[API_PWRFL], INT_V_PWRFL) }, { FLDATAD (PWRFL, int_hwre[API_PWRFL], INT_V_PWRFL, "power fail flag") },
#endif #endif
{ BRDATA (PCQ, pcq, 8, ADDRSIZE, PCQ_SIZE), REG_RO+REG_CIRC }, { BRDATAD (PCQ, pcq, 8, ADDRSIZE, PCQ_SIZE, "PC prior to last JMP, JMS, CAL or interrupt; most recent PC change first stop on undefineds instruction"), REG_RO+REG_CIRC },
{ ORDATA (PCQP, pcq_p, 6), REG_HRO }, { ORDATA (PCQP, pcq_p, 6), REG_HRO },
{ FLDATA (STOP_INST, stop_inst, 0) }, { FLDATAD (STOP_INST, stop_inst, 0, "stop on defined instruction") },
{ DRDATA (XCT_MAX, xct_max, 8), PV_LEFT + REG_NZ }, { DRDATAD (XCT_MAX, xct_max, 8, "max numb of chained XCT's allowed"), PV_LEFT + REG_NZ },
{ ORDATA (WRU, sim_int_char, 8) }, { ORDATAD (WRU, sim_int_char, 8, "interrupt character") },
{ NULL } }; { NULL } };
MTAB cpu_mod[] = { MTAB cpu_mod[] = {

16
PDP18B/pdp18b_drm.c
View file

@ -100,14 +100,14 @@ UNIT drm_unit = {
}; };
REG drm_reg[] = { REG drm_reg[] = {
{ ORDATA (DA, drm_da, 9) }, { ORDATAD (DA, drm_da, 9, "drum address (sector number") },
{ ORDATA (MA, drm_ma, 16) }, { ORDATAD (MA, drm_ma, 16, "current memor address") },
{ FLDATA (INT, int_hwre[API_DRM], INT_V_DRM) }, { FLDATAD (INT, int_hwre[API_DRM], INT_V_DRM, "interrupt pending flag") },
{ FLDATA (DONE, int_hwre[API_DRM], INT_V_DRM) }, { FLDATAD (DONE, int_hwre[API_DRM], INT_V_DRM, "device done flag") },
{ FLDATA (ERR, drm_err, 0) }, { FLDATAD (ERR, drm_err, 0, "error flag") },
{ ORDATA (WLK, drm_wlk, 32) }, { ORDATAD (WLK, drm_wlk, 32, "write lock switches") },
{ DRDATA (TIME, drm_time, 24), REG_NZ + PV_LEFT }, { DRDATAD (TIME, drm_time, 24, "rotational latency, per word"), REG_NZ + PV_LEFT },
{ FLDATA (STOP_IOE, drm_stopioe, 0) }, { FLDATAD (STOP_IOE, drm_stopioe, 0, "stop on I/O error") },
{ ORDATA (DEVNO, drm_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, drm_dib.dev, 6), REG_HRO },
{ NULL } { NULL }
}; };

32
PDP18B/pdp18b_dt.c
View file

@ -396,30 +396,30 @@ UNIT dt_unit[] = {
}; };
REG dt_reg[] = { REG dt_reg[] = {
{ ORDATA (DTSA, dtsa, 18) }, { ORDATAD (DTSA, dtsa, 18, "status register A") },
{ ORDATA (DTSB, dtsb, 18) }, { ORDATAD (DTSB, dtsb, 18, "status register B") },
{ ORDATA (DTDB, dtdb, 18) }, { ORDATAD (DTDB, dtdb, 18, "data buffer") },
{ FLDATA (INT, int_hwre[API_DTA], INT_V_DTA) }, { FLDATAD (INT, int_hwre[API_DTA], INT_V_DTA, "interrupt pending flag") },
#if defined (DTA_V_ENB) #if defined (DTA_V_ENB)
{ FLDATA (ENB, dtsa, DTA_V_ENB) }, { FLDATAD (ENB, dtsa, DTA_V_ENB, "interrupt enable flag") },
#endif #endif
{ FLDATA (DTF, dtsb, DTB_V_DTF) }, { FLDATAD (DTF, dtsb, DTB_V_DTF, "DECtape flag") },
#if defined (DTB_V_BEF) #if defined (DTB_V_BEF)
{ FLDATA (BEF, dtsb, DTB_V_BEF) }, { FLDATAD (BEF, dtsb, DTB_V_BEF, "block and flag") },
#endif #endif
{ FLDATA (ERF, dtsb, DTB_V_ERF) }, { FLDATAD (ERF, dtsb, DTB_V_ERF, "error flag") },
{ DRDATA (LTIME, dt_ltime, 31), REG_NZ }, { DRDATAD (LTIME, dt_ltime, 31, "time between lines"), REG_NZ },
{ DRDATA (DCTIME, dt_dctime, 31), REG_NZ }, { DRDATAD (DCTIME, dt_dctime, 31, "time to declarate to a full stop"), REG_NZ },
{ ORDATA (SUBSTATE, dt_substate, 2) }, { ORDATAD (SUBSTATE, dt_substate, 2, "read/write command substate") },
{ DRDATA (LBLK, dt_logblk, 12), REG_HIDDEN }, { DRDATA (LBLK, dt_logblk, 12), REG_HIDDEN },
{ URDATA (POS, dt_unit[0].pos, 10, T_ADDR_W, 0, { URDATAD (POS, dt_unit[0].pos, 10, T_ADDR_W, 0,
DT_NUMDR, PV_LEFT | REG_RO) }, DT_NUMDR, PV_LEFT | REG_RO, "positions in lines, units 0 to 7") },
{ URDATA (STATT, dt_unit[0].STATE, 8, 18, 0, { URDATAD (STATT, dt_unit[0].STATE, 8, 18, 0,
DT_NUMDR, REG_RO) }, DT_NUMDR, REG_RO, "unit state, units 0 to 7") },
{ URDATA (LASTT, dt_unit[0].LASTT, 10, T_ADDR_W, 0, { URDATA (LASTT, dt_unit[0].LASTT, 10, T_ADDR_W, 0,
DT_NUMDR, REG_HRO) }, DT_NUMDR, REG_HRO) },
{ ORDATA (DEVNO, dt_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, dt_dib.dev, 6), REG_HRO },
{ FLDATA (STOP_OFFR, dt_stopoffr, 0) }, { FLDATAD (STOP_OFFR, dt_stopoffr, 0, "stop on off-reel error") },
#if defined (TC02) #if defined (TC02)
{ ORDATA (APIVEC, api_vec[API_DTA][INT_V_DTA], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_DTA][INT_V_DTA], 6), REG_HRO },
#endif #endif

28
PDP18B/pdp18b_fpp.c
View file

@ -194,20 +194,20 @@ extern int32 Jms_word (int32 t);
UNIT fpp_unit = { UDATA (NULL, 0, 0) }; UNIT fpp_unit = { UDATA (NULL, 0, 0) };
REG fpp_reg[] = { REG fpp_reg[] = {
{ ORDATA (FIR, fir, 12) }, { ORDATAD (FIR, fir, 12, "floating instruction register") },
{ ORDATA (EPA, fma.exp, 18) }, { ORDATAD (EPA, fma.exp, 18, "EPA (A exponent") },
{ FLDATA (FMAS, fma.sign, 0) }, { FLDATAD (FMAS, fma.sign, 0, "FMA sign") },
{ ORDATA (FMAH, fma.hi, 17) }, { ORDATAD (FMAH, fma.hi, 17, "FMA<1:17>") },
{ ORDATA (FMAL, fma.lo, 18) }, { ORDATAD (FMAL, fma.lo, 18, "FMA<18:35>") },
{ ORDATA (EPB, fmb.exp, 18) }, { ORDATAD (EPB, fmb.exp, 18, "EPB (B exponent)") },
{ FLDATA (FMBS, fmb.sign, 0) }, { FLDATAD (FMBS, fmb.sign, 0, "FMB sign") },
{ ORDATA (FMBH, fmb.hi, 17) }, { ORDATAD (FMBH, fmb.hi, 17, "FMB<1:17>") },
{ ORDATA (FMBL, fmb.lo, 18) }, { ORDATAD (FMBL, fmb.lo, 18, "FMB<18:35>" ) },
{ FLDATA (FGUARD, fguard, 0) }, { FLDATAD (FGUARD, fguard, 0, "guard bit") },
{ ORDATA (FMQH, fmq.hi, 17) }, { ORDATAD (FMQH, fmq.hi, 17, "FMQ<1:17>") },
{ ORDATA (FMQL, fmq.lo, 18) }, { ORDATAD (FMQL, fmq.lo, 18, "FMQ<18:35>") },
{ ORDATA (JEA, jea, 15) }, { ORDATAD (JEA, jea, 15, "exception address register") },
{ FLDATA (STOP_FPP, stop_fpp, 0) }, { FLDATAD (STOP_FPP, stop_fpp, 0, "stop if FB15 instruction decoded while FB15 is disabled") },
{ NULL } { NULL }
}; };

74
PDP18B/pdp18b_lp.c
View file

@ -106,17 +106,17 @@ UNIT lp62_unit = {
}; };
REG lp62_reg[] = { REG lp62_reg[] = {
{ ORDATA (BUF, lp62_unit.buf, 8) }, { ORDATAD (BUF, lp62_unit.buf, 8, "last data item processed") },
{ FLDATA (INT, int_hwre[API_LPT], INT_V_LPT) }, { FLDATAD (INT, int_hwre[API_LPT], INT_V_LPT, "interrupt pending flag") },
{ FLDATA (DONE, int_hwre[API_LPT], INT_V_LPT) }, { FLDATAD (DONE, int_hwre[API_LPT], INT_V_LPT, "device done flag") },
{ FLDATA (SPC, int_hwre[API_LPTSPC], INT_V_LPTSPC) }, { FLDATAD (SPC, int_hwre[API_LPTSPC], INT_V_LPTSPC, "spacing done flag") },
{ DRDATA (BPTR, lp62_bp, 6) }, { DRDATAD (BPTR, lp62_bp, 6, "print buffer pointer") },
{ ORDATA (STATE, lp62_spc, 6), REG_HRO }, { ORDATA (STATE, lp62_spc, 6), REG_HRO },
{ FLDATA (OVRPR, lp62_ovrpr, 0), REG_HRO }, { FLDATA (OVRPR, lp62_ovrpr, 0), REG_HRO },
{ DRDATA (POS, lp62_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, lp62_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
{ DRDATA (TIME, lp62_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, lp62_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATA (STOP_IOE, lp62_stopioe, 0) }, { FLDATAD (STOP_IOE, lp62_stopioe, 0, "stop on I/O error") },
{ BRDATA (LBUF, lp62_buf, 8, 8, LP62_BSIZE) }, { BRDATAD (LBUF, lp62_buf, 8, 8, LP62_BSIZE, "line buffer") },
{ ORDATA (DEVNO, lp62_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, lp62_dib.dev, 6), REG_HRO },
{ NULL } { NULL }
}; };
@ -292,19 +292,19 @@ UNIT lp647_unit = {
}; };
REG lp647_reg[] = { REG lp647_reg[] = {
{ ORDATA (BUF, lp647_unit.buf, 8) }, { ORDATAD (BUF, lp647_unit.buf, 8, "last data item processed") },
{ FLDATA (INT, int_hwre[API_LPT], INT_V_LPT) }, { FLDATAD (INT, int_hwre[API_LPT], INT_V_LPT, "interrupt pending flag") },
{ FLDATA (DONE, lp647_don, 0) }, { FLDATAD (DONE, lp647_don, 0, "device done flag") },
#if defined (PDP9) #if defined (PDP9)
{ FLDATA (ENABLE, lp647_ie, 0) }, { FLDATAD (ENABLE, lp647_ie, 0, "interrupt enable") },
#endif #endif
{ FLDATA (ERR, lp647_err, 0) }, { FLDATAD (ERR, lp647_err, 0, "error flag") },
{ DRDATA (BPTR, lp647_bp, 7) }, { DRDATAD (BPTR, lp647_bp, 7, "print buffer pointer") },
{ ORDATA (SCMD, lp647_iot, 6), REG_HRO }, { ORDATA (SCMD, lp647_iot, 6), REG_HRO },
{ DRDATA (POS, lp647_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, lp647_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
{ DRDATA (TIME, lp647_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, lp647_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATA (STOP_IOE, lp647_stopioe, 0) }, { FLDATAD (STOP_IOE, lp647_stopioe, 0, "stop on I/O error") },
{ BRDATA (LBUF, lp647_buf, 8, 8, LP647_BSIZE) }, { BRDATAD (LBUF, lp647_buf, 8, 8, LP647_BSIZE, "line buffer") },
{ ORDATA (DEVNO, lp647_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, lp647_dib.dev, 6), REG_HRO },
{ NULL } { NULL }
}; };
@ -531,14 +531,14 @@ UNIT lp09_unit = {
}; };
REG lp09_reg[] = { REG lp09_reg[] = {
{ ORDATA (BUF, lp09_unit.buf, 7) }, { ORDATAD (BUF, lp09_unit.buf, 7, "last data item processed") },
{ FLDATA (INT, int_hwre[API_LPT], INT_V_LPT) }, { FLDATAD (INT, int_hwre[API_LPT], INT_V_LPT, "interrupt pending flag") },
{ FLDATA (DONE, lp09_don, 0) }, { FLDATAD (DONE, lp09_don, 0, "device done flag") },
{ FLDATA (ENABLE, lp09_ie, 0) }, { FLDATAD (ENABLE, lp09_ie, 0, "interrupt enable") },
{ FLDATA (ERR, lp09_err, 0) }, { FLDATAD (ERR, lp09_err, 0, "error flag") },
{ DRDATA (POS, lp09_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, lp09_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
{ DRDATA (TIME, lp09_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, lp09_unit.wait, 24, "time from initiation to inturrupt"), PV_LEFT },
{ FLDATA (STOP_IOE, lp09_stopioe, 0) }, { FLDATAD (STOP_IOE, lp09_stopioe, 0, "stop on I/O error") },
{ ORDATA (DEVNO, lp09_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, lp09_dib.dev, 6), REG_HRO },
{ ORDATA (APIVEC, api_vec[API_LPT][INT_V_LPT], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_LPT][INT_V_LPT], 6), REG_HRO },
{ NULL } { NULL }
@ -714,16 +714,16 @@ UNIT lp15_unit = {
}; };
REG lp15_reg[] = { REG lp15_reg[] = {
{ ORDATA (STA, lp15_sta, 18) }, { ORDATAD (STA, lp15_sta, 18, "status register") },
{ FLDATA (INT, int_hwre[API_LPT], INT_V_LPT) }, { FLDATAD (INT, int_hwre[API_LPT], INT_V_LPT, "interrupt pending flag") },
{ FLDATA (ENABLE, lp15_ie, 0) }, { FLDATAD (ENABLE, lp15_ie, 0, "interrupt enable") },
{ DRDATA (LCNT, lp15_lc, 9) }, { DRDATAD (LCNT, lp15_lc, 9, "line counter") },
{ DRDATA (BPTR, lp15_bp, 8) }, { DRDATAD (BPTR, lp15_bp, 8, "print buffer pointer") },
{ FLDATA (MODE, lp15_mode, 0) }, { FLDATAD (MODE, lp15_mode, 0, "mode flag") },
{ DRDATA (POS, lp15_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, lp15_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
{ DRDATA (TIME, lp15_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, lp15_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATA (STOP_IOE, lp15_stopioe, 0) }, { FLDATAD (STOP_IOE, lp15_stopioe, 0, "stop on I/O error") },
{ BRDATA (LBUF, lp15_buf, 8, 8, LP15_BSIZE) }, { BRDATAD (LBUF, lp15_buf, 8, 8, LP15_BSIZE, "line buffer") },
{ ORDATA (DEVNO, lp15_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, lp15_dib.dev, 6), REG_HRO },
{ ORDATA (APIVEC, api_vec[API_LPT][INT_V_LPT], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_LPT][INT_V_LPT], 6), REG_HRO },
{ NULL } { NULL }

16
PDP18B/pdp18b_mt.c
View file

@ -171,14 +171,14 @@ UNIT mt_unit[] = {
}; };
REG mt_reg[] = { REG mt_reg[] = {
{ ORDATA (STA, mt_sta, 18) }, { ORDATAD (STA, mt_sta, 18, "main status") },
{ ORDATA (CMD, mt_cu, 18) }, { ORDATAD (CMD, mt_cu, 18, "command") },
{ FLDATA (INT, int_hwre[API_MTA], INT_V_MTA) }, { FLDATAD (INT, int_hwre[API_MTA], INT_V_MTA, "interrupt pending flag") },
{ FLDATA (STOP_IOE, mt_stopioe, 0) }, { FLDATAD (STOP_IOE, mt_stopioe, 0, "stop on I/O error") },
{ DRDATA (TIME, mt_time, 24), PV_LEFT }, { DRDATAD (TIME, mt_time, 24, "record delay"), PV_LEFT },
{ URDATA (UST, mt_unit[0].USTAT, 8, 16, 0, MT_NUMDR, 0) }, { URDATAD (UST, mt_unit[0].USTAT, 8, 16, 0, MT_NUMDR, 0, "unit status, units 0 to 7") },
{ URDATA (POS, mt_unit[0].pos, 10, T_ADDR_W, 0, { URDATAD (POS, mt_unit[0].pos, 10, T_ADDR_W, 0,
MT_NUMDR, PV_LEFT | REG_RO) }, MT_NUMDR, PV_LEFT | REG_RO, "position units 0 to 7") },
{ ORDATA (DEVNO, mt_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, mt_dib.dev, 6), REG_HRO },
{ ORDATA (APIVEC, api_vec[API_MTA][INT_V_MTA], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_MTA][INT_V_MTA], 6), REG_HRO },
{ NULL } { NULL }

16
PDP18B/pdp18b_rf.c
View file

@ -149,14 +149,14 @@ UNIT rf_unit = {
}; };
REG rf_reg[] = { REG rf_reg[] = {
{ ORDATA (STA, rf_sta, 18) }, { ORDATAD (STA, rf_sta, 18, "status") },
{ ORDATA (DA, rf_da, 22) }, { ORDATAD (DA, rf_da, 22, "current disk address") },
{ ORDATA (BUF, rf_dbuf, 18) }, { ORDATAD (BUF, rf_dbuf, 18, "data buffer (diagnostic only)") },
{ FLDATA (INT, int_hwre[API_RF], INT_V_RF) }, { FLDATAD (INT, int_hwre[API_RF], INT_V_RF, "interrupt pending flag") },
{ BRDATA (WLK, rf_wlk, 8, 16, RF_NUMDK) }, { BRDATAD (WLK, rf_wlk, 8, 16, RF_NUMDK, "write lock switches for disks 0 to 7") },
{ DRDATA (TIME, rf_time, 24), PV_LEFT + REG_NZ }, { DRDATAD (TIME, rf_time, 24, "rotational delay per word"), PV_LEFT + REG_NZ },
{ FLDATA (BURST, rf_burst, 0) }, { FLDATAD (BURST, rf_burst, 0, "burst flag") },
{ FLDATA (STOP_IOE, rf_stopioe, 0) }, { FLDATAD (STOP_IOE, rf_stopioe, 0, "stop on I/O error") },
{ DRDATA (CAPAC, rf_unit.capac, 31), PV_LEFT + REG_HRO }, { DRDATA (CAPAC, rf_unit.capac, 31), PV_LEFT + REG_HRO },
{ ORDATA (DEVNO, rf_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, rf_dib.dev, 6), REG_HRO },
{ ORDATA (APIVEC, api_vec[API_RF][INT_V_RF], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_RF][INT_V_RF], 6), REG_HRO },

20
PDP18B/pdp18b_rp.c
View file

@ -195,16 +195,16 @@ UNIT rp_unit[] = {
}; };
REG rp_reg[] = { REG rp_reg[] = {
{ ORDATA (STA, rp_sta, 18) }, { ORDATAD (STA, rp_sta, 18, "status A") },
{ ORDATA (STB, rp_stb, 18) }, { ORDATAD (STB, rp_stb, 18, "status B") },
{ ORDATA (DA, rp_da, 18) }, { ORDATAD (DA, rp_da, 18, "disk address") },
{ ORDATA (MA, rp_ma, 18) }, { ORDATAD (MA, rp_ma, 18, "current memory address") },
{ ORDATA (WC, rp_wc, 18) }, { ORDATAD (WC, rp_wc, 18, "word count") },
{ FLDATA (INT, int_hwre[API_RP], INT_V_RP) }, { FLDATAD (INT, int_hwre[API_RP], INT_V_RP, "interrupt pending flag") },
{ FLDATA (BUSY, rp_busy, 0) }, { FLDATAD (BUSY, rp_busy, 0, "control busy flag") },
{ FLDATA (STOP_IOE, rp_stopioe, 0) }, { FLDATAD (STOP_IOE, rp_stopioe, 0, "stop on I/O error") },
{ DRDATA (STIME, rp_swait, 24), PV_LEFT }, { DRDATAD (STIME, rp_swait, 24, "seek time per cylinder"), PV_LEFT },
{ DRDATA (RTIME, rp_rwait, 24), PV_LEFT }, { DRDATAD (RTIME, rp_rwait, 24, "rotational delay"), PV_LEFT },
{ ORDATA (DEVNO, rp_dib.dev, 6), REG_HRO }, { ORDATA (DEVNO, rp_dib.dev, 6), REG_HRO },
{ ORDATA (APIVEC, api_vec[API_RP][INT_V_RP], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_RP][INT_V_RP], 6), REG_HRO },
{ NULL } { NULL }

58
PDP18B/pdp18b_stddev.c
View file

@ -177,14 +177,14 @@ DIB clk_dib = { 0, 0, &clk_iors, { NULL } };
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 16000 }; UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), 16000 };
REG clk_reg[] = { REG clk_reg[] = {
{ FLDATA (INT, int_hwre[API_CLK], INT_V_CLK) }, { FLDATAD (INT, int_hwre[API_CLK], INT_V_CLK, "interrupt pending flag") },
{ FLDATA (DONE, int_hwre[API_CLK], INT_V_CLK) }, { FLDATAD (DONE, int_hwre[API_CLK], INT_V_CLK, "device done flag") },
{ FLDATA (ENABLE, clk_state, 0) }, { FLDATAD (ENABLE, clk_state, 0, "clock enable") },
#if defined (PDP15) #if defined (PDP15)
{ ORDATA (TASKTIMER, clk_task_timer, 18) }, { ORDATAD (TASKTIMER, clk_task_timer, 18, "task timer") },
{ DRDATA (TASKLAST, clk_task_last, 32), REG_HRO }, { DRDATA (TASKLAST, clk_task_last, 32), REG_HRO },
#endif #endif
{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT }, { DRDATAD (TIME, clk_unit.wait, 24, "clock frequency"), REG_NZ + PV_LEFT },
{ DRDATA (TPS, clk_tps, 8), PV_LEFT + REG_HRO }, { DRDATA (TPS, clk_tps, 8), PV_LEFT + REG_HRO },
{ ORDATA (APIVEC, api_vec[API_CLK][INT_V_CLK], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_CLK][INT_V_CLK], 6), REG_HRO },
{ NULL } { NULL }
@ -224,16 +224,16 @@ UNIT ptr_unit = {
}; };
REG ptr_reg[] = { REG ptr_reg[] = {
{ ORDATA (BUF, ptr_unit.buf, 18) }, { ORDATAD (BUF, ptr_unit.buf, 18, "last data item processed") },
{ FLDATA (INT, int_hwre[API_PTR], INT_V_PTR) }, { FLDATAD (INT, int_hwre[API_PTR], INT_V_PTR, "interrupt pending flag") },
{ FLDATA (DONE, int_hwre[API_PTR], INT_V_PTR) }, { FLDATAD (DONE, int_hwre[API_PTR], INT_V_PTR, "device done flag") },
#if defined (IOS_PTRERR) #if defined (IOS_PTRERR)
{ FLDATA (ERR, ptr_err, 0) }, { FLDATAD (ERR, ptr_err, 0, "error flag") },
#endif #endif
{ ORDATA (STATE, ptr_state, 5), REG_HRO }, { ORDATA (STATE, ptr_state, 5), REG_HRO },
{ DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, ptr_unit.pos, T_ADDR_W, "position in the input file"), PV_LEFT },
{ DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, ptr_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ FLDATA (STOP_IOE, ptr_stopioe, 0) }, { FLDATAD(STOP_IOE, ptr_stopioe, 0, "stop on I/O error") },
{ ORDATA (APIVEC, api_vec[API_PTR][INT_V_PTR], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_PTR][INT_V_PTR], 6), REG_HRO },
{ NULL } { NULL }
}; };
@ -267,15 +267,15 @@ UNIT ptp_unit = {
}; };
REG ptp_reg[] = { REG ptp_reg[] = {
{ ORDATA (BUF, ptp_unit.buf, 8) }, { ORDATAD (BUF, ptp_unit.buf, 8, "last data item processed") },
{ FLDATA (INT, int_hwre[API_PTP], INT_V_PTP) }, { FLDATAD (INT, int_hwre[API_PTP], INT_V_PTP, "interrupt pending flag") },
{ FLDATA (DONE, int_hwre[API_PTP], INT_V_PTP) }, { FLDATAD (DONE, int_hwre[API_PTP], INT_V_PTP, "device done flag") },
#if defined (IOS_PTPERR) #if defined (IOS_PTPERR)
{ FLDATA (ERR, ptp_err, 0) }, { FLDATAD (ERR, ptp_err, 0, "error flag") },
#endif #endif
{ DRDATA (POS, ptp_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, ptp_unit.pos, T_ADDR_W, "position in the output file"), PV_LEFT },
{ DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, ptp_unit.wait, 24, "time from I/O initiation to inturrupt"), PV_LEFT },
{ FLDATA (STOP_IOE, ptp_stopioe, 0) }, { FLDATAD (STOP_IOE, ptp_stopioe, 0, "stop on I/O error") },
{ NULL } { NULL }
}; };
@ -323,17 +323,17 @@ DIB tti_dib = { DEV_TTI, 1, &tti_iors, { &tti } };
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE+TT_MODE_KSR+TTUF_HDX, 0), 0 }; UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE+TT_MODE_KSR+TTUF_HDX, 0), 0 };
REG tti_reg[] = { REG tti_reg[] = {
{ ORDATA (BUF, tti_unit.buf, TTI_WIDTH) }, { ORDATAD (BUF, tti_unit.buf, TTI_WIDTH, "last data item processed") },
#if defined (KSR28) #if defined (KSR28)
{ ORDATA (BUF2ND, tti_2nd, TTI_WIDTH), REG_HRO }, { ORDATA (BUF2ND, tti_2nd, TTI_WIDTH), REG_HRO },
#endif #endif
{ FLDATA (INT, int_hwre[API_TTI], INT_V_TTI) }, { FLDATAD (INT, int_hwre[API_TTI], INT_V_TTI, "interrupt pending flag") },
{ FLDATA (DONE, int_hwre[API_TTI], INT_V_TTI) }, { FLDATAD (DONE, int_hwre[API_TTI], INT_V_TTI, "device done flag") },
#if defined (PDP15) #if defined (PDP15)
{ FLDATA (FDPX, tti_fdpx, 0) }, { FLDATA (FDPX, tti_fdpx, 0) },
#endif #endif
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, tti_unit.pos, T_ADDR_W, "number of characters input"), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, tti_unit.wait, 24, "input polling interval (if 0, the keyboard is polled synchronously with line clock)"), PV_LEFT },
{ NULL } { NULL }
}; };
@ -384,14 +384,14 @@ DIB tto_dib = { DEV_TTO, 1, &tto_iors, { &tto } };
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_KSR, 0), 1000 }; UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_KSR, 0), 1000 };
REG tto_reg[] = { REG tto_reg[] = {
{ ORDATA (BUF, tto_unit.buf, TTO_WIDTH) }, { ORDATAD (BUF, tto_unit.buf, TTO_WIDTH, "last data item processed") },
#if defined (KSR28) #if defined (KSR28)
{ FLDATA (SHIFT, tty_shift, 0), REG_HRO }, { FLDATA (SHIFT, tty_shift, 0), REG_HRO },
#endif #endif
{ FLDATA (INT, int_hwre[API_TTO], INT_V_TTO) }, { FLDATAD (INT, int_hwre[API_TTO], INT_V_TTO, "interrupt pending flag") },
{ FLDATA (DONE, int_hwre[API_TTO], INT_V_TTO) }, { FLDATAD (DONE, int_hwre[API_TTO], INT_V_TTO, "device done flag") },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT }, { DRDATAD (POS, tto_unit.pos, T_ADDR_W, "number of characters output"), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT }, { DRDATAD (TIME, tto_unit.wait, 24, "time from I/O initiation to interrupt"), PV_LEFT },
{ NULL } { NULL }
}; };

18
PDP18B/pdp18b_tt1.c
View file

@ -102,10 +102,10 @@ DIB ttix_dib = {
UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), KBD_POLL_WAIT }; UNIT ttix_unit = { UDATA (&ttix_svc, UNIT_IDLE|UNIT_ATTABLE, 0), KBD_POLL_WAIT };
REG ttix_reg[] = { REG ttix_reg[] = {
{ BRDATA (BUF, ttix_buf, 8, 8, TTX_MAXL) }, { BRDATAD (BUF, ttix_buf, 8, 8, TTX_MAXL, "last character received, lines 0 to 3/15") },
{ ORDATA (DONE, ttix_done, TTX_MAXL) }, { ORDATAD (DONE, ttix_done, TTX_MAXL, "input ready flags, line 0 on right") },
{ FLDATA (INT, int_hwre[API_TTI1], INT_V_TTI1) }, { FLDATAD (INT, int_hwre[API_TTI1], INT_V_TTI1, "interrupt pending flag") },
{ DRDATA (TIME, ttix_unit.wait, 24), REG_NZ + PV_LEFT }, { DRDATAD (TIME, ttix_unit.wait, 24, "keyboard polling interval"), REG_NZ + PV_LEFT },
{ ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO }, { ORDATA (DEVNUM, ttix_dib.dev, 6), REG_HRO },
#if defined (PDP15) #if defined (PDP15)
{ ORDATA (APIVEC, api_vec[API_TTI1][INT_V_TTI1], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_TTI1][INT_V_TTI1], 6), REG_HRO },
@ -164,11 +164,11 @@ UNIT ttox_unit[] = {
}; };
REG ttox_reg[] = { REG ttox_reg[] = {
{ BRDATA (BUF, ttox_buf, 8, 8, TTX_MAXL) }, { BRDATAD (BUF, ttox_buf, 8, 8, TTX_MAXL, "last character transmitted, lines 0 to 3/15") },
{ ORDATA (DONE, ttox_done, TTX_MAXL) }, { ORDATAD (DONE, ttox_done, TTX_MAXL, "output ready flags, line 0 on right") },
{ FLDATA (INT, int_hwre[API_TTO1], INT_V_TTO1) }, { FLDATAD (INT, int_hwre[API_TTO1], INT_V_TTO1, "interrupt pending flag") },
{ URDATA (TIME, ttox_unit[0].wait, 10, 24, 0, { URDATAD (TIME, ttox_unit[0].wait, 10, 24, 0,
TTX_MAXL, PV_LEFT) }, TTX_MAXL, PV_LEFT, "time from initiation to interrupt, lines 0 to 3/15") },
#if defined (PDP15) #if defined (PDP15)
{ ORDATA (APIVEC, api_vec[API_TTO1][INT_V_TTO1], 6), REG_HRO }, { ORDATA (APIVEC, api_vec[API_TTO1][INT_V_TTO1], 6), REG_HRO },
#endif #endif