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HP3000: Preset the unit wait field. (from Dave Bryan)

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PROBLEM:  Attempting to LOAD after a RESTORE of an MPE session aborts
   the simulator with an "integer division by zero" exception.

   OBSERVATION:  Stopping the simulator during an idle MPE session,
   saving the state to a file, exiting, restarting, restoring, and
   attempting to perform a cold load aborts with a "divide by 0" error.

   CAUSE:  The "clk_update_counter" routine in hp3000_clk.c is called as
   part of the instruction postlude to update the clock's counter
   register.  A calculation divides the elapsed time since the last tick
   by the clock unit's "wait" value.  The developer's manual stated that
   this field is saved and restored automatically, but this is not true.
   When the simulator is restarted, the "wait" field is initially zero.
   If "clk_update_counter" is called before the clock's event service
   routine resets the value, the calculation will divide by zero, which
   causes the abort.

   RESOLUTION:  Modify "clk_reg" (hp3000_clk.c) to preset the unit wait
   field with the MPE clock resolution value.
This commit is contained in:
Mark Pizzolato 2016-07-10 06:49:22 -07:00
parent 07f99bb8c3
commit e93b55b488
1 changed files with 2 additions and 1 deletions
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3
HP3000/hp3000_clk.c
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@ -25,6 +25,7 @@
CLK HP 30135A System Clock/Fault Logging Interface CLK HP 30135A System Clock/Fault Logging Interface
08-Jul-16 JDB Preset the unit wait field
09-Jun-16 JDB Clarified the IRQ FF set code in DRESETINT 09-Jun-16 JDB Clarified the IRQ FF set code in DRESETINT
08-Jun-16 JDB Corrected %d format to %u for unsigned values 08-Jun-16 JDB Corrected %d format to %u for unsigned values
21-Mar-16 JDB Changed inbound_value and outbound_value types to HP_WORD 21-Mar-16 JDB Changed inbound_value and outbound_value types to HP_WORD
@ -392,7 +393,7 @@ static DIB clk_dib = {
/* Unit list */ /* Unit list */
static UNIT clk_unit = { static UNIT clk_unit = {
UDATA (&clk_service, UNIT_IDLE | UNIT_CALTIME, 0) UDATA (&clk_service, UNIT_IDLE | UNIT_CALTIME, 0), mS (1)
}; };
/* Register list */ /* Register list */