diff --git a/Intel-Systems/common/i8080.c b/Intel-Systems/common/i8080.c index d2bfd226..98fd1a4b 100644 --- a/Intel-Systems/common/i8080.c +++ b/Intel-Systems/common/i8080.c @@ -169,9 +169,9 @@ uint32 IM = 0; /* Interrupt Mask Register */ uint8 xack = 0; /* XACK signal */ uint32 int_req = 0; /* Interrupt request */ uint8 INTA = 0; // interrupt acknowledge -int32 PCX; /* External view of PC */ -int32 PCY; /* Internal view of PC */ -int32 PC; +uint16 PCX; /* External view of PC */ +uint16 PCY; /* Internal view of PC */ +uint16 PC; UNIT *uptr; uint16 port; //port used in any IN/OUT uint16 addr; //addr used for operand fetch diff --git a/Intel-Systems/common/i8237.c b/Intel-Systems/common/i8237.c index c443bb9f..0c736e18 100644 --- a/Intel-Systems/common/i8237.c +++ b/Intel-Systems/common/i8237.c @@ -264,7 +264,7 @@ uint8 i8237_rFx(t_bool io, uint8 data); /* external function prototypes */ -extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8), uint16); +extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8); /* globals */ @@ -429,7 +429,7 @@ t_stat i8237_svc(UNIT *uptr) /* Reset routine */ -t_stat i8237_reset(DEVICE *dptr, uint16 base) +t_stat i8237_reset(DEVICE *dptr) { if (i8237_devnum > I8237_NUM) { sim_printf("i8237_reset: too many devices!\n"); diff --git a/Intel-Systems/common/i8253.c b/Intel-Systems/common/i8253.c index 5c0ec31e..44deb308 100644 --- a/Intel-Systems/common/i8253.c +++ b/Intel-Systems/common/i8253.c @@ -145,7 +145,7 @@ t_stat i8253_reset (DEVICE *dptr) { uint8 devnum; - for (devnum=0; devnumcapac = size; /* set EPROM size */ - EPROM_unit->u3 = base & 0xFFFF; /* set EPROM base */ + EPROM_unit.capac = size; /* set EPROM size */ + EPROM_unit.u3 = base & 0xFFFF; /* set EPROM base */ sim_printf(" EPROM: 0%04XH bytes at base 0%04XH\n", - EPROM_unit->capac, EPROM_unit->u3); + EPROM_unit.capac, EPROM_unit.u3); return SCPE_OK; } @@ -135,9 +135,9 @@ uint8 EPROM_get_mbyte(uint16 addr) { uint8 val; - if ((addr >= EPROM_unit->u3) && ((uint32) addr <= (EPROM_unit->u3 + EPROM_unit->capac))) { + if ((addr >= EPROM_unit.u3) && ((uint32) addr <= (EPROM_unit.u3 + EPROM_unit.capac))) { SET_XACK(1); /* good memory address */ - val = *((uint8 *)EPROM_unit->filebuf + (addr - EPROM_unit->u3)); + val = *((uint8 *)EPROM_unit.filebuf + (addr - EPROM_unit.u3)); val &= 0xFF; return val; } else { diff --git a/Intel-Systems/common/ioc-cont.c b/Intel-Systems/common/ioc-cont.c index d075fe20..828e1ba7 100644 --- a/Intel-Systems/common/ioc-cont.c +++ b/Intel-Systems/common/ioc-cont.c @@ -71,7 +71,7 @@ /* external globals */ -extern int32 PCX; +extern uint16 PCX; /* function prototypes */ diff --git a/Intel-Systems/common/ipb.c b/Intel-Systems/common/ipb.c index 93837f69..a86931a4 100644 --- a/Intel-Systems/common/ipb.c +++ b/Intel-Systems/common/ipb.c @@ -69,19 +69,19 @@ int onetime = 0; /* extern globals */ -extern uint32 PCX; /* program counter */ +extern uint16 PCX; /* program counter */ extern UNIT i8255_unit; extern UNIT EPROM_unit; extern UNIT RAM_unit; extern UNIT ipc_cont_unit; extern UNIT ioc_cont_unit; -extern DEVICE *i8080_dev; -extern DEVICE *i8251_dev; -extern DEVICE *i8253_dev; -extern DEVICE *i8255_dev; -extern DEVICE *i8259_dev; -extern DEVICE *ipc_cont_dev; -extern DEVICE *ioc_cont_dev; +extern DEVICE i8080_dev; +extern DEVICE i8251_dev; +extern DEVICE i8253_dev; +extern DEVICE i8255_dev; +extern DEVICE i8259_dev; +extern DEVICE ipc_cont_dev; +extern DEVICE ioc_cont_dev; t_stat SBC_config(void) { @@ -110,13 +110,13 @@ t_stat SBC_reset (DEVICE *dptr) multibus_cfg(); onetime++; } - i8080_reset(i8080_dev); - i8251_reset(i8251_dev); - i8253_reset(i8253_dev); - i8255_reset(i8255_dev); - i8259_reset(i8259_dev); - ipc_cont_reset(ipc_cont_dev); - ioc_cont_reset(ioc_cont_dev); + i8080_reset(&i8080_dev); + i8251_reset(&i8251_dev); + i8253_reset(&i8253_dev); + i8255_reset(&i8255_dev); + i8259_reset(&i8259_dev); + ipc_cont_reset(&ipc_cont_dev); + ioc_cont_reset(&ioc_cont_dev); return SCPE_OK; } diff --git a/Intel-Systems/common/ipc-cont.c b/Intel-Systems/common/ipc-cont.c index 21438c0c..ec6009f1 100644 --- a/Intel-Systems/common/ipc-cont.c +++ b/Intel-Systems/common/ipc-cont.c @@ -36,7 +36,7 @@ /* function prototypes */ t_stat ipc_cont_cfg(uint8 base, uint8 devnum); -uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum); /* ipc_cont*/ +uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum); /* ipc_cont*/ t_stat ipc_cont_reset (DEVICE *dptr); /* external function prototypes */ @@ -45,12 +45,12 @@ extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); /* globals */ -UNIT ipc_cont_unit[] = { - { UDATA (0, 0, 0) }, /* ipc_cont*/ -}; +UNIT ipc_cont_unit = + { UDATA (0, 0, 0) }; /* ipc_cont*/ + REG ipc_cont_reg[] = { - { HRDATA (CONTROL0, ipc_cont_unit[0].u3, 8) }, /* ipc_cont */ + { HRDATA (CONTROL0, ipc_cont_unit.u3, 8) }, /* ipc_cont */ { NULL } }; @@ -68,9 +68,9 @@ DEBTAB ipc_cont_debug[] = { /* address width is set to 16 bits to use devices in 8086/8088 implementations */ DEVICE ipc_cont_dev = { - "IPC-CONT", //name - ipc_cont_unit, //units - ipc_cont_reg, //registers + "IPC-CONT", //name + &ipc_cont_unit, //units + ipc_cont_reg, //registers NULL, //modifiers 1, //numunits 16, //aradix @@ -80,14 +80,14 @@ DEVICE ipc_cont_dev = { 8, //dwidth NULL, //examine NULL, //deposit - NULL, //reset + NULL, //reset NULL, //boot NULL, //attach NULL, //detach NULL, //ctxt 0, //flags 0, //dctrl - ipc_cont_debug, //debflags + ipc_cont_debug, //debflags NULL, //msize NULL //lname }; @@ -106,7 +106,7 @@ t_stat ipc_cont_cfg(uint8 base, uint8 devnum) t_stat ipc_cont_reset(DEVICE *dptr) { - ipc_cont_unit[0].u3 = 0x00; /* ipc reset */ + ipc_cont_unit.u3 = 0x00; /* ipc reset */ return SCPE_OK; } @@ -119,40 +119,40 @@ t_stat ipc_cont_reset(DEVICE *dptr) uint8 ipc_cont(t_bool io, uint8 data, uint8 devnum) { if (io == 0) { /* read status port */ - return ipc_cont_unit[0].u3; + return ipc_cont_unit.u3; } else { /* write control port */ //this simulates an 74LS259 register //d0-d2 address the reg(in reverse order!), d3 is the data to be latched (inverted) switch(data & 0x07) { case 5: //interrupt enable 8085 INTR if(data & 0x08) //bit low - ipc_cont_unit[0].u3 &= 0xBF; + ipc_cont_unit.u3 &= 0xBF; else //bit high - ipc_cont_unit[0].u3 |= 0x20; + ipc_cont_unit.u3 |= 0x20; break; case 4: //*selboot ROM @ 0E800h if(data & 0x08) //bit low - ipc_cont_unit[0].u3 &= 0xEF; + ipc_cont_unit.u3 &= 0xEF; else //bit high - ipc_cont_unit[0].u3 |= 0x10; + ipc_cont_unit.u3 |= 0x10; break; case 2: //*startup ROM @ 00000h if(data & 0x08) //bit low - ipc_cont_unit[0].u3 &= 0xFB; + ipc_cont_unit.u3 &= 0xFB; else //bit high - ipc_cont_unit[0].u3 |= 0x04; + ipc_cont_unit.u3 |= 0x04; break; case 1: //override inhibit other multibus users if(data & 0x08) //bit low - ipc_cont_unit[0].u3 &= 0xFD; + ipc_cont_unit.u3 &= 0xFD; else //bit high - ipc_cont_unit[0].u3 |= 0x02; + ipc_cont_unit.u3 |= 0x02; break; case 0: //aux prom enable if(data & 0x08) //bit low - ipc_cont_unit[0].u3 &= 0xFE; + ipc_cont_unit.u3 &= 0xFE; else //bit high - ipc_cont_unit[0].u3 |= 0x01; + ipc_cont_unit.u3 |= 0x01; break; default: break; diff --git a/Intel-Systems/common/ipc.c b/Intel-Systems/common/ipc.c index fb42e7b8..ff7fe24a 100644 --- a/Intel-Systems/common/ipc.c +++ b/Intel-Systems/common/ipc.c @@ -73,13 +73,13 @@ extern UNIT EPROM_unit; extern UNIT RAM_unit; extern UNIT ipc_cont_unit; extern UNIT ioc_cont_unit; -extern DEVICE *i8080_dev; -extern DEVICE *i8251_dev; -extern DEVICE *i8253_dev; -extern DEVICE *i8255_dev; -extern DEVICE *i8259_dev; -extern DEVICE *ipc_cont_dev; -extern DEVICE *ioc_cont_dev; +extern DEVICE i8080_dev; +extern DEVICE i8251_dev; +extern DEVICE i8253_dev; +extern DEVICE i8255_dev; +extern DEVICE i8259_dev; +extern DEVICE ipc_cont_dev; +extern DEVICE ioc_cont_dev; /* globals */ @@ -112,13 +112,13 @@ t_stat SBC_reset (DEVICE *dptr) multibus_cfg(); onetime++; } - i8080_reset(i8080_dev); - i8251_reset(i8251_dev); - i8253_reset(i8253_dev); - i8255_reset(i8255_dev); - i8259_reset(i8259_dev); - ipc_cont_reset(ipc_cont_dev); - ioc_cont_reset(ioc_cont_dev); + i8080_reset(&i8080_dev); + i8251_reset(&i8251_dev); + i8253_reset(&i8253_dev); + i8255_reset(&i8255_dev); + i8259_reset(&i8259_dev); + ipc_cont_reset(&ipc_cont_dev); + ioc_cont_reset(&ioc_cont_dev); return SCPE_OK; } diff --git a/Intel-Systems/common/iram8.c b/Intel-Systems/common/iram8.c index 87014b6b..8d540441 100644 --- a/Intel-Systems/common/iram8.c +++ b/Intel-Systems/common/iram8.c @@ -95,7 +95,7 @@ t_stat RAM_cfg(uint16 base, uint16 size) { RAM_unit.capac = size & 0xFFFF; /* set RAM size */ RAM_unit.u3 = base & 0xFFFF; /* set RAM base */ - RAM_unit.filebuf = (uint8 *)malloc(size * sizeof(uint8)); + RAM_unit.filebuf = (uint8 *)calloc(size, size * sizeof(uint8)); if (RAM_unit.filebuf == NULL) { sim_printf (" RAM: Malloc error\n"); return SCPE_MEM; diff --git a/Intel-Systems/common/isbc064.c b/Intel-Systems/common/isbc064.c index cc17913d..82301795 100644 --- a/Intel-Systems/common/isbc064.c +++ b/Intel-Systems/common/isbc064.c @@ -56,7 +56,7 @@ void isbc064_put_mbyte(uint16 addr, uint8 val); /* external globals */ -extern uint32 PCX; /* program counter */ +extern uint16 PCX; /* program counter */ extern uint8 xack; /* isbc064 Standard SIMH Device Data Structures */ diff --git a/Intel-Systems/common/isbc201.c b/Intel-Systems/common/isbc201.c index fd9af33f..28d28d7a 100644 --- a/Intel-Systems/common/isbc201.c +++ b/Intel-Systems/common/isbc201.c @@ -206,7 +206,7 @@ /* external globals */ -extern int32 PCX; +extern uint16 PCX; /* external function prototypes */ diff --git a/Intel-Systems/common/isbc202.c b/Intel-Systems/common/isbc202.c index 162af5d8..fb0dbfdb 100644 --- a/Intel-Systems/common/isbc202.c +++ b/Intel-Systems/common/isbc202.c @@ -184,7 +184,7 @@ /* external globals */ -extern int32 PCX; +extern uint16 PCX; /* external function prototypes */ diff --git a/Intel-Systems/common/isbc206.c b/Intel-Systems/common/isbc206.c index be613ca2..b68802b7 100644 --- a/Intel-Systems/common/isbc206.c +++ b/Intel-Systems/common/isbc206.c @@ -174,7 +174,7 @@ /* external globals */ -extern int32 PCX; +extern uint16 PCX; /* external function prototypes */ diff --git a/Intel-Systems/common/isbc208.c b/Intel-Systems/common/isbc208.c index cd803bc9..0b3f16f2 100644 --- a/Intel-Systems/common/isbc208.c +++ b/Intel-Systems/common/isbc208.c @@ -510,7 +510,7 @@ extern int32 multibus_get_mbyte(uint16 addr); /* external globals */ -extern int32 PCX; +extern uint16 PCX; /* 8237 physical register definitions */ uint16 i8237_r0; // 8237 ch 0 address register diff --git a/Intel-Systems/common/isbc464.c b/Intel-Systems/common/isbc464.c index 673ffd98..356b73d7 100644 --- a/Intel-Systems/common/isbc464.c +++ b/Intel-Systems/common/isbc464.c @@ -53,7 +53,7 @@ extern uint8 xack; /* XACK signal */ /* isbc464 Standard I/O Data Structures */ -UNIT isbc464_unit[] = { +UNIT isbc464_unit = { UDATA (NULL, UNIT_ATTABLE+UNIT_BINK+UNIT_ROABLE+UNIT_RO+UNIT_BUFABLE+UNIT_MUSTBUF, 0), 0 }; @@ -70,7 +70,7 @@ DEBTAB isbc464_debug[] = { DEVICE isbc464_dev = { "SBC464", //name - isbc464_unit, //units + &isbc464_unit, //units NULL, //registers NULL, //modifiers 1, //numunits @@ -101,8 +101,8 @@ t_stat isbc464_cfg(uint16 base, uint16 size) { sim_printf(" sbc464: 0%04XH bytes at base 0%04XH\n", size, base); - isbc464_unit->capac = size; //set size - isbc464_unit->u3 = base; //and base + isbc464_unit.capac = size; //set size + isbc464_unit.u3 = base; //and base return SCPE_OK; } @@ -135,9 +135,9 @@ uint8 isbc464_get_mbyte(uint16 addr) uint8 *fbuf; if ((isbc464_dev.flags & DEV_DIS) == 0) { - org = isbc464_unit->u3; - len = isbc464_unit->capac; - fbuf = (uint8 *) isbc464_unit->filebuf; + org = isbc464_unit.u3; + len = isbc464_unit.capac; + fbuf = (uint8 *) isbc464_unit.filebuf; if ((addr >= org) && (addr < (org + len))) { SET_XACK(1); /* good memory address */ val = *(fbuf + (addr - org)); @@ -158,8 +158,8 @@ void isbc464_put_mbyte(uint16 addr, uint8 val) uint32 org, len; if ((isbc464_dev.flags & DEV_DIS) == 0) { - org = isbc464_unit->u3; - len = isbc464_unit->capac; + org = isbc464_unit.u3; + len = isbc464_unit.capac; if ((addr >= org) && (addr < (org + len))) { // SET_XACK(1); /* good memory address */ sim_printf ("isbc464_put_mbyte: Read-only Memory\n"); diff --git a/Intel-Systems/common/multibus.c b/Intel-Systems/common/multibus.c index 9d073c55..5dea5d52 100644 --- a/Intel-Systems/common/multibus.c +++ b/Intel-Systems/common/multibus.c @@ -77,7 +77,7 @@ int32 mbirq = 0; /* set no multibus interrupts */ extern uint8 xack; /* XACK signal */ extern int32 int_req; /* i8080 INT signal */ -extern int32 PCX; +extern uint16 PCX; extern DEVICE isbc064_dev; extern DEVICE isbc464_dev; extern DEVICE isbc201_dev; diff --git a/Intel-Systems/common/zx200a.c b/Intel-Systems/common/zx200a.c index 446ca791..89c50acb 100644 --- a/Intel-Systems/common/zx200a.c +++ b/Intel-Systems/common/zx200a.c @@ -198,7 +198,7 @@ extern void multibus_put_mbyte(uint16 addr, uint8 val); /* external globals */ -extern int32 PCX; +extern uint16 PCX; /* internal function prototypes */ diff --git a/Intel-Systems/ibmpcxt/system_defs.h b/Intel-Systems/ibmpcxt/system_defs.h index a9e0172b..ca46d04b 100644 --- a/Intel-Systems/ibmpcxt/system_defs.h +++ b/Intel-Systems/ibmpcxt/system_defs.h @@ -28,7 +28,7 @@ #include #include -#include "sim_defs.h" /* simulator defns */ +#include "sim_defs.h" /* simulator defns */ /* set the base I/O address and device count for the 8237 */ #define I8237_BASE_0 0x000 @@ -82,11 +82,11 @@ #define ADDRMASK16 0xFFFF #define ADDRMASK20 0xFFFFF -#define MAXMEMSIZE20 0xFFFFF /* 8080 max memory size */ +#define MAXMEMSIZE20 0xFFFFF /* 8080 max memory size */ -#define MEMSIZE (i8088_unit.capac) /* 8088 actual memory size */ -#define ADDRMASK (MAXMEMSIZE - 1) /* 8088 address mask */ -#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) +#define MEMSIZE (i8088_unit.capac) /* 8088 actual memory size */ +#define ADDRMASK (MAXMEMSIZE - 1) /* 8088 address mask */ +#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) /* debug definitions */ @@ -101,10 +101,10 @@ /* Simulator stop codes */ -#define STOP_RSRV 1 /* must be 1 */ -#define STOP_HALT 2 /* HALT */ -#define STOP_IBKPT 3 /* breakpoint */ -#define STOP_OPCODE 4 /* Invalid Opcode */ -#define STOP_IO 5 /* I/O error */ -#define STOP_MEM 6 /* Memory error */ +#define STOP_RSRV 1 /* must be 1 */ +#define STOP_HALT 2 /* HALT */ +#define STOP_IBKPT 3 /* breakpoint */ +#define STOP_OPCODE 4 /* Invalid Opcode */ +#define STOP_IO 5 /* I/O error */ +#define STOP_MEM 6 /* Memory error */ diff --git a/Intel-Systems/imds-220/system_defs.h b/Intel-Systems/imds-220/system_defs.h index 93a719be..57e38b4c 100644 --- a/Intel-Systems/imds-220/system_defs.h +++ b/Intel-Systems/imds-220/system_defs.h @@ -60,19 +60,19 @@ /* set the base and size for the EPROM on the MDS 220 */ #define ROM_BASE 0x0000 -#define ROM_SIZE 0x1000 +#define ROM_SIZE 0x0FFF #define ROM_DISABLE 1 #define EPROM_NUM 1 /* set the base and size for the RAM on the MDS 220 */ #define RAM_BASE 0x0000 -#define RAM_SIZE 0x8000 +#define RAM_SIZE 0x7FFF //board definitions for the multibus /* set the base I/O address for the iSBC 201 */ -#define SBC201_BASE 0x78 +#define SBC201_BASE 0x88 #define SBC201_INT INT_2 -#define SBC201_NUM 0 +#define SBC201_NUM 1 /* set the base I/O address for the iSBC 202 */ #define SBC202_BASE 0x78 @@ -92,16 +92,16 @@ /* set the base for the zx-200a disk controller */ #define ZX200A_BASE 0x78 #define ZX200A_INT INT_2 -#define ZX200A_NUM 1 +#define ZX200A_NUM 0 /* set the base and size for the iSBC 064 RAM*/ #define SBC064_BASE 0x8000 -#define SBC064_SIZE 0x8000 +#define SBC064_SIZE 0x7FFF #define SBC064_NUM 1 /* set the base and size for the iSBC 464 ROM */ #define SBC464_BASE 0xA800 -#define SBC464_SIZE 0x4800 +#define SBC464_SIZE 0x47FF #define SBC464_NUM 0 /* set INTR for CPU */ diff --git a/Intel-Systems/imds-800/front_panel.c b/Intel-Systems/imds-800/front_panel.c index d3dfe492..109e40e3 100644 --- a/Intel-Systems/imds-800/front_panel.c +++ b/Intel-Systems/imds-800/front_panel.c @@ -43,7 +43,7 @@ extern t_stat EPROM_cfg(uint16 base, uint16 size); /* external globals */ -extern DEVICE *EPROM_dev; +extern DEVICE EPROM_dev; t_stat fp_cfg(void) { @@ -57,7 +57,7 @@ t_stat fp_cfg(void) t_stat fp_reset (void) { - EPROM_reset(EPROM_dev); + EPROM_reset(&EPROM_dev); return SCPE_OK; } diff --git a/Intel-Systems/imds-800/monitor.c b/Intel-Systems/imds-800/monitor.c index 8384a942..f02e2822 100644 --- a/Intel-Systems/imds-800/monitor.c +++ b/Intel-Systems/imds-800/monitor.c @@ -48,8 +48,8 @@ extern uint8 i3214_monitor_do_boot(t_bool io, uint8 data, uint8 devnum); // external globals extern uint32 PCX; /* program counter */ -extern DEVICE *i8251_dev; -extern DEVICE *EPROM1_dev; +extern DEVICE i8251_dev; +extern DEVICE EPROM1_dev; extern uint8 monitor_boot; // globals @@ -69,8 +69,8 @@ t_stat monitor_cfg(void) t_stat monitor_reset (void) { monitor_boot = 0x00; - i8251_reset(i8251_dev); - EPROM1_reset(EPROM1_dev); + i8251_reset(&i8251_dev); + EPROM1_reset(&EPROM1_dev); return SCPE_OK; } diff --git a/Intel-Systems/imds-810/cpu.c b/Intel-Systems/imds-810/cpu.c index e7614fa0..9778d400 100644 --- a/Intel-Systems/imds-810/cpu.c +++ b/Intel-Systems/imds-810/cpu.c @@ -62,7 +62,7 @@ extern t_stat multibus_cfg(void); // external globals -extern uint32 PCX; /* program counter */ +extern uint16 PCX; /* program counter */ extern DEVICE i3214_dev; extern DEVICE i8080_dev; extern uint8 EPROM_enable; diff --git a/Intel-Systems/imds-810/front_panel.c b/Intel-Systems/imds-810/front_panel.c index e4b4d87a..83416ab8 100644 --- a/Intel-Systems/imds-810/front_panel.c +++ b/Intel-Systems/imds-810/front_panel.c @@ -45,7 +45,7 @@ extern t_stat EPROM_cfg(uint16 base, uint16 size); // external globals extern UNIT EPROM_unit; //1702 EPROM -extern uint32 PCX; /* program counter */ +extern uint16 PCX; /* program counter */ // fp configuration diff --git a/Intel-Systems/imds-810/monitor.c b/Intel-Systems/imds-810/monitor.c index de18ea30..bd6a8b40 100644 --- a/Intel-Systems/imds-810/monitor.c +++ b/Intel-Systems/imds-810/monitor.c @@ -49,10 +49,10 @@ extern t_stat i8251_cfg(uint8 base, uint8 size); // external globals -extern uint32 PCX; /* program counter */ +extern uint16 PCX; /* program counter */ extern UNIT EPROM1_unit; //8316 PROM -extern DEVICE *i8251_dev; -extern DEVICE *EPROM1_dev; +extern DEVICE i8251_dev; +extern DEVICE EPROM1_dev; // globals @@ -75,8 +75,8 @@ t_stat monitor_cfg(void) t_stat monitor_reset (void) { monitor_boot = 0x00; - i8251_reset(i8251_dev); - EPROM1_reset(EPROM1_dev); + i8251_reset(&i8251_dev); + EPROM1_reset(&EPROM1_dev); return SCPE_OK; } diff --git a/Intel-Systems/isys8010/isbc8010.c b/Intel-Systems/isys8010/isbc8010.c index d0e348e5..6e7e3bd8 100644 --- a/Intel-Systems/isys8010/isbc8010.c +++ b/Intel-Systems/isys8010/isbc8010.c @@ -48,12 +48,12 @@ void put_mword(uint16 addr, uint16 val); /* external globals */ extern uint8 i8255_C[4]; //port C byte I/O -extern DEVICE *i8080_dev; -extern DEVICE *i8251_dev; -extern DEVICE *i8255_dev; -extern DEVICE *EPROM_dev; +extern DEVICE i8080_dev; +extern DEVICE i8251_dev; +extern DEVICE i8255_dev; +extern DEVICE EPROM_dev; extern UNIT EPROM_unit; -extern DEVICE *RAM_dev; +extern DEVICE RAM_dev; extern UNIT RAM_unit; /* external function prototypes */ @@ -99,9 +99,9 @@ t_stat SBC_reset (DEVICE *dptr) multibus_cfg(); onetime++; } - i8080_reset(i8080_dev); - i8251_reset(i8251_dev); - i8255_reset(i8255_dev); + i8080_reset(&i8080_dev); + i8251_reset(&i8251_dev); + i8255_reset(&i8255_dev); return SCPE_OK; } diff --git a/Intel-Systems/isys8010/system_defs.h b/Intel-Systems/isys8010/system_defs.h index 171cae14..02d9cc27 100644 --- a/Intel-Systems/isys8010/system_defs.h +++ b/Intel-Systems/isys8010/system_defs.h @@ -76,7 +76,7 @@ /* set the base I/O address for the iSBC 208 */ #define SBC208_BASE 0x40 #define SBC208_INT INT_2 -#define SBC208_NUM 1 +#define SBC208_NUM 0 /* set the base for the zx-200a disk controller */ #define ZX200A_BASE 0x78 diff --git a/Intel-Systems/isys8020/isbc8020.c b/Intel-Systems/isys8020/isbc8020.c index 95cd1b99..7bb07775 100644 --- a/Intel-Systems/isys8020/isbc8020.c +++ b/Intel-Systems/isys8020/isbc8020.c @@ -51,27 +51,27 @@ extern uint8 i8255_C[4]; //port C byte I/O extern uint8 multibus_get_mbyte(uint16 addr); extern void multibus_put_mbyte(uint16 addr, uint8 val); extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ -extern DEVICE *i8080_dev; +extern DEVICE i8080_dev; extern t_stat i8251_reset (DEVICE *dptr); extern uint8 i8251s(t_bool io, uint8 data, uint8 devnum); extern uint8 i8251d(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8251_dev; +extern DEVICE i8251_dev; extern t_stat i8253_reset (DEVICE *dptr); extern uint8 i8253t0(t_bool io, uint8 data, uint8 devnum); extern uint8 i8253t1(t_bool io, uint8 data, uint8 devnum); extern uint8 i8253t2(t_bool io, uint8 data, uint8 devnum); extern uint8 i8253c(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8253_dev; +extern DEVICE i8253_dev; extern t_stat i8255_reset (DEVICE *dptr); extern uint8 i8255a(t_bool io, uint8 data, uint8 devnum); extern uint8 i8255b(t_bool io, uint8 data, uint8 devnum); extern uint8 i8255c(t_bool io, uint8 data, uint8 devnum); extern uint8 i8255s(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8255_dev; +extern DEVICE i8255_dev; extern t_stat i8259_reset (DEVICE *dptr); extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum); extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8259_dev; +extern DEVICE i8259_dev; extern uint8 EPROM_get_mbyte(uint16 addr); extern UNIT EPROM_unit; extern t_stat EPROM_reset (DEVICE *dptr); @@ -86,7 +86,7 @@ extern t_stat i8259_cfg(uint8 base, uint8 devnum); extern t_stat RAM_cfg(uint16 base, uint16 size); extern t_stat EPROM_cfg(uint16 base, uint16 size); extern t_stat multibus_cfg(); -extern uint16 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); +extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8); // globals @@ -115,12 +115,12 @@ t_stat SBC_reset (DEVICE *dptr) multibus_cfg(); onetime++; } - i8080_reset(i8080_dev); - i8251_reset(i8251_dev); - i8253_reset(i8253_dev); - i8255_reset(i8255_dev); - i8255_reset(i8255_dev); - i8259_reset(i8259_dev); + i8080_reset(&i8080_dev); + i8251_reset(&i8251_dev); + i8253_reset(&i8253_dev); + i8255_reset(&i8255_dev); + i8255_reset(&i8255_dev); + i8259_reset(&i8259_dev); return SCPE_OK; } diff --git a/Intel-Systems/isys8024/isbc8024.c b/Intel-Systems/isys8024/isbc8024.c index 5689f41f..ccca17d2 100644 --- a/Intel-Systems/isys8024/isbc8024.c +++ b/Intel-Systems/isys8024/isbc8024.c @@ -47,34 +47,34 @@ t_stat SBC_reset (DEVICE *dptr); /* external globals */ extern uint8 i8255_C[4]; //port C byte I/O -extern int32 PCX; /* External view of PC */ +extern uint16 PCX; /* External view of PC */ /* external function prototypes */ extern uint8 multibus_get_mbyte(uint16 addr); extern void multibus_put_mbyte(uint16 addr, uint8 val); extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ -extern DEVICE *i8080_dev; +extern DEVICE i8080_dev; extern t_stat i8251_reset (DEVICE *dptr); extern uint8 i8251s(t_bool io, uint8 data, uint8 devnum); extern uint8 i8251d(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8251_dev; +extern DEVICE i8251_dev; extern t_stat i8253_reset (DEVICE *dptr); extern uint8 i8253t0(t_bool io, uint8 data, uint8 devnum); extern uint8 i8253t1(t_bool io, uint8 data, uint8 devnum); extern uint8 i8253t2(t_bool io, uint8 data, uint8 devnum); extern uint8 i8253c(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8253_dev; +extern DEVICE i8253_dev; extern t_stat i8255_reset (DEVICE *dptr); extern uint8 i8255a(t_bool io, uint8 data, uint8 devnum); extern uint8 i8255b(t_bool io, uint8 data, uint8 devnum); extern uint8 i8255c(t_bool io, uint8 data, uint8 devnum); extern uint8 i8255s(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8255_dev; +extern DEVICE i8255_dev; extern t_stat i8259_reset (DEVICE *dptr); extern uint8 i8259a(t_bool io, uint8 data, uint8 devnum); extern uint8 i8259b(t_bool io, uint8 data, uint8 devnum); -extern DEVICE *i8259_dev; +extern DEVICE i8259_dev; extern uint8 EPROM_get_mbyte(uint16 addr); extern UNIT EPROM_unit; extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size); @@ -116,12 +116,12 @@ t_stat SBC_reset (DEVICE *dptr) multibus_cfg(); onetime++; } - i8080_reset(i8080_dev); - i8251_reset(i8251_dev); - i8253_reset(i8253_dev); - i8255_reset(i8255_dev); - i8255_reset(i8255_dev); - i8259_reset(i8259_dev); + i8080_reset(&i8080_dev); + i8251_reset(&i8251_dev); + i8253_reset(&i8253_dev); + i8255_reset(&i8255_dev); + i8255_reset(&i8255_dev); + i8259_reset(&i8259_dev); return SCPE_OK; } diff --git a/Intel-Systems/isys8030/isbc8030.c b/Intel-Systems/isys8030/isbc8030.c index f3bb4649..69ce8a97 100644 --- a/Intel-Systems/isys8030/isbc8030.c +++ b/Intel-Systems/isys8030/isbc8030.c @@ -47,22 +47,22 @@ t_stat SBC_reset (DEVICE *dptr); /* external globals */ extern uint8 i8255_C[4]; //port C byte I/O -extern int32 PCX; +extern uint16 PCX; /* external function prototypes */ extern uint8 multibus_get_mbyte(uint16 addr); extern void multibus_put_mbyte(uint16 addr, uint8 val); extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */ -extern DEVICE *i8080_dev; +extern DEVICE i8080_dev; extern t_stat i8251_reset (DEVICE *dptr); -extern DEVICE *i8251_dev; +extern DEVICE i8251_dev; extern t_stat i8253_reset (DEVICE *dptr); -extern DEVICE *i8253_dev; +extern DEVICE i8253_dev; extern t_stat i8255_reset (DEVICE *dptr); -extern DEVICE *i8255_dev; +extern DEVICE i8255_dev; extern t_stat i8259_reset (DEVICE *dptr); -extern DEVICE *i8259_dev; +extern DEVICE i8259_dev; extern uint8 EPROM_get_mbyte(uint16 addr); extern UNIT EPROM_unit; extern t_stat EPROM_reset (DEVICE *dptr, uint16 base, uint16 size); @@ -103,11 +103,11 @@ t_stat SBC_reset (DEVICE *dptr) multibus_cfg(); onetime++; } - i8080_reset(i8080_dev); - i8251_reset(i8251_dev); - i8253_reset(i8253_dev); - i8255_reset(i8255_dev); - i8259_reset(i8259_dev); + i8080_reset(&i8080_dev); + i8251_reset(&i8251_dev); + i8253_reset(&i8253_dev); + i8255_reset(&i8255_dev); + i8259_reset(&i8259_dev); return SCPE_OK; }