diff --git a/PDQ-3/pdq3_fdc.c b/PDQ-3/pdq3_fdc.c
index 1420a331..a0dbbc3c 100644
--- a/PDQ-3/pdq3_fdc.c
+++ b/PDQ-3/pdq3_fdc.c
@@ -824,43 +824,43 @@ static void debug_fdccmd(uint16 cmd) {
 
   buf[0] = 0;
   if (cmd & 0xff00) {
-    strcat(buf,"DSR=[");
-    strcat(buf,dsel & FDC_SEL_SIDE ? "SIDE1" : "SIDE0");
-    if (dsel & FDC_SEL_SDEN) strcat(buf,",SDEN");
-    strcat(buf,",UNIT");
-    if (dsel & FDC_SEL_UNIT3) strcat(buf,"3");
-    else if (dsel & FDC_SEL_UNIT2) strcat(buf,"2");
-    else if (dsel & FDC_SEL_UNIT1) strcat(buf,"1");
-    else if (dsel & FDC_SEL_UNIT0) strcat(buf,"0");
-    strcat(buf,"] ");
+    sim_strlcat(buf,"DSR=[",sizeof(buf));
+    sim_strlcat(buf,dsel & FDC_SEL_SIDE ? "SIDE1" : "SIDE0",sizeof(buf));
+    if (dsel & FDC_SEL_SDEN) sim_strlcat(buf,",SDEN",sizeof(buf));
+    sim_strlcat(buf,",UNIT",sizeof(buf));
+    if (dsel & FDC_SEL_UNIT3) sim_strlcat(buf,"3",sizeof(buf));
+    else if (dsel & FDC_SEL_UNIT2) sim_strlcat(buf,"2",sizeof(buf));
+    else if (dsel & FDC_SEL_UNIT1) sim_strlcat(buf,"1",sizeof(buf));
+    else if (dsel & FDC_SEL_UNIT0) sim_strlcat(buf,"0",sizeof(buf));
+    sim_strlcat(buf,"] ",sizeof(buf));
   }
-  strcat(buf,"CR=[");
-  strcat(buf,cmdlist[cr]);
+  sim_strlcat(buf,"CR=[",sizeof(buf));
+  sim_strlcat(buf,cmdlist[cr],sizeof(buf));
   if (cr < 8) {
-    if (cmd & FDC_BIT_HEADLOAD) strcat(buf,"+Load");
-    if (cmd & FDC_BIT_VERIFY) strcat(buf,"+Vrfy");
+    if (cmd & FDC_BIT_HEADLOAD) sim_strlcat(buf,"+Load",sizeof(buf));
+    if (cmd & FDC_BIT_VERIFY) sim_strlcat(buf,"+Vrfy",sizeof(buf));
     cmd &= FDC_BIT_STEP15;
-    if (cmd == FDC_BIT_STEP3) strcat(buf,"+Step3");
-    else if (cmd == FDC_BIT_STEP6) strcat(buf,"+Step6");
-    else if (cmd == FDC_BIT_STEP10) strcat(buf,"+Step10");
-    else if (cmd == FDC_BIT_STEP15) strcat(buf,"+Step15");
+    if (cmd == FDC_BIT_STEP3) sim_strlcat(buf,"+Step3",sizeof(buf));
+    else if (cmd == FDC_BIT_STEP6) sim_strlcat(buf,"+Step6",sizeof(buf));
+    else if (cmd == FDC_BIT_STEP10) sim_strlcat(buf,"+Step10",sizeof(buf));
+    else if (cmd == FDC_BIT_STEP15) sim_strlcat(buf,"+Step15",sizeof(buf));
   } else
     switch (cr) {
     case 8: case 9:
     case 0xa: case 0xb:
-      strcat(buf, cmd & FDC_BIT_SIDESEL ? "+SideSel1" : "+SideSel0");
-      strcat(buf, cmd & FDC_BIT_SIDECMP ? "+SideCmp1" : "+SideCmp0");
+      sim_strlcat(buf, cmd & FDC_BIT_SIDESEL ? "+SideSel1" : "+SideSel0",sizeof(buf));
+      sim_strlcat(buf, cmd & FDC_BIT_SIDECMP ? "+SideCmp1" : "+SideCmp0",sizeof(buf));
       if (cr > 9)
-        strcat(buf, cmd & FDC_BIT_DATAMARK ? "+DelMark" : "+DataMark");
+        sim_strlcat(buf, cmd & FDC_BIT_DATAMARK ? "+DelMark" : "+DataMark",sizeof(buf));
     default:
       break;
     case 0x0f:
-      if (cmd & FDC_BIT_INTIMM) strcat(buf,"+IMM");
-      if (cmd & FDC_BIT_INTIDX) strcat(buf,"+IDX");
-      if (cmd & FDC_BIT_INTN2R) strcat(buf,"+N2R");
-      if (cmd & FDC_BIT_INTR2N) strcat(buf,"+R2N");
+      if (cmd & FDC_BIT_INTIMM) sim_strlcat(buf,"+IMM",sizeof(buf));
+      if (cmd & FDC_BIT_INTIDX) sim_strlcat(buf,"+IDX",sizeof(buf));
+      if (cmd & FDC_BIT_INTN2R) sim_strlcat(buf,"+N2R",sizeof(buf));
+      if (cmd & FDC_BIT_INTR2N) sim_strlcat(buf,"+R2N",sizeof(buf));
     }
-  strcat(buf,"]");
+  sim_strlcat(buf,"]",sizeof(buf));
   sim_debug(DBG_FD_CMD, &fdc_dev, DBG_PCFORMAT2 "Command: %s\n", DBG_PC,buf);  
 }