diff --git a/README.md b/README.md index c573a4c6..2fac409e 100644 --- a/README.md +++ b/README.md @@ -60,7 +60,19 @@ MicroVAX I & VAXStation I MicroVAX II & VAXStation II & VAXStation II GPX rtVAX 1000 (or Industrial VAX 620) - + MicroVAX 2000 & VAXstation 2000 + MicroVAX 3100 M10/M20 + MicroVAX 3100 M10e/M20e + InfoServer 100 + InfoServer 150 VXT + VAXstation 3100 M30 + VAXstation 3100 M38 + VAXstation 3100 M76 + VAXstation 4000 VLC + VAXstation 4000 M60 + MicroVAX 3100 M80 + InfoServer 1000 + #### Howard Harte has implemented a Lincoln Labs TX-0 simulator. #### Gerardo Ospina has implemented a Manchester University SSEM (Small Scale Experimental Machine) simulator. diff --git a/VAX/is1000.bin b/VAX/is1000.bin new file mode 100644 index 00000000..cd08b63f Binary files /dev/null and b/VAX/is1000.bin differ diff --git a/VAX/is1000_defs.h b/VAX/is1000_defs.h new file mode 100644 index 00000000..5fe01f00 --- /dev/null +++ b/VAX/is1000_defs.h @@ -0,0 +1,286 @@ +/* is1000_defs.h: InfoServer 1000 model-specific definitions file + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This file covers the InfoServer 1000. + + System memory map + + 0000 0000 - 003F FFFF main memory + 0040 0000 - 2003 FFFF reserved + 2004 0000 - 2007 FFFF ROM space + 2008 0000 - 20FF FFFF reserved + 2100 0000 - 2100 0008 network controller + 2100 0020 - 2100 0024 configuration/test register + 2200 0000 - 2200 00C0 scsi controller + 2300 0000 - 2300 xxxx watch chip registers + 2400 0000 - 2400 xxxx local register space + 2400 0060 - 2400 0070 serial line controller + 3002 0000 - 3FFF FFFF reserved +*/ + +#ifdef FULL_VAX /* subset VAX */ +#undef FULL_VAX +#endif + +#ifndef _IS_1000_DEFS_H_ +#define _IS_1000_DEFS_H_ 1 + +/* Microcode constructs */ + +#define CVAX_SID (10 << 24) /* system ID */ +#define CVAX_UREV 6 /* ucode revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_PWRUP 0x0300 /* powerup code */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define CON_DBLMCK 0x0500 /* Machine check in machine check */ +#define CON_BADPSL 0x4000 /* invalid PSL flag */ +#define CON_MAPON 0x8000 /* mapping on flag */ +#define MCHK_READ 0x80 /* read check */ +#define MCHK_WRITE 0x82 /* write check */ + +/* Machine specific IPRs */ + +#define MT_CADR 37 /* Cache disable reg */ +#define MT_MCESR 38 /* Machine check error/status reg */ +#define MT_CAER 39 /* Cache error reg */ +#define MT_ACCS 40 /* FPA control */ +#define MT_CONISP 41 /* Console Saved ISP */ +#define MT_CONPC 42 /* Console Saved PC */ +#define MT_CONPSL 43 /* Console Saved PSL */ +#define MT_MAX 127 /* last valid IPR */ + +/* Cache disable register */ + +#define CADR_RW 0xF3 +#define CADR_MBO 0x0C + +/* CPU */ + +#define CPU_MODEL_MODIFIERS \ + { 0 } + +/* Memory */ + +#define MAXMEMWIDTH 22 /* max mem, std KA420 */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */ +#define MAXMEMWIDTH_X 22 /* max mem, KA420 */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << 24) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size } + +/* Read only memory */ + +#define ROMAWIDTH 19 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */ +#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */ +#define ROMBASE 0x20040000 /* ROM base */ +#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \ + (((uint32) (x)) < (ROMBASE + ROMSIZE))) + +/* LANCE Ethernet controller */ + +#define XSSIZE 0x8 /* XS length */ +#define XSBASE 0x21000000 /* XS base */ + +/* Config/test register */ + +#define CFGSIZE 4 /* CFG length */ +#define CFGBASE 0x21000020 /* CFG base */ + +/* SCSI disk controller */ + +#define RZSIZE 0xC0 /* RZ length */ +#define RZBASE 0x22000000 /* RZ base */ + +/* Non-volatile RAM - 32KB Bytes long */ + +#define NVRAWIDTH 15 /* NVR addr width */ +#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */ +#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */ +#define NVRBASE 0x23000000 /* NVR base */ +#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \ + (((uint32) (x)) < (NVRBASE + NVRSIZE))) + +/* IS1000 board registers */ + +#define KASIZE 0x60 /* REG length */ +#define KABASE 0x24000000 /* REG addr base */ + +/* Serial line controller */ + +#define DZSIZE 0x10 /* DZ length */ +#define DZBASE 0x24000060 /* DZ base */ + +/* Network address ROM */ + +#define NARAWIDTH 5 /* NAR addr width */ +#define NARSIZE (1u << NARAWIDTH) /* NAR length */ +#define NARAMASK (NARSIZE - 1) /* NAR addr mask */ + +/* Other address spaces */ + +#define ADDR_IS_IO(x) (0) +#define ADDR_IS_CDG(x) (0) + +/* Machine specific reserved operand tests (mostly NOPs) */ + +#define ML_PA_TEST(r) +#define ML_LR_TEST(r) +#define ML_SBR_TEST(r) +#define ML_PXBR_TEST(r) +#define LP_AST_TEST(r) +#define LP_MBZ84_TEST(r) +#define LP_MBZ92_TEST(r) + +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* SCSI Bus */ + +#define RZ_SCSI_ID 6 /* initiator SCSI id */ + +/* I/O system definitions */ + +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_4XX (DEV_V_UF + 0) /* KA4xx I/O */ +#define DEV_4XX (1u << DEV_V_4XX) + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + int32 rom_index; /* option ROM index */ + uint8 *rom_array; /* option ROM code */ + t_addr rom_size; /* option ROM size */ + } DIB; + +/* Within each IPL, priority is left to right */ + +/* IPL 14 */ + +#define INT_V_SC 0 /* storage controller */ +#define INT_V_XS1 1 /* network */ +#define INT_V_DZTX 2 /* serial transmitter */ +#define INT_V_DZRX 3 /* serial receiver */ +#define INT_V_PE 6 /* parity error */ + +#define INT_SC (1u << INT_V_SC) +#define INT_XS1 (1u << INT_V_XS1) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_DZRX (1u << INT_V_DZRX) +#define INT_PE (1u << INT_V_PE) + +#define IPL_CLK 0x16 +#define IPL_HW 0x14 /* hwre level */ +#define IPL_SC (0x14 - IPL_HMIN) +#define IPL_XS1 (0x14 - IPL_HMIN) +#define IPL_DZTX (0x14 - IPL_HMIN) +#define IPL_DZRX (0x14 - IPL_HMIN) +#define IPL_HMIN IPL_HW +#define IPL_HMAX IPL_HW +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + + +/* Device vectors */ + +#define VEC_QBUS 0 /* Not a Qbus system */ +#define VEC_Q 0 + +/* Interrupt macros */ + +#define IREQ(dv) int_req[0] +#define SET_INT(dv) int_req[0] = int_req[0] | (INT_##dv) +#define CLR_INT(dv) int_req[0] = int_req[0] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* System model */ + +extern int32 sys_model; + +/* Machine specific definitions - DZ */ + +#define DZ_L3C 1 /* line 3 console */ + +/* Machine specific definitions - RZ94 */ + +#define RZ_READB(ba,bc,buf) Map_ReadB(ba, bc, buf, TRUE) +#define RZ_READW(ba,bc,buf) Map_ReadW(ba, bc, buf, TRUE) +#define RZ_WRITEB(ba,bc,buf) Map_WriteB(ba, bc, buf, TRUE) +#define RZ_WRITEW(ba,bc,buf) Map_WriteW(ba, bc, buf, TRUE) + +/* Machine specific definitions - XS */ + +#define XS_ROM_INDEX -1 /* no ROM needed */ +#define XS_FLAGS 0 +#define XS_READB(ba,bc,buf) Map_ReadB(ba, bc, buf, FALSE) +#define XS_READW(ba,bc,buf) Map_ReadW(ba, bc, buf, FALSE) +#define XS_WRITEB(ba,bc,buf) Map_WriteB(ba, bc, buf, FALSE) +#define XS_WRITEW(ba,bc,buf) Map_WriteW(ba, bc, buf, FALSE) + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf, t_bool map); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf, t_bool map); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf, t_bool map); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf, t_bool map); + +/* Function prototypes for system-specific unaligned support */ + +int32 ReadIOU (uint32 pa, int32 lnt); +int32 ReadRegU (uint32 pa, int32 lnt); +void WriteIOU (uint32 pa, int32 val, int32 lnt); +void WriteRegU (uint32 pa, int32 val, int32 lnt); + +t_stat auto_config (const char *name, int32 nctrl); + +/* Function prototypes for virtual and physical memory interface (inlined) */ + +#include "vax_mmu.h" + +#endif diff --git a/VAX/is1000_sysdev.c b/VAX/is1000_sysdev.c new file mode 100644 index 00000000..8e758731 --- /dev/null +++ b/VAX/is1000_sysdev.c @@ -0,0 +1,1066 @@ +/* is1000_sysdev.c: InfoServer 1000 system-specific logic + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the InfoServer 1000 system-specific registers and devices. + + sysd system devices +*/ + +#include "vax_defs.h" +#include "sim_tmxr.h" +#include "sim_ether.h" +#include + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "is1000.bin" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_is1000_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ + + +t_stat is1000_boot (int32 flag, CONST char *ptr); + +/* Special boot command, overrides regular boot */ + +CTAB is1000_cmd[] = { + { "BOOT", &is1000_boot, RU_BOOT, + "bo{ot} boot simulator\n", NULL, &run_cmd_message }, + { NULL } + }; + +/* IS1000 configuration & test register */ + +#define CFGT_MEM 0x003F /* memory option */ +#define CFGT_V_VID 6 +#define CFGT_M_VID 0x3 +#define CFGT_VID (CFGT_M_VID << CFGT_V_VID) /* video option */ +#define CFGT_L3C 0x0100 /* line 3 console */ +#define CFGT_V_SIM 9 +#define CFGT_M_SIM 0x3F +#define CFGT_SIM (CFGT_M_SIM << CFGT_V_SIM) /* SIMM type */ + +/* IS1000 parity control register */ + +#define PARCTL_CPEN 0x00000001 /* system wide parity */ +#define PARCTL_REV 0x000000F0 +#define PARCTL_NPEN 0x00000100 /* NI parity en */ +#define PARCTL_NPERR 0x00000200 /* NI parity err */ +#define PARCTL_NMAP 0x00000400 +#define PARCTL_SPEN 0x00010000 /* SCSI parity en */ +#define PARCTL_SPERR 0x00020000 /* SCSI parity err */ +#define PARCTL_SMAP 0x00040000 +#define PARCTL_INVEN 0x01000000 +#define PARCTL_AGS 0x02000000 /* AG stall */ +#define PARCTL_ADP 0x80000000 +#define PARCTL_RD 0x830707F1 +#define PARCTL_WR 0x01010101 + +/* IS1000 Memory system error register */ + +#define MSER_WWP 0x00000002 /* Write Wrong Parity */ + +#define ROM_VEC 0x8 /* ROM longword for first device vector */ + +/* DMA map registers */ + +#define DMANMAPR 32768 /* number of map reg */ +#define DMAMAP_VLD 0x80000000 /* valid */ +#define DMAMAP_PAG 0x0000FFFF /* mem page */ +#define DMAMAP_RD (QBMAP_VLD | QBMAP_PAG) +#define DMAMAP_WR (QBMAP_VLD | QBMAP_PAG) + +#define CSR_XDONE 0x01 +#define CSR_RDONE 0x02 +#define TMXR_MULT 1 /* 100 Hz */ +#define TTIBUF_VLD 0x8000 /* valid */ +#define TTIBUF_OVR 0x4000 /* overrun */ +#define TTIBUF_FRM 0x2000 /* framing error */ +#define TTIBUF_RBR 0x0400 /* receive break */ + +extern int32 tmr_int; +extern UNIT clk_unit; +extern int32 tmr_poll; +extern uint32 *rom; + +uint32 *invfl = NULL; /* invalidate filter */ +int32 conisp, conpc, conpsl; /* console reg */ +int32 ka_hltcod = 0; /* IS1000 halt code */ +int32 ka_mapbase = 0; /* IS1000 map base */ +int32 ka_boff = 0; /* IS1000 byte offset */ +int32 ka_mser = 0; /* IS1000 mem sys err */ +int32 ka_mear = 0; /* IS1000 mem err addr */ +int32 ka_cfgtst = 0xFFAB; /* IS1000 config/test */ +int32 ka_parctl = 0xF0; /* IS1000 parity control */ +int32 ka_tmr = 0; /* IS1000 diag timer */ +int32 CADR = 0; /* cache disable reg */ +int32 SCCR = 0; /* secondary cache control */ +int32 sys_model = 0; /* MicroVAX or VAXstation */ +int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */ +int32 int_mask = 0; /* interrupt mask */ +int32 vc_sel, vc_org; +int32 dz_csr = 0; /* control/status */ +int32 dz_lpr = 0; /* line param */ +uint32 dz_buftime; /* time input character arrived */ +uint32 dma_csr = 0; +uint32 dma_txc = 0; +uint32 dma_addr = 0; + +t_stat tti_svc (UNIT *uptr); +t_stat tto_svc (UNIT *uptr); +t_stat dz_reset (DEVICE *dptr); +t_stat sysd_reset (DEVICE *dptr); +const char *dz_description (DEVICE *dptr); +const char *sysd_description (DEVICE *dptr); +t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +int32 dz_rd (int32 pa); +int32 ka_rd (int32 pa); +void dz_wr (int32 pa, int32 val, int32 lnt); +void ka_wr (int32 pa, int32 val, int32 lnt); +int32 con_halt (int32 code, int32 cc); + +extern int32 iccs_rd (void); +extern int32 rom_rd (int32 pa); +extern int32 nvr_rd (int32 pa); +extern int32 rz_rd (int32 pa); +extern int32 xs_rd (int32 pa); +extern void iccs_wr (int32 dat); +extern void nvr_wr (int32 pa, int32 val, int32 lnt); +extern void rz_wr (int32 pa, int32 val, int32 lnt); +extern void xs_wr (int32 pa, int32 val, int32 lnt); + +/* TTI data structures + + tti_dev TTI device descriptor + tti_unit TTI unit descriptor + tti_reg TTI register list +*/ + +UNIT dz_unit[] = { + { UDATA (&tti_svc, UNIT_IDLE|TT_MODE_8B, 0), TMLN_SPD_9600_BPS }, + { UDATA (&tto_svc, TT_MODE_8B, 0), SERIAL_OUT_WAIT } + }; + +REG dz_reg[] = { + { HRDATAD (RBUF, dz_unit[0].buf, 16, "last data item received") }, + { HRDATAD (XBUF, dz_unit[1].buf, 8, "last data item sent") }, + { HRDATAD (CSR, dz_csr, 8, "control/status register") }, + { DRDATAD (RPOS, dz_unit[0].pos, T_ADDR_W, "number of characters input"), PV_LEFT }, + { DRDATAD (RTIME, dz_unit[0].wait, 24, "input polling interval"), PV_LEFT }, + { DRDATAD (XPOS, dz_unit[1].pos, T_ADDR_W, "number of characters output"), PV_LEFT }, + { DRDATAD (XTIME, dz_unit[1].wait, 24, "time from I/O initiation to interrupt"), PV_LEFT }, + { FLDATAD (TXINT, int_req[IPL_DZTX], INT_V_DZTX, "transmit interrupt pending flag") }, + { FLDATAD (RXINT, int_req[IPL_DZRX], INT_V_DZRX, "receive interrupt pending flag") }, + { NULL } + }; + +MTAB dz_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "Set 7 bit mode" }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "Set 8 bit mode" }, + { 0 } + }; + +DEVICE dz_dev = { + "DZ", dz_unit, dz_reg, dz_mod, + 2, 10, 31, 1, 16, 8, + NULL, NULL, &dz_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, &dz_help, NULL, NULL, + &dz_description + }; + +/* debugging bitmaps */ + +#define DBG_REG 0x0001 /* trace read/write registers */ + +UNIT sysd_unit = { UDATA (NULL, 0, 0) }; + +REG sysd_reg[] = { + { HRDATAD (CONISP, conisp, 32, "console ISP") }, + { HRDATAD (CONPC, conpc, 32, "console PD") }, + { HRDATAD (CONPSL, conpsl, 32, "console PSL") }, + { HRDATAD (HLTCOD, ka_hltcod, 32, "halt code") }, + { HRDATAD (MSER, ka_mser, 32, "mem sys err") }, + { HRDATAD (MEAR, ka_mear, 32, "mem err addr") }, + { HRDATAD (IMSK, int_mask, 8, "interrupt mask") }, + { NULL } + }; + +MTAB sysd_mod[] = { + { 0 }, + }; + +DEBTAB sysd_debug[] = { + { "REG", DBG_REG, "Register activity" }, + { 0 } + }; + +DEVICE sysd_dev = { + "SYSD", &sysd_unit, sysd_reg, sysd_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysd_reset, + NULL, NULL, NULL, + NULL, DEV_DEBUG, + 0, sysd_debug, NULL, NULL, NULL, NULL, NULL, + &sysd_description + }; + +/* Find highest priority outstanding interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_CLK) && tmr_int) /* clock int */ + return IPL_CLK; +if (ipl < IPL_HW) { /* chk hwre int */ + if ((ka_mser & MSER_WWP) && (int_req[0] & INT_SC)) /* to make ROM test pass */ + SET_INT (PE); /* parity error */ + if (int_req[0] & int_mask & 0xF) + return IPL_HW; + } +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i; +int32 int_unmask = int_req[0] & int_mask; + +if (lvl == IPL_CLK) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +for (i = 3; int_unmask && (i >= 0); i--) { + if ((int_unmask >> i) & 1) { + switch (i) { + case 0: return rom[ROM_VEC + 1] & 0x3FF; /* get vectors from ROM */ + case 1: return rom[ROM_VEC + 4] & 0x3FF; + case 2: return rom[ROM_VEC + 6] & 0x3FF; + case 3: return rom[ROM_VEC + 7] & 0x3FF; + default: return 0; + } + } + } +return 0; +} + +/* Map an address via the translation map */ + +t_bool dma_map_addr (uint32 da, uint32 *ma, t_bool map) +{ +if (map) { /* using map? */ + int32 dblk = (da >> VA_V_VPN); /* DMA blk */ + if (dblk <= DMANMAPR) { + int32 dmap = ReadL (ka_mapbase + (dblk << 2)); + if (mapen) { + if (dmap & DMAMAP_VLD) { /* valid? */ + *ma = ((dmap & DMAMAP_PAG) << VA_V_VPN) + VA_GETOFF (da); + if (ADDR_IS_MEM (*ma)) /* legit addr */ + return TRUE; + } + } + else { + *ma = (ka_mapbase << 7) + da; + return TRUE; + } + } + return FALSE; + } +else + *ma = da; +return TRUE; +} + +/* DMA buffer routines, aligned access + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf, t_bool map) +{ +int32 i; +uint32 ma, dat; + +if (map) /* using map? */ + ba = ba + ka_boff; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + *buf = ReadB (ma); + ma = ma + 1; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ma = ma + 4; + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf, t_bool map) +{ +int32 i; +uint32 ma,dat; + +if (map) /* using map? */ + ba = ba + ka_boff; +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + *buf = ReadW (ma); + ma = ma + 2; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf, t_bool map) +{ +int32 i; +uint32 ma, dat; + +if (map) /* using map? */ + ba = ba + ka_boff; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + WriteB (ma, *buf); + ma = ma + 1; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf, t_bool map) +{ +int32 i; +uint32 ma, dat; + +if (map) /* using map? */ + ba = ba + ka_boff; +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + WriteW (ma, *buf); + ma = ma + 2; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma, map)) /* inv or NXM? */ + return (bc - i); + } + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 dz_rd (int32 pa) +{ +int32 rg = (pa >> 2) & 0x7; +int32 val; + +switch (rg) { + + case 0: /* CSR */ + val = dz_csr; + break; + + case 1: /* LPR? */ + val = dz_lpr; + break; + + case 2: /* RBUF */ + val = dz_unit[0].buf; /* char + error */ + + if (dz_csr & CSR_RDONE) { /* Input pending ? */ + dz_csr = dz_csr & ~CSR_RDONE; /* clr done */ + dz_unit[0].buf = dz_unit[0].buf & 0377; /* clr errors */ + CLR_INT (DZRX); + sim_activate_after_abs (&dz_unit[0], dz_unit[0].wait); /* check soon for more input */ + } + break; + + case 3: /* XBUF */ + val = dz_unit[1].buf; + break; + + default: + val = 0; + break; + } +SET_IRQL; +return val; +} + +void dz_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa >> 2) & 0x7; + +switch (rg) { + + case 0: /* CSR */ + dz_csr = val; + break; + + case 1: /* LPR? */ + dz_lpr = val; + break; + + case 2: /* RBUF */ + dz_csr = dz_csr & ~CSR_RDONE; /* clr done */ + break; + + case 3: /* XBUF */ + dz_unit[1].buf = val & 0377; + dz_csr = dz_csr & ~CSR_XDONE; + CLR_INT (DZTX); + sim_activate (&dz_unit[1], dz_unit[1].wait); + break; + + default: + break; + } +SET_IRQL; +} + +int32 cfg_rd (int32 pa) +{ +return ka_cfgtst; +} + +void led_wr (int32 pa, int32 val, int32 lnt) +{ +} + +/* Read IS1000 specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_MCESR: /* MCESR (not impl) */ + val = 0; + break; + + case MT_ACCS: /* ACCS (not impl) */ + val = 0; + break; + + case MT_CONISP: /* console ISP */ + val = conisp; + break; + + case MT_CONPC: /* console PC */ + val = conpc; + break; + + case MT_CONPSL: /* console PSL */ + val = conpsl; + break; + + case MT_CADR: /* CADR */ + val = CADR & 0xFF; + break; + + case MT_CAER: /* CAER */ + val = 0; + break; + + case MT_SID: /* SID */ + val = CVAX_SID | CVAX_UREV; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write IS1000 specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_NICR: /* NICR (not impl) */ + break; + + case MT_MCESR: /* MCESR (not impl) */ + break; + + case MT_ACCS: /* ACCS (not impl) */ + break; + + case MT_CONISP: /* console ISP */ + conisp = val; + break; + + case MT_CONPC: /* console PC */ + conpc = val; + break; + + case MT_CONPSL: /* console PSL */ + conpsl = val; + break; + + case MT_CADR: /* CADR */ + CADR = (val & CADR_RW) | CADR_MBO; + break; + + case MT_CAER: /* CAER */ + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* Read/write I/O register space + + These routines are the 'catch all' for address space map. Any + address that doesn't explicitly belong to memory, I/O, or ROM + is given to these routines for processing. +*/ + +struct reglink { /* register linkage */ + uint32 low; /* low addr */ + uint32 high; /* high addr */ + int32 (*read)(int32 pa); /* read routine */ + void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */ + }; + +struct reglink regtable[] = { + { XSBASE, XSBASE+XSSIZE, &xs_rd, &xs_wr }, + { DZBASE, DZBASE+DZSIZE, &dz_rd, &dz_wr }, + { RZBASE, RZBASE+RZSIZE, &rz_rd, &rz_wr }, + { CFGBASE, CFGBASE+CFGSIZE, &cfg_rd, &led_wr }, + { ROMBASE, ROMBASE+ROMSIZE, &rom_rd, NULL }, + { NVRBASE, NVRBASE+NVRSIZE, &nvr_rd, &nvr_wr }, + { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr }, + { 0, 0, NULL, NULL } + }; + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) - ignored + Output: + longword of data +*/ + +int32 ReadReg (uint32 pa, int32 lnt) +{ +struct reglink *p; +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) + return p->read (pa); + } +return 0xFFFFFFFF; +} + +/* ReadRegU - read register space, unaligned + + Inputs: + pa = physical address + lnt = length in bytes (1, 2, or 3) + Output: + returned data, not shifted +*/ + +int32 ReadRegU (uint32 pa, int32 lnt) +{ +return ReadReg (pa & ~03, L_LONG); +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + p->write (pa, val, lnt); + return; + } + } +return; +} + +/* WriteRegU - write register space, unaligned + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (1, 2, or 3) + Outputs: + none +*/ + +void WriteRegU (uint32 pa, int32 val, int32 lnt) +{ +int32 sc = (pa & 03) << 3; +int32 dat = ReadReg (pa & ~03, L_LONG); + +dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc); +WriteReg (pa & ~03, dat, L_LONG); +return; +} + +/* IS1000 registers */ + +int32 ka_rd (int32 pa) +{ +int32 rg = (pa >> 2) & 0x1B; /* registers appear multiple times */ +int32 val = 0; + +switch (rg) { + + case 0: /* diag timer */ + case 1: + ka_tmr = (ka_tmr + 1) & 0xFFFF; + sim_debug (DBG_REG, &sysd_dev, "ka_rd: TMR = %04X at %08X\n", ka_tmr, fault_PC); + val = ka_tmr; + break; + + case 2: /* halt code */ + val = ka_hltcod; + break; + + case 3: /* MEAR */ + val = ka_mear; + break; + + case 8: /* int req */ + case 10: + val = int_req[0]; + break; + + case 9: /* int mask */ + case 11: + val = int_mask; + break; + + case 16: /* MSER */ + val = ka_mser; + break; + + case 17: /* DMA byte offset */ + val = ka_boff; + break; + + case 18: /* ? */ + val = 0; + break; + + case 19: /* DMA map base */ + val = ka_mapbase; + break; + } + +return val; +} + +void ka_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa >> 2) & 0x1B; /* registers appear multiple times */ + +switch (rg) { + + case 0: /* diag timer */ + case 1: + ka_tmr = val; + sim_debug (DBG_REG, &sysd_dev, "ka_wr: TMR = %04X at %08X\n", ka_tmr, fault_PC); + break; + + case 2: /* halt code */ + ka_hltcod = val; + break; + + case 3: /* MEAR */ + break; + + case 8: /* int req */ + case 10: + int_req[0] = int_req[0] & ~val; + break; + + case 9: /* int mask */ + case 11: + int_mask = val; + SET_IRQL; + break; + + case 16: /* MSER */ + ka_mser = val; + break; + + case 17: /* DMA byte offset */ + ka_boff = val; + break; + + case 18: /* ? */ + break; + + case 19: /* DMA map base */ + ka_mapbase = val; + break; + } +return; +} + +int32 sysd_hlt_enb (void) +{ +return 1; +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 p2, acc; + +if (in_ie) { + in_ie = 0; + return con_halt (CON_DBLMCK, cc); /* double machine check */ + } +if (p1 & 0x80) /* mref? set v/p */ + p1 = p1 + mchk_ref; +p2 = mchk_va + 4; /* save vap */ +cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 28; /* push 7 words */ +Write (SP, 24, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +Write (SP + 8, p2, L_LONG, WA); /* address */ +Write (SP + 12, 0, L_LONG, WA); /* VIBA */ +Write (SP + 16, 0, L_LONG, WA); /* ICCS..SISR */ +Write (SP + 20, 0, L_LONG, WA); /* state */ +Write (SP + 24, 0, L_LONG, WA); /* SC */ +in_ie = 0; +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +int32 temp; + +conisp = IS; /* save ISP */ +conpc = PC; /* save PC */ +conpsl = ((PSL | cc) & 0xFFFF00FF) | code; /* PSL, param */ +temp = (PSL >> PSL_V_CUR) & 0x7; /* get is'cur */ +if (temp > 4) /* invalid? */ + conpsl = conpsl | CON_BADPSL; +else STK[temp] = SP; /* save stack */ +if (mapen) /* mapping on? */ + conpsl = conpsl | CON_MAPON; +mapen = 0; /* turn off map */ +SP = IS; /* set SP from IS */ +PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */ +JUMP (ROMBASE); /* PC = 20040000 */ +return 0; /* new cc = 0 */ +} + + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {CPU} + +*/ + +t_stat is1000_boot (int32 flag, CONST char *ptr) +{ +char gbuf[CBUFSIZE]; + +get_glyph (ptr, gbuf, 0); /* get glyph */ +if (gbuf[0] && strcmp (gbuf, "CPU")) + return SCPE_ARG; /* Only can specify CPU device */ +return run_cmd (flag, "CPU"); +} + + +/* Bootstrap */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; + +PC = ROMBASE; +PSL = PSL_IS | PSL_IPL1F; +conisp = 0; +conpc = 0; +conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP; +if (rom == NULL) + return SCPE_IERR; +if (*rom == 0) { /* no boot? */ + r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0); + if (r != SCPE_OK) + return r; + } +return SCPE_OK; +} + +/* SYSD reset */ + +t_stat sysd_reset (DEVICE *dptr) +{ +ka_hltcod = 0; +ka_cfgtst = 0xFFAB; +ka_mapbase = 0; +ka_boff = 0; +ka_mser = 0; +ka_mear = 0; +ka_tmr = 0; +sim_vm_cmd = is1000_cmd; +return SCPE_OK; +} + +const char *sysd_description (DEVICE *dptr) +{ +return "system devices"; +} + +/* Terminal input routines + + tti_svc process event (character ready) +*/ + +t_stat tti_svc (UNIT *uptr) +{ +int32 c; + +sim_clock_coschedule_tmr (uptr, TMR_CLK, TMXR_MULT); /* continue poll */ + +if ((dz_csr & CSR_RDONE) && /* input still pending and < 500ms? */ + ((sim_os_msec () - dz_buftime) < 500)) + return SCPE_OK; +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +if (c & SCPE_BREAK) { /* break? */ + if (sysd_hlt_enb ()) /* if enabled, halt */ + hlt_pin = 1; + uptr->buf = TTIBUF_FRM | TTIBUF_RBR; + } +else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags)); +uptr->buf = uptr->buf | TTIBUF_VLD; +dz_buftime = sim_os_msec (); +uptr->pos = uptr->pos + 1; +dz_csr = dz_csr | CSR_RDONE; +SET_INT (DZRX); +return SCPE_OK; +} + +/* Terminal output routines + + tto_svc process event (character typed) +*/ + +t_stat tto_svc (UNIT *uptr) +{ +int32 c; +t_stat r; + +c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags)); +if (c >= 0) { + if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */ + sim_activate (uptr, uptr->wait); /* retry */ + return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */ + } + } +dz_csr = dz_csr | CSR_XDONE; +SET_INT (DZTX); +uptr->pos = uptr->pos + 1; +return SCPE_OK; +} + +t_stat dz_reset (DEVICE *dptr) +{ +tmxr_set_console_units (&dz_unit[0], &dz_unit[1]); +dz_unit[0].buf = 0; +dz_unit[1].buf = 0; +dz_csr = CSR_XDONE; +sim_activate (&dz_unit[0], tmr_poll); +sim_cancel (&dz_unit[1]); /* deactivate unit */ +return SCPE_OK; +} + +t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Console Terminal (DZ)\n\n"); +fprintf (st, "The terminal input (DZ) polls the console keyboard for input.\n\n"); +fprintf (st, "When the console terminal is attached to a Telnet session or the simulator is\n"); +fprintf (st, "running from a Windows command prompt, it recognizes BREAK. If BREAK is\n"); +fprintf (st, "entered, and BDR<7> is set (also known as SET CPU NOAUTOBOOT), control returns\n"); +fprintf (st, "to the console firmware; otherwise, BREAK is treated as a normal terminal\n"); +fprintf (st, "input condition.\n\n"); +fprint_set_help (st, dptr); +fprint_show_help (st, dptr); +fprint_reg_help (st, dptr); +return SCPE_OK; +} + +const char *dz_description (DEVICE *dptr) +{ +return "console terminal"; +} + +t_stat auto_config (const char *name, int32 nctrl) +{ +return SCPE_OK; +} + +t_stat build_dib_tab (void) +{ +return SCPE_OK; +} + +t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +return SCPE_ARG; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "%s", sim_name); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Initial memory size is 4MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BOOT\n\n"); +return SCPE_OK; +} diff --git a/VAX/is1000_syslist.c b/VAX/is1000_syslist.c new file mode 100644 index 00000000..aab4c39f --- /dev/null +++ b/VAX/is1000_syslist.c @@ -0,0 +1,115 @@ +/* is1000_syslist.c: InfoServer 1000 device list + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). +*/ + +#include "vax_defs.h" + +char sim_name[64] = "InfoServer 1000"; + +void vax_init(void) +{ +sim_savename = "InfoServer 1000"; +} + +WEAK void (*sim_vm_init) (void) = &vax_init; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE rom_dev; +extern DEVICE nvr_dev; +extern DEVICE nar_dev; +extern DEVICE wtc_dev; +extern DEVICE sysd_dev; +extern DEVICE clk_dev; +extern DEVICE rz_dev; +extern DEVICE dz_dev; +extern DEVICE xs_dev; + +extern void WriteB (uint32 pa, int32 val); +extern void rom_wr_B (int32 pa, int32 val); +extern UNIT cpu_unit; + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &rom_dev, + &nvr_dev, + &nar_dev, + &wtc_dev, + &sysd_dev, + &clk_dev, + &dz_dev, + &rz_dev, + &xs_dev, + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -r load ROM + -n load NVR + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag) +{ +t_stat r; +int32 i; +uint32 origin, limit; + +if (flag) /* dump? */ + return sim_messagef (SCPE_NOFNC, "Command Not Implemented\n"); +if (sim_switches & SWMASK ('R')) { /* ROM? */ + origin = ROMBASE; + limit = ROMBASE + ROMSIZE; + } +else if (sim_switches & SWMASK ('N')) { /* NVR? */ + origin = NVRBASE; + limit = NVRBASE + NVRSIZE; + } +else { + origin = 0; /* memory */ + limit = (uint32) cpu_unit.capac; + if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + } +while ((i = Fgetc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + if (sim_switches & SWMASK ('R')) /* ROM? */ + rom_wr_B (origin, i); /* not writeable */ + else WriteB (origin, i); /* store byte */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/ka410.bin b/VAX/ka410.bin new file mode 100644 index 00000000..1d349df3 Binary files /dev/null and b/VAX/ka410.bin differ diff --git a/VAX/ka410_orig.bin b/VAX/ka410_orig.bin new file mode 100755 index 00000000..ffed4924 Binary files /dev/null and b/VAX/ka410_orig.bin differ diff --git a/VAX/ka410_patch.com b/VAX/ka410_patch.com new file mode 100644 index 00000000..e248362d --- /dev/null +++ b/VAX/ka410_patch.com @@ -0,0 +1,54 @@ +$! +$! This procedure patches KA410.BIN (V2.3) Boot ROM image to work under +$! the SIMH simulator +$! +$ PATCH /ABSOLUTE /NEW_VERSION /OUTPUT=KA410.BIN KA410_ORIG.BIN +! +! Test B - MEM +! +! - Memory parity is not implemented +! +REPLACE/INSTRUCTION 02C67 = 'CLRL W^0168(R11)' +'BRW 00002D01' +'NOP' +EXIT +! +! Test A - MM +! +! - Memory management fails selftest for an unknown reason +! +REPLACE/INSTRUCTION 0E488 = 'JMP @#2004E61B' +'JMP @#2004E600' +EXIT +! +! Test 8 - IT +! +! - Interval timer fails selftest +! +REPLACE/INSTRUCTION 03252 = 'MOVZBL #02,R0' +'MOVZBL #01,R0' +EXIT +! +! Test 5 - SYS +! +! - Ignore ROM checksum errors due to other changes +! +REPLACE/INSTRUCTION 0118A = 'MOVZWL #0FFFE,R0' +'MOVL #01,R0' +'NOP' +'NOP' +EXIT +! +! Test 4 - 4PLN +! +! - Ignore failures in 4PLN test for now +! +REPLACE/INSTRUCTION 006BC = 'BLBC R0,000006E3' +'NOP' +'NOP' +'NOP' +EXIT +! +UPDATE +EXIT +$ diff --git a/VAX/ka410_xs.bin b/VAX/ka410_xs.bin new file mode 100644 index 00000000..9faf4a8a Binary files /dev/null and b/VAX/ka410_xs.bin differ diff --git a/VAX/ka410_xs_patch.com b/VAX/ka410_xs_patch.com new file mode 100644 index 00000000..1b13f56b --- /dev/null +++ b/VAX/ka410_xs_patch.com @@ -0,0 +1,18 @@ +$! +$! This procedure patches KA410_XS.BIN (V1.3) Option ROM image to work under +$! the SIMH simulator +$! +$ PATCH /ABSOLUTE /NEW_VERSION /OUTPUT=KA410_XS.BIN KA410_XS_ORIG.BIN +! +! Test 1 - NI +! +! - Bypass network test +! +REPLACE/INSTRUCTION 00332 = 'BRB 00000384' +'NOP' +'NOP' +EXIT +! +UPDATE +EXIT +$ diff --git a/VAX/ka411.bin b/VAX/ka411.bin new file mode 100644 index 00000000..78d47fa4 Binary files /dev/null and b/VAX/ka411.bin differ diff --git a/VAX/ka412.bin b/VAX/ka412.bin new file mode 100644 index 00000000..e726cef5 Binary files /dev/null and b/VAX/ka412.bin differ diff --git a/VAX/ka41a.bin b/VAX/ka41a.bin new file mode 100644 index 00000000..fa64b3b4 Binary files /dev/null and b/VAX/ka41a.bin differ diff --git a/VAX/ka41d.bin b/VAX/ka41d.bin new file mode 100644 index 00000000..ee5a94b3 Binary files /dev/null and b/VAX/ka41d.bin differ diff --git a/VAX/ka420_rdrz.bin b/VAX/ka420_rdrz.bin new file mode 100644 index 00000000..8ec31e97 Binary files /dev/null and b/VAX/ka420_rdrz.bin differ diff --git a/VAX/ka420_rzrz.bin b/VAX/ka420_rzrz.bin new file mode 100644 index 00000000..7c8b9ad3 Binary files /dev/null and b/VAX/ka420_rzrz.bin differ diff --git a/VAX/ka42a.bin b/VAX/ka42a.bin new file mode 100644 index 00000000..1f2069c9 Binary files /dev/null and b/VAX/ka42a.bin differ diff --git a/VAX/ka42a_orig.bin b/VAX/ka42a_orig.bin new file mode 100644 index 00000000..ba5087a2 Binary files /dev/null and b/VAX/ka42a_orig.bin differ diff --git a/VAX/ka42a_patch.com b/VAX/ka42a_patch.com new file mode 100644 index 00000000..a7d5c22f --- /dev/null +++ b/VAX/ka42a_patch.com @@ -0,0 +1,19 @@ +$! +$! This procedure patches KA42A.BIN (V1.3) Boot ROM image to work under +$! the SIMH simulator +$! +$ PATCH /ABSOLUTE /NEW_VERSION /OUTPUT=KA42A.BIN KA42A_ORIG.BIN +! +! Test 4 - 8PLN +! +! - Ignore failures in 8PLN test for now +! +REPLACE/INSTRUCTION 00767 = 'BLBC R0,0000078E' +'NOP' +'NOP' +'NOP' +EXIT +! +UPDATE +EXIT +$ diff --git a/VAX/ka42b.bin b/VAX/ka42b.bin new file mode 100644 index 00000000..819ff5bb Binary files /dev/null and b/VAX/ka42b.bin differ diff --git a/VAX/ka42b_orig.bin b/VAX/ka42b_orig.bin new file mode 100644 index 00000000..610d5b17 Binary files /dev/null and b/VAX/ka42b_orig.bin differ diff --git a/VAX/ka42b_patch.com b/VAX/ka42b_patch.com new file mode 100644 index 00000000..b4a96f71 --- /dev/null +++ b/VAX/ka42b_patch.com @@ -0,0 +1,19 @@ +$! +$! This procedure patches KA42B.BIN (V1.5) Boot ROM image to work under +$! the SIMH simulator +$! +$ PATCH /ABSOLUTE /NEW_VERSION /OUTPUT=KA42B.BIN KA42B_ORIG.BIN +! +! Test 4 - 8PLN +! +! - Ignore failures in 8PLN test for now +! +REPLACE/INSTRUCTION 00767 = 'BLBC R0,0000078E' +'NOP' +'NOP' +'NOP' +EXIT +! +UPDATE +EXIT +$ diff --git a/VAX/ka43a.bin b/VAX/ka43a.bin new file mode 100644 index 00000000..54d89118 Binary files /dev/null and b/VAX/ka43a.bin differ diff --git a/VAX/ka46a.bin b/VAX/ka46a.bin new file mode 100644 index 00000000..d8647e38 Binary files /dev/null and b/VAX/ka46a.bin differ diff --git a/VAX/ka47a.bin b/VAX/ka47a.bin new file mode 100644 index 00000000..4de9758d Binary files /dev/null and b/VAX/ka47a.bin differ diff --git a/VAX/ka48a.bin b/VAX/ka48a.bin new file mode 100644 index 00000000..0c6ff1d5 Binary files /dev/null and b/VAX/ka48a.bin differ diff --git a/VAX/ka4xx_4pln.bin b/VAX/ka4xx_4pln.bin new file mode 100644 index 00000000..cdc0be05 Binary files /dev/null and b/VAX/ka4xx_4pln.bin differ diff --git a/VAX/ka4xx_8pln.bin b/VAX/ka4xx_8pln.bin new file mode 100644 index 00000000..a537f878 Binary files /dev/null and b/VAX/ka4xx_8pln.bin differ diff --git a/VAX/ka4xx_dz.bin b/VAX/ka4xx_dz.bin new file mode 100644 index 00000000..b1e16137 Binary files /dev/null and b/VAX/ka4xx_dz.bin differ diff --git a/VAX/ka4xx_spx.bin b/VAX/ka4xx_spx.bin new file mode 100644 index 00000000..c07b48ab Binary files /dev/null and b/VAX/ka4xx_spx.bin differ diff --git a/VAX/tests/vax-diag_test.ini b/VAX/tests/vax-diag_test.ini index 55109545..6ec217d5 100644 --- a/VAX/tests/vax-diag_test.ini +++ b/VAX/tests/vax-diag_test.ini @@ -23,9 +23,21 @@ if ("%1" == "-v") set console notelnet else set -qu console telnet=65432,telnet=buffered; set env -a DIAG_QUIET_MODE=1 goto DIAG_%SIM_BIN_NAME% +:DIAG_INFOSERVER100 +:DIAG_INFOSERVER1000 +:DIAG_INFOSERVER150VTX :DIAG_MICROVAX1 :DIAG_MICROVAX2 +:DIAG_MICROVAX2000 +:DIAG_MICROVAX3100 +:DIAG_MICROVAX3100E +:DIAG_MICROVAX3100M76 +:DIAG_MICROVAX3100M80 :DIAG_RTVAX1000 +:DIAG_VAXSTATION3100M30 +:DIAG_VAXSTATION3100M38 +:DIAG_VAXSTATION4000M60 +:DIAG_VAXSTATION4000VLC echof "No diagnostics are available for the %SIM_NAME% Simulator\n" exit 0 diff --git a/VAX/vax410_defs.h b/VAX/vax410_defs.h new file mode 100644 index 00000000..7f75db7f --- /dev/null +++ b/VAX/vax410_defs.h @@ -0,0 +1,361 @@ +/* vax410_defs.h: MicroVAX 2000 model-specific definitions file + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This file covers the KA410 ("TeamMate") system. + + System memory map + + 0000 0000 - 00FF FFFF main memory + 0100 0000 - 201F FFFF reserved + 2002 0000 - 2002 0003 configuration/test register + 2004 0000 - 2007 FFFF ROM space + 2008 0000 - 2008 000F local register space + 2009 0000 - 2009 007F network address ROM + 200A 0000 - 200A 000F serial line controller + 200B 0000 - 200B 00FF watch chip registers + 200C 0000 - 200C 0007 disk controller + 200C 0080 - 200C 00FF tape controller + 200D 0000 - 200D 3FFF disk/tape data buffer + 200F 0000 - 200F 003F monochrome video cursor chip + 2010 0000 - 2013 FFFF option ROMs + 3000 0000 - 3001 FFFF monochrome video RAM + 3002 0000 - 3FFF FFFF reserved +*/ + +#ifdef FULL_VAX /* subset VAX */ +#undef FULL_VAX +#endif + +#ifndef _VAX_410_DEFS_H_ +#define _VAX_410_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX410_SID (8 << 24) /* system ID */ +#define VAX410_UREV 0 /* ucode revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_PWRUP 0x0300 /* powerup code */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define CON_DBLMCK 0x0500 /* Machine check in machine check */ +#define CON_BADPSL 0x4000 /* invalid PSL flag */ +#define CON_MAPON 0x8000 /* mapping on flag */ +#define MCHK_READ 0x80 /* read check */ +#define MCHK_WRITE 0x82 /* write check */ + +/* Machine specific IPRs */ + +#define MT_CONISP 41 /* Console Saved ISP */ +#define MT_CONPC 42 /* Console Saved PC */ +#define MT_CONPSL 43 /* Console Saved PSL */ +#define MT_MAX 127 /* last valid IPR */ + +/* CPU */ + +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONGPX}", \ + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + +/* Memory */ + +#define MAXMEMWIDTH 24 /* max mem, std KA410 */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */ +#define MAXMEMWIDTH_X 24 /* max mem, KA410 */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << 24) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 21) + (1u << 20), NULL, "3M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 22) + (1u << 21), NULL, "6M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23) + (1u << 21), NULL, "10M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23) + (1u << 22) + (1u << 21), NULL, "14M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size } + +/* Config/test register */ + +#define CFGSIZE 4 /* CFG length */ +#define CFGBASE 0x20020000 /* CFG base */ + +/* Read only memory */ + +#define ROMAWIDTH 18 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */ +#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */ +#define ROMBASE 0x20040000 /* ROM base */ +#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \ + (((uint32) (x)) < (ROMBASE + ROMSIZE))) + +/* KA410 board registers */ + +#define KAAWIDTH 4 /* REG addr width */ +#define KASIZE (1u << KAAWIDTH) /* REG length */ +#define KABASE 0x20080000 /* REG addr base */ + +/* Network address ROM */ + +#define NARAWIDTH 5 /* NAR addr width */ +#define NARSIZE (1u << NARAWIDTH) /* NAR length */ +#define NARAMASK (NARSIZE - 1) /* NAR addr mask */ +#define NARBASE 0x20090000 /* NAR base */ + +/* Serial line controller */ + +#define DZSIZE 0x10 /* DZ length */ +#define DZBASE 0x200A0000 /* DZ base */ + +/* Non-volatile RAM - 1KB Bytes long */ + +#define NVRAWIDTH 10 /* NVR addr width */ +#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */ +#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */ +#define NVRBASE 0x200B0000 /* NVR base */ +#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \ + (((uint32) (x)) < (NVRBASE + NVRSIZE))) + +/* MFM disk controller */ + +#define RDSIZE 0x8 /* RD length */ +#define RDBASE 0x200C0000 /* RD base */ + +/* SCSI disk controller */ + +#define RZSIZE 0x50 /* RZ length */ +#define RZBASE 0x200C0080 /* RZ base */ + +/* 16k disk buffer */ + +#define D16AWIDTH 14 /* D16 addr width */ +#define D16SIZE (1u << D16AWIDTH) /* D16 length */ +#define D16AMASK (D16SIZE - 1) /* D16 addr mask */ +#define D16BASE 0x200D0000 /* D16 base */ + +/* LANCE Ethernet controller */ + +#define XSSIZE 0x8 /* XS length */ +#define XSBASE 0x200E0000 /* XS base */ + +/* Cursor chip */ + +#define CURSIZE 0x40 /* CUR length */ +#define CURBASE 0x200F0000 /* CUR base */ + +/* Option ROMs */ + +#define ORAWIDTH 20 /* OR addr width */ +#define ORSIZE (1u << ORAWIDTH) /* OR length */ +#define ORMASK (ORSIZE - 1) /* OR addr mask */ +#define ORBASE 0x20100000 /* OR base */ + +/* VC memory space */ + +#define VCAWIDTH 17 /* VC mem addr width */ +#define VCSIZE (1u << VCAWIDTH) /* VC mem length */ +#define VCAMASK (VCSIZE - 1) /* VC mem addr mask */ +#define VCBASE 0x30000000 /* VC mem base */ + +/* VA memory space */ + +#define VAAWIDTH 16 /* VA mem addr width */ +#define VASIZE (1u << VAAWIDTH) /* VA mem length */ +#define VAAMASK (VASIZE - 1) /* VA mem addr mask */ +#define VABASE 0x3C000000 /* VA mem base */ + +/* Other address spaces */ + +#define ADDR_IS_IO(x) (0) +#define ADDR_IS_CDG(x) (0) + +/* Machine specific reserved operand tests (mostly NOPs) */ + +#define ML_PA_TEST(r) +#define ML_LR_TEST(r) +#define ML_SBR_TEST(r) +#define ML_PXBR_TEST(r) +#define LP_AST_TEST(r) +#define LP_MBZ84_TEST(r) +#define LP_MBZ92_TEST(r) + +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_4XX (DEV_V_UF + 0) /* KA4xx I/O */ +#define DEV_4XX (1u << DEV_V_4XX) + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + int32 rom_index; /* option ROM index */ + uint8 *rom_array; /* option ROM code */ + t_addr rom_size; /* option ROM size */ + } DIB; + +/* Within each IPL, priority is left to right */ + +/* IPL 14 */ + +#define INT_V_SCA 0 /* storage controller 1 */ +#define INT_V_SCB 1 /* storage controller 2 */ +#define INT_V_VC2 2 /* video secondary */ +#define INT_V_VC1 3 /* video primary */ +#define INT_V_XS2 4 /* network secondary */ +#define INT_V_XS1 5 /* network primary */ +#define INT_V_DZTX 6 /* serial transmitter */ +#define INT_V_DZRX 7 /* serial receiver */ + +#define INT_SCA (1u << INT_V_SCA) +#define INT_SCB (1u << INT_V_SCB) +#define INT_VC2 (1u << INT_V_VC2) +#define INT_VC1 (1u << INT_V_VC1) +#define INT_XS2 (1u << INT_V_XS2) +#define INT_XS1 (1u << INT_V_XS1) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_DZRX (1u << INT_V_DZRX) + +#define IPL_CLK 0x16 +#define IPL_HW 0x14 /* hwre level */ +#define IPL_SCA (0x14 - IPL_HMIN) +#define IPL_SCB (0x14 - IPL_HMIN) +#define IPL_XS1 (0x14 - IPL_HMIN) +#define IPL_DZTX (0x14 - IPL_HMIN) +#define IPL_DZRX (0x14 - IPL_HMIN) +#define IPL_HMIN IPL_HW +#define IPL_HMAX IPL_HW +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Device vectors */ + +#define VEC_QBUS 0 /* Not a Qbus system */ +#define VEC_Q 0 + +/* Interrupt macros */ + +#define IREQ(dv) int_req[0] +#define SET_INT(dv) int_req[0] = int_req[0] | (INT_##dv) +#define CLR_INT(dv) int_req[0] = int_req[0] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* System model */ + +extern int32 sys_model; + +/* Machine specific definitions - DZ */ + +#define DZ_L3C 1 /* line 3 console */ + +/* Machine specific definitions - OR */ + +#define OR_COUNT 4 /* max number of option ROMs */ + +/* Machine specific definitions - RZ80 */ + +#define RZ_ROM_INDEX -1 /* no ROM needed */ +#define DMA_SIZE 0x4000 /* DMA count register */ +#define DCNT_MASK 0xFFFF +#define RZ_FLAGS 0 /* permanently enabled */ +#define RZB_FLAGS (DEV_DIS) /* not present */ +#define RZ_SCSI_ID 0 /* initiator SCSI id */ + +/* Machine specific definitions - RD */ + +#define RD_ROM_INDEX -1 /* no ROM needed */ +#define RD_FLAGS 0 /* permanently enabled */ + +/* Machine specific definitions - VA */ + +#define VA_ROM_INDEX 1 +#define VA_PLANES 4 /* 4bpp */ + +/* Machine specific definitions - VC */ + +#define VC_BYSIZE 1024 /* buffer height */ +#define VC_BUFSIZE (1u << 15) /* number of longwords */ +#define VC_ORSC 2 /* screen origin multiplier */ + +/* Machine specific definitions - XS */ + +#define XS_ROM_INDEX 0 +#define XS_FLAGS (DEV_DIS | DEV_DISABLE) +#define XS_READB Map_ReadB +#define XS_READW Map_ReadW +#define XS_WRITEB Map_WriteB +#define XS_WRITEW Map_WriteW + + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +/* Function prototypes for disk buffer */ + +void ddb_WriteB (uint32 ba, uint32 bc, uint8 *buf); +void ddb_WriteW (uint32 ba, uint32 bc, uint16 *buf); +void ddb_ReadB (uint32 ba, uint32 bc, uint8 *buf); +void ddb_ReadW (uint32 ba, uint32 bc, uint16 *buf); + +/* Function prototypes for system-specific unaligned support */ + +int32 ReadIOU (uint32 pa, int32 lnt); +int32 ReadRegU (uint32 pa, int32 lnt); +void WriteIOU (uint32 pa, int32 val, int32 lnt); +void WriteRegU (uint32 pa, int32 val, int32 lnt); + +t_stat auto_config (const char *name, int32 nctrl); + +/* Function prototypes for virtual and physical memory interface (inlined) */ + +#include "vax_mmu.h" + +#endif diff --git a/VAX/vax410_sysdev.c b/VAX/vax410_sysdev.c new file mode 100644 index 00000000..f224c045 --- /dev/null +++ b/VAX/vax410_sysdev.c @@ -0,0 +1,981 @@ +/* vax410_sysdev.c: MicroVAX 2000 system-specific logic + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the MicroVAX 2000 system-specific registers and devices. + + sysd system devices +*/ + +#include "vax_defs.h" +#include + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "ka410.bin" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_ka410_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ + + +t_stat vax410_boot (int32 flag, CONST char *ptr); + +/* Special boot command, overrides regular boot */ + +CTAB vax410_cmd[] = { + { "BOOT", &vax410_boot, RU_BOOT, + "bo{ot} boot simulator\n", NULL, &run_cmd_message }, + { NULL } + }; + +/* KA410 configuration & test register */ + +#define CFGT_MEM 0x07 /* memory option */ +#define CFGT_VID 0x08 /* video option */ +#define CFGT_CUR 0x10 /* cursor test */ +#define CFGT_L3C 0x20 /* line 3 console */ +#define CFGT_NET 0x40 /* network option */ +#define CFGT_TYP 0x80 /* multi-char user */ + +/* KA410 Memory system error register */ + +#define MSER_PE 0x00000001 /* Parity Enable */ +#define MSER_WWP 0x00000002 /* Write Wrong Parity */ +#define MSER_PER 0x00000040 /* Parity Error */ +#define MSER_MCD0 0x00000100 /* Mem Code 0 */ +#define MSER_MBZ 0xFFFFFEBC +#define MSER_RD (MSER_PE | MSER_WWP | MSER_PER | \ + MSER_PER | MSER_MCD0) +#define MSER_WR (MSER_PE | MSER_WWP) +#define MSER_RS (MSER_PER) + +/* KA410 memory error address reg */ + +#define MEAR_FAD 0x00007FFF /* failing addr */ +#define MEAR_RD (MEAR_FAD) + +#define ROM_VEC 0x8 /* ROM longword for first device vector */ + +extern int32 tmr_int; +extern UNIT clk_unit; +extern int32 tmr_poll; +extern uint32 vc_sel, vc_org; +extern DEVICE va_dev, vc_dev, lk_dev, vs_dev; +extern DEVICE xs_dev; +extern uint32 *rom; + +uint32 *ddb = NULL; /* 16k disk buffer */ +int32 conisp, conpc, conpsl; /* console reg */ +int32 ka_hltcod = 0; /* KA410 halt code */ +int32 ka_mser = 0; /* KA410 mem sys err */ +int32 ka_mear = 0; /* KA410 memory err */ +int32 ka_cfgtst = 0; /* KA410 config/test */ +int32 buf_sel = 0; /* buffer select */ +int32 sys_model = 0; /* MicroVAX or VAXstation */ +int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */ +int32 int_mask = 0; /* interrupt mask */ + +t_stat sysd_reset (DEVICE *dptr); +const char *sysd_description (DEVICE *dptr); +int32 ka_rd (int32 pa); +void ka_wr (int32 pa, int32 val, int32 lnt); +int32 con_halt (int32 code, int32 cc); + +extern t_stat or_map (uint32 index, uint8 *rom, t_addr size); +extern t_stat or_unmap (uint32 index); +extern void rom_wr_B (int32 pa, int32 val); +extern int32 iccs_rd (void); +extern int32 rom_rd (int32 pa); +extern int32 nvr_rd (int32 pa); +extern int32 nar_rd (int32 pa); +extern int32 dz_rd (int32 pa); +extern int32 rd_rd (int32 pa); +extern int32 rz_rd (int32 pa); +extern int32 or_rd (int32 pa); +extern int32 xs_rd (int32 pa); +extern int32 va_rd (int32 pa); +extern int32 vc_mem_rd (int32 pa); +extern void iccs_wr (int32 dat); +extern void nvr_wr (int32 pa, int32 val, int32 lnt); +extern void rd_wr (int32 pa, int32 val, int32 lnt); +extern void dz_wr (int32 pa, int32 val, int32 lnt); +extern void vc_wr (int32 pa, int32 val, int32 lnt); +extern void xs_wr (int32 pa, int32 val, int32 lnt); +extern void rz_wr (int32 pa, int32 val, int32 lnt); +extern void va_wr (int32 pa, int32 val, int32 lnt); +extern void vc_mem_wr (int32 pa, int32 val, int32 lnt); + +/* SYSD data structures + + sysd_dev SYSD device descriptor + sysd_unit SYSD units + sysd_reg SYSD register list +*/ + +UNIT sysd_unit = { UDATA (NULL, 0, 0) }; + +REG sysd_reg[] = { + { HRDATAD (CONISP, conisp, 32, "console ISP") }, + { HRDATAD (CONPC, conpc, 32, "console PD") }, + { HRDATAD (CONPSL, conpsl, 32, "console PSL") }, + { HRDATAD (HLTCOD, ka_hltcod, 16, "KA410 halt code") }, + { HRDATAD (MSER, ka_mser, 8, "KA410 mem sys err") }, + { HRDATAD (MEAR, ka_mear, 8, "KA410 mem err") }, + { HRDATAD (CFGTST, ka_cfgtst, 8, "KA410 config/test register") }, + { NULL } + }; + +MTAB sysd_mod[] = { + { 0 }, + }; + +DEVICE sysd_dev = { + "SYSD", &sysd_unit, sysd_reg, sysd_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysd_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, + &sysd_description + }; + +/* Find highest priority outstanding interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_CLK) && tmr_int) /* clock int */ + return IPL_CLK; +if (ipl < IPL_HW) { /* chk hwre int */ + if (int_req[0] & int_mask) + return IPL_HW; + } +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i; +int32 int_unmask = int_req[0] & int_mask; + +if (lvl == IPL_CLK) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +for (i = 7; int_unmask && (i >= 0); i--) { + if ((int_unmask >> i) & 1) { + int_req[0] = int_req[0] & ~(1u << i); + return rom[ROM_VEC + i] & 0x3FF; /* get vector from ROM */ + } + } +return 0; +} + +/* DMA buffer routines, aligned access + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + *buf = ReadB (ma); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ma = ma + 4; + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + *buf = ReadW (ma); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + WriteB (ma, *buf); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + WriteW (ma, *buf); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +void ddb_WriteB (uint32 ba, uint32 bc, uint8 *buf) +{ +uint32 i, id, sc, mask, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + id = (ba >> 2) & 0xFFF; + sc = (ba & 3) << 3; + mask = 0xFF << sc; + ddb[id] = (ddb[id] & ~mask) | (*buf << sc); + ba++; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0xFFF; + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + ddb[id] = dat; /* store lw */ + ba = ba + 4; + } + } +} + +void ddb_WriteW (uint32 ba, uint32 bc, uint16 *buf) +{ +uint32 i, id, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + id = (ba >> 2) & 0xFFF; + ddb[id] = (ba & 2)? (ddb[id] & 0xFFFF) | (*buf << 16): + (ddb[id] & ~0xFFFF) | *buf; + ba = ba + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0xFFF; + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + ddb[id] = dat; /* store lw */ + ba = ba + 4; + } + } +} + +void ddb_ReadB (uint32 ba, uint32 bc, uint8 *buf) +{ +uint32 i, id, sc, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + id = (ba >> 2) & 0xFFF; + sc = (ba & 3) << 3; + *buf = (ddb[id] >> sc) & BMASK; + ba++; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0xFFF; + dat = ddb[id]; /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ba = ba + 4; + } + } +} + +void ddb_ReadW (uint32 ba, uint32 bc, uint16 *buf) +{ +uint32 i, id, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + id = (ba >> 2) & 0xFFF; + *buf = (ba & 2)? ((ddb[id] >> 16) & 0xFFFF) : + (ddb[id] & 0xFFFF); + ba = ba + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0xFFF; + dat = ddb[id]; /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ba = ba + 4; + } + } +} + +int32 ddb_rd (int32 pa) +{ +int32 rg = (pa - D16BASE) >> 2; +return ddb[rg]; +} + +void ddb_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - D16BASE) >> 2; +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + ddb[rg] = ((val & mask) << sc) | (ddb[rg] & ~(mask << sc)); + } +else ddb[rg] = val; +} + +int32 cfg_rd (int32 pa) +{ +return ka_cfgtst; +} + +void ioreset_wr (int32 pa, int32 val, int32 lnt) +{ +reset_all (7); +} + +/* Read KA410 specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_NICR: + val = 0; + break; + + case MT_CONISP: /* console ISP */ + val = conisp; + break; + + case MT_CONPC: /* console PC */ + val = conpc; + break; + + case MT_CONPSL: /* console PSL */ + val = conpsl; + break; + + case MT_SID: /* SID */ + val = VAX410_SID | VAX410_UREV; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write KA410 specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_NICR: + break; + + case MT_CONISP: /* console ISP */ + conisp = val; + break; + + case MT_CONPC: /* console PC */ + conpc = val; + break; + + case MT_CONPSL: /* console PSL */ + conpsl = val; + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* Read/write I/O register space + + These routines are the 'catch all' for address space map. Any + address that doesn't explicitly belong to memory, I/O, or ROM + is given to these routines for processing. +*/ + +struct reglink { /* register linkage */ + uint32 low; /* low addr */ + uint32 high; /* high addr */ + int32 (*read)(int32 pa); /* read routine */ + void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */ + int32 width; /* data path width */ + }; + +struct reglink regtable[] = { + { VCBASE, VCBASE+VCSIZE, &vc_mem_rd, &vc_mem_wr, L_LONG }, + { VABASE, VABASE+VASIZE, &va_rd, &va_wr, L_WORD }, + { D16BASE, D16BASE+D16SIZE, &ddb_rd, &ddb_wr, L_LONG }, + { RDBASE, RDBASE+RDSIZE, &rd_rd, &rd_wr, L_LONG }, + { RZBASE, RZBASE+RZSIZE, &rz_rd, &rz_wr, L_LONG }, + { XSBASE, XSBASE+XSSIZE, &xs_rd, &xs_wr, L_LONG }, + { DZBASE, DZBASE+DZSIZE, &dz_rd, dz_wr, L_LONG }, + { CURBASE, CURBASE+CURSIZE, NULL, &vc_wr, L_LONG }, + { ORBASE, ORBASE+ORSIZE, &or_rd, NULL, L_LONG }, + { NARBASE, NARBASE+NARSIZE, &nar_rd, NULL, L_LONG }, + { CFGBASE, CFGBASE+CFGSIZE, &cfg_rd, &ioreset_wr, L_LONG }, + { ROMBASE, ROMBASE+ROMSIZE, &rom_rd, NULL, L_LONG }, + { NVRBASE, NVRBASE+NVRSIZE, &nvr_rd, &nvr_wr, L_LONG }, + { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr, L_LONG }, + { 0, 0, NULL, NULL } + }; + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) - ignored + Output: + longword of data +*/ + +int32 ReadReg (uint32 pa, int32 lnt) +{ +struct reglink *p; +int32 val; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) { + val = p->read (pa); + if (p->width < L_LONG) { + if (lnt < L_LONG) + val = val << ((pa & 2)? 16: 0); + else val = (p->read (pa + 2) << 16) | val; + } + return val; + } + } +return 0xFFFFFFFF; +} + +/* ReadRegU - read register space, unaligned + + Inputs: + pa = physical address + lnt = length in bytes (1, 2, or 3) + Output: + returned data, not shifted +*/ + +int32 ReadRegU (uint32 pa, int32 lnt) +{ +struct reglink *p; +int32 val; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) { + if (p->width < L_LONG) { + val = p->read (pa); + if ((lnt + (pa & 1)) <= 2) + val = val << ((pa & 2)? 16: 0); + else val = (p->read (pa + 2) << 16) | val; + } + else { + if (lnt == L_BYTE) + val = p->read (pa & ~03); + else val = (p->read (pa & ~03) & WMASK) | (p->read ((pa & ~03) + 2) & (WMASK << 16)); + } + return val; + } + } +return 0xFFFFFFFF; +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + if (lnt > p->width) { + p->write (pa, val & WMASK, L_WORD); + p->write (pa + 2, (val >> 16) & WMASK, L_WORD); + } + else p->write (pa, val, lnt); + return; + } + } +return; +} + +/* WriteRegU - write register space, unaligned + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (1, 2, or 3) + Outputs: + none +*/ + +void WriteRegU (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + if (p->width < L_LONG) { + switch (lnt) { + case L_BYTE: /* byte */ + p->write (pa, val & BMASK, L_BYTE); + break; + + case L_WORD: /* word */ + if (pa & 1) { /* odd addr */ + p->write (pa, val & BMASK, L_BYTE); + p->write (pa + 1, (val >> 8) & BMASK, L_BYTE); + } + else p->write (pa, val & WMASK, L_WORD); + break; + + case 3: /* tribyte */ + if (pa & 1) { /* odd addr */ + p->write (pa, val & BMASK, L_BYTE); /* byte then word */ + p->write (pa + 1, (val >> 8) & WMASK, L_WORD); + } + else { /* even */ + p->write (pa, val & WMASK, L_WORD); /* word then byte */ + p->write (pa + 2, (val >> 16) & BMASK, L_BYTE); + } + break; + } + } + else if (p->read) { + int32 sc = (pa & 03) << 3; + int32 dat = p->read (pa & ~03); + + dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc); + p->write (pa & ~03, dat, L_LONG); + } + return; + } + } +return; +} + +/* KA410 registers */ + +int32 ka_rd (int32 pa) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* HLTCOD */ + return ka_hltcod; + + case 1: /* MSER */ + return ka_mser & MSER_RD; + + case 2: /* MEAR */ + return ka_mear & MEAR_RD; + + case 3: /* INT_REQ, VDC_SEL, VDC_ORG, INT_MSK */ + return ((int_req[0] & BMASK) << 24) | \ + ((vc_sel & 1) << 16) | \ + ((vc_org & BMASK) << 8) | \ + (int_mask & BMASK); + } + +return 0; +} + +void ka_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* HLTCOD */ + ka_hltcod = val; + break; + + case 1: /* MSER */ + ka_mser = (ka_mser & ~MSER_WR) | (val & MSER_WR); + ka_mser = ka_mser & ~(val & MSER_RS); + break; + + case 2: /* MEAR */ + /* read only? */ + break; + + case 3: + switch (pa & 3) { + case 0: /* INT_MSK */ + int_mask = val & BMASK; + SET_IRQL; + break; + + case 1: /* VDC_ORG */ + vc_org = val & BMASK; + break; + + case 2: /* VDC_SEL */ + vc_sel = val & 1; + break; + + case 3: /* INT_CLR */ + int_req[0] = int_req[0] & ~(val & BMASK); + break; + } + break; + } +return; +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 st, p2, acc; + +if (in_ie) { + in_ie = 0; + return con_halt(CON_DBLMCK, cc); /* double machine check */ + } +if (p1 & 0x80) /* mref? set v/p */ + p1 = p1 + mchk_ref; +p2 = mchk_va + 4; /* save vap */ +st = 0; +if (p1 & 0x80) /* mref? */ + cc = intexc (SCB_MCHK, cc, 0, IE_EXC); /* take normal exception */ +else cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take severe exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 16; /* push 4 words */ +Write (SP, 12, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +Write (SP + 8, p2, L_LONG, WA); /* address */ +Write (SP + 12, st, L_LONG, WA); /* state */ +in_ie = 0; +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +int32 temp; + +conisp = IS; /* save ISP */ +conpc = PC; /* save PC */ +conpsl = ((PSL | cc) & 0xFFFF00FF) | code; /* PSL, param */ +temp = (PSL >> PSL_V_CUR) & 0x7; /* get is'cur */ +if (temp > 4) /* invalid? */ + conpsl = conpsl | CON_BADPSL; +else STK[temp] = SP; /* save stack */ +if (mapen) /* mapping on? */ + conpsl = conpsl | CON_MAPON; +mapen = 0; /* turn off map */ +SP = IS; /* set SP from IS */ +PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */ +JUMP (ROMBASE); /* PC = 20040000 */ +return 0; /* new cc = 0 */ +} + + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {CPU} + +*/ + +t_stat vax410_boot (int32 flag, CONST char *ptr) +{ +char gbuf[CBUFSIZE]; + +get_glyph (ptr, gbuf, 0); /* get glyph */ +if (gbuf[0] && strcmp (gbuf, "CPU")) + return SCPE_ARG; /* Only can specify CPU device */ +return run_cmd (flag, "CPU"); +} + + +/* Bootstrap */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; +DEVICE *cdptr; +int32 i; + +PC = ROMBASE; +PSL = PSL_IS | PSL_IPL1F; +conisp = 0; +conpc = 0; +conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP; +if (rom == NULL) + return SCPE_IERR; +if (*rom == 0) { /* no boot? */ + r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0); + if (r != SCPE_OK) + return r; + } +rom_wr_B (ROMBASE+4, sys_model ? 2 : 1); /* Set Magic Byte to determine system type */ +rom_wr_B (ROMBASE+0x14B6, (int32)(sys_model ? 'B' : 'A')); +for (i = 0; i < OR_COUNT; i++) /* unmap all option ROMs */ + or_unmap (i); +for (i = 0; (cdptr = sim_devices[i]) != NULL; i++) { /* loop over all devices */ + DIB *cdibp = (DIB *)(cdptr->ctxt); + + if (!cdibp || (cdptr->flags & DEV_DIS)) /* device enabled and has DIB? */ + continue; + + if (cdibp->rom_array != NULL) /* device has an option ROM? */ + or_map (cdibp->rom_index, cdibp->rom_array, cdibp->rom_size); + } +return SCPE_OK; +} + +/* SYSD reset */ + +t_stat sysd_reset (DEVICE *dptr) +{ +ka_mser = 0; +ka_mear = 0; +ka_cfgtst = (CFGT_TYP | CFGT_CUR); +if (MEMSIZE > (1u << 21)) /* more than 2MB? */ + ka_cfgtst |= ((MEMSIZE >> 21) & CFGT_MEM); +if ((vc_dev.flags & DEV_DIS) == 0) /* mono video enabled? */ + ka_cfgtst &= ~CFGT_TYP; +if ((va_dev.flags & DEV_DIS) == 0) { /* video option present? */ + ka_cfgtst &= ~CFGT_TYP; + ka_cfgtst |= CFGT_VID; + } +if ((xs_dev.flags & DEV_DIS) == 0) /* network option present? */ + ka_cfgtst |= CFGT_NET; +if (DZ_L3C && (sys_model == 0)) /* line 3 console */ + ka_cfgtst |= CFGT_L3C; + +if (ddb == NULL) + ddb = (uint32 *) calloc (D16SIZE >> 2, sizeof (uint32)); +if (ddb == NULL) + return SCPE_MEM; + +sim_vm_cmd = vax410_cmd; + +return SCPE_OK; +} + +const char *sysd_description (DEVICE *dptr) +{ +return "system devices"; +} + +t_stat auto_config (const char *name, int32 nctrl) +{ +return SCPE_OK; +} + +t_stat build_dib_tab (void) +{ +return SCPE_OK; +} + +t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +char gbuf[CBUFSIZE]; + +if ((cptr == NULL) || (!*cptr)) + return SCPE_ARG; +cptr = get_glyph (cptr, gbuf, 0); +if (MATCH_CMD(gbuf, "MICROVAX") == 0) { + sys_model = 0; +#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL) + va_dev.flags = vc_dev.flags | DEV_DIS; /* disable GPX */ + vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable MVO */ + lk_dev.flags = lk_dev.flags | DEV_DIS; /* disable keyboard */ + vs_dev.flags = vs_dev.flags | DEV_DIS; /* disable mouse */ +#endif + strcpy (sim_name, "MicroVAX 2000 (KA410)"); + reset_all (0); /* reset everything */ + } +else if (MATCH_CMD(gbuf, "VAXSTATION") == 0) { +#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL) + sys_model = 1; + va_dev.flags = va_dev.flags | DEV_DIS; /* disable GPX */ + vc_dev.flags = vc_dev.flags & ~DEV_DIS; /* enable MVO */ + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ + strcpy (sim_name, "VAXStation 2000 (KA410)"); + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +else if (MATCH_CMD(gbuf, "VAXSTATIONGPX") == 0) { +#if defined (USE_SIM_VIDEO) && defined (HAVE_LIBSDL) + sys_model = 1; + vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable MVO */ + va_dev.flags = va_dev.flags & ~DEV_DIS; /* enable GPX */ + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ + strcpy (sim_name, "VAXStation 2000 GPX (KA410)"); + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +else + return SCPE_ARG; +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "%s", sim_name); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Initial memory size is 16MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BOOT\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax410_syslist.c b/VAX/vax410_syslist.c new file mode 100644 index 00000000..66b5381c --- /dev/null +++ b/VAX/vax410_syslist.c @@ -0,0 +1,127 @@ +/* vax410_syslist.c: MicroVAX 2000 device list + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). +*/ + +#include "vax_defs.h" + +char sim_name[64] = "MicroVAX 2000 (KA410)"; + +void vax_init(void) +{ +sim_savename = "MicroVAX 2000 (KA410)"; +} + +WEAK void (*sim_vm_init) (void) = &vax_init; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE rom_dev; +extern DEVICE nvr_dev; +extern DEVICE nar_dev; +extern DEVICE wtc_dev; +extern DEVICE sysd_dev; +extern DEVICE clk_dev; +extern DEVICE or_dev; +extern DEVICE rd_dev; +extern DEVICE rz_dev; +extern DEVICE dz_dev; +extern DEVICE xs_dev; +extern DEVICE va_dev; +extern DEVICE vc_dev; +extern DEVICE lk_dev; +extern DEVICE vs_dev; + +extern void WriteB (uint32 pa, int32 val); +extern void rom_wr_B (int32 pa, int32 val); +extern UNIT cpu_unit; + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &rom_dev, + &nvr_dev, + &nar_dev, + &wtc_dev, + &sysd_dev, + &clk_dev, + &or_dev, + &dz_dev, + &va_dev, + &vc_dev, + &lk_dev, + &vs_dev, + &rd_dev, + &rz_dev, + &xs_dev, + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -r load ROM + -n load NVR + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag) +{ +t_stat r; +int32 i; +uint32 origin, limit; + +if (flag) /* dump? */ + return sim_messagef (SCPE_NOFNC, "Command Not Implemented\n"); +if (sim_switches & SWMASK ('R')) { /* ROM? */ + origin = ROMBASE; + limit = ROMBASE + ROMSIZE; + } +else if (sim_switches & SWMASK ('N')) { /* NVR? */ + origin = NVRBASE; + limit = NVRBASE + NVRSIZE; + } +else { + origin = 0; /* memory */ + limit = (uint32) cpu_unit.capac; + if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + } +while ((i = Fgetc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + if (sim_switches & SWMASK ('R')) /* ROM? */ + rom_wr_B (origin, i); /* not writeable */ + else WriteB (origin, i); /* store byte */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax420_defs.h b/VAX/vax420_defs.h new file mode 100644 index 00000000..21c4da98 --- /dev/null +++ b/VAX/vax420_defs.h @@ -0,0 +1,412 @@ +/* vax420_defs.h: MicroVAX 3100 model-specific definitions file + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This file covers the KA420 ("TeamMate II" & "PVAX") systems. + + System memory map + + 0000 0000 - 01FF FFFF main memory + 0200 0000 - 201F FFFF reserved + 2002 0000 - 2002 0003 configuration/test register + 2004 0000 - 2007 FFFF ROM space + 2008 0000 - 2008 001F local register space + 2009 0000 - 2009 007F network address ROM + 200A 0000 - 200A 000F serial line controller + 200B 0000 - 200B 00FF watch chip registers + 200C 0000 - 200C 0007 st506 disk controller + 200C 0080 - 200C 00FF scsi controller A + 200C 0180 - 200C 01FF scsi controller B + 200D 0000 - 200D 3FFF 16k disk data buffer + 200F 0000 - 200F 003F monochrome video cursor chip + 2010 0000 - 2013 FFFF option ROMs + 202D 0000 - 202E FFFF 128k disk data buffer + 3000 0000 - 3001 FFFF monochrome video RAM + 3002 0000 - 3FFF FFFF reserved +*/ + +#ifdef FULL_VAX /* subset VAX */ +#undef FULL_VAX +#endif + +#ifndef _VAX_420_DEFS_H_ +#define _VAX_420_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX420_SID (10 << 24) /* system ID */ +#define VAX420_UREV 5 /* ucode revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_PWRUP 0x0300 /* powerup code */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define CON_DBLMCK 0x0500 /* Machine check in machine check */ +#define CON_BADPSL 0x4000 /* invalid PSL flag */ +#define CON_MAPON 0x8000 /* mapping on flag */ +#define MCHK_READ 0x80 /* read check */ +#define MCHK_WRITE 0x82 /* write check */ + +/* Machine specific IPRs */ + +#define MT_CADR 37 /* Cache disable reg */ +#define MT_CAER 39 /* Cache error reg */ +#define MT_CONISP 41 /* Console Saved ISP */ +#define MT_CONPC 42 /* Console Saved PC */ +#define MT_CONPSL 43 /* Console Saved PSL */ +#define MT_MAX 127 /* last valid IPR */ + +/* Cache disable register */ + +#define CADR_RW 0xF3 +#define CADR_MBO 0x0C + +/* CPU */ + +#if defined (VAX_411) || defined (VAX_412) +#define CPU_MODEL_MODIFIERS \ + { 0 } +#else +#if defined (VAX_41A) || defined (VAX_41D) +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSERVER}", \ + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } +#else /* defined (VAX_42A) || defined (VAX_42B) */ +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONGPX|VAXSTATIONSPX}", \ + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } +#endif +#endif + +/* Memory */ + +#define MAXMEMWIDTH 25 /* max mem, std KA420 */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */ +#define MAXMEMWIDTH_X 25 /* max mem, KA420 */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << 24) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23) + (1u << 22), NULL, "12M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24) + (1u << 22), NULL, "20M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24) + (1u << 23), NULL, "24M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24) + (1u << 23) + (1u << 22), NULL, "28M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size } + +/* Config/test register */ + +#define CFGSIZE 4 /* CFG length */ +#define CFGBASE 0x20020000 /* CFG base */ + +/* Read only memory */ + +#define ROMAWIDTH 18 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */ +#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */ +#define ROMBASE 0x20040000 /* ROM base */ +#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \ + (((uint32) (x)) < (ROMBASE + ROMSIZE))) + +/* KA420 board registers */ + +#define KAAWIDTH 5 /* REG addr width */ +#define KASIZE (1u << KAAWIDTH) /* REG length */ +#define KABASE 0x20080000 /* REG addr base */ + +/* Network address ROM */ + +#define NARAWIDTH 5 /* NAR addr width */ +#define NARSIZE (1u << NARAWIDTH) /* NAR length */ +#define NARAMASK (NARSIZE - 1) /* NAR addr mask */ +#define NARBASE 0x20090000 /* NAR base */ + +/* Serial line controller */ + +#define DZSIZE 0x10 /* DZ length */ +#define DZBASE 0x200A0000 /* DZ base */ + +/* Non-volatile RAM - 1KB Bytes long */ + +#define NVRAWIDTH 10 /* NVR addr width */ +#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */ +#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */ +#define NVRBASE 0x200B0000 /* NVR base */ +#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \ + (((uint32) (x)) < (NVRBASE + NVRSIZE))) + +/* MFM disk controller */ + +#define RDSIZE 0x8 /* RD length */ +#define RDBASE 0x200C0000 /* RD base */ + +/* SCSI disk controller */ + +#define RZSIZE 0x50 /* RZ length */ +#define RZBASE 0x200C0080 /* RZ base */ +#define RZBBASE 0x200C0180 /* RZB base */ + +/* 16k disk buffer */ + +#define D16AWIDTH 14 /* D16 addr width */ +#define D16SIZE (1u << D16AWIDTH) /* D16 length */ +#define D16AMASK (D16SIZE - 1) /* D16 addr mask */ +#define D16BASE 0x200D0000 /* D16 base */ + +/* LANCE Ethernet controller */ + +#define XSSIZE 0x8 /* XS length */ +#define XSBASE 0x200E0000 /* XS base */ + +/* Cursor chip */ + +#define CURSIZE 0x40 /* CUR length */ +#define CURBASE 0x200F0000 /* CUR base */ + +/* Option ROMs */ + +#define ORAWIDTH 20 /* OR addr width */ +#define ORSIZE (1u << ORAWIDTH) /* OR length */ +#define ORMASK (ORSIZE - 1) /* OR addr mask */ +#define ORBASE 0x20100000 /* OR base */ + +/* 128k disk buffer */ + +#define D128AWIDTH 17 /* D128 addr width */ +#define D128SIZE (1u << D128AWIDTH) /* D128 length */ +#define D128AMASK (D128SIZE - 1) /* D128 addr mask */ +#define D128BASE 0x202D0000 /* D128 base */ + +/* VC memory space */ + +#define VCAWIDTH 17 /* VC mem addr width */ +#define VCSIZE (1u << VCAWIDTH) /* VC mem length */ +#define VCAMASK (VCSIZE - 1) /* VC mem addr mask */ +#define VCBASE 0x30000000 /* VC mem base */ + +/* VE memory space */ + +#define VEAWIDTH 26 /* VE mem addr width */ +#define VESIZE (1u << VEAWIDTH) /* VE mem length */ +#define VEAMASK (VESIZE - 1) /* VE mem addr mask */ +#define VEBASE 0x38000000 /* VE mem base */ + +/* VA memory space */ + +#define VAAWIDTH 16 /* VA mem addr width */ +#define VASIZE (1u << VAAWIDTH) /* VA mem length */ +#define VAAMASK (VASIZE - 1) /* VA mem addr mask */ +#define VABASE 0x3C000000 /* VA mem base */ + +/* Other address spaces */ + +#define ADDR_IS_IO(x) (0) +#define ADDR_IS_CDG(x) (0) + +/* Machine specific reserved operand tests (mostly NOPs) */ + +#define ML_PA_TEST(r) +#define ML_LR_TEST(r) +#define ML_SBR_TEST(r) +#define ML_PXBR_TEST(r) +#define LP_AST_TEST(r) +#define LP_MBZ84_TEST(r) +#define LP_MBZ92_TEST(r) + +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_4XX (DEV_V_UF + 0) /* KA4xx I/O */ +#define DEV_4XX (1u << DEV_V_4XX) + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + int32 rom_index; /* option ROM index */ + uint8 *rom_array; /* option ROM code */ + t_addr rom_size; /* option ROM size */ + } DIB; + +/* Within each IPL, priority is left to right */ + +/* IPL 14 */ + +#define INT_V_SCA 0 /* storage controller 1 */ +#define INT_V_SCB 1 /* storage controller 2 */ +#define INT_V_VC2 2 /* video secondary */ +#define INT_V_VC1 3 /* video primary */ +#define INT_V_XS2 4 /* network secondary */ +#define INT_V_XS1 5 /* network primary */ +#define INT_V_DZTX 6 /* serial transmitter */ +#define INT_V_DZRX 7 /* serial receiver */ + +#define INT_SCA (1u << INT_V_SCA) +#define INT_SCB (1u << INT_V_SCB) +#define INT_VC2 (1u << INT_V_VC2) +#define INT_VC1 (1u << INT_V_VC1) +#define INT_XS2 (1u << INT_V_XS2) +#define INT_XS1 (1u << INT_V_XS1) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_DZRX (1u << INT_V_DZRX) + +#define IPL_CLK 0x16 +#define IPL_HW 0x14 /* hwre level */ +#define IPL_SCA (0x14 - IPL_HMIN) +#define IPL_SCB (0x14 - IPL_HMIN) +#define IPL_XS1 (0x14 - IPL_HMIN) +#define IPL_DZTX (0x14 - IPL_HMIN) +#define IPL_DZRX (0x14 - IPL_HMIN) +#define IPL_HMIN IPL_HW +#define IPL_HMAX IPL_HW +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Device vectors */ + +#define VEC_QBUS 0 /* Not a Qbus system */ +#define VEC_Q 0 + +/* Interrupt macros */ + +#define IREQ(dv) int_req[0] +#define SET_INT(dv) int_req[0] = int_req[0] | (INT_##dv) +#define CLR_INT(dv) int_req[0] = int_req[0] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* System model */ + +extern int32 sys_model; + +/* Machine specific definitions - DZ */ + +#if (defined (VAX_411) || defined (VAX_412)) /* infoserver? */ +#define DZ_L3C 0 /* line 0 console */ +#else +#define DZ_L3C 1 /* line 3 console */ +#endif + +/* Machine specific definitions - OR */ + +#define OR_COUNT 4 /* max number of option ROMs */ + +/* Machine specific definitions - RZ80 */ + +#define RZ_ROM_INDEX 0 +#define DMA_SIZE 0x20000 /* DMA count register */ +#define DCNT_MASK 0x1FFFF +#if defined (VAX_42A) || defined (VAX_42B) +#define RZ_FLAGS (DEV_DISABLE) /* allow disable */ +#define RZB_FLAGS (DEV_DIS | DEV_DISABLE) /* allow disable */ +#else +#define RZ_FLAGS 0 /* permanently enabled */ +#define RZB_FLAGS 0 /* permanently enabled */ +#endif +#define RZ_SCSI_ID 6 /* initiator SCSI id */ + +/* Machine specific definitions - RD */ + +#define RD_ROM_INDEX 0 +#if defined (VAX_42A) || defined (VAX_42B) +#define RD_FLAGS (DEV_DISABLE) /* allow disable */ +#else +#define RD_FLAGS (DEV_DIS) /* not present */ +#endif + +/* Machine specific definitions - VA */ + +#define VA_ROM_INDEX 1 +#define VA_PLANES 8 + +/* Machine specific definitions - VC */ + +#define VC_BYSIZE 2048 /* buffer height */ +#define VC_BUFSIZE (1u << 16) /* number of longwords */ +#define VC_ORSC 3 /* screen origin multiplier */ + +/* Machine specific definitions - VE */ + +#define VE_ROM_INDEX 1 + +/* Machine specific definitions - XS */ + +#define XS_ROM_INDEX -1 /* no ROM needed */ +#define XS_FLAGS 0 +#define XS_READB Map_ReadB +#define XS_READW Map_ReadW +#define XS_WRITEB Map_WriteB +#define XS_WRITEW Map_WriteW + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +/* Function prototypes for disk buffer */ + +void ddb_WriteB (uint32 ba, uint32 bc, uint8 *buf); +void ddb_WriteW (uint32 ba, uint32 bc, uint16 *buf); +void ddb_ReadB (uint32 ba, uint32 bc, uint8 *buf); +void ddb_ReadW (uint32 ba, uint32 bc, uint16 *buf); + +/* Function prototypes for system-specific unaligned support */ + +int32 ReadIOU (uint32 pa, int32 lnt); +int32 ReadRegU (uint32 pa, int32 lnt); +void WriteIOU (uint32 pa, int32 val, int32 lnt); +void WriteRegU (uint32 pa, int32 val, int32 lnt); + +t_stat auto_config (const char *name, int32 nctrl); + +/* Function prototypes for virtual and physical memory interface (inlined) */ + +#include "vax_mmu.h" + +#endif diff --git a/VAX/vax420_sysdev.c b/VAX/vax420_sysdev.c new file mode 100644 index 00000000..d7651fc4 --- /dev/null +++ b/VAX/vax420_sysdev.c @@ -0,0 +1,1225 @@ +/* vax420_sysdev.c: MicroVAX 3100 system-specific logic + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the MicroVAX 3100 system-specific registers and devices. + + sysd system devices +*/ + +#include "vax_defs.h" +#include "sim_ether.h" +#include + +#ifdef DONT_USE_INTERNAL_ROM +#if defined (VAX_411) +#define BOOT_CODE_FILENAME "ka411.bin" +#elif defined (VAX_412) +#define BOOT_CODE_FILENAME "ka412.bin" +#elif defined (VAX_41A) +#define BOOT_CODE_FILENAME "ka41a.bin" +#elif defined (VAX_41D) +#define BOOT_CODE_FILENAME "ka41d.bin" +#elif defined (VAX_42A) +#define BOOT_CODE_FILENAME "ka42a.bin" +#elif defined (VAX_42B) +#define BOOT_CODE_FILENAME "ka42b.bin" +#endif +#else /* !DONT_USE_INTERNAL_ROM */ +#if defined (VAX_411) +#include "vax_ka411_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#elif defined (VAX_412) +#include "vax_ka412_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#elif defined (VAX_41A) +#include "vax_ka41a_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#elif defined (VAX_41D) +#include "vax_ka41d_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#elif defined (VAX_42A) +#include "vax_ka42a_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#elif defined (VAX_42B) +#include "vax_ka42b_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif +#endif /* DONT_USE_INTERNAL_ROM */ + + +t_stat vax420_boot (int32 flag, CONST char *ptr); + +/* Special boot command, overrides regular boot */ + +CTAB vax420_cmd[] = { + { "BOOT", &vax420_boot, RU_BOOT, + "bo{ot} boot simulator\n", NULL, &run_cmd_message }, + { NULL } + }; + +/* KA420 configuration & test register */ + +#define CFGT_MEM 0x0007 /* memory option */ +#define CFGT_VID 0x0008 /* video option present */ +#define CFGT_CUR 0x0010 /* cursor test */ +#define CFGT_L3C 0x0020 /* line 3 console */ +#define CFGT_NET 0x0040 /* network option present */ +#define CFGT_TYP 0x0080 /* system type */ +#define CFGT_V_DSK 8 +#define CFGT_M_DSK 0xF +#define CFGT_DSK (CFGT_M_DSK << CFGT_V_DSK) /* disk mask */ +#define CFGT_RX23 0x1000 /* 0 = RX23, 1 = RX33 */ +#define CFGT_V_STC 14 +#define CFGT_M_STC 0x3 +#define CFGT_STC (CFGT_M_STC << CFGT_V_STC) /* storage controller */ + +#define STC_SCSI 0 /* SCSI/SCSI controller */ +#define STC_ST506 1 /* ST506/SCSI controller */ + +/* KA420 Memory system error register */ + +#define MSER_PE 0x00000001 /* Parity Enable */ +#define MSER_WWP 0x00000002 /* Write Wrong Parity */ +#define MSER_PER 0x00000040 /* Parity Error */ +#define MSER_MCD0 0x00000100 /* Mem Code 0 */ +#define MSER_MBZ 0xFFFFFEBC +#define MSER_RD (MSER_PE | MSER_WWP | MSER_PER | \ + MSER_PER | MSER_MCD0) +#define MSER_WR (MSER_PE | MSER_WWP) +#define MSER_W1C (MSER_PER) + +/* KA420 memory error address reg */ + +#define MEAR_FAD 0x00007FFF /* failing addr */ +#define MEAR_RD (MEAR_FAD) + +#define ROM_VEC 0x8 /* ROM longword for first device vector */ + +#define TMR_INC 10000 /* usec/interval */ + +extern int32 tmr_int; +extern UNIT clk_unit; +extern int32 tmr_poll; +extern uint32 vc_sel, vc_org; +extern DEVICE rd_dev; +extern DEVICE va_dev, vc_dev, ve_dev, lk_dev, vs_dev; +extern DEVICE xs_dev; +extern uint32 *rom; + +uint32 *ddb = NULL; /* 128k disk buffer */ +int32 conisp, conpc, conpsl; /* console reg */ +int32 ka_hltcod = 0; /* KA420 halt code */ +int32 ka_mser = 0; /* KA420 mem sys err */ +int32 ka_mear = 0; /* KA420 memory err */ +int32 ka_cfgtst = 0; /* KA420 config/test */ +int32 ka_led = 0; /* KA420 selftest LEDs */ +int32 ka_pctl = 0; /* KA420 parity control */ +int32 CADR = 0; /* cache disable reg */ +int32 MSER = 0; /* mem sys error reg */ +int32 buf_sel = 0; /* buffer select */ +int32 sys_model = 0; /* MicroVAX or VAXstation */ +int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */ +int32 int_mask = 0; /* interrupt mask */ +uint32 tmr_tir = 0; /* curr interval */ +t_bool tmr_inst = FALSE; /* wait instructions vs usecs */ + +t_stat tmr_svc (UNIT *uptr); +t_stat sysd_reset (DEVICE *dptr); +const char *sysd_description (DEVICE *dptr); +int32 ka_rd (int32 pa); +void ka_wr (int32 pa, int32 val, int32 lnt); +int32 con_halt (int32 code, int32 cc); +int32 tmr_tir_rd (void); +void tmr_sched (); + +extern t_stat or_map (uint32 index, uint8 *rom, t_addr size); +extern t_stat or_unmap (uint32 index); +extern void rom_wr_B (int32 pa, int32 val); +extern int32 iccs_rd (void); +extern int32 rom_rd (int32 pa); +extern int32 nvr_rd (int32 pa); +extern int32 nar_rd (int32 pa); +extern int32 dz_rd (int32 pa); +extern int32 or_rd (int32 pa); +extern int32 rd_rd (int32 pa); +extern int32 rz_rd (int32 pa); +extern int32 xs_rd (int32 pa); +extern int32 vc_mem_rd (int32 pa); +extern int32 va_rd (int32 pa); +extern int32 ve_rd (int32 pa); +extern void iccs_wr (int32 dat); +extern void nvr_wr (int32 pa, int32 val, int32 lnt); +extern void dz_wr (int32 pa, int32 val, int32 lnt); +extern void rd_wr (int32 pa, int32 val, int32 lnt); +extern void rz_wr (int32 pa, int32 data, int32 lnt); +extern void xs_wr (int32 pa, int32 val, int32 lnt); +extern void vc_wr (int32 pa, int32 val, int32 lnt); +extern void vc_mem_wr (int32 pa, int32 val, int32 lnt); +extern void va_wr (int32 pa, int32 val, int32 lnt); +extern void ve_wr (int32 pa, int32 val, int32 lnt); + +/* SYSD data structures + + sysd_dev SYSD device descriptor + sysd_unit SYSD units + sysd_reg SYSD register list +*/ + +UNIT sysd_unit = { UDATA (&tmr_svc, 0, 0) }; + +REG sysd_reg[] = { + { HRDATAD (CADR, CADR, 8, "cache disable register") }, + { HRDATAD (MSER, MSER, 8, "memory system error register") }, + { HRDATAD (CONISP, conisp, 32, "console ISP") }, + { HRDATAD (CONPC, conpc, 32, "console PD") }, + { HRDATAD (CONPSL, conpsl, 32, "console PSL") }, + { HRDATAD (HLTCOD, ka_hltcod, 16, "KA420 halt code") }, + { HRDATAD (MSER, ka_mser, 8, "KA420 mem sys err") }, + { HRDATAD (MEAR, ka_mear, 8, "KA420 mem err") }, + { HRDATAD (CFGTST, ka_cfgtst, 8, "KA420 config/test register") }, + { NULL } + }; + +MTAB sysd_mod[] = { + { 0 }, + }; + +DEVICE sysd_dev = { + "SYSD", &sysd_unit, sysd_reg, sysd_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysd_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, + &sysd_description + }; + +/* Find highest priority outstanding interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_CRDERR) && crd_err) /* crd err int */ + return IPL_CRDERR; +if ((ipl < IPL_CLK) && tmr_int) /* clock int */ + return IPL_CLK; +if (ipl < IPL_HW) { /* chk hwre int */ + if (int_req[0] & int_mask) + return IPL_HW; + } +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i; +int32 int_unmask = int_req[0] & int_mask; + +if (lvl == IPL_CRDERR) { /* CRD error? */ + crd_err = 0; + return SCB_CRDERR; + } +if (lvl == IPL_CLK) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +for (i = 7; int_unmask && (i >= 0); i--) { + if ((int_unmask >> i) & 1) { + int_req[0] = int_req[0] & ~(1u << i); + return rom[ROM_VEC + i] & 0x3FF; /* get vector from ROM */ + } + } +return 0; +} + +/* DMA buffer routines, aligned access + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + *buf = ReadB (ma); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ma = ma + 4; + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + *buf = ReadW (ma); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + WriteB (ma, *buf); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + WriteW (ma, *buf); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +void ddb_WriteB (uint32 ba, uint32 bc, uint8 *buf) +{ +uint32 i, id, sc, mask, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + sc = (ba & 3) << 3; + mask = 0xFF << sc; + ddb[id] = (ddb[id] & ~mask) | (*buf << sc); + ba++; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + ddb[id] = dat; /* store lw */ + ba = ba + 4; + } + } +} + +void ddb_WriteW (uint32 ba, uint32 bc, uint16 *buf) +{ +uint32 i, id, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + ddb[id] = (ba & 2)? (ddb[id] & 0xFFFF) | (*buf << 16): + (ddb[id] & ~0xFFFF) | *buf; + ba = ba + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + ddb[id] = dat; /* store lw */ + ba = ba + 4; + } + } +} + +void ddb_ReadB (uint32 ba, uint32 bc, uint8 *buf) +{ +uint32 i, id, sc, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + sc = (ba & 3) << 3; + *buf = (ddb[id] >> sc) & BMASK; + ba++; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + dat = ddb[id]; /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ba = ba + 4; + } + } +} + +void ddb_ReadW (uint32 ba, uint32 bc, uint16 *buf) +{ +uint32 i, id, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + *buf = (ba & 2)? ((ddb[id] >> 16) & 0xFFFF) : + (ddb[id] & 0xFFFF); + ba = ba + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & ((buf_sel == 0) ? 0xFFF : 0x7FFF); + dat = ddb[id]; /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ba = ba + 4; + } + } +} + +int32 ddb_rd (int32 pa) +{ +int32 rg = ((pa - D128BASE) >> 2); +rg = rg & ((buf_sel == 0) ? 0xFFF : 0x7FFF); +return ddb[rg]; +} + +void ddb_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = ((pa - D128BASE) >> 2); +rg = rg & ((buf_sel == 0) ? 0xFFF : 0x7FFF); +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + ddb[rg] = ((val & mask) << sc) | (ddb[rg] & ~(mask << sc)); + } +else ddb[rg] = val; +return; +} + +int32 buf_sel_rd (int32 pa) +{ +return buf_sel; +} + +void buf_sel_wr (int32 pa, int32 val, int32 lnt) +{ +buf_sel = val; +return; +} + +int32 null_rd (int32 pa) +{ +return 0; +} + +void null_wr (int32 pa, int32 val, int32 lnt) +{ +return; +} + +int32 cfg_rd (int32 pa) +{ +return ka_cfgtst; +} + +void ioreset_wr (int32 pa, int32 val, int32 lnt) +{ +reset_all (7); +} + +/* Read KA420 specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_CONISP: /* console ISP */ + val = conisp; + break; + + case MT_CONPC: /* console PC */ + val = conpc; + break; + + case MT_CONPSL: /* console PSL */ + val = conpsl; + break; + + case MT_CADR: /* CADR */ + val = CADR & 0xFF; + break; + + case MT_CAER: /* CAER */ + val = 0; + break; + + case MT_SID: /* SID */ + val = VAX420_SID | VAX420_UREV; + break; + + default: + val = 0; + } + +return val; +} + +/* Write KA420 specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_CONISP: /* console ISP */ + conisp = val; + break; + + case MT_CONPC: /* console PC */ + conpc = val; + break; + + case MT_CONPSL: /* console PSL */ + conpsl = val; + break; + + case MT_CADR: /* CADR */ + CADR = (val & CADR_RW) | CADR_MBO; + break; + + case MT_CAER: /* CAER */ + break; + + default: + break; + } + +return; +} + +/* Read/write I/O register space + + These routines are the 'catch all' for address space map. Any + address that doesn't explicitly belong to memory, I/O, or ROM + is given to these routines for processing. +*/ + +struct reglink { /* register linkage */ + uint32 low; /* low addr */ + uint32 high; /* high addr */ + int32 (*read)(int32 pa); /* read routine */ + void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */ + int32 width; /* data path width */ + }; + +struct reglink regtable[] = { +#if defined (VAX_42A) || defined (VAX_42B) + { VEBASE, VEBASE+VESIZE, &ve_rd, &ve_wr, L_LONG }, + { VABASE, VABASE+VASIZE, &va_rd, &va_wr, L_WORD }, + { VCBASE, VCBASE+VCSIZE, &vc_mem_rd, &vc_mem_wr, L_LONG }, +#endif + { D16BASE, D16BASE+D16SIZE+D16SIZE, &ddb_rd, &ddb_wr, L_LONG }, +#if defined (VAX_42A) || defined (VAX_42B) + { RDBASE, RDBASE+RDSIZE, &rd_rd, &rd_wr, L_LONG }, +#endif + { RZBASE, RZBASE+RZSIZE, &rz_rd, &rz_wr, L_LONG }, + { RZBBASE, RZBBASE+RZSIZE, &rz_rd, &rz_wr, L_LONG }, + { XSBASE, XSBASE+XSSIZE, &xs_rd, &xs_wr, L_LONG }, + { DZBASE, DZBASE+DZSIZE, &dz_rd, dz_wr, L_LONG }, +#if defined (VAX_42A) || defined (VAX_42B) + { CURBASE, CURBASE+CURSIZE, NULL, &vc_wr, L_LONG }, +#endif + { D128BASE, D128BASE+D128SIZE, &ddb_rd, &ddb_wr, L_LONG }, + { 0x200C00E0, 0x200C00E4, &buf_sel_rd, &buf_sel_wr, L_LONG }, + { 0x20084000, 0x20084004, &null_rd, &null_wr, L_LONG }, + { ORBASE, ORBASE+ORSIZE, &or_rd, NULL, L_LONG }, + { NARBASE, NARBASE+NARSIZE, &nar_rd, NULL, L_LONG }, + { CFGBASE, CFGBASE+CFGSIZE, &cfg_rd, &ioreset_wr, L_LONG }, + { ROMBASE, ROMBASE+ROMSIZE, &rom_rd, NULL, L_LONG }, + { NVRBASE, NVRBASE+NVRSIZE, &nvr_rd, &nvr_wr, L_LONG }, + { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr, L_LONG }, + { 0, 0, NULL, NULL } + }; + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) - ignored + Output: + longword of data +*/ + +int32 ReadReg (uint32 pa, int32 lnt) +{ +struct reglink *p; +int32 val; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) { + val = p->read (pa); + if (p->width < L_LONG) { + if (lnt < L_LONG) + val = val << ((pa & 2)? 16: 0); + else val = (p->read (pa + 2) << 16) | val; + } + return val; + } + } +return 0xFFFFFFFF; +} + +/* ReadRegU - read register space, unaligned + + Inputs: + pa = physical address + lnt = length in bytes (1, 2, or 3) + Output: + returned data, not shifted +*/ + +int32 ReadRegU (uint32 pa, int32 lnt) +{ +struct reglink *p; +int32 val; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) { + if (p->width < L_LONG) { + val = p->read (pa); + if ((lnt + (pa & 1)) <= 2) + val = val << ((pa & 2)? 16: 0); + else val = (p->read (pa + 2) << 16) | val; + } + else { + if (lnt == L_BYTE) + val = p->read (pa & ~03); + else val = (p->read (pa & ~03) & WMASK) | (p->read ((pa & ~03) + 2) & (WMASK << 16)); + } + return val; + } + } +return 0xFFFFFFFF; +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + if (lnt > p->width) { + p->write (pa, val & WMASK, L_WORD); + p->write (pa + 2, (val >> 16) & WMASK, L_WORD); + } + else p->write (pa, val, lnt); + return; + } + } +return; +} + +/* WriteRegU - write register space, unaligned + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (1, 2, or 3) + Outputs: + none +*/ + +void WriteRegU (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + if (p->width < L_LONG) { + switch (lnt) { + case L_BYTE: /* byte */ + p->write (pa, val & BMASK, L_BYTE); + break; + + case L_WORD: /* word */ + if (pa & 1) { /* odd addr */ + p->write (pa, val & BMASK, L_BYTE); + p->write (pa + 1, (val >> 8) & BMASK, L_BYTE); + } + else p->write (pa, val & WMASK, L_WORD); + break; + + case 3: /* tribyte */ + if (pa & 1) { /* odd addr */ + p->write (pa, val & BMASK, L_BYTE); /* byte then word */ + p->write (pa + 1, (val >> 8) & WMASK, L_WORD); + } + else { /* even */ + p->write (pa, val & WMASK, L_WORD); /* word then byte */ + p->write (pa + 2, (val >> 16) & BMASK, L_BYTE); + } + break; + } + } + else if (p->read) { + int32 sc = (pa & 03) << 3; + int32 dat = p->read (pa & ~03); + + dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc); + p->write (pa & ~03, dat, L_LONG); + } + return; + } + } +return; +} + +/* KA420 registers */ + +int32 ka_rd (int32 pa) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* HLTCOD */ + return ka_hltcod; + + case 1: /* MSER */ + return ka_mser & MSER_RD; + + case 2: /* MEAR */ + return ka_mear & MEAR_RD; + + case 3: /* INT_REQ, VDC_SEL, VDC_ORG, INT_MSK */ + return ((int_req[0] & BMASK) << 24) | \ + ((vc_sel & 1) << 16) | \ + ((vc_org & BMASK) << 8) | \ + (int_mask & BMASK); + + case 4: /* LED */ + return ka_led; + + case 5: /* parity control */ + return ka_pctl; + + case 7: /* timer */ + return ((tmr_tir_rd ()) << 16); + } + +return 0; +} + +void ka_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* HLTCOD */ + ka_hltcod = val; + break; + + case 1: /* MSER */ + ka_mser = (ka_mser & ~MSER_WR) | (val & MSER_WR); + ka_mser = ka_mser & ~(val & MSER_W1C); + break; + + case 2: /* MEAR */ + break; /* read only? */ + + case 3: + switch (pa & 3) { + case 0: /* INT_MSK */ + int_mask = val & BMASK; + SET_IRQL; + break; + + case 1: /* VDC_ORG */ + vc_org = val & BMASK; + break; + + case 2: /* VDC_SEL */ + vc_sel = val & 1; + break; + + case 3: /* INT_CLR */ + int_req[0] = int_req[0] & ~(val & BMASK); + break; + } + break; + + case 4: /* LED */ + ka_led = val; + break; + + case 5: /* parity control */ + ka_pctl = val; + break; + + case 7: /* timer */ + tmr_tir = (val >> 16); + break; + } +return; +} + +int32 tmr_tir_rd (void) +{ +uint32 usecs_remaining, cur_tir; + +if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */ + (tmr_inst)) /* waiting instructions? */ + usecs_remaining = sim_activate_time (&sysd_unit) - 1; +else + usecs_remaining = (uint32)sim_activate_time_usecs (&sysd_unit); +cur_tir = (~usecs_remaining + 1) & 0xFFFF; +return cur_tir; +} + +/* Unit service */ + +t_stat tmr_svc (UNIT *uptr) +{ +tmr_sched (); /* reactivate */ +return SCPE_OK; +} + +/* Timer scheduling */ + +void tmr_sched () +{ +uint32 usecs_sched = tmr_tir ? (~tmr_tir + 1) : 0xFFFF; +tmr_tir = 0; + +if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */ + (usecs_sched < TMR_INC)) { /* short delay? */ + tmr_inst = TRUE; /* wait for instructions */ + sim_activate (&sysd_unit, usecs_sched); + } +else { + tmr_inst = FALSE; + sim_activate_after (&sysd_unit, usecs_sched); + } +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 i, st1, st2, p2, hsir, acc; + +if (in_ie) /* in exc? panic */ + ABORT (STOP_INIE); +if (p1 & 0x80) /* mref? set v/p */ + p1 = p1 + mchk_ref; +p2 = mchk_va + 4; /* save vap */ +for (i = hsir = 0; i < 16; i++) { /* find hsir */ + if ((SISR >> i) & 1) + hsir = i; + } +st1 = ((((uint32) opc) & 0xFF) << 24) | + (hsir << 16) | + ((CADR & 0xFF) << 8) | + (MSER & 0xFF); +st2 = 0x00C07000 + (delta & 0xFF); +cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 20; /* push 5 words */ +Write (SP, 16, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +Write (SP + 8, p2, L_LONG, WA); /* address */ +Write (SP + 12, st1, L_LONG, WA); /* state 1 */ +Write (SP + 16, st2, L_LONG, WA); /* state 2 */ +in_ie = 0; +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +int32 temp; + +conisp = IS; /* save ISP */ +conpc = PC; /* save PC */ +conpsl = ((PSL | cc) & 0xFFFF00FF) | code; /* PSL, param */ +temp = (PSL >> PSL_V_CUR) & 0x7; /* get is'cur */ +if (temp > 4) /* invalid? */ + conpsl = conpsl | CON_BADPSL; +else STK[temp] = SP; /* save stack */ +if (mapen) /* mapping on? */ + conpsl = conpsl | CON_MAPON; +mapen = 0; /* turn off map */ +SP = IS; /* set SP from IS */ +PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */ +JUMP (ROMBASE); /* PC = 20040000 */ +return 0; /* new cc = 0 */ +} + + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {CPU} + +*/ + +t_stat vax420_boot (int32 flag, CONST char *ptr) +{ +char gbuf[CBUFSIZE]; + +get_glyph (ptr, gbuf, 0); /* get glyph */ +if (gbuf[0] && strcmp (gbuf, "CPU")) + return SCPE_ARG; /* Only can specify CPU device */ +return run_cmd (flag, "CPU"); +} + + +/* Bootstrap */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; +DEVICE *cdptr; +int32 i; + +PC = ROMBASE; +PSL = PSL_IS | PSL_IPL1F; +conisp = 0; +conpc = 0; +conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP; +if (rom == NULL) + return SCPE_IERR; +if (*rom == 0) { /* no boot? */ + r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0); + if (r != SCPE_OK) + return r; + } +#if defined (VAX_41A) || defined (VAX_41D) +rom_wr_B (ROMBASE+4, sys_model ? 2 : 1); /* Set Magic Byte to determine system type */ +#endif +#if defined (VAX_41A) +rom_wr_B (ROMBASE+7, 8); /* ROM goes into endless loop without this? */ +#endif +for (i = 0; i < OR_COUNT; i++) /* unmap all option ROMs */ + or_unmap (i); +for (i = 0; (cdptr = sim_devices[i]) != NULL; i++) { /* loop over all devices */ + DIB *cdibp = (DIB *)(cdptr->ctxt); + + if (!cdibp || (cdptr->flags & DEV_DIS)) /* device enabled and has DIB? */ + continue; + + if (cdibp->rom_array != NULL) /* device has an option ROM? */ + or_map (cdibp->rom_index, cdibp->rom_array, cdibp->rom_size); + } +return SCPE_OK; +} + +/* SYSD reset */ + +t_stat sysd_reset (DEVICE *dptr) +{ +int unit; + +sim_cancel (&sysd_unit); +ka_mser = 0; +ka_mear = 0; +ka_led = 0; +ka_pctl = 0; +ka_cfgtst = (CFGT_TYP | CFGT_CUR); +ka_cfgtst |= ((MEMSIZE >> 22) - 1); /* memory option */ +if ((vc_dev.flags & DEV_DIS) == 0) /* mono video enabled? */ + ka_cfgtst &= ~CFGT_TYP; +if ((va_dev.flags & DEV_DIS) == 0) { /* video option present? */ + ka_cfgtst &= ~CFGT_TYP; + ka_cfgtst |= CFGT_VID; + } +if ((ve_dev.flags & DEV_DIS) == 0) { /* video option present? */ + ka_cfgtst &= ~CFGT_TYP; + ka_cfgtst |= CFGT_VID; + } +if ((xs_dev.flags & DEV_DIS) == 0) /* network option present? */ + ka_cfgtst |= CFGT_NET; +if ((rd_dev.flags & DEV_DIS) == 0) /* storage option */ + ka_cfgtst |= (STC_ST506 << CFGT_V_STC); +if (DZ_L3C && (sys_model == 0)) /* line 3 console */ + ka_cfgtst |= CFGT_L3C; +for (unit = 0; unit < 3; unit++) { /* disk mask */ + if ((rd_dev.units[unit].flags & UNIT_ATT) == 0) + ka_cfgtst |= (1u << (CFGT_V_DSK + unit)); + } +ka_cfgtst |= (1u << (CFGT_V_DSK + 3)); /* no unit 3 for now */ +tmr_tir = 0; +tmr_inst = FALSE; +tmr_sched (); /* activate */ + +if (ddb == NULL) + ddb = (uint32 *) calloc (D128SIZE >> 2, sizeof (uint32)); +if (ddb == NULL) + return SCPE_MEM; +buf_sel = 1; /* 128k buffer selected */ + +sim_vm_cmd = vax420_cmd; +return SCPE_OK; +} + +const char *sysd_description (DEVICE *dptr) +{ +return "system devices"; +} + +t_stat auto_config (const char *name, int32 nctrl) +{ +return SCPE_OK; +} + +t_stat build_dib_tab (void) +{ +return SCPE_OK; +} + +t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +char gbuf[CBUFSIZE]; + +if ((cptr == NULL) || (!*cptr)) + return SCPE_ARG; +cptr = get_glyph (cptr, gbuf, 0); +#if defined (VAX_41A) || defined (VAX_41D) +if (MATCH_CMD(gbuf, "MICROVAX") == 0) { + sys_model = 0; +#if defined (VAX_41A) + strcpy (sim_name, "MicroVAX 3100 M10/M20 (KA41-A)"); +#else /* VAX_41D */ + strcpy (sim_name, "MicroVAX 3100 M10e/M20e (KA41-D)"); +#endif + reset_all (0); /* reset everything */ + } +else if (MATCH_CMD(gbuf, "VAXSERVER") == 0) { + sys_model = 1; +#if defined (VAX_41A) + strcpy (sim_name, "VAXServer 3100 M10/M20 (KA41-A)"); +#else /* VAX_41D */ + strcpy (sim_name, "VAXServer 3100 M10e/M20e (KA41-D)"); +#endif + reset_all (0); /* reset everything */ + } +else + return SCPE_ARG; +#endif +#if defined (VAX_42A) || defined (VAX_42B) +if ((MATCH_CMD(gbuf, "VAXSERVER") == 0) || + (MATCH_CMD(gbuf, "MICROVAX") == 0)) { + sys_model = 0; +#if defined (USE_SIM_VIDEO) && defined (HAVE_LIBSDL) + va_dev.flags = vc_dev.flags | DEV_DIS; /* disable GPX */ + vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable MVO */ + ve_dev.flags = vc_dev.flags | DEV_DIS; /* disable SPX */ + lk_dev.flags = lk_dev.flags | DEV_DIS; /* disable keyboard */ + vs_dev.flags = vs_dev.flags | DEV_DIS; /* disable mouse */ +#endif +#if defined (VAX_42A) + strcpy (sim_name, "MicroVAX 3100 M30 (KA42-A)"); +#else /* VAX_42B */ + strcpy (sim_name, "MicroVAX 3100 M38 (KA42-B)"); +#endif + reset_all (0); /* reset everything */ + } +else if (MATCH_CMD(gbuf, "VAXSTATION") == 0) { +#if defined (USE_SIM_VIDEO) && defined (HAVE_LIBSDL) + sys_model = 1; + va_dev.flags = va_dev.flags | DEV_DIS; /* disable GPX */ + ve_dev.flags = ve_dev.flags | DEV_DIS; /* disable SPX */ + vc_dev.flags = vc_dev.flags & ~DEV_DIS; /* enable MVO */ + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ +#if defined (VAX_42A) + strcpy (sim_name, "VAXStation 3100 M30 (KA42-A)"); +#else /* VAX_42B */ + strcpy (sim_name, "VAXStation 3100 M38 (KA42-B)"); +#endif + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +else if (MATCH_CMD(gbuf, "VAXSTATIONGPX") == 0) { +#if defined (USE_SIM_VIDEO) && defined (HAVE_LIBSDL) + sys_model = 1; + vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable MVO */ + ve_dev.flags = ve_dev.flags | DEV_DIS; /* disable SPX */ + va_dev.flags = va_dev.flags & ~DEV_DIS; /* enable GPX */ + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ +#if defined (VAX_42A) + strcpy (sim_name, "VAXStation GPX 3100 M30 (KA42-A)"); +#else /* VAX_42B */ + strcpy (sim_name, "VAXStation GPX 3100 M38 (KA42-B)"); +#endif + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +else if (MATCH_CMD(gbuf, "VAXSTATIONSPX") == 0) { +#if defined (USE_SIM_VIDEO) && defined (HAVE_LIBSDL) + sys_model = 1; + vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable MVO */ + va_dev.flags = va_dev.flags | DEV_DIS; /* disable GPX */ + ve_dev.flags = ve_dev.flags & ~DEV_DIS; /* enable SPX */ + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ +#if defined (VAX_42A) + strcpy (sim_name, "VAXStation SPX 3100 M30 (KA42-A)"); +#else /* VAX_42B */ + strcpy (sim_name, "VAXStation SPX 3100 M38 (KA42-B)"); +#endif + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +else + return SCPE_ARG; +#endif +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "%s", sim_name); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Initial memory size is 16MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BOOT\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax420_syslist.c b/VAX/vax420_syslist.c new file mode 100644 index 00000000..0c7014fc --- /dev/null +++ b/VAX/vax420_syslist.c @@ -0,0 +1,157 @@ +/* vax420_syslist.c: MicroVAX 3100 device list + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). +*/ + +#include "vax_defs.h" + +#if defined (VAX_411) +char sim_name[64] = "Infoserver 100 (KA41-1)"; +#elif defined (VAX_412) +char sim_name[64] = "Infoserver 150 VXT (KA41-2)"; +#elif defined (VAX_41A) +char sim_name[64] = "MicroVAX 3100 M10/M20 (KA41-A)"; +#elif defined (VAX_41D) +char sim_name[64] = "MicroVAX 3100 M10e/M20e (KA41-D)"; +#elif defined (VAX_42A) +char sim_name[64] = "VAXstation 3100 M30 (KA42-A)"; +#elif defined (VAX_42B) +char sim_name[64] = "VAXstation 3100 M38 (KA42-B)"; +#endif + +void vax_init(void) +{ +#if defined (VAX_411) +sim_savename = "Infoserver 100 (KA41-1)"; +#elif defined (VAX_412) +sim_savename = "Infoserver 150 VXT (KA41-2)"; +#elif defined (VAX_41A) +sim_savename = "MicroVAX 3100 M10/M20 (KA41-A)"; +#elif defined (VAX_41D) +sim_savename = "MicroVAX 3100 M10e/M20e (KA41-D)"; +#elif defined (VAX_42A) +sim_savename = "VAXstation 3100 M30 (KA42-A)"; +#elif defined (VAX_42B) +sim_savename = "VAXstation 3100 M38 (KA42-B)"; +#endif +} + +WEAK void (*sim_vm_init) (void) = &vax_init; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE rom_dev; +extern DEVICE nvr_dev; +extern DEVICE nar_dev; +extern DEVICE wtc_dev; +extern DEVICE sysd_dev; +extern DEVICE clk_dev; +extern DEVICE or_dev; +extern DEVICE rz_dev; +extern DEVICE rzb_dev; +extern DEVICE dz_dev; +extern DEVICE xs_dev; +extern DEVICE rd_dev; +extern DEVICE va_dev; +extern DEVICE vc_dev; +extern DEVICE ve_dev; +extern DEVICE lk_dev; +extern DEVICE vs_dev; + +extern void WriteB (uint32 pa, int32 val); +extern void rom_wr_B (int32 pa, int32 val); +extern UNIT cpu_unit; + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &rom_dev, + &nvr_dev, + &nar_dev, + &wtc_dev, + &sysd_dev, + &clk_dev, + &or_dev, + &dz_dev, +#if defined (VAX_42A) || defined (VAX_42B) + &va_dev, + &vc_dev, + &ve_dev, + &lk_dev, + &vs_dev, + &rd_dev, +#endif + &rz_dev, + &rzb_dev, + &xs_dev, + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -r load ROM + -n load NVR + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag) +{ +t_stat r; +int32 i; +uint32 origin, limit; + +if (flag) /* dump? */ + return sim_messagef (SCPE_NOFNC, "Command Not Implemented\n"); +if (sim_switches & SWMASK ('R')) { /* ROM? */ + origin = ROMBASE; + limit = ROMBASE + ROMSIZE; + } +else if (sim_switches & SWMASK ('N')) { /* NVR? */ + origin = NVRBASE; + limit = NVRBASE + NVRSIZE; + } +else { + origin = 0; /* memory */ + limit = (uint32) cpu_unit.capac; + if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + } +while ((i = Fgetc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + if (sim_switches & SWMASK ('R')) /* ROM? */ + rom_wr_B (origin, i); /* not writeable */ + else WriteB (origin, i); /* store byte */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax43_defs.h b/VAX/vax43_defs.h new file mode 100644 index 00000000..578282df --- /dev/null +++ b/VAX/vax43_defs.h @@ -0,0 +1,387 @@ +/* vax43_defs.h: MicroVAX 3100 M76 model-specific definitions file + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This file covers the KA43 ("RigelMAX") systems. + + System memory map + + 0000 0000 - 01FF FFFF main memory + 1000 0000 - 1001 FFFF cache diagnostic space + 2002 0000 - 2002 0003 configuration/test register + 2004 0000 - 2007 FFFF ROM space + 2008 0000 - 2008 001F local register space + 2009 0000 - 2009 007F network address ROM + 200A 0000 - 200A 000F serial line controller + 200B 0000 - 200B 00FF watch chip registers + 200C 0080 - 200C 00FF scsi controller A + 200C 0180 - 200C 01FF scsi controller B + 200E 0000 - 200E 0007 ethernet controller + 200F 0000 - 200F 003F monochrome video cursor chip + 2010 0000 - 2013 FFFF option ROMs + 202D 0000 - 202E FFFF 128k disk data buffer + 2100 0000 - 2011 FFFF cache tag store + 2110 0000 - 2110 0003 software error summary register + 2800 0000 - 2009 FFFF ? diagnostic space + 3000 0000 - 3001 FFFF monochrome video RAM + 3800 0000 - 3BFF FFFF SPX video RAM +*/ + +#ifdef FULL_VAX /* subset VAX */ +#undef FULL_VAX +#endif + +#ifndef _VAX_43A_DEFS_H_ +#define _VAX_43A_DEFS_H_ 1 + +/* Microcode constructs */ + +#define VAX43A_SID (11 << 24) /* system ID */ +#define VAX43A_UREV 5 /* ucode revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_PWRUP 0x0300 /* powerup code */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define CON_DBLMCK 0x0500 /* Machine check in machine check */ +#define CON_BADPSL 0x4000 /* invalid PSL flag */ +#define CON_MAPON 0x8000 /* mapping on flag */ +#define MCHK_READ 0x80 /* read check */ +#define MCHK_WRITE 0x82 /* write check */ + +/* Machine specific IPRs */ + +#define MT_CADR 37 /* Cache disable reg */ +#define MT_MCESR 38 /* Machine check error/status reg */ +#define MT_CAER 39 /* Cache error reg */ +#define MT_ACCS 40 /* FPA control */ +#define MT_CONISP 41 /* Console Saved ISP */ +#define MT_CONPC 42 /* Console Saved PC */ +#define MT_CONPSL 43 /* Console Saved PSL */ +#define MT_PCTAG 124 /* Primary cache tag reg */ +#define MT_PCIDX 125 /* Primary cache index reg */ +#define MT_PCERR 126 /* Primary cache error reg */ +#define MT_PCSTS 127 /* Primary cache status reg */ +#define MT_MAX 127 /* last valid IPR */ + +/* Cache disable register */ + +#define CADR_RW 0xF3 +#define CADR_MBO 0x0C + +/* CPU */ + +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION|VAXSTATIONSPX}", \ + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } + +/* Memory */ + +#define MAXMEMWIDTH 25 /* max mem, std KA43A */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */ +#define MAXMEMWIDTH_X 25 /* max mem, KA43A */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << 24) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 23) + (1u << 22), NULL, "12M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24) + (1u << 22), NULL, "20M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24) + (1u << 23), NULL, "24M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24) + (1u << 23) + (1u << 22), NULL, "28M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size } + +/* Cache diagnostic space */ + +#define CDAAWIDTH 17 /* cache dat addr width */ +#define CDASIZE (1u << CDAAWIDTH) /* cache dat length */ +#define CDAMASK (CDASIZE - 1) /* cache dat mask */ +#define CTGAWIDTH 17 /* cache tag addr width */ +#define CTGSIZE (1u << CTGAWIDTH) /* cache tag length */ +#define CTGMASK (CTGSIZE - 1) /* cache tag mask */ +#define CTGBASE 0x21000000 /* diag addr base */ +#define CDGSIZE (CDASIZE) /* diag addr length */ +#define CDGBASE 0x10000000 /* diag addr base */ +#define CDG_GETROW(x) (((x) & CDAMASK) >> 2) +#define CDG_GETTAG(x) (((x) >> CDAAWIDTH) & CTGMASK) +#define CTG_V (1u << (CTGAWIDTH + 0)) /* tag valid */ +#define CTG_WP (1u << (CTGAWIDTH + 1)) /* wrong parity */ +#define ADDR_IS_CDG(x) ((((uint32) (x)) >= CDGBASE) && \ + (((uint32) (x)) < (CDGBASE + CDGSIZE))) + +/* Config/test register */ + +#define CFGSIZE 4 /* CFG length */ +#define CFGBASE 0x20020000 /* CFG base */ + +/* Read only memory */ + +#define ROMAWIDTH 18 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */ +#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */ +#define ROMBASE 0x20040000 /* ROM base */ +#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \ + (((uint32) (x)) < (ROMBASE + ROMSIZE))) + +/* KA43A board registers */ + +#define KAAWIDTH 5 /* REG addr width */ +#define KASIZE (1u << KAAWIDTH) /* REG length */ +#define KABASE 0x20080000 /* REG addr base */ + +/* Network address ROM */ + +#define NARAWIDTH 7 /* NAR addr width */ +#define NARSIZE (1u << NARAWIDTH) /* NAR length */ +#define NARAMASK (NARSIZE - 1) /* NAR addr mask */ +#define NARBASE 0x20090000 /* NAR base */ + +/* Serial line controller */ + +#define DZSIZE 0x10 /* DZ length */ +#define DZBASE 0x200A0000 /* DZ base */ + +/* Non-volatile RAM - 1KB Bytes long */ + +#define NVRAWIDTH 10 /* NVR addr width */ +#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */ +#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */ +#define NVRBASE 0x200B0000 /* NVR base */ +#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \ + (((uint32) (x)) < (NVRBASE + NVRSIZE))) + +/* SCSI disk controller */ + +#define RZSIZE 0x50 /* RZ length */ +#define RZBASE 0x200C0080 /* RZ base */ +#define RZBBASE 0x200C0180 /* RZB base */ + +/* LANCE Ethernet controller */ + +#define XSSIZE 0x8 /* XS length */ +#define XSBASE 0x200E0000 /* XS base */ + +/* Cursor chip */ + +#define CURSIZE 0x40 /* CUR length */ +#define CURBASE 0x200F0000 /* CUR base */ + +/* Option ROMs */ + +#define ORAWIDTH 20 /* OR addr width */ +#define ORSIZE (1u << ORAWIDTH) /* OR length */ +#define ORMASK (ORSIZE - 1) /* OR addr mask */ +#define ORBASE 0x20100000 /* OR base */ + +/* 128k disk buffer */ + +#define D128AWIDTH 17 /* D128 addr width */ +#define D128SIZE (1u << D128AWIDTH) /* D128 length */ +#define D128AMASK (D128SIZE - 1) /* D128 addr mask */ +#define D128BASE 0x202D0000 /* D128 base */ + +/* VC memory space */ + +#define VCAWIDTH 18 /* VC mem addr width */ +#define VCSIZE (1u << VCAWIDTH) /* VC mem length */ +#define VCAMASK (VCSIZE - 1) /* VC mem addr mask */ +#define VCBASE 0x30000000 /* VC mem base */ + +/* VE memory space */ + +#define VEAWIDTH 26 /* VE mem addr width */ +#define VESIZE (1u << VEAWIDTH) /* VE mem length */ +#define VEAMASK (VESIZE - 1) /* VE mem addr mask */ +#define VEBASE 0x38000000 /* VE mem base */ + +/* Other address spaces */ + +#define ADDR_IS_IO(x) (0) + +/* Machine specific reserved operand tests (mostly NOPs) */ + +#define ML_PA_TEST(r) +#define ML_LR_TEST(r) +#define ML_SBR_TEST(r) +#define ML_PXBR_TEST(r) +#define LP_AST_TEST(r) +#define LP_MBZ84_TEST(r) +#define LP_MBZ92_TEST(r) + +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* SCSI Bus */ + +#define RZ_SCSI_ID 6 /* initiator SCSI id */ + +/* I/O system definitions */ + +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_4XX (DEV_V_UF + 0) /* KA4xx I/O */ +#define DEV_4XX (1u << DEV_V_4XX) + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + int32 rom_index; /* option ROM index */ + uint8 *rom_array; /* option ROM code */ + t_addr rom_size; /* option ROM size */ + } DIB; + +/* Within each IPL, priority is left to right */ + +/* IPL 14 */ + +#define INT_V_SCA 0 /* storage controller 1 */ +#define INT_V_SCB 1 /* storage controller 2 */ +#define INT_V_VC2 2 /* video secondary */ +#define INT_V_VC1 3 /* video primary */ +#define INT_V_XS2 4 /* network secondary */ +#define INT_V_XS1 5 /* network primary */ +#define INT_V_DZTX 6 /* serial transmitter */ +#define INT_V_DZRX 7 /* serial receiver */ + +#define INT_SCA (1u << INT_V_SCA) +#define INT_SCB (1u << INT_V_SCB) +#define INT_VC2 (1u << INT_V_VC2) +#define INT_VC1 (1u << INT_V_VC1) +#define INT_XS2 (1u << INT_V_XS2) +#define INT_XS1 (1u << INT_V_XS1) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_DZRX (1u << INT_V_DZRX) + +#define IPL_CLK 0x16 +#define IPL_HW 0x14 /* hwre level */ +#define IPL_SCA (0x14 - IPL_HMIN) +#define IPL_SCB (0x14 - IPL_HMIN) +#define IPL_XS1 (0x14 - IPL_HMIN) +#define IPL_DZTX (0x14 - IPL_HMIN) +#define IPL_DZRX (0x14 - IPL_HMIN) +#define IPL_HMIN IPL_HW +#define IPL_HMAX IPL_HW +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Device vectors */ + +#define VEC_QBUS 0 /* Not a Qbus system */ +#define VEC_Q 0 + +/* Interrupt macros */ + +#define IREQ(dv) int_req[0] +#define SET_INT(dv) int_req[0] = int_req[0] | (INT_##dv) +#define CLR_INT(dv) int_req[0] = int_req[0] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* System model */ + +extern int32 sys_model; + +/* Machine specific definitions - DZ */ + +#define DZ_L3C 1 /* line 3 console */ + +/* Machine specific definitions - OR */ + +#define OR_COUNT 4 /* max number of option ROMs */ + +/* Machine specific definitions - RZ80 */ + +#define RZ_ROM_INDEX -1 /* no ROM needed */ +#define DMA_SIZE 0x20000 /* DMA count register */ +#define DCNT_MASK 0x1FFFF +#define RZ_FLAGS 0 /* permanently enabled */ +#define RZB_FLAGS 0 /* permanently enabled */ + +/* Machine specific definitions - VC */ + +#define VC_BYSIZE 2048 /* buffer height */ +#define VC_BUFSIZE (1u << 16) /* number of longwords */ +#define VC_ORSC 3 /* screen origin multiplier */ + +/* Machine specific definitions - VE */ + +#define VE_ROM_INDEX 1 + +/* Machine specific definitions - XS */ + +#define XS_ROM_INDEX -1 /* no ROM needed */ +#define XS_FLAGS 0 +#define XS_READB Map_ReadB +#define XS_READW Map_ReadW +#define XS_WRITEB Map_WriteB +#define XS_WRITEW Map_WriteW + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +/* Function prototypes for disk buffer */ + +void ddb_WriteB (uint32 ba, uint32 bc, uint8 *buf); +void ddb_WriteW (uint32 ba, uint32 bc, uint16 *buf); +void ddb_ReadB (uint32 ba, uint32 bc, uint8 *buf); +void ddb_ReadW (uint32 ba, uint32 bc, uint16 *buf); + +/* Function prototypes for system-specific unaligned support */ + +int32 ReadIOU (uint32 pa, int32 lnt); +int32 ReadRegU (uint32 pa, int32 lnt); +void WriteIOU (uint32 pa, int32 val, int32 lnt); +void WriteRegU (uint32 pa, int32 val, int32 lnt); + +t_stat auto_config (const char *name, int32 nctrl); + +/* Function prototypes for virtual and physical memory interface (inlined) */ + +#include "vax_mmu.h" + +#endif diff --git a/VAX/vax43_sysdev.c b/VAX/vax43_sysdev.c new file mode 100644 index 00000000..b43f43b0 --- /dev/null +++ b/VAX/vax43_sysdev.c @@ -0,0 +1,1115 @@ +/* vax43_sysdev.c: MicroVAX 3100 system-specific logic + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the MicroVAX 3100 system-specific registers and devices. + + sysd system devices +*/ + +#include "vax_defs.h" +#include "sim_ether.h" +#include + +#ifdef DONT_USE_INTERNAL_ROM +#define BOOT_CODE_FILENAME "ka43a.bin" +#else /* !DONT_USE_INTERNAL_ROM */ +#include "vax_ka43a_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif /* DONT_USE_INTERNAL_ROM */ + + +t_stat vax43a_boot (int32 flag, CONST char *ptr); + +/* Special boot command, overrides regular boot */ + +CTAB vax43a_cmd[] = { + { "BOOT", &vax43a_boot, RU_BOOT, + "bo{ot} boot simulator\n", NULL, &run_cmd_message }, + { NULL } + }; + +/* KA43A configuration & test register */ + +#define CFGT_MEM 0x0007 /* memory option */ +#define CFGT_VID 0x0008 /* video option present */ +#define CFGT_CUR 0x0010 /* cursor test */ +#define CFGT_L3C 0x0020 /* line 3 console */ +#define CFGT_NET 0x0040 /* network option present */ +#define CFGT_TYP 0x0080 /* system type */ +#define CFGT_V_DSK 8 +#define CFGT_M_DSK 0xF +#define CFGT_DSK (CFGT_M_DSK << CFGT_V_DSK) /* disk mask */ +#define CFGT_RX23 0x1000 /* 0 = RX23, 1 = RX33 */ +#define CFGT_V_STC 14 +#define CFGT_M_STC 0x3 +#define CFGT_STC (CFGT_M_STC << CFGT_V_STC) /* storage controller */ + +#define STC_SCSI 0 /* SCSI/SCSI controller */ +#define STC_ST506 1 /* ST506/SCSI controller */ + +/* KA43A Memory system error register */ + +#define MSER_PE 0x00000001 /* Parity Enable */ +#define MSER_WWP 0x00000002 /* Write Wrong Parity */ +#define MSER_PER 0x00000040 /* Parity Error */ +#define MSER_MCD0 0x00000100 /* Mem Code 0 */ +#define MSER_MBZ 0xFFFFFEBC +#define MSER_RD (MSER_PE | MSER_WWP | MSER_PER | \ + MSER_PER | MSER_MCD0) +#define MSER_WR (MSER_PE | MSER_WWP) +#define MSER_RS (MSER_PER) + +/* KA43A memory error address reg */ + +#define MEAR_FAD 0x00007FFF /* failing addr */ +#define MEAR_RD (MEAR_FAD) + +#define ROM_VEC 0x8 /* ROM longword for first device vector */ + +#define TMR_INC 10000 /* usec/interval */ + +extern int32 tmr_int; +extern UNIT clk_unit; +extern int32 tmr_poll; +extern uint32 vc_sel, vc_org; +extern DEVICE vc_dev, ve_dev, lk_dev, vs_dev; +extern DEVICE xs_dev; +extern uint32 *rom; + +uint32 *ddb = NULL; /* 128k disk buffer */ +int32 conisp, conpc, conpsl; /* console reg */ +int32 ka_hltcod = 0; /* KA43A halt code */ +int32 ka_mser = 0; /* KA43A mem sys err */ +int32 ka_mear = 0; /* KA43A memory err */ +int32 ka_cfgtst = 0; /* KA43A config/test */ +int32 CADR = 0; /* cache disable reg */ +int32 SESR = 0; /* software error summary reg */ +int32 sys_model = 0; /* MicroVAX or VAXstation */ +int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */ +int32 int_mask = 0; /* interrupt mask */ +uint32 tmr_tir = 0; /* curr interval */ +t_bool tmr_inst = FALSE; /* wait instructions vs usecs */ +uint32 diag[128] = { 0 }; +int32 cdg_dat[CDASIZE >> 2]; /* cache data */ +int32 ctg_dat[CTGSIZE >> 2]; /* cache tags */ + +t_stat tmr_svc (UNIT *uptr); +t_stat sysd_reset (DEVICE *dptr); +const char *sysd_description (DEVICE *dptr); +int32 ka_rd (int32 pa); +void ka_wr (int32 pa, int32 val, int32 lnt); +int32 con_halt (int32 code, int32 cc); +int32 tmr_tir_rd (void); +void tmr_sched (); + +extern t_stat or_map (uint32 index, uint8 *rom, t_addr size); +extern t_stat or_unmap (uint32 index); +extern void rom_wr_B (int32 pa, int32 val); +extern int32 iccs_rd (void); +extern int32 rom_rd (int32 pa); +extern int32 nvr_rd (int32 pa); +extern int32 nar_rd (int32 pa); +extern int32 dz_rd (int32 pa); +extern int32 or_rd (int32 pa); +extern int32 rd_rd (int32 pa); +extern int32 rz_rd (int32 pa); +extern int32 xs_rd (int32 pa); +extern int32 vc_mem_rd (int32 pa); +extern int32 ve_rd (int32 pa); +extern void iccs_wr (int32 dat); +extern void nvr_wr (int32 pa, int32 val, int32 lnt); +extern void dz_wr (int32 pa, int32 val, int32 lnt); +extern void rd_wr (int32 pa, int32 val, int32 lnt); +extern void rz_wr (int32 pa, int32 data, int32 lnt); +extern void xs_wr (int32 pa, int32 val, int32 lnt); +extern void vc_wr (int32 pa, int32 val, int32 lnt); +extern void vc_mem_wr (int32 pa, int32 val, int32 lnt); +extern void ve_wr (int32 pa, int32 val, int32 lnt); + +/* SYSD data structures + + sysd_dev SYSD device descriptor + sysd_unit SYSD units + sysd_reg SYSD register list +*/ + +UNIT sysd_unit = { UDATA (&tmr_svc, 0, 0) }; + +REG sysd_reg[] = { + { HRDATAD (CONISP, conisp, 32, "console ISP") }, + { HRDATAD (CONPC, conpc, 32, "console PD") }, + { HRDATAD (CONPSL, conpsl, 32, "console PSL") }, + { HRDATAD (HLTCOD, ka_hltcod, 16, "KA43A halt code") }, + { HRDATAD (MSER, ka_mser, 8, "KA43A mem sys err") }, + { HRDATAD (MEAR, ka_mear, 8, "KA43A mem err") }, + { NULL } + }; + +MTAB sysd_mod[] = { + { 0 }, + }; + +DEVICE sysd_dev = { + "SYSD", &sysd_unit, sysd_reg, sysd_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysd_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, + &sysd_description + }; + +/* Find highest priority outstanding interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_CLK) && tmr_int) /* clock int */ + return IPL_CLK; +if (ipl < IPL_HW) { /* chk hwre int */ + if (int_req[0] & int_mask) + return IPL_HW; + } +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i; +int32 int_unmask = int_req[0] & int_mask; + +if (lvl == IPL_CLK) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +for (i = 7; int_unmask && (i >= 0); i--) { + if ((int_unmask >> i) & 1) { + int_req[0] = int_req[0] & ~(1u << i); + return rom[ROM_VEC + i] & 0x3FF; /* get vector from ROM */ + } + } +return 0; +} + +/* DMA buffer routines, aligned access + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + *buf = ReadB (ma); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ma = ma + 4; + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + *buf = ReadW (ma); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + WriteB (ma, *buf); + ma = ma + 1; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma = ba; +uint32 dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + WriteW (ma, *buf); + ma = ma + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +void ddb_WriteB (uint32 ba, uint32 bc, uint8 *buf) +{ +uint32 i, id, sc, mask, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + id = (ba >> 2) & 0x7FFF; + sc = (ba & 3) << 3; + mask = 0xFF << sc; + ddb[id] = (ddb[id] & ~mask) | (*buf << sc); + ba++; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0x7FFF; + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + ddb[id] = dat; /* store lw */ + ba = ba + 4; + } + } +} + +void ddb_WriteW (uint32 ba, uint32 bc, uint16 *buf) +{ +uint32 i, id, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + id = (ba >> 2) & 0x7FFF; + ddb[id] = (ba & 2)? (ddb[id] & 0xFFFF) | (*buf << 16): + (ddb[id] & ~0xFFFF) | *buf; + ba = ba + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0x7FFF; + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + ddb[id] = dat; /* store lw */ + ba = ba + 4; + } + } +} + +void ddb_ReadB (uint32 ba, uint32 bc, uint8 *buf) +{ +uint32 i, id, sc, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i++, buf++) { /* by bytes */ + id = (ba >> 2) & 0x7FFF; + sc = (ba & 3) << 3; + *buf = (ddb[id] >> sc) & BMASK; + ba++; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0x7FFF; + dat = ddb[id]; /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ba = ba + 4; + } + } +} + +void ddb_ReadW (uint32 ba, uint32 bc, uint16 *buf) +{ +uint32 i, id, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = 0; i < bc; i = i + 2, buf++) { /* by words */ + id = (ba >> 2) & 0x7FFF; + *buf = (ba & 2)? ((ddb[id] >> 16) & 0xFFFF) : + (ddb[id] & 0xFFFF); + ba = ba + 2; + } + } +else { + for (i = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + id = (ba >> 2) & 0x7FFF; + dat = ddb[id]; /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ba = ba + 4; + } + } +} + +int32 ddb_rd (int32 pa) +{ +int32 rg = ((pa - D128BASE) >> 2); +rg = rg & 0x7FFF; +return ddb[rg]; +} + +void ddb_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = ((pa - D128BASE) >> 2); +rg = rg & 0x7FFF; +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + ddb[rg] = ((val & mask) << sc) | (ddb[rg] & ~(mask << sc)); + } +else ddb[rg] = val; +return; +} + +int32 sesr_rd (int32 pa) +{ +return 0; +} + +void sesr_wr (int32 pa, int32 val, int32 lnt) +{ +return; +} + +int32 cdg_rd (int32 pa) +{ +int32 row = CDG_GETROW (pa); + +return cdg_dat[row]; +} + +void cdg_wr (int32 pa, int32 val, int32 lnt) +{ +int32 row = CDG_GETROW (pa); + +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + int32 t = cdg_dat[row]; + val = ((val & mask) << sc) | (t & ~(mask << sc)); + } +cdg_dat[row] = val; /* store data */ +} + +int32 ctg_rd (int32 pa) +{ +return 0; +} + +void ctg_wr (int32 pa, int32 val, int32 lnt) +{ +return; +} + +int32 diag_rd (int32 pa) +{ +return ReadL (pa & 0xFFFFFF); +} + +void diag_wr (int32 pa, int32 val, int32 lnt) +{ +if (lnt >= L_LONG) /* long, quad? */ + WriteL (pa & 0xFFFFFF, val); +else if (lnt == L_WORD) /* word? */ + WriteW (pa & 0xFFFFFF, val); +else WriteB (pa & 0xFFFFFF, val); /* byte */ +return; +} + +int32 cfg_rd (int32 pa) +{ +return ka_cfgtst; +} + +void ioreset_wr (int32 pa, int32 val, int32 lnt) +{ +reset_all (7); +} + +/* Read KA43A specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_NICR: + val = 0; + break; + + case MT_ICR: /* for NetBSD */ + val = 0; + break; + + case MT_MCESR: /* MCESR (not impl) */ + val = 0; + break; + + case MT_ACCS: /* ACCS (not impl) */ + val = 0; + break; + + case MT_CONISP: /* console ISP */ + val = conisp; + break; + + case MT_CONPC: /* console PC */ + val = conpc; + break; + + case MT_CONPSL: /* console PSL */ + val = conpsl; + break; + + case MT_CADR: /* CADR */ + val = CADR & 0xFF; + break; + + case MT_CAER: /* CAER */ + val = 0; + break; + + case MT_TXCS: /* for Ultrix */ + val = 0; + break; + + case MT_PCTAG: /* PCTAG (not impl) */ + val = 0; + break; + + case MT_PCIDX: /* PCIDX (not impl) */ + val = 0; + break; + + case MT_PCERR: /* PCERR (not impl) */ + val = 0; + break; + + case MT_PCSTS: /* PCSTS (not impl) */ + val = 0; + break; + + case MT_SID: /* SID */ + val = VAX43A_SID | VAX43A_UREV; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write KA43A specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_NICR: /* for VAXELN */ + break; + + case MT_MCESR: /* MCESR (not impl) */ + break; + + case MT_ACCS: /* ACCS (not impl) */ + break; + + case MT_CONISP: /* console ISP */ + conisp = val; + break; + + case MT_CONPC: /* console PC */ + conpc = val; + break; + + case MT_CONPSL: /* console PSL */ + conpsl = val; + break; + + case MT_CADR: /* CADR */ + CADR = (val & CADR_RW) | CADR_MBO; + break; + + case MT_CAER: /* CAER */ + break; + + case MT_TXCS: /* for Ultrix */ + break; + + case MT_TXDB: /* for Ultrix */ + break; + + case MT_PCTAG: /* PCTAG (not impl) */ + break; + + case MT_PCIDX: /* PCIDX (not impl) */ + break; + + case MT_PCERR: /* PCERR (not impl) */ + break; + + case MT_PCSTS: /* PCSTS (not impl) */ + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +/* Read/write I/O register space + + These routines are the 'catch all' for address space map. Any + address that doesn't explicitly belong to memory, I/O, or ROM + is given to these routines for processing. +*/ + +struct reglink { /* register linkage */ + uint32 low; /* low addr */ + uint32 high; /* high addr */ + int32 (*read)(int32 pa); /* read routine */ + void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */ + }; + +struct reglink regtable[] = { + { VEBASE, VEBASE+VESIZE, &ve_rd, &ve_wr }, + { VCBASE, VCBASE+VCSIZE, &vc_mem_rd, &vc_mem_wr }, + { RZBASE, RZBASE+RZSIZE, &rz_rd, &rz_wr }, + { RZBASE, RZBBASE+RZSIZE, &rz_rd, &rz_wr }, + { XSBASE, XSBASE+XSSIZE, &xs_rd, &xs_wr }, + { DZBASE, DZBASE+DZSIZE, &dz_rd, dz_wr }, + { CURBASE, CURBASE+CURSIZE, NULL, &vc_wr }, + { D128BASE, D128BASE+D128SIZE, &ddb_rd, &ddb_wr }, + { ORBASE, ORBASE+ORSIZE, &or_rd, NULL }, + { NARBASE, NARBASE+NARSIZE, &nar_rd, NULL }, + { CFGBASE, CFGBASE+CFGSIZE, &cfg_rd, &ioreset_wr }, + { ROMBASE, ROMBASE+ROMSIZE, &rom_rd, NULL }, + { NVRBASE, NVRBASE+NVRSIZE, &nvr_rd, &nvr_wr }, + { 0x21100000, 0x21100004, &sesr_rd, &sesr_wr }, + { CDGBASE, CDGBASE+CDGSIZE, &cdg_rd, &cdg_wr }, + { CTGBASE, CTGBASE+CTGSIZE, &ctg_rd, &ctg_wr }, + { 0x28000000, 0x2A000000, &diag_rd, &diag_wr }, + { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr }, + { 0, 0, NULL, NULL } + }; + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) - ignored + Output: + longword of data +*/ + +int32 ReadReg (uint32 pa, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) + return p->read (pa); + } +return 0xFFFFFFFF; +} + +/* ReadRegU - read register space, unaligned + + Inputs: + pa = physical address + lnt = length in bytes (1, 2, or 3) + Output: + returned data, not shifted +*/ + +int32 ReadRegU (uint32 pa, int32 lnt) +{ +return ReadReg (pa & ~03, L_LONG); +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + p->write (pa, val, lnt); + return; + } + } +return; +} + +/* WriteRegU - write register space, unaligned + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (1, 2, or 3) + Outputs: + none +*/ + +void WriteRegU (uint32 pa, int32 val, int32 lnt) +{ +int32 sc = (pa & 03) << 3; +int32 dat = ReadReg (pa & ~03, L_LONG); + +dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc); +WriteReg (pa & ~03, dat, L_LONG); +return; +} + +/* KA43A registers */ + +int32 ka_rd (int32 pa) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* HLTCOD */ + return ka_hltcod; + + case 1: /* MSER */ + return ka_mser & MSER_RD; + + case 2: /* MEAR */ + return ka_mear & MEAR_RD; + + case 3: /* INT_REQ, VDC_SEL, VDC_ORG, INT_MSK */ + return ((int_req[0] & BMASK) << 24) | \ + ((vc_sel & 1) << 16) | \ + ((vc_org & BMASK) << 8) | \ + (int_mask & BMASK); + + case 7: /* timer */ + return ((tmr_tir_rd ()) << 16); + } + +return 0; +} + +void ka_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* HLTCOD */ + ka_hltcod = val; + break; + + case 1: /* MSER */ + ka_mser = (ka_mser & ~MSER_WR) | (val & MSER_WR); + ka_mser = ka_mser & ~(val & MSER_RS); + break; + + case 2: /* MEAR */ + /* read only? */ + break; + + case 3: + switch (pa & 3) { + case 0: /* INT_MSK */ + int_mask = val & BMASK; + SET_IRQL; + break; + + case 1: /* VDC_ORG */ + vc_org = val & BMASK; + break; + + case 2: /* VDC_SEL */ + vc_sel = val & 1; + break; + + case 3: /* INT_CLR */ + int_req[0] = int_req[0] & ~(val & BMASK); + break; + } + break; + + case 4: /* LED */ + break; + + case 7: /* timer */ + tmr_tir = (val >> 16); + break; + } +return; +} + +int32 tmr_tir_rd (void) +{ +uint32 usecs_remaining, cur_tir; + +if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */ + (tmr_inst)) /* waiting instructions? */ + usecs_remaining = sim_activate_time (&sysd_unit) - 1; +else + usecs_remaining = (uint32)sim_activate_time_usecs (&sysd_unit); +cur_tir = (~usecs_remaining + 1) & 0xFFFF; +return cur_tir; +} + +/* Unit service */ + +t_stat tmr_svc (UNIT *uptr) +{ +tmr_sched (); /* reactivate */ +return SCPE_OK; +} + +/* Timer scheduling */ + +void tmr_sched () +{ +uint32 usecs_sched = tmr_tir ? (~tmr_tir + 1) : 0xFFFF; +tmr_tir = 0; + +if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */ + (usecs_sched < TMR_INC)) { /* short delay? */ + tmr_inst = TRUE; /* wait for instructions */ + sim_activate (&sysd_unit, usecs_sched); + } +else { + tmr_inst = FALSE; + sim_activate_after (&sysd_unit, usecs_sched); + } +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 p2, acc; + +if (in_ie) { + in_ie = 0; + return con_halt (CON_DBLMCK, cc); /* double machine check */ + } +if (p1 & 0x80) /* mref? set v/p */ + p1 = p1 + mchk_ref; +p2 = mchk_va + 4; /* save vap */ +cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 28; /* push 7 words */ +Write (SP, 24, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +Write (SP + 8, p2, L_LONG, WA); /* address */ +Write (SP + 12, 0, L_LONG, WA); /* VIBA */ +Write (SP + 16, 0, L_LONG, WA); /* ICCS..SISR */ +Write (SP + 20, 0, L_LONG, WA); /* state */ +Write (SP + 24, 0, L_LONG, WA); /* SC */ +in_ie = 0; +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +int32 temp; + +conisp = IS; /* save ISP */ +conpc = PC; /* save PC */ +conpsl = ((PSL | cc) & 0xFFFF00FF) | code; /* PSL, param */ +temp = (PSL >> PSL_V_CUR) & 0x7; /* get is'cur */ +if (temp > 4) /* invalid? */ + conpsl = conpsl | CON_BADPSL; +else STK[temp] = SP; /* save stack */ +if (mapen) /* mapping on? */ + conpsl = conpsl | CON_MAPON; +mapen = 0; /* turn off map */ +SP = IS; /* set SP from IS */ +PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */ +JUMP (ROMBASE); /* PC = 20040000 */ +return 0; /* new cc = 0 */ +} + + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {CPU} + +*/ + +t_stat vax43a_boot (int32 flag, CONST char *ptr) +{ +char gbuf[CBUFSIZE]; + +get_glyph (ptr, gbuf, 0); /* get glyph */ +if (gbuf[0] && strcmp (gbuf, "CPU")) + return SCPE_ARG; /* Only can specify CPU device */ +return run_cmd (flag, "CPU"); +} + + +/* Bootstrap */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; +DEVICE *cdptr; +int32 i; + +PC = ROMBASE; +PSL = PSL_IS | PSL_IPL1F; +conisp = 0; +conpc = 0; +conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP; +if (rom == NULL) + return SCPE_IERR; +if (*rom == 0) { /* no boot? */ + r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0); + if (r != SCPE_OK) + return r; + } +for (i = 0; i < OR_COUNT; i++) /* unmap all option ROMs */ + or_unmap (i); +for (i = 0; (cdptr = sim_devices[i]) != NULL; i++) { /* loop over all devices */ + DIB *cdibp = (DIB *)(cdptr->ctxt); + + if (!cdibp || (cdptr->flags & DEV_DIS)) /* device enabled and has DIB? */ + continue; + + if (cdibp->rom_array != NULL) /* device has an option ROM? */ + or_map (cdibp->rom_index, cdibp->rom_array, cdibp->rom_size); + } +return SCPE_OK; +} + +/* SYSD reset */ + +t_stat sysd_reset (DEVICE *dptr) +{ +sim_cancel (&sysd_unit); +ka_mser = 0; +ka_mear = 0; +ka_cfgtst = (CFGT_TYP | CFGT_CUR); +ka_cfgtst |= ((MEMSIZE >> 22) - 1); /* memory option */ +if ((ve_dev.flags & DEV_DIS) == 0) /* video option present? */ + ka_cfgtst |= CFGT_VID; +if ((xs_dev.flags & DEV_DIS) == 0) /* network option present? */ + ka_cfgtst |= CFGT_NET; +if (DZ_L3C && (sys_model == 0)) /* line 3 console */ + ka_cfgtst |= CFGT_L3C; +tmr_tir = 0; +tmr_inst = FALSE; +tmr_sched (); /* activate */ + +if (ddb == NULL) + ddb = (uint32 *) calloc (D128SIZE >> 2, sizeof (uint32)); +if (ddb == NULL) + return SCPE_MEM; + +tmr_sched (); +sim_vm_cmd = vax43a_cmd; + +return SCPE_OK; +} + +const char *sysd_description (DEVICE *dptr) +{ +return "system devices"; +} + +t_stat auto_config (const char *name, int32 nctrl) +{ +return SCPE_OK; +} + +t_stat build_dib_tab (void) +{ +return SCPE_OK; +} + +t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +char gbuf[CBUFSIZE]; + +if ((cptr == NULL) || (!*cptr)) + return SCPE_ARG; +cptr = get_glyph (cptr, gbuf, 0); +if (MATCH_CMD(gbuf, "MICROVAX") == 0) { + sys_model = 0; +#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL) + vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable MVO */ + ve_dev.flags = vc_dev.flags | DEV_DIS; /* disable SPX */ + lk_dev.flags = lk_dev.flags | DEV_DIS; /* disable keyboard */ + vs_dev.flags = vs_dev.flags | DEV_DIS; /* disable mouse */ +#endif + strcpy (sim_name, "MicroVAX 3100 M76 (KA43-A)"); + reset_all (0); /* reset everything */ + } +else if (MATCH_CMD(gbuf, "VAXSTATION") == 0) { +#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL) + sys_model = 1; + ve_dev.flags = ve_dev.flags | DEV_DIS; /* disable SPX */ + vc_dev.flags = vc_dev.flags & ~DEV_DIS; /* enable MVO */ + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ + strcpy (sim_name, "VAXstation 3100 M76 (KA43-A)"); + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +else if (MATCH_CMD(gbuf, "VAXSTATIONSPX") == 0) { +#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL) + sys_model = 1; + vc_dev.flags = vc_dev.flags | DEV_DIS; /* disable MVO */ + ve_dev.flags = ve_dev.flags & ~DEV_DIS; /* enable SPX */ + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ + strcpy (sim_name, "VAXstation 3100 M76/SPX (KA43-A)"); + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +else + return SCPE_ARG; +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "%s", sim_name); +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Initial memory size is 16MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BOOT\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax43_syslist.c b/VAX/vax43_syslist.c new file mode 100644 index 00000000..a6b4f7d8 --- /dev/null +++ b/VAX/vax43_syslist.c @@ -0,0 +1,127 @@ +/* vax43_syslist.c: MicroVAX 3100 M76 device list + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). +*/ + +#include "vax_defs.h" + +char sim_name[64] = "MicroVAX 3100 M76 (KA43-A)"; + +void vax_init(void) +{ +sim_savename = "MicroVAX 3100 M76 (KA43-A)"; +} + +WEAK void (*sim_vm_init) (void) = &vax_init; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE rom_dev; +extern DEVICE nvr_dev; +extern DEVICE nar_dev; +extern DEVICE wtc_dev; +extern DEVICE sysd_dev; +extern DEVICE clk_dev; +extern DEVICE or_dev; +extern DEVICE rz_dev; +extern DEVICE rzb_dev; +extern DEVICE dz_dev; +extern DEVICE xs_dev; +extern DEVICE vc_dev; +extern DEVICE ve_dev; +extern DEVICE lk_dev; +extern DEVICE vs_dev; + +extern void WriteB (uint32 pa, int32 val); +extern void rom_wr_B (int32 pa, int32 val); +extern UNIT cpu_unit; + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &rom_dev, + &nvr_dev, + &nar_dev, + &wtc_dev, + &sysd_dev, + &clk_dev, + &or_dev, + &dz_dev, + &vc_dev, + &ve_dev, + &lk_dev, + &vs_dev, + &rz_dev, + &rzb_dev, + &xs_dev, + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -r load ROM + -n load NVR + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag) +{ +t_stat r; +int32 i; +uint32 origin, limit; + +if (flag) /* dump? */ + return sim_messagef (SCPE_NOFNC, "Command Not Implemented\n"); +if (sim_switches & SWMASK ('R')) { /* ROM? */ + origin = ROMBASE; + limit = ROMBASE + ROMSIZE; + } +else if (sim_switches & SWMASK ('N')) { /* NVR? */ + origin = NVRBASE; + limit = NVRBASE + NVRSIZE; + } +else { + origin = 0; /* memory */ + limit = (uint32) cpu_unit.capac; + if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + } +while ((i = Fgetc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + if (sim_switches & SWMASK ('R')) /* ROM? */ + rom_wr_B (origin, i); /* not writeable */ + else WriteB (origin, i); /* store byte */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax440_defs.h b/VAX/vax440_defs.h new file mode 100644 index 00000000..9e5ac985 --- /dev/null +++ b/VAX/vax440_defs.h @@ -0,0 +1,339 @@ +/* vax440_defs.h: MicroVAX 4000 model-specific definitions file + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This file covers the KA440 ("PVAX2") systems. + + System memory map + + 0000 0000 - 00FF FFFF main memory + 0800 0000 - 0803 FFFF secondary cache data store + 2000 0000 - 2001 FFFF DMA map + 2002 0000 - 2002 0003 configuration/test register + 2004 0000 - 2007 FFFF ROM space + 2008 0000 - 2008 001F local register space + 2009 0000 - 2009 007F network address ROM + 200A 0000 - 200A 000F serial line controller + 200B 0000 - 200B 00FF watch chip registers + 200C 0000 - 200C 00BF scsi controller + 200D 0000 - 200D 3FFF ISDN/audio controller + 200E 0000 - 200E 0007 ethernet contoller + 2010 0000 - 2013 FFFF option ROMs + 2010 1800 - 2010 180F memory registers + 2010 1A00 - 2010 1FFF invalidate single + 2020 0000 - 2021 FFFF invalidate filter + 2200 0000 - 2203 FFFF secondary cache tag store + 2300 0000 - 2300 0003 secondary cache control registers + 3680 0000 - 3680 0003 turbochannel registers +*/ + +#ifdef FULL_VAX /* subset VAX */ +#undef FULL_VAX +#endif + +#ifndef _VAX_440_DEFS_H_ +#define _VAX_440_DEFS_H_ 1 + +/* Microcode constructs */ + +#if defined (VAX_46) || defined (VAX_47) +#define VAX4X_SID (18 << 24) /* system ID */ +#else +#define VAX4X_SID (20 << 24) /* system ID */ +#endif +#define VAX4X_UREV 14 /* ucode revision */ +#define CON_HLTPIN 0x0200 /* external CPU halt */ +#define CON_PWRUP 0x0300 /* powerup code */ +#define CON_HLTINS 0x0600 /* HALT instruction */ +#define CON_DBLMCK 0x0500 /* Machine check in machine check */ +#define CON_BADPSL 0x4000 /* invalid PSL flag */ +#define CON_MAPON 0x8000 /* mapping on flag */ +#define MCHK_READ 0x80 /* read check */ +#define MCHK_WRITE 0x82 /* write check */ + +/* Machine specific IPRs */ + +#define MT_CADR 37 /* Cache disable reg */ +#define MT_MCESR 38 /* Machine check error/status reg */ +#define MT_CAER 39 /* Cache error reg */ +#define MT_ACCS 40 /* FPA control */ +#define MT_CONISP 41 /* Console Saved ISP */ +#define MT_CONPC 42 /* Console Saved PC */ +#define MT_CONPSL 43 /* Console Saved PSL */ +#define MT_PCTAG 124 /* Primary cache tag reg */ +#define MT_PCIDX 125 /* Primary cache index reg */ +#define MT_PCERR 126 /* Primary cache error reg */ +#define MT_PCSTS 127 /* Primary cache status reg */ +#define MT_MAX 127 /* last valid IPR */ + +/* Cache disable register */ + +#define CADR_RW 0xF3 +#define CADR_MBO 0x0C + +/* CPU */ + +#if defined (VAX_46) || defined (VAX_48) +#define CPU_MODEL_MODIFIERS \ + { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={MICROVAX|VAXSTATION}", \ + cpu_set_model, &cpu_show_model, NULL, "Set/Show the simulator CPU Model" } +#else +#define CPU_MODEL_MODIFIERS \ + { 0 } +#endif + +/* Memory */ + +#define MAXMEMWIDTH 25 /* max mem, std KA440 */ +#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */ +#define MAXMEMWIDTH_X 27 /* max mem, KA440 */ +#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) +#define INITMEMSIZE (1 << 24) /* initial memory size */ +#define MEMSIZE (cpu_unit.capac) +#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) +#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 24) + (1u << 23), NULL, "24M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25) + (1u << 23), NULL, "40M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 25) + (1u << 24) + (1u << 23), NULL, "56M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 26) + (1u << 23), NULL, "72M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 26) + (1u << 24), NULL, "80M", &cpu_set_size }, \ + { UNIT_MSIZE, (1u << 26) + (1u << 25) + (1u << 24), NULL, "104M", &cpu_set_size } + +/* DMA map */ + +#define DMAAWIDTH 17 /* DMA addr width */ +#define DMASIZE (1u << DMAAWIDTH) /* DMA length */ +#define DMAAMASK (DMASIZE - 1) /* DMA addr mask */ +#define DMABASE 0x20000000 /* DMA base */ + +/* Config/test register */ + +#define CFGSIZE 4 /* CFG length */ +#define CFGBASE 0x20020000 /* CFG base */ + +/* Read only memory */ + +#define ROMAWIDTH 18 /* ROM addr width */ +#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */ +#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */ +#define ROMBASE 0x20040000 /* ROM base */ +#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \ + (((uint32) (x)) < (ROMBASE + ROMSIZE))) + +/* KA440 board registers */ + +#define KAAWIDTH 5 /* REG addr width */ +#define KASIZE (1u << KAAWIDTH) /* REG length */ +#define KABASE 0x20080000 /* REG addr base */ + +/* Network address ROM */ + +#define NARAWIDTH 5 /* NAR addr width */ +#define NARSIZE (1u << NARAWIDTH) /* NAR length */ +#define NARAMASK (NARSIZE - 1) /* NAR addr mask */ +#define NARBASE 0x20090000 /* NAR base */ + +/* Serial line controller */ + +#define DZSIZE 0x10 /* DZ length */ +#define DZBASE 0x200A0000 /* DZ base */ + +/* Non-volatile RAM - 1KB Bytes long */ + +#define NVRAWIDTH 10 /* NVR addr width */ +#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */ +#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */ +#define NVRBASE 0x200B0000 /* NVR base */ +#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \ + (((uint32) (x)) < (NVRBASE + NVRSIZE))) + +/* SCSI disk controller */ + +#define RZSIZE 0xC0 /* RZ length */ +#define RZBASE 0x200C0000 /* RZ base */ + +/* LANCE Ethernet controller */ + +#define XSSIZE 0x8 /* XS length */ +#define XSBASE 0x200E0000 /* XS base */ + +/* Option ROMs */ + +#define ORAWIDTH 20 /* OR addr width */ +#define ORSIZE (1u << ORAWIDTH) /* OR length */ +#define ORMASK (ORSIZE - 1) /* OR addr mask */ +#define ORBASE 0x20100000 /* OR base */ + +/* Other address spaces */ + +#define ADDR_IS_IO(x) (0) +#define ADDR_IS_CDG(x) (0) + +/* Machine specific reserved operand tests (mostly NOPs) */ + +#define ML_PA_TEST(r) +#define ML_LR_TEST(r) +#define ML_SBR_TEST(r) +#define ML_PXBR_TEST(r) +#define LP_AST_TEST(r) +#define LP_MBZ84_TEST(r) +#define LP_MBZ92_TEST(r) + +#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT + +/* Common CSI flags */ + +#define CSR_V_GO 0 /* go */ +#define CSR_V_IE 6 /* interrupt enable */ +#define CSR_V_DONE 7 /* done */ +#define CSR_V_BUSY 11 /* busy */ +#define CSR_V_ERR 15 /* error */ +#define CSR_GO (1u << CSR_V_GO) +#define CSR_IE (1u << CSR_V_IE) +#define CSR_DONE (1u << CSR_V_DONE) +#define CSR_BUSY (1u << CSR_V_BUSY) +#define CSR_ERR (1u << CSR_V_ERR) + +/* Timers */ + +#define TMR_CLK 0 /* 100Hz clock */ + +/* I/O system definitions */ + +#define MT_MAXFR (1 << 16) /* magtape max rec */ + +#define DEV_V_4XX (DEV_V_UF + 0) /* KA4xx I/O */ +#define DEV_4XX (1u << DEV_V_4XX) + +#define DEV_RDX 16 /* default device radix */ + +/* Device information block */ + +#define VEC_DEVMAX 4 /* max device vec */ + +typedef struct { + int32 rom_index; /* option ROM index */ + uint8 *rom_array; /* option ROM code */ + t_addr rom_size; /* option ROM size */ + } DIB; + +/* Within each IPL, priority is left to right */ + +/* IPL 14 */ + +#define INT_V_SC 0 /* storage controller */ +#define INT_V_XS1 1 /* network */ +#define INT_V_VC1 2 /* video primary */ +#define INT_V_VC2 3 /* video secondary */ +#define INT_V_DZTX 4 /* serial transmitter */ +#define INT_V_DZRX 5 /* serial receiver */ +#define INT_V_SP 6 /* audio/ISDN */ +#define INT_V_CO 7 /* sync comm (PV21X-DA) */ + +#define INT_SC (1u << INT_V_SC) +#define INT_XS1 (1u << INT_V_XS1) +#define INT_VC1 (1u << INT_V_VC1) +#define INT_VC2 (1u << INT_V_VC2) +#define INT_DZTX (1u << INT_V_DZTX) +#define INT_DZRX (1u << INT_V_DZRX) +#define INT_SP (1u << INT_V_SP) +#define INT_CO (1u << INT_V_CO) + +#define IPL_CLK 0x16 +#define IPL_HW 0x14 /* hwre level */ +#define IPL_SC (0x14 - IPL_HMIN) +#define IPL_XS1 (0x14 - IPL_HMIN) +#define IPL_DZTX (0x14 - IPL_HMIN) +#define IPL_DZRX (0x14 - IPL_HMIN) +#define IPL_HMIN IPL_HW +#define IPL_HMAX IPL_HW +#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ +#define IPL_SMAX 0xF /* highest swre level */ + +/* Device vectors */ + +#define VEC_QBUS 0 /* Not a Qbus system */ +#define VEC_Q 0 + +/* Interrupt macros */ + +#define IREQ(dv) int_req[0] +#define SET_INT(dv) int_req[0] = int_req[0] | (INT_##dv) +#define CLR_INT(dv) int_req[0] = int_req[0] & ~(INT_##dv) +#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ + +/* System model */ + +extern int32 sys_model; + +/* Machine specific definitions - DZ */ + +#define DZ_L3C 1 /* line 3 console */ + +/* Machine specific definitions - OR */ + +#define OR_COUNT 4 /* max number of option ROMs */ + +/* Machine specific definitions - RZ94 */ + +#define RZ_SCSI_ID 6 /* initiator SCSI id */ +#define RZ_READB Map_ReadB +#define RZ_READW Map_ReadW +#define RZ_WRITEB Map_WriteB +#define RZ_WRITEW Map_WriteW + +/* Machine specific definitions - XS */ + +#define XS_ROM_INDEX -1 /* no ROM needed */ +#define XS_FLAGS 0 +#define XS_READB Map_ReadB +#define XS_READW Map_ReadW +#define XS_WRITEB Map_WriteB +#define XS_WRITEW Map_WriteW + +/* Function prototypes for I/O */ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); + +/* Function prototypes for system-specific unaligned support */ + +int32 ReadIOU (uint32 pa, int32 lnt); +int32 ReadRegU (uint32 pa, int32 lnt); +void WriteIOU (uint32 pa, int32 val, int32 lnt); +void WriteRegU (uint32 pa, int32 val, int32 lnt); + +t_stat auto_config (const char *name, int32 nctrl); + +/* Function prototypes for virtual and physical memory interface (inlined) */ + +#include "vax_mmu.h" + +#endif diff --git a/VAX/vax440_sysdev.c b/VAX/vax440_sysdev.c new file mode 100644 index 00000000..efe86cd4 --- /dev/null +++ b/VAX/vax440_sysdev.c @@ -0,0 +1,1089 @@ +/* vax440_sysdev.c: MicroVAX 4000-60 system-specific logic + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + This module contains the MicroVAX 4000-60 system-specific registers and devices. + + sysd system devices +*/ + +#include "vax_defs.h" +#include "sim_ether.h" +#include + +#ifdef DONT_USE_INTERNAL_ROM +#if defined (VAX_46) +#define BOOT_CODE_FILENAME "ka46a.bin" +#elif defined (VAX_47) +#define BOOT_CODE_FILENAME "ka47a.bin" +#elif defined (VAX_48) +#define BOOT_CODE_FILENAME "ka48a.bin" +#endif +#else /* !DONT_USE_INTERNAL_ROM */ +#if defined (VAX_46) +#include "vax_ka46a_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#elif defined (VAX_47) +#include "vax_ka47a_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#elif defined (VAX_48) +#include "vax_ka48a_bin.h" /* Defines BOOT_CODE_FILENAME and BOOT_CODE_ARRAY, etc */ +#endif +#endif /* DONT_USE_INTERNAL_ROM */ + + +t_stat vax460_boot (int32 flag, CONST char *ptr); + +/* Special boot command, overrides regular boot */ + +CTAB vax460_cmd[] = { + { "BOOT", &vax460_boot, RU_BOOT, + "bo{ot} boot simulator\n", NULL, &run_cmd_message }, + { NULL } + }; + +/* KA460 configuration & test register */ + +#define CFGT_MEM 0x003F /* memory option */ +#define CFGT_V_VID 6 +#define CFGT_M_VID 0x3 +#define CFGT_VID (CFGT_M_VID << CFGT_V_VID) /* video option */ +#define CFGT_L3C 0x0100 /* line 3 console */ +#define CFGT_V_SIM 9 +#define CFGT_M_SIM 0x3F +#define CFGT_SIM (CFGT_M_SIM << CFGT_V_SIM) /* SIMM type */ + +/* KA460 parity control register - checked */ + +#define PARCTL_CPEN 0x00000001 /* system wide parity */ +#define PARCTL_REV 0x000000F0 +#define PARCTL_NPEN 0x00000100 /* NI parity en */ +#define PARCTL_NPERR 0x00000200 /* NI parity err */ +#define PARCTL_NMAP 0x00000400 +#define PARCTL_SPEN 0x00010000 /* SCSI parity en */ +#define PARCTL_SPERR 0x00020000 /* SCSI parity err */ +#define PARCTL_SMAP 0x00040000 +#define PARCTL_INVEN 0x01000000 +#define PARCTL_AGS 0x02000000 /* AG stall */ +#define PARCTL_ADP 0x80000000 +#define PARCTL_RD 0x830707F1 +#define PARCTL_WR 0x01010101 + +/* KA460 secondary cache control register - checked */ + +#define SCCR_CENA 0x00000001 +#define SCCR_TERR 0x00000002 +#define SCCR_WBMODE 0x00000080 +#define SCCR_SPECIO 0x00000100 /* SPECIO inhibit */ +#define SCCR_FONFUL 0x00000200 +#define SCCR_REV 0x00000400 +#define SCCR_RD 0x00000783 +#define SCCR_WR 0x00000101 + +/* KA460 Memory system error register */ + +#define MSER_PE 0x00000001 /* Parity Enable */ +#define MSER_WWP 0x00000002 /* Write Wrong Parity */ +#define MSER_PER 0x00000040 /* Parity Error */ +#define MSER_MCD0 0x00000100 /* Mem Code 0 */ +#define MSER_MBZ 0xFFFFFEBC +#define MSER_RD (MSER_PE | MSER_WWP | MSER_PER | \ + MSER_PER | MSER_MCD0) +#define MSER_WR (MSER_PE | MSER_WWP) +#define MSER_RS (MSER_PER) + +/* KA460 memory error address reg */ + +#define MEAR_FAD 0x00007FFF /* failing addr */ +#define MEAR_RD (MEAR_FAD) + +#define ROM_VEC 0x8 /* ROM longword for first device vector */ + +/* DMA map registers */ + +#define DMANMAPR 32768 /* number of map reg */ +#define DMAMAP_VLD 0x80000000 /* valid */ +#define DMAMAP_PAG 0x0000FFFF /* mem page */ +#define DMAMAP_RD (QBMAP_VLD | QBMAP_PAG) +#define DMAMAP_WR (QBMAP_VLD | QBMAP_PAG) + +extern int32 tmr_int; +extern DEVICE lk_dev, vs_dev; +extern uint32 *rom; + +uint32 *isdn = NULL; /* ISDN/audio registers */ +uint32 *invfl = NULL; /* invalidate filter */ +uint32 *cache2ds = NULL; /* cache 2 data store */ +uint32 *cache2ts = NULL; /* cache 2 tag store */ +int32 conisp, conpc, conpsl; /* console reg */ +int32 ka_hltcod = 0; /* KA460 halt code */ +int32 ka_mapbase = 0; /* KA460 map base */ +int32 ka_cfgtst = 0x90; /* KA460 config/test */ +int32 ka_led = 0; /* KA460 diag display */ +int32 ka_parctl = 0xF0; /* KA460 parity control */ +int32 mem_cnfg = 0; +int32 CADR = 0; /* cache disable reg */ +int32 SCCR = 0; /* secondary cache control */ +int32 sys_model = 0; /* MicroVAX or VAXstation */ +int32 int_req[IPL_HLVL] = { 0 }; /* interrupt requests */ +int32 int_mask = 0; /* interrupt mask */ +uint32 tmr_tir = 0; /* curr interval */ + +t_stat sysd_reset (DEVICE *dptr); +const char *sysd_description (DEVICE *dptr); +int32 ka_rd (int32 pa); +void ka_wr (int32 pa, int32 val, int32 lnt); +int32 con_halt (int32 code, int32 cc); + +extern int32 iccs_rd (void); +extern int32 rom_rd (int32 pa); +extern int32 nvr_rd (int32 pa); +extern int32 nar_rd (int32 pa); +extern int32 dz_rd (int32 pa); +extern int32 or_rd (int32 pa); +extern int32 rz_rd (int32 pa); +extern int32 xs_rd (int32 pa); +extern void iccs_wr (int32 dat); +extern void nvr_wr (int32 pa, int32 val, int32 lnt); +extern void dz_wr (int32 pa, int32 val, int32 lnt); +extern void rz_wr (int32 pa, int32 val, int32 lnt); +extern void xs_wr (int32 pa, int32 val, int32 lnt); + +UNIT sysd_unit = { UDATA (NULL, 0, 0) }; + +REG sysd_reg[] = { + { HRDATAD (CONISP, conisp, 32, "console ISP") }, + { HRDATAD (CONPC, conpc, 32, "console PD") }, + { HRDATAD (CONPSL, conpsl, 32, "console PSL") }, + { HRDATAD (CFGTST, ka_cfgtst, 16, "KA460 config/test") }, + { HRDATAD (HLTCOD, ka_hltcod, 32, "KA460 halt code") }, + { HRDATAD (MAPBASE, ka_mapbase, 32, "KA460 DMA map base") }, + { HRDATAD (LED, ka_led, 16, "KA460 diag display") }, + { HRDATAD (PARCTL, ka_parctl, 32, "KA460 parity control") }, + { NULL } + }; + +MTAB sysd_mod[] = { + { 0 }, + }; + +DEVICE sysd_dev = { + "SYSD", &sysd_unit, sysd_reg, sysd_mod, + 1, 16, 16, 1, 16, 8, + NULL, NULL, &sysd_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, + &sysd_description + }; + +/* Find highest priority outstanding interrupt */ + +int32 eval_int (void) +{ +int32 ipl = PSL_GETIPL (PSL); +int32 i, t; + +static const int32 sw_int_mask[IPL_SMAX] = { + 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, /* 0 - 3 */ + 0xFFE0, 0xFFC0, 0xFF80, 0xFF00, /* 4 - 7 */ + 0xFE00, 0xFC00, 0xF800, 0xF000, /* 8 - B */ + 0xE000, 0xC000, 0x8000 /* C - E */ + }; + +if (hlt_pin) /* hlt pin int */ + return IPL_HLTPIN; +if ((ipl < IPL_CLK) && tmr_int) /* clock int */ + return IPL_CLK; +if (ipl < IPL_HW) { /* chk hwre int */ + if (int_req[0] & int_mask) + return IPL_HW; + } +if (ipl >= IPL_SMAX) /* ipl >= sw max? */ + return 0; +if ((t = SISR & sw_int_mask[ipl]) == 0) /* eligible req */ + return 0; +for (i = IPL_SMAX; i > ipl; i--) { /* check swre int */ + if ((t >> i) & 1) /* req != 0? int */ + return i; + } +return 0; +} + +/* Return vector for highest priority hardware interrupt at IPL lvl */ + +int32 get_vector (int32 lvl) +{ +int32 i; +int32 int_unmask = int_req[0] & int_mask; + +if (lvl == IPL_CLK) { /* clock? */ + tmr_int = 0; /* clear req */ + return SCB_INTTIM; /* return vector */ + } +if (lvl > IPL_HMAX) { /* error req lvl? */ + ABORT (STOP_UIPL); /* unknown intr */ + } +for (i = 7; int_unmask && (i >= 0); i--) { + if ((int_unmask >> i) & 1) { + int_req[0] = int_req[0] & ~(1u << i); + return rom[ROM_VEC + i] & 0x3FF; /* get vector from ROM */ + } + } +return 0; +} + +/* Map an address via the translation map */ + +t_bool dma_map_addr (uint32 da, uint32 *ma) +{ +int32 dblk = (da >> VA_V_VPN); /* DMA blk */ +if (dblk <= DMANMAPR) { + int32 dmap = ReadL (ka_mapbase + (dblk << 2)); + if (dmap & DMAMAP_VLD) { /* valid? */ + *ma = ((dmap & DMAMAP_PAG) << VA_V_VPN) + VA_GETOFF (da); + if (ADDR_IS_MEM (*ma)) /* legit addr */ + return TRUE; + } + } +return FALSE; +} + +/* DMA buffer routines, aligned access + + Map_ReadB - fetch byte buffer from memory + Map_ReadW - fetch word buffer from memory + Map_WriteB - store byte buffer into memory + Map_WriteW - store word buffer into memory +*/ + +int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + *buf = ReadB (ma); + ma = ma + 1; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = ReadL (ma); /* get lw */ + *buf++ = dat & BMASK; /* low 8b */ + *buf++ = (dat >> 8) & BMASK; /* next 8b */ + *buf++ = (dat >> 16) & BMASK; /* next 8b */ + *buf = (dat >> 24) & BMASK; + ma = ma + 4; + } + } +return 0; +} + +int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma,dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + *buf = ReadW (ma); + ma = ma + 2; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = ReadL (ma); /* get lw */ + *buf++ = dat & WMASK; /* low 16b */ + *buf = (dat >> 16) & WMASK; /* high 16b */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf) +{ +int32 i; +uint32 ma, dat; + +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i++, buf++) { /* by bytes */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + WriteB (ma, *buf); + ma = ma + 1; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = (uint32) *buf++; /* get low 8b */ + dat = dat | (((uint32) *buf++) << 8); /* merge next 8b */ + dat = dat | (((uint32) *buf++) << 16); /* merge next 8b */ + dat = dat | (((uint32) *buf) << 24); /* merge hi 8b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf) +{ +int32 i; +uint32 ma, dat; + +ba = ba & ~01; +bc = bc & ~01; +if ((ba | bc) & 03) { /* check alignment */ + for (i = ma = 0; i < bc; i = i + 2, buf++) { /* by words */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + WriteW (ma, *buf); + ma = ma + 2; + } + } +else { + for (i = ma = 0; i < bc; i = i + 4, buf++) { /* by longwords */ + if ((ma & VA_M_OFF) == 0) { /* need map? */ + if (!dma_map_addr (ba + i, &ma)) /* inv or NXM? */ + return (bc - i); + } + dat = (uint32) *buf++; /* get low 16b */ + dat = dat | (((uint32) *buf) << 16); /* merge hi 16b */ + WriteL (ma, dat); /* store lw */ + ma = ma + 4; + } + } +return 0; +} + +int32 isdn_rd (int32 pa) +{ +int32 rg = (pa - 0x200D0000) >> 2; +return isdn[rg]; +} + +void isdn_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - 0x200D0000) >> 2; +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + isdn[rg] = ((val & mask) << sc) | (isdn[rg] & ~(mask << sc)); + } +else isdn[rg] = val; +} + +int32 cfg_rd (int32 pa) +{ +int32 val = ka_cfgtst; +t_addr mem = MEMSIZE; +uint32 sc; + +#if defined (VAX_46) || defined (VAX_47) +mem -= (1u << 23); /* 8MB on system board */ +#endif +for (sc = 0; mem > 0; sc+=2) { + if (mem >= (1u << 25)) { + val |= (0x3 << sc); /* add two 16MB SIMMs */ + val |= (0x3 << (sc + CFGT_V_SIM)); + mem -= (1u << 25); + } + else { + val |= (0x3 << sc); /* add two 4MB SIMMs */ + mem -= (1u << 23); + } + } +return val; +} + +void ioreset_wr (int32 pa, int32 val, int32 lnt) +{ +reset_all (6); +} + +/* Read KA460 specific IPR's */ + +int32 ReadIPR (int32 rg) +{ +int32 val; + +switch (rg) { + + case MT_ICCS: /* ICCS */ + val = iccs_rd (); + break; + + case MT_MCESR: /* MCESR (not impl) */ + val = 0; + break; + + case MT_ACCS: /* ACCS (not impl) */ + val = 0; + break; + + case MT_CONISP: /* console ISP */ + val = conisp; + break; + + case MT_CONPC: /* console PC */ + val = conpc; + break; + + case MT_CONPSL: /* console PSL */ + val = conpsl; + break; + + case MT_CADR: /* CADR */ + val = CADR & 0xFF; + break; + + case MT_CAER: /* CAER */ + val = 0; + break; + + case MT_PCTAG: /* PCTAG (not impl) */ + val = 0; + break; + + case MT_PCIDX: /* PCIDX (not impl) */ + val = 0; + break; + + case MT_PCERR: /* PCERR (not impl) */ + val = 0; + break; + + case MT_PCSTS: /* PCSTS (not impl) */ + val = 0; + break; + + case MT_SID: /* SID */ + val = VAX4X_SID | VAX4X_UREV; + break; + + default: + RSVD_OPND_FAULT; + } + +return val; +} + +/* Write KA460 specific IPR's */ + +void WriteIPR (int32 rg, int32 val) +{ +switch (rg) { + + case MT_ICCS: /* ICCS */ + iccs_wr (val); + break; + + case MT_NICR: /* NICR (not impl) */ + break; + + case MT_MCESR: /* MCESR (not impl) */ + break; + + case MT_ACCS: /* ACCS (not impl) */ + break; + + case MT_CONISP: /* console ISP */ + conisp = val; + break; + + case MT_CONPC: /* console PC */ + conpc = val; + break; + + case MT_CONPSL: /* console PSL */ + conpsl = val; + break; + + case MT_CADR: /* CADR */ + CADR = (val & CADR_RW) | CADR_MBO; + break; + + case MT_CAER: /* CAER */ + break; + + case MT_PCTAG: /* PCTAG (not impl) */ + break; + + case MT_PCIDX: /* PCIDX (not impl) */ + break; + + case MT_PCERR: /* PCERR (not impl) */ + break; + + case MT_PCSTS: /* PCSTS (not impl) */ + break; + + default: + RSVD_OPND_FAULT; + } + +return; +} + +int32 invfl_rd (int32 pa) +{ +int32 rg = (pa - 0x20200000) >> 2; +return invfl[rg]; +} + +void invfl_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - 0x20200000) >> 2; +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + invfl[rg] = ((val & mask) << sc) | (invfl[rg] & ~(mask << sc)); + } +else invfl[rg] = val; +} + +int32 cache2ds_rd (int32 pa) +{ +int32 rg = (pa - 0x08000000) >> 2; +return cache2ds[rg]; +} + +void cache2ds_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - 0x08000000) >> 2; +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + cache2ds[rg] = ((val & mask) << sc) | (cache2ds[rg] & ~(mask << sc)); + } +else cache2ds[rg] = val; +} + +int32 cache2ts_rd (int32 pa) +{ +int32 rg = (pa - 0x22000000) >> 2; +return cache2ts[rg]; +} + +void cache2ts_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - 0x22000000) >> 2; +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + cache2ts[rg] = ((val & mask) << sc) | (cache2ts[rg] & ~(mask << sc)); + } +else cache2ts[rg] = val; +} + +int32 dma_map_rd (int32 pa) +{ +int32 rg = (pa - DMABASE); +int32 val = ReadL (ka_mapbase + rg); +return val; +} + +void dma_map_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - DMABASE); +WriteL (ka_mapbase + rg, val); +} + +int32 sccr_rd (int32 pa) +{ +return SCCR & SCCR_RD; +} + +void sccr_wr (int32 pa, int32 val, int32 lnt) +{ +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + SCCR = (((val & mask) << sc) | (SCCR & ~(mask << sc))) & SCCR_WR; + } +else SCCR = val & SCCR_WR; +} + +int32 memrg_rd (int32 pa) +{ +int32 rg = (pa - 0x20101800) >> 2; + +switch (rg) { + + case 0: /* MEMCNFG */ + return mem_cnfg; + + case 1: /* MEMSTAT */ + return 0; + + case 2: /* MEMCUR */ + return 0; + + case 3: /* MEMERR */ + return 0; + } + +return 0; +} + +void memrg_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - 0x20101800) >> 2; + +switch (rg) { + + case 0: /* MEMCNFG */ + mem_cnfg = val; + break; + + case 1: /* MEMSTAT - RO? */ + break; + + case 2: /* MEMCUR - RO? */ + break; + + case 3: /* MEMERR - RO? */ + break; + } +return; +} + +int32 null_rd (int32 pa) +{ +return 0; +} + +void null_wr (int32 pa, int32 val, int32 lnt) +{ +} + +/* Read/write I/O register space + + These routines are the 'catch all' for address space map. Any + address that doesn't explicitly belong to memory, I/O, or ROM + is given to these routines for processing. +*/ + +struct reglink { /* register linkage */ + uint32 low; /* low addr */ + uint32 high; /* high addr */ + int32 (*read)(int32 pa); /* read routine */ + void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */ + }; + +struct reglink regtable[] = { + { DMABASE, DMABASE+DMASIZE, &dma_map_rd, &dma_map_wr }, + { 0x200D0000, 0x200D4000, &isdn_rd, &isdn_wr }, /* ISDN/audio */ + { XSBASE, XSBASE+XSSIZE, &xs_rd, &xs_wr }, + { DZBASE, DZBASE+DZSIZE, &dz_rd, dz_wr }, /* needs extra register */ + { RZBASE, RZBASE+RZSIZE, &rz_rd, rz_wr }, + { ORBASE, ORBASE+ORSIZE, &or_rd, NULL }, + { NARBASE, NARBASE+NARSIZE, &nar_rd, NULL }, + { CFGBASE, CFGBASE+CFGSIZE, &cfg_rd, &ioreset_wr }, + { 0x20200000, 0x20220000, &invfl_rd, &invfl_wr }, /* Invalidate filter */ + { 0x23000000, 0x23000004, &sccr_rd, &sccr_wr }, + { 0x36800000, 0x36800004, &null_rd, &null_wr }, /* Turbo CSR */ + { 0x08000000, 0x08040000, &cache2ds_rd, &cache2ds_wr }, /* Cache second data store */ + { 0x22000000, 0x22040000, &cache2ts_rd, &cache2ts_wr }, /* Cache second tag store - should be at 0x2D000000? */ + { 0x20101800, 0x20101810, &memrg_rd, &memrg_wr }, + { 0x20101A00, 0x20102000, NULL, &null_wr }, /* invalidate single - check size */ + { ROMBASE, ROMBASE+ROMSIZE, &rom_rd, NULL }, + { NVRBASE, NVRBASE+NVRSIZE, &nvr_rd, &nvr_wr }, + { KABASE, KABASE+KASIZE, &ka_rd, &ka_wr }, /* needs extending */ + { 0, 0, NULL, NULL } + }; + +/* ReadReg - read register space + + Inputs: + pa = physical address + lnt = length (BWLQ) - ignored + Output: + longword of data +*/ + +int32 ReadReg (uint32 pa, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->read) + return p->read (pa); + } +return 0xFFFFFFFF; +} + +/* ReadRegU - read register space, unaligned + + Inputs: + pa = physical address + lnt = length in bytes (1, 2, or 3) + Output: + returned data, not shifted +*/ + +int32 ReadRegU (uint32 pa, int32 lnt) +{ +return ReadReg (pa & ~03, L_LONG); +} + +/* WriteReg - write register space + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (BWLQ) + Outputs: + none +*/ + +void WriteReg (uint32 pa, int32 val, int32 lnt) +{ +struct reglink *p; + +for (p = ®table[0]; p->low != 0; p++) { + if ((pa >= p->low) && (pa < p->high) && p->write) { + p->write (pa, val, lnt); + return; + } + } +return; +} + +/* WriteRegU - write register space, unaligned + + Inputs: + pa = physical address + val = data to write, right justified in 32b longword + lnt = length (1, 2, or 3) + Outputs: + none +*/ + +void WriteRegU (uint32 pa, int32 val, int32 lnt) +{ +int32 sc = (pa & 03) << 3; +int32 dat = ReadReg (pa & ~03, L_LONG); + +dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc); +WriteReg (pa & ~03, dat, L_LONG); +return; +} + +/* KA460 registers */ + +int32 ka_rd (int32 pa) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* halt code */ + return ka_hltcod; + + case 2: /* DMA map base */ + return ka_mapbase; + + case 3: /* int req, int mask */ + return ((int_req[0] & BMASK) << 24) | \ + (int_mask & BMASK); + + case 5: /* parity ctl */ + /* Schip revision in bits (7:4) */ + return ka_parctl & PARCTL_RD; + + case 7: /* diag timer */ + tmr_tir = (tmr_tir + 5) & 0xFFFF; + return (tmr_tir << 16) | tmr_tir; + } + +return 0; +} + +void ka_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - KABASE) >> 2; + +switch (rg) { + + case 0: /* halt code */ + ka_hltcod = val; + break; + + case 2: /* DMA map base */ + ka_mapbase = val; + break; + + case 3: + switch (pa & 3) { + case 0: /* int mask */ + int_mask = val & BMASK; + SET_IRQL; + break; + + case 1: + case 2: + break; + + case 3: /* int clear */ + int_req[0] = int_req[0] & ~(val & BMASK); + break; + } + break; + + case 4: /* LED */ + ka_led = val; + break; + + case 5: /* parity ctl */ + ka_parctl = (ka_parctl & ~PARCTL_WR) | (val & PARCTL_WR); + break; + + case 7: /* diag timer */ + tmr_tir = (val >> 16); + } +return; +} + +/* Machine check */ + +int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta) +{ +int32 p2, acc; + +if (in_ie) { + in_ie = 0; + return con_halt (CON_DBLMCK, cc); /* double machine check */ + } +if (p1 & 0x80) /* mref? set v/p */ + p1 = p1 + mchk_ref; +p2 = mchk_va + 4; /* save vap */ +cc = intexc (SCB_MCHK, cc, 0, IE_SVE); /* take exception */ +acc = ACC_MASK (KERN); /* in kernel mode */ +in_ie = 1; +SP = SP - 28; /* push 7 words */ +Write (SP, 24, L_LONG, WA); /* # bytes */ +Write (SP + 4, p1, L_LONG, WA); /* mcheck type */ +Write (SP + 8, p2, L_LONG, WA); /* address */ +Write (SP + 12, 0, L_LONG, WA); /* VIBA */ +Write (SP + 16, 0, L_LONG, WA); /* ICCS..SISR */ +Write (SP + 20, 0, L_LONG, WA); /* state */ +Write (SP + 24, 0, L_LONG, WA); /* SC */ +in_ie = 0; +return cc; +} + +/* Console entry */ + +int32 con_halt (int32 code, int32 cc) +{ +int32 temp; + +conisp = IS; /* save ISP */ +conpc = PC; /* save PC */ +conpsl = ((PSL | cc) & 0xFFFF00FF) | code; /* PSL, param */ +temp = (PSL >> PSL_V_CUR) & 0x7; /* get is'cur */ +if (temp > 4) /* invalid? */ + conpsl = conpsl | CON_BADPSL; +else STK[temp] = SP; /* save stack */ +if (mapen) /* mapping on? */ + conpsl = conpsl | CON_MAPON; +mapen = 0; /* turn off map */ +SP = IS; /* set SP from IS */ +PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */ +JUMP (ROMBASE); /* PC = 20040000 */ +return 0; /* new cc = 0 */ +} + + +/* Special boot command - linked into SCP by initial reset + + Syntax: BOOT {CPU} + +*/ + +t_stat vax460_boot (int32 flag, CONST char *ptr) +{ +char gbuf[CBUFSIZE]; + +get_glyph (ptr, gbuf, 0); /* get glyph */ +if (gbuf[0] && strcmp (gbuf, "CPU")) + return SCPE_ARG; /* Only can specify CPU device */ +return run_cmd (flag, "CPU"); +} + + +/* Bootstrap */ + +t_stat cpu_boot (int32 unitno, DEVICE *dptr) +{ +t_stat r; + +PC = ROMBASE; +PSL = PSL_IS | PSL_IPL1F; +conisp = 0; +conpc = 0; +conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP; +if (rom == NULL) + return SCPE_IERR; +if (*rom == 0) { /* no boot? */ + r = cpu_load_bootcode (BOOT_CODE_FILENAME, BOOT_CODE_ARRAY, BOOT_CODE_SIZE, TRUE, 0); + if (r != SCPE_OK) + return r; + } +return SCPE_OK; +} + +/* SYSD reset */ + +t_stat sysd_reset (DEVICE *dptr) +{ +ka_mapbase = 0; +ka_cfgtst = CFGT_L3C; +ka_led = 0; +ka_parctl = 0xF0; +tmr_tir = 0; + +if (isdn == NULL) /* dummy mem for ISDN */ + isdn = (uint32 *) calloc (0x4000 >> 2, sizeof (uint32)); +if (isdn == NULL) + return SCPE_MEM; +if (invfl == NULL) /* dummy mem for invalidate filter */ + invfl = (uint32 *) calloc (0x8000, sizeof (uint32)); +if (invfl == NULL) + return SCPE_MEM; +if (cache2ds == NULL) /* dummy mem for cache data store */ + cache2ds = (uint32 *) calloc (0x10002, sizeof (uint32)); +if (cache2ds == NULL) + return SCPE_MEM; +if (cache2ts == NULL) /* dummy mem for cache tag store */ + cache2ts = (uint32 *) calloc (0x10000, sizeof (uint32)); +if (cache2ts == NULL) + return SCPE_MEM; + +sim_vm_cmd = vax460_cmd; + +return SCPE_OK; +} + +const char *sysd_description (DEVICE *dptr) +{ +return "system devices"; +} + +t_stat auto_config (const char *name, int32 nctrl) +{ +return SCPE_OK; +} + +t_stat build_dib_tab (void) +{ +return SCPE_OK; +} + +t_stat cpu_set_model (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +char gbuf[CBUFSIZE]; + +if ((cptr == NULL) || (!*cptr)) + return SCPE_ARG; +cptr = get_glyph (cptr, gbuf, 0); +if (MATCH_CMD(gbuf, "MICROVAX") == 0) { + sys_model = 0; +#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL) + lk_dev.flags = lk_dev.flags | DEV_DIS; /* disable keyboard */ + vs_dev.flags = vs_dev.flags | DEV_DIS; /* disable mouse */ +#endif + strcpy (sim_name, "MicroVAX 3100-80 (KA47)"); + reset_all (0); /* reset everything */ + } +#if defined (VAX_46) || defined (VAX_48) +else if (MATCH_CMD(gbuf, "VAXSTATION") == 0) { +#if defined(USE_SIM_VIDEO) && defined(HAVE_LIBSDL) + sys_model = 1; + lk_dev.flags = lk_dev.flags & ~DEV_DIS; /* enable keyboard */ + vs_dev.flags = vs_dev.flags & ~DEV_DIS; /* enable mouse */ +#if defined (VAX_46) + strcpy (sim_name, "VAXstation 4000-60 (KA46)"); +#else /* VAX_48 */ + strcpy (sim_name, "VAXstation 4000-VLC (KA48)"); +#endif + reset_all (0); /* reset everything */ +#else + return sim_messagef (SCPE_ARG, "Simulator built without Graphic Device Support\n"); +#endif + } +#endif +else + return SCPE_ARG; +return SCPE_OK; +} + +t_stat cpu_print_model (FILE *st) +{ +fprintf (st, "%s", sim_name); +#if defined (VAX_46) +fprintf (st, "VAXstation 4000-60 (KA46)"); +#elif defined (VAX_47) +fprintf (st, "MicroVAX 3100-80 (KA47)"); +#elif defined (VAX_48) +fprintf (st, "VAXstation 4000-VLC (KA48)"); +#endif +return SCPE_OK; +} + +t_stat cpu_model_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Initial memory size is 16MB.\n\n"); +fprintf (st, "The simulator is booted with the BOOT command:\n\n"); +fprintf (st, " sim> BOOT\n\n"); +return SCPE_OK; +} diff --git a/VAX/vax440_syslist.c b/VAX/vax440_syslist.c new file mode 100644 index 00000000..53db6700 --- /dev/null +++ b/VAX/vax440_syslist.c @@ -0,0 +1,135 @@ +/* vax440_syslist.c: MicroVAX 4000-60 device list + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). +*/ + +#include "vax_defs.h" + +#if defined (VAX_46) +char sim_name[64] = "VAXstation 4000-60 (KA46)"; +#elif defined (VAX_47) +char sim_name[64] = "MicroVAX 3100-80 (KA47)"; +#elif defined (VAX_48) +char sim_name[64] = "VAXstation 4000-VLC (KA48)"; +#endif + +void vax_init(void) +{ +#if defined (VAX_46) +sim_savename = "VAXstation 4000-60 (KA46)"; +#elif defined (VAX_47) +sim_savename = "MicroVAX 3100-80 (KA47)"; +#elif defined (VAX_48) +sim_savename = "VAXstation 4000-VLC (KA48)"; +#endif +} + +WEAK void (*sim_vm_init) (void) = &vax_init; + +extern DEVICE cpu_dev; +extern DEVICE tlb_dev; +extern DEVICE rom_dev; +extern DEVICE nvr_dev; +extern DEVICE nar_dev; +extern DEVICE wtc_dev; +extern DEVICE sysd_dev; +extern DEVICE clk_dev; +extern DEVICE or_dev; +extern DEVICE dz_dev; +extern DEVICE rz_dev; +extern DEVICE xs_dev; +extern DEVICE lk_dev; +extern DEVICE vs_dev; + +extern void WriteB (uint32 pa, int32 val); +extern void rom_wr_B (int32 pa, int32 val); +extern UNIT cpu_unit; + +DEVICE *sim_devices[] = { + &cpu_dev, + &tlb_dev, + &rom_dev, + &nvr_dev, + &nar_dev, + &wtc_dev, + &sysd_dev, + &clk_dev, + &or_dev, + &dz_dev, + &rz_dev, +#if defined (VAX_46) || defined (VAX_48) + &lk_dev, + &vs_dev, +#endif + &xs_dev, + NULL + }; + +/* Binary loader + + The binary loader handles absolute system images, that is, system + images linked /SYSTEM. These are simply a byte stream, with no + origin or relocation information. + + -r load ROM + -n load NVR + -o for memory, specify origin +*/ + +t_stat sim_load (FILE *fileref, CONST char *cptr, CONST char *fnam, int flag) +{ +t_stat r; +int32 i; +uint32 origin, limit; + +if (flag) /* dump? */ + return sim_messagef (SCPE_NOFNC, "Command Not Implemented\n"); +if (sim_switches & SWMASK ('R')) { /* ROM? */ + origin = ROMBASE; + limit = ROMBASE + ROMSIZE; + } +else if (sim_switches & SWMASK ('N')) { /* NVR? */ + origin = NVRBASE; + limit = NVRBASE + NVRSIZE; + } +else { + origin = 0; /* memory */ + limit = (uint32) cpu_unit.capac; + if (sim_switches & SWMASK ('O')) { /* origin? */ + origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r); + if (r != SCPE_OK) + return SCPE_ARG; + } + } +while ((i = Fgetc (fileref)) != EOF) { /* read byte stream */ + if (origin >= limit) /* NXM? */ + return SCPE_NXM; + if (sim_switches & SWMASK ('R')) /* ROM? */ + rom_wr_B (origin, i); /* not writeable */ + else WriteB (origin, i); /* store byte */ + origin = origin + 1; + } +return SCPE_OK; +} diff --git a/VAX/vax4nn_stddev.c b/VAX/vax4nn_stddev.c new file mode 100644 index 00000000..830e2c8d --- /dev/null +++ b/VAX/vax4nn_stddev.c @@ -0,0 +1,446 @@ +/* vax4nn_stddev.c: KA4nn standard devices + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + rom bootstrap ROM (no registers) + nvr non-volatile ROM (no registers) + clk 100Hz and TODR clock +*/ + +#include "vax_defs.h" +#include + +#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */ +#define UNIT_NODELAY (1u << UNIT_V_NODELAY) + +#define CLKCSR_IMP (CSR_IE) /* real-time clock */ +#define CLKCSR_RW (CSR_IE) +#define CLK_DELAY 5000 /* 100 Hz */ +#define TMXR_MULT 1 /* 100 Hz */ + +uint32 *rom = NULL; /* boot ROM */ +uint8 *nvr = NULL; /* non-volatile mem */ +int32 clk_csr = 0; /* control/status */ +int32 clk_tps = 100; /* ticks/second */ +int32 tmr_int = 0; /* interrupt */ +int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ +int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ + +t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat rom_reset (DEVICE *dptr); +t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *rom_description (DEVICE *dptr); +t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat nvr_reset (DEVICE *dptr); +t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +t_stat nvr_attach (UNIT *uptr, CONST char *cptr); +t_stat nvr_detach (UNIT *uptr); +const char *nvr_description (DEVICE *dptr); +t_stat clk_svc (UNIT *uptr); +t_stat clk_reset (DEVICE *dptr); +const char *clk_description (DEVICE *dptr); + +extern int32 sysd_hlt_enb (void); +extern int32 nar_rd (int32 pa); +extern int32 wtc_rd (int32 rg); +extern void wtc_wr (int32 rg, int32 val); +extern void wtc_set_valid (void); +extern void wtc_set_invalid (void); + +/* ROM data structures + + rom_dev ROM device descriptor + rom_unit ROM units + rom_reg ROM register list +*/ + +UNIT rom_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, ROMSIZE) }; + +REG rom_reg[] = { + { NULL } + }; + +MTAB rom_mod[] = { + { UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL, NULL, NULL, "Disable calibrated ROM access speed" }, + { UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL, NULL, NULL, "Enable calibrated ROM access speed" }, + { 0 } + }; + +DEVICE rom_dev = { + "ROM", &rom_unit, rom_reg, rom_mod, + 1, 16, ROMAWIDTH, 4, 16, 32, + &rom_ex, &rom_dep, &rom_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, &rom_help, NULL, NULL, + &rom_description + }; + +/* NVR data structures + + nvr_dev NVR device descriptor + nvr_unit NVR units + nvr_reg NVR register list +*/ + +UNIT nvr_unit = + { UDATA (NULL, UNIT_FIX+UNIT_BINK, NVRSIZE) }; + +REG nvr_reg[] = { + { NULL } + }; + +DEVICE nvr_dev = { + "NVR", &nvr_unit, nvr_reg, NULL, + 1, 16, NVRAWIDTH, 4, 16, 8, + &nvr_ex, &nvr_dep, &nvr_reset, + NULL, &nvr_attach, &nvr_detach, + NULL, 0, 0, NULL, NULL, NULL, &nvr_help, NULL, NULL, + &nvr_description + }; + +/* CLK data structures + + clk_dev CLK device descriptor + clk_unit CLK unit descriptor + clk_reg CLK register list +*/ + +UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY }; + +REG clk_reg[] = { + { HRDATAD (CSR, clk_csr, 16, "control/status register") }, + { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, +#if defined (SIM_ASYNCH_IO) + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, +#endif + { NULL } + }; + +DEVICE clk_dev = { + "CLK", &clk_unit, clk_reg, NULL, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &clk_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, + &clk_description + }; + +/* ROM: read only memory - stored in a buffered file + Register space access routines see ROM twice + + ROM access has been 'regulated' to about 1Mhz to avoid issues + with testing the interval timers in self-test. Specifically, + the VAX boot ROM (ka4xx.bin) contains code which presumes that + the VAX runs at a particular slower speed when code is running + from ROM (which is not cached). These assumptions are built + into instruction based timing loops. As the host platform gets + much faster than the original VAX, the assumptions embedded in + these code loops are no longer valid. + + Code has been added to the ROM implementation to limit CPU speed + to about 500K instructions per second. This heads off any future + issues with the embedded timing loops. +*/ + +int32 rom_rd (int32 pa) +{ +int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2; +int32 val = rom[rg]; + +if (rom_unit.flags & UNIT_NODELAY) + return val; + +return sim_rom_read_with_delay (val); +} + +void rom_wr_B (int32 pa, int32 val) +{ +int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2; +int32 sc = (pa & 3) << 3; + +rom[rg] = ((val & 0xFF) << sc) | (rom[rg] & ~(0xFF << sc)); +return; +} + +/* ROM examine */ + +t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if ((vptr == NULL) || (addr & 03)) + return SCPE_ARG; +if (addr >= ROMSIZE) + return SCPE_NXM; +*vptr = rom[addr >> 2]; +return SCPE_OK; +} + +/* ROM deposit */ + +t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if (addr & 03) + return SCPE_ARG; +if (addr >= ROMSIZE) + return SCPE_NXM; +rom[addr >> 2] = (uint32) val; +return SCPE_OK; +} + +/* ROM reset */ + +t_stat rom_reset (DEVICE *dptr) +{ +if (rom == NULL) + rom = (uint32 *) calloc (ROMSIZE >> 2, sizeof (uint32)); +if (rom == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Read-only memory (ROM)\n\n"); +fprintf (st, "The boot ROM consists of a single unit, simulating the 256KB boot ROM. It has\n"); +fprintf (st, "no registers. The boot ROM is loaded with a binary byte stream using the \n"); +fprintf (st, "LOAD -r command:\n\n"); +fprintf (st, " LOAD -r KA410.BIN load ROM image KA410.BIN\n\n"); +fprintf (st, "When the simulator starts running (via the BOOT command), if the ROM has\n"); +fprintf (st, "not yet been loaded, an attempt will be made to automatically load the\n"); +fprintf (st, "ROM image from the file ka410.bin in the current working directory.\n"); +fprintf (st, "If that load attempt fails, then a copy of the missing ROM file is\n"); +fprintf (st, "written to the current directory and the load attempt is retried.\n\n"); +fprintf (st, "ROM accesses a use a calibrated delay that slows ROM-based execution to\n"); +fprintf (st, "about 500K instructions per second. This delay is required to make the\n"); +fprintf (st, "power-up self-test routines run correctly on very fast hosts.\n"); +fprint_set_help (st, dptr); +return SCPE_OK; +} + +const char *rom_description (DEVICE *dptr) +{ +return "read-only memory"; +} + +/* NVR: non-volatile RAM - stored in a buffered file */ + +int32 nvr_rd (int32 pa) +{ +int32 rg = (pa - NVRBASE) >> 2; +int32 val; + +val = nvr[rg]; +if (rg < 0x40) /* network addr */ + val = val | (nar_rd (pa) << 8); +return val; +} + +void nvr_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - NVRBASE) >> 2; +nvr[rg] = (val & BMASK); +} + +/* NVR examine */ + +t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if ((vptr == NULL) || (addr & 03)) + return SCPE_ARG; +if (addr >= NVRSIZE) + return SCPE_NXM; +*vptr = nvr[addr >> 2]; +return SCPE_OK; +} + +/* NVR deposit */ + +t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if (addr & 03) + return SCPE_ARG; +if (addr >= NVRSIZE) + return SCPE_NXM; +nvr[addr >> 2] = (uint32) val; +return SCPE_OK; +} + +/* NVR reset */ + +t_stat nvr_reset (DEVICE *dptr) +{ +if (nvr == NULL) { + nvr = (uint8 *) calloc (NVRSIZE >> 2, sizeof (uint32)); + nvr_unit.filebuf = nvr; + } +if (nvr == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Non-volatile Memory (NVR)\n\n"); +fprintf (st, "The NVR simulates %d bytes of battery-backed up memory.\n", NVRSIZE); +fprintf (st, "When the simulator starts, NVR is cleared to 0, and the battery-low indicator\n"); +fprintf (st, "is set. Alternately, NVR can be attached to a file. This allows the NVR\n"); +fprintf (st, "state to be preserved across simulator runs. Successfully attaching an NVR\n"); +fprintf (st, "image clears the battery-low indicator.\n\n"); +return SCPE_OK; +} + +/* NVR attach */ + +t_stat nvr_attach (UNIT *uptr, CONST char *cptr) +{ +t_stat r; + +uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE); +r = attach_unit (uptr, cptr); +if (r != SCPE_OK) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +else { + uptr->hwmark = (uint32) uptr->capac; + wtc_set_valid (); + } +return r; +} + +/* NVR detach */ + +t_stat nvr_detach (UNIT *uptr) +{ +t_stat r; + +r = detach_unit (uptr); +if ((uptr->flags & UNIT_ATT) == 0) { + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); + wtc_set_invalid (); + } +return r; +} + +const char *nvr_description (DEVICE *dptr) +{ +return "non-volatile memory"; +} + +/* Clock MxPR routines + + iccs_rd/wr interval timer +*/ + +int32 iccs_rd (void) +{ +return (clk_csr & CLKCSR_IMP); +} + +void iccs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + tmr_int = 0; +if (data & CSR_DONE) + sim_rtcn_tick_ack (20, TMR_CLK); +clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW); +return; +} + +/* Clock routines + + clk_svc process event (clock tick) + clk_reset process reset + clk_description return device description +*/ + +t_stat clk_svc (UNIT *uptr) +{ +int32 t; + +if (clk_csr & CSR_IE) + tmr_int = 1; +t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ +sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ +return SCPE_OK; +} + +/* Reset routine */ + +t_stat clk_reset (DEVICE *dptr) +{ +int32 t; + +clk_csr = 0; +tmr_int = 0; +t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */ +sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +return SCPE_OK; +} + +const char *clk_description (DEVICE *dptr) +{ +return "100hz clock tick"; +} + +/* Dummy I/O space functions */ + +int32 ReadIO (uint32 pa, int32 lnt) +{ +return 0; +} + +void WriteIO (uint32 pa, int32 val, int32 lnt) +{ +return; +} + +int32 ReadIOU (uint32 pa, int32 lnt) +{ +return 0; +} + +void WriteIOU (uint32 pa, int32 val, int32 lnt) +{ +return; +} diff --git a/VAX/vax4xx_dz.c b/VAX/vax4xx_dz.c new file mode 100644 index 00000000..540054de --- /dev/null +++ b/VAX/vax4xx_dz.c @@ -0,0 +1,892 @@ +/* vax4xx_dz.c: Built-in DZ terminal multiplexor simulator + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 2001-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + dz DZ terminal multiplexor +*/ + +#include "vax_defs.h" +#include "sim_sock.h" +#include "sim_tmxr.h" +#include "vax_lk.h" +#include "vax_vs.h" + +#define DZ_LINES 4 +#define DZ_LNOMASK (DZ_LINES - 1) /* mask for lineno */ +#define DZ_LMASK ((1 << DZ_LINES) - 1) /* mask of lines */ +#define DZ_SILO_ALM 16 /* silo alarm level */ + +/* line functions */ + +#define DZ_TMXR 0 +#define DZ_CONSOLE 1 +#define DZ_KEYBOARD 2 +#define DZ_MOUSE 3 + +/* DZCSR - 200A0000 - control/status register */ + +#define CSR_MAINT 0x0008 /* maint - NI */ +#define CSR_CLR 0x0010 /* clear */ +#define CSR_MSE 0x0020 /* master scan enb */ +#define CSR_RDONE 0x0080 /* rcv done - RO */ +#define CSR_V_TLINE 8 /* xmit line - RO */ +#define CSR_TLINE (DZ_LNOMASK << CSR_V_TLINE) +#define CSR_SAE 0x1000 /* silo alm enb */ +#define CSR_SA 0x2000 /* silo alm - RO */ +#define CSR_TRDY 0x8000 /* xmit rdy - RO */ +#define CSR_RW (CSR_MAINT | CSR_MSE | CSR_SAE) +#define CSR_MBZ (0xC07 | CSR_CLR) + +#define CSR_GETTL(x) (((x) >> CSR_V_TLINE) & DZ_LNOMASK) +#define CSR_PUTTL(x,y) x = ((x) & ~CSR_TLINE) | (((y) & DZ_LNOMASK) << CSR_V_TLINE) + +BITFIELD dz_csr_bits[] = { + BITNCF(3), /* not used */ + BIT(MAINT), /* Maint */ + BIT(CLR), /* clear */ + BIT(MSE), /* naster scan enable */ + BITNCF(1), /* not used */ + BIT(RDONE), /* receive done */ + BITF(TLINE,2), /* transmit line */ + BITNCF(2), /* not used */ + BIT(SAE), /* silo alarm enable */ + BIT(SA), /* silo alarm */ + BITNCF(1), /* not used */ + BIT(TRDY), /* transmit ready */ + ENDBITS + }; + +/* DZRBUF - 200A0004 - receive buffer, read only */ + +#define RBUF_CHAR 0x00FF /* rcv char */ +#define RBUF_V_RLINE 8 /* rcv line */ +#define RBUF_RLINE (DZ_LNOMASK << RBUF_V_RLINE) +#define RBUF_PARE 0x1000 /* parity err - NI */ +#define RBUF_FRME 0x2000 /* frame err */ +#define RBUF_OVRE 0x4000 /* overrun err - NI */ +#define RBUF_VALID 0x8000 /* rcv valid */ +#define RBUF_MBZ 0x0C00 + +#define RBUF_GETRL(x) (((x) >> RBUF_V_RLINE) & DZ_LNOMASK) +#define RBUF_PUTRL(x,y) x = ((x) & ~RBUF_RLINE) | (((y) & DZ_LNOMASK) << RBUF_V_RLINE) + +BITFIELD dz_rbuf_bits[] = { + BITFFMT(RBUF,8,"%02X"), /* Received Character */ + BITF(RLINE,2), /* receive line */ + BITNCF(2), /* not used */ + BIT(PARE), /* parity error */ + BIT(FRME), /* frame error */ + BIT(OVRE), /* overrun error */ + BIT(VALID), /* receive valid */ + ENDBITS + }; + +const char *dz_charsizes[] = {"5", "6", "7", "8"}; +const char *dz_baudrates[] = {"50", "75", "110", "134.5", "150", "300", "600", "1200", + "1800", "2000", "2400", "3600", "4800", "7200", "9600", "19200"}; +const char *dz_parity[] = {"N", "E", "N", "O"}; +const char *dz_stopbits[] = {"1", "2", "1", "1.5"}; + +/* DZLPR - 200A0004 - line parameter register, write only, word access only */ + +#define LPR_V_LINE 0 /* line */ +#define LPR_V_SPEED 8 /* speed code */ +#define LPR_M_SPEED 0x0F00 /* speed code mask */ +#define LPR_V_CHARSIZE 3 /* char size code */ +#define LPR_M_CHARSIZE 0x0018 /* char size code mask */ +#define LPR_V_STOPBITS 5 /* stop bits code */ +#define LPR_V_PARENB 6 /* parity enable */ +#define LPR_V_PARODD 7 /* parity odd */ +#define LPR_GETSPD(x) dz_baudrates[((x) & LPR_M_SPEED) >> LPR_V_SPEED] +#define LPR_GETCHARSIZE(x) dz_charsizes[((x) & LPR_M_CHARSIZE) >> LPR_V_CHARSIZE] +#define LPR_GETPARITY(x) dz_parity[(((x) >> LPR_V_PARENB) & 1) | (((x) >> (LPR_V_PARODD-1)) & 2)] +#define LPR_GETSTOPBITS(x) dz_stopbits[(((x) >> LPR_V_STOPBITS) & 1) + (((((x) & LPR_M_CHARSIZE) >> LPR_V_CHARSIZE) == 0) ? 2 : 0)] +#define LPR_LPAR 0x0FF8 /* line pars - NI */ +#define LPR_RCVE 0x1000 /* receive enb */ +#define LPR_GETLN(x) (((x) >> LPR_V_LINE) & DZ_LNOMASK) + +BITFIELD dz_lpr_bits[] = { + BITF(LINE,2), /* line */ + BITFNAM(CHARSIZE,2,dz_charsizes), /* character size */ + BIT(STOPBITS), /* stop bits code */ + BIT(PARENB), /* parity error */ + BIT(PARODD), /* frame error */ + BITFNAM(SPEED,4,dz_baudrates), /* speed code */ + BIT(RCVE), /* receive enable */ + BITNCF(3), /* not used */ + ENDBITS + }; + +/* DZTCR - 200A0008 - transmission control register */ + +#define TCR_V_XMTE 0 /* xmit enables */ +#define TCR_V_RTS2 8 /* RTS (line 2) */ +#define TCR_V_DSRS2 9 /* DSRS (line 2) */ +#define TCR_V_DTR2 10 /* DTR (line 2) */ +#define TCR_V_LLBK2 11 /* local loopback (line 2) */ +#define TCR_MBZ 0xF0F0 + +BITFIELD dz_tcr_bits[] = { + BITFFMT(XMTE,8,%02X), /* Transmit enable */ + BIT(RTS2), /* RTS (line 2) */ + BIT(DSRS2), /* DSRS (line 2) */ + BIT(DTR2), /* DTR (line 2) */ + BIT(LLBK2), /* local loopback (line 2) */ + BITNCF(4), /* not used */ + ENDBITS + }; + +/* DZMSR - 200A000C - modem status register, read only */ + +#define MSR_V_TMI2 0 /* test mode indicate (line2) */ +#define MSR_V_RI2 2 /* ring indicator (line 2) */ +#define MSR_V_CTS2 8 /* CTS (line 2) */ +#define MSR_V_DSR2 9 /* DSR (line 2) */ +#define MSR_V_CD2 10 /* carrier detect (line 2) */ +#define MSR_V_SPDI2 11 /* speed mode indicate (line 2) */ + +BITFIELD dz_msr_bits[] = { + BIT(TMI2), /* test mode indicate (line2) */ + BIT(RI2), /* ring indicator (line 2) */ + BIT(CTS2), /* CTS (line 2) */ + BIT(DSR2), /* DSR (line 2) */ + BIT(CD2), /* carrier detect (line 2) */ + BIT(SPDI2), /* speed mode indicate (line 2) */ + BITNCF(4), + ENDBITS + }; + +/* DZTDR - 200A000C - transmit data, write only */ + +#define TDR_CHAR 0x00FF /* xmit char */ +#define TDR_V_TBR 8 /* xmit break - NI */ + +BITFIELD dz_tdr_bits[] = { + BITFFMT(CHAR,8,%02X), /* xmit char */ + BITFFMT(TBR, 4,%02X), /* xmit break - NI */ + BITNCF(4), + ENDBITS + }; + +extern int32 tmxr_poll; /* calibrated delay */ + +uint16 dz_csr = 0; /* csr */ +uint16 dz_rbuf = 0; /* rcv buffer */ +uint16 dz_lpr = 0; /* line param */ +uint16 dz_tcr = 0; /* xmit control */ +uint16 dz_msr = 0; /* modem status */ +uint16 dz_tdr = 0; /* xmit data */ +uint16 dz_silo[DZ_SILO_ALM] = { 0 }; /* silo */ +uint16 dz_scnt = 0; /* silo used */ +uint8 dz_sae = 0; /* silo alarm enabled */ +int32 dz_mctl = 0; /* modem ctrl enabled */ +int32 dz_auto = 0; /* autodiscon enabled */ +uint32 dz_func[DZ_LINES] = { DZ_TMXR }; /* line function */ +uint32 dz_char[DZ_LINES] = { 0 }; /* character buffer */ +int32 dz_lnorder[DZ_LINES] = { 0 }; /* line order */ +TMLN *dz_ldsc = NULL; /* line descriptors */ +TMXR dz_desc = { DZ_LINES, 0, 0, NULL, dz_lnorder }; /* mux descriptor */ + +/* debugging bitmaps */ +#define DBG_REG 0x0001 /* trace read/write registers */ +#define DBG_INT 0x0002 /* display interrupt activities */ +#define DBG_XMT TMXR_DBG_XMT /* display Transmitted Data */ +#define DBG_RCV TMXR_DBG_RCV /* display Received Data */ +#define DBG_RET TMXR_DBG_RET /* display Read Data */ +#define DBG_MDM TMXR_DBG_MDM /* display Modem Signals */ +#define DBG_CON TMXR_DBG_CON /* display connection activities */ +#define DBG_TRC TMXR_DBG_TRC /* display trace routine calls */ +#define DBG_ASY TMXR_DBG_ASY /* display Asynchronous Activities */ + +DEBTAB dz_debug[] = { + { "REG", DBG_REG, "read/write registers" }, + { "INT", DBG_INT, "interrupt activities" }, + { "XMT", DBG_XMT, "Transmitted Data" }, + { "RCV", DBG_RCV, "Received Data" }, + { "RET", DBG_RET, "Read Data" }, + { "MDM", DBG_MDM, "Modem Signals" }, + { "CON", DBG_CON, "connection activities" }, + { "TRC", DBG_TRC, "trace routine calls" }, + { "ASY", DBG_ASY, "Asynchronous Activities" }, + { 0 } + }; + +t_stat dz_svc (UNIT *uptr); +t_stat dz_xmt_svc (UNIT *uptr); +t_stat dz_reset (DEVICE *dptr); +t_stat dz_attach (UNIT *uptr, CONST char *cptr); +t_stat dz_detach (UNIT *uptr); +t_stat dz_clear (t_bool flag); +uint16 dz_getc (void); +void dz_putc (int32 line, uint16 data); +void dz_update_rcvi (void); +void dz_update_xmti (void); +t_stat dz_set_log (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat dz_set_nolog (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +t_stat dz_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *dz_description (DEVICE *dptr); + +/* DZ data structures + + dz_dev DZ device descriptor + dz_unit DZ unit list + dz_reg DZ register list +*/ + +UNIT dz_unit[2] = { + { UDATA (&dz_svc, UNIT_IDLE|UNIT_ATTABLE|TT_MODE_8B, 0) }, + { UDATA (&dz_xmt_svc, UNIT_DIS, 0), SERIAL_OUT_WAIT } }; + +REG dz_reg[] = { + { HRDATADF (CSR, dz_csr, 16, "control/status register", dz_csr_bits) }, + { HRDATADF (RBUF, dz_rbuf, 16, "receive buffer", dz_rbuf_bits) }, + { HRDATADF (LPR, dz_lpr, 16, "line parameter register", dz_lpr_bits) }, + { HRDATADF (TCR, dz_tcr, 16, "transmission control register", dz_tcr_bits) }, + { HRDATADF (MSR, dz_msr, 16, "modem status register", dz_msr_bits) }, + { HRDATADF (TDR, dz_tdr, 16, "transmit data register", dz_tdr_bits) }, + { HRDATAD (SAENB, dz_sae, 1, "silo alarm enabled") }, + { DRDATAD (TIME, dz_unit[1].wait, 24, "output character delay"), PV_LEFT }, + { FLDATAD (MDMCTL, dz_mctl, 0, "modem control enabled") }, + { FLDATAD (AUTODS, dz_auto, 0, "autodisconnect enabled") }, + { FLDATAD (TXINT, int_req[IPL_DZTX], INT_V_DZTX, "transmit interrupt pending flag") }, + { FLDATAD (RXINT, int_req[IPL_DZRX], INT_V_DZRX, "receive interrupt pending flag") }, + { NULL } + }; + +MTAB dz_mod[] = { + { TT_MODE, TT_MODE_7B, "7b", "7B", NULL, NULL, NULL, "7 bit mode" }, + { TT_MODE, TT_MODE_8B, "8b", "8B", NULL, NULL, NULL, "8 bit mode" }, + { TT_MODE, TT_MODE_7P, "7p", "7P", NULL, NULL, NULL, "7 bit mode - non printing suppressed" }, + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 1, NULL, "DISCONNECT", + &tmxr_dscln, NULL, &dz_desc, "Disconnect a specific line" }, + { UNIT_ATT, UNIT_ATT, "summary", NULL, + NULL, &tmxr_show_summ, (void *) &dz_desc, "Display a summary of line states" }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "CONNECTIONS", NULL, + NULL, &tmxr_show_cstat, (void *) &dz_desc, "Display current connections" }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "STATISTICS", NULL, + NULL, &tmxr_show_cstat, (void *) &dz_desc, "Display multiplexer statistics" }, + { MTAB_XTD | MTAB_VDV, 0, "LINES", NULL, + NULL, &tmxr_show_lines, (void *) &dz_desc }, + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "LINES", NULL, + NULL, &tmxr_show_lines, (void *) &dz_desc, "Display number of lines" }, + { MTAB_XTD|MTAB_VDV|MTAB_NC, 0, NULL, "LOG=n=file", + &dz_set_log, NULL, &dz_desc }, + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, NULL, "NOLOG=n", + &dz_set_nolog, NULL, &dz_desc, "Disable logging on designated line" }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "LOG", NULL, + NULL, &dz_show_log, &dz_desc, "Display logging for all lines" }, + { 0 } + }; + +DEVICE dz_dev = { + "DZ", dz_unit, dz_reg, dz_mod, + 2, DEV_RDX, 8, 1, DEV_RDX, 8, + &tmxr_ex, &tmxr_dep, &dz_reset, + NULL, &dz_attach, &dz_detach, + NULL, DEV_DISABLE | DEV_DEBUG | DEV_MUX, + 0, dz_debug, NULL, NULL, + &dz_help, &dz_help_attach, /* help and attach_help routines */ + (void *)&dz_desc, /* help context variable */ + &dz_description /* description routine */ + }; + +/* Register names for Debug tracing */ +static const char *dz_rd_regs[] = + {"CSR ", "RBUF", "TCR ", "MSR " }; +static const char *dz_wr_regs[] = + {"CSR ", "LPR ", "TCR ", "TDR "}; + +/* IO dispatch routines */ + +int32 dz_rd (int32 pa) +{ +int32 data = 0; + +switch ((pa >> 2) & 03) { /* case on PA<2:1> */ + + case 00: /* CSR */ + data = dz_csr = dz_csr & ~CSR_MBZ; + break; + + case 01: /* RBUF */ + dz_csr = dz_csr & ~CSR_SA; /* clr silo alarm */ + if (dz_csr & CSR_MSE) { /* scanner on? */ + dz_rbuf = dz_getc (); /* get top of silo */ + if (!dz_rbuf) /* empty? re-enable */ + dz_sae = 1; + tmxr_poll_rx (&dz_desc); /* poll input */ + dz_update_rcvi (); /* update rx intr */ + if (dz_rbuf) { + /* Reschedule the next poll preceisely so that the + the programmed input speed is observed. */ + sim_clock_coschedule_abs (dz_unit, tmxr_poll); + } + } + else { + dz_rbuf = 0; /* no data */ + dz_update_rcvi (); /* no rx intr */ + } + data = dz_rbuf; + + break; + + case 02: /* TCR */ + data = dz_tcr = dz_tcr & ~TCR_MBZ; + break; + + case 03: /* MSR */ + if (dz_mctl) { + int32 modem_bits; + TMLN *lp; + + lp = &dz_ldsc[2]; /* get line desc */ + tmxr_set_get_modem_bits (lp, 0, 0, &modem_bits); + + dz_msr &= ~(MSR_V_RI2 | MSR_V_CD2); + dz_msr |= ((modem_bits&TMXR_MDM_RNG) ? MSR_V_RI2 : 0) | + ((modem_bits&TMXR_MDM_DCD) ? MSR_V_CD2 : 0); + } + data = dz_msr; + break; + } + +sim_debug(DBG_REG, &dz_dev, "dz_rd(PA=0x%08X [%s], data=0x%X)\n", pa, dz_rd_regs[(pa >> 2) & 03], data); + +SET_IRQL; +return data; +} + +void dz_wr (int32 pa, int32 data, int32 access) +{ +int32 line; +char lineconfig[16]; +TMLN *lp; + +sim_debug(DBG_REG, &dz_dev, "dz_wr(PA=0x%08X [%s], access=%d, data=0x%X)\n", pa, dz_wr_regs[(pa >> 2) & 03], access, data); + +switch ((pa >> 2) & 03) { /* case on PA<2:1> */ + + case 00: /* CSR */ + if (access == L_BYTE) data = (pa & 1)? /* byte? merge */ + (dz_csr & BMASK) | (data << 8): + (dz_csr & ~BMASK) | data; + if (data & CSR_CLR) /* clr? reset */ + dz_clear (FALSE); + if (data & CSR_MSE) /* MSE? start poll */ + sim_clock_coschedule (&dz_unit[0], tmxr_poll); + else + dz_csr &= ~(CSR_SA | CSR_RDONE | CSR_TRDY); + dz_csr = (dz_csr & ~CSR_RW) | (data & CSR_RW); + break; + + case 01: /* LPR */ + dz_lpr = data; + line = LPR_GETLN (data); /* get line num */ + lp = &dz_ldsc[line]; /* get line desc */ + if (dz_lpr & LPR_RCVE) /* rcv enb? on */ + lp->rcve = 1; + else + lp->rcve = 0; /* else line off */ + sprintf(lineconfig, "%s-%s%s%s", LPR_GETSPD(data), LPR_GETCHARSIZE(data), LPR_GETPARITY(data), LPR_GETSTOPBITS(data)); + if (!lp->serconfig || (0 != strcmp(lp->serconfig, lineconfig))) /* config changed? */ + tmxr_set_config_line (lp, lineconfig); /* set it */ + tmxr_poll_rx (&dz_desc); /* poll input */ + dz_update_rcvi (); /* update rx intr */ + break; + + case 02: /* TCR */ + if (access == L_BYTE) data = (pa & 1)? /* byte? merge */ + (dz_tcr & BMASK) | (data << 8): + (dz_tcr & ~BMASK) | data; + if (dz_mctl) { /* modem ctl? */ + int32 changed = data ^ dz_tcr; + + for (line = 0; line < DZ_LINES; line++) { + if (0 == (changed & (1 << (TCR_V_DTR2 + line)))) + continue; /* line unchanged skip */ + lp = &dz_ldsc[line]; /* get line desc */ + if (data & (1 << (TCR_V_DTR2 + line))) + tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL); + else + if (dz_auto) + tmxr_set_get_modem_bits (lp, 0, TMXR_MDM_DTR|TMXR_MDM_RTS, NULL); + } + } + dz_tcr = data; + tmxr_poll_tx (&dz_desc); /* poll output */ + dz_update_xmti (); /* update int */ + break; + + case 03: /* TDR */ + if (pa & 1) { /* odd byte? */ + dz_tdr = (dz_tdr & BMASK) | (data << 8); /* just save */ + break; + } + dz_tdr = data; + if (dz_csr & CSR_MSE) { /* enabled? */ + line = CSR_GETTL (dz_csr); + if (dz_csr & CSR_MAINT) { /* test mode? */ + dz_char[line] = (dz_tdr & BMASK) | RBUF_VALID;/* loop data back */ + dz_char[line] |= (line << RBUF_V_RLINE); + if (dz_tdr & (1u << (TDR_V_TBR + line))) + dz_char[line] = dz_char[line] | RBUF_FRME; + dz_csr &= ~CSR_TRDY; + sim_debug(DBG_REG, &dz_dev, "maint char for line %d : %X\n", line, dz_char[line]); + break; + } + dz_putc (line, dz_tdr); + sim_activate (&dz_unit[1], dz_unit[1].wait); + } + break; + } + +SET_IRQL; +} + +/* Unit input service routine + + The DZ polls to see if asynchronous activity has occurred and now + needs to be processed. The polling interval is controlled by the clock + simulator, so for most environments, it is calibrated to real time. + Typical polling intervals are 50-60 times per second. + + The simulator assumes that software enables all of the multiplexors, + or none of them. +*/ + +t_stat dz_svc (UNIT *uptr) +{ +int32 newln, muxln; + +if (dz_csr & CSR_MSE) { /* enabled? */ + newln = tmxr_poll_conn (&dz_desc); /* poll connect */ + if ((newln >= 0) && dz_mctl) { /* got a live one? */ + muxln = newln % DZ_LINES; /* get line in mux */ + if (muxln == 2) { + if (dz_tcr & (1 << TCR_V_DTR2)) /* DTR set? */ + dz_msr |= (1 << MSR_V_CD2); /* set cdet */ + else dz_msr |= (1 << MSR_V_RI2); /* set ring */ + } + } + tmxr_poll_rx (&dz_desc); /* poll input */ + dz_update_rcvi (); /* upd rcv intr */ + tmxr_poll_tx (&dz_desc); /* poll output */ + dz_update_xmti (); /* upd xmt intr */ + if ((dz_csr & CSR_RDONE) == 0) + sim_clock_coschedule (uptr, tmxr_poll); /* reactivate */ + } +return SCPE_OK; +} + +t_stat dz_xmt_svc (UNIT *uptr) +{ +tmxr_poll_tx (&dz_desc); /* poll output */ +dz_update_xmti (); /* update int */ +return SCPE_OK; +} + +/* Put a character to the specified line */ + +void dz_putc (int32 line, uint16 data) +{ +int32 c; +TMLN *lp; + +switch (dz_func[line]) { + case DZ_TMXR: + lp = &dz_ldsc[line]; /* get line desc */ + c = sim_tt_outcvt (data, TT_GET_MODE (dz_unit[0].flags)); + if (c >= 0) /* store char */ + tmxr_putc_ln (lp, c); + break; + + case DZ_CONSOLE: + c = sim_tt_outcvt (data, TT_GET_MODE (dz_unit[0].flags)); + if (c >= 0) + sim_putchar_s (c); /* send to console */ + break; + + case DZ_KEYBOARD: + lk_wr ((uint8)data); /* send to keyboard */ + break; + + case DZ_MOUSE: + vs_wr ((uint8)data); /* send to mouse */ + break; + } +return; +} + +/* Get first available character for mux, if any */ + +uint16 dz_getc (void) +{ +uint16 ret; +uint32 i; + +if (!dz_scnt) + return 0; +ret = dz_silo[0]; /* first fifo element */ +for (i = 1; i < dz_scnt; i++) /* slide down remaining entries */ + dz_silo[i-1] = dz_silo[i]; +--dz_scnt; /* adjust count */ +sim_debug (DBG_RCV, &dz_dev, "DZ Line %d - Received: 0x%X - '%c'\n", i, ret, sim_isprint(ret&0xFF) ? ret & 0xFF : '.'); +return ret; +} + +/* Update receive interrupts */ + +void dz_update_rcvi (void) +{ +int32 line, c; +TMLN *lp; + +if (dz_csr & CSR_MSE) { /* enabled? */ + for (line = 0; line < DZ_LINES; line++) { /* poll lines */ + if (dz_scnt >= DZ_SILO_ALM) + break; + c = 0; + if ((dz_func[line] == DZ_TMXR) && ((dz_csr & CSR_MAINT) == 0)) { + lp = &dz_ldsc[line]; /* get line desc */ + c = tmxr_getc_ln (lp); /* test for input */ + if (c & SCPE_BREAK) /* break? frame err */ + c = RBUF_FRME; + if (line == 2) { + if (dz_mctl && !lp->conn) /* if disconn */ + dz_msr &= ~(1 << MSR_V_CD2); /* reset car det */ + } + } + else { + switch (dz_func[line]) { + case DZ_KEYBOARD: + if (lk_rd ((uint8*)&c) == SCPE_OK) /* test for input */ + c |= RBUF_VALID; + break; + + case DZ_MOUSE: + if (vs_rd ((uint8*)&c) == SCPE_OK) /* test for input */ + c |= RBUF_VALID; + break; + + case DZ_CONSOLE: + if ((c = sim_poll_kbd ()) < SCPE_KFLAG) { + if (SCPE_BARE_STATUS(c) == SCPE_OK) /* no char */ + continue; + else + ABORT (c); /* error */ + } + if (c & SCPE_BREAK) { /* break? frame err */ + hlt_pin = 1; + c = RBUF_FRME; + } + else + c = sim_tt_inpcvt (c, TT_GET_MODE (dz_unit[0].flags)); + break; + + default: /* no action for other lines */ + continue; + } + } + if (c) { /* save in silo */ + c = (c & (RBUF_CHAR | RBUF_FRME)) | RBUF_VALID;; + RBUF_PUTRL (c, line); /* add line # */ + dz_silo[dz_scnt] = (uint16)c; + ++dz_scnt; + } + + } + } +if (dz_scnt && (dz_csr & CSR_MSE)) { /* input & enabled? */ + dz_csr |= CSR_RDONE; /* set done */ + if (dz_sae && (dz_scnt >= DZ_SILO_ALM)) { /* alm enb & cnt hi? */ + dz_csr |= CSR_SA; /* set status */ + dz_sae = 0; /* disable alarm */ + } + } +else + dz_csr &= ~CSR_RDONE; /* no, clear done */ +if (((dz_csr & CSR_SAE)? + (dz_csr & CSR_SA): (dz_csr & CSR_RDONE))) + SET_INT (DZRX); /* alm/done? */ +else + CLR_INT (DZRX); /* no, clear int */ +return; +} + +/* Update transmit interrupts */ + +void dz_update_xmti (void) +{ +int32 linemask, i, line; + +linemask = dz_tcr & DZ_LMASK; /* enabled lines */ +dz_csr &= ~CSR_TRDY; /* assume not rdy */ +line = CSR_GETTL (dz_csr); /* start at current */ +for (i = 0; i < DZ_LINES; i++) { /* loop thru lines */ + line = (line + 1) & DZ_LNOMASK; /* next line */ + if ((linemask & (1 << line)) && dz_ldsc[line].xmte) { + CSR_PUTTL (dz_csr, line); /* put ln in csr */ + dz_csr |= CSR_TRDY; /* set xmt rdy */ + break; + } + } +if (dz_csr & CSR_TRDY) /* ready? */ + SET_INT (DZTX); +else + CLR_INT (DZTX); /* no int req */ +return; +} + +/* Device reset */ + +t_stat dz_clear (t_bool flag) +{ +int32 i; + +dz_csr = 0; /* clear CSR */ +dz_rbuf = 0; /* silo empty */ +dz_lpr = 0; /* no params */ +if (flag) /* INIT? clr all */ + dz_tcr = 0; +else dz_tcr &= ~0377; /* else save dtr */ +dz_tdr = 0; +dz_sae = 1; /* alarm on */ +dz_scnt = 0; +CLR_INT (DZRX); /* clear int */ +CLR_INT (DZTX); +for (i = 0; i < DZ_LINES; i++) { /* loop thru lines */ + if (!dz_ldsc[i].conn) /* set xmt enb */ + dz_ldsc[i].xmte = 1; + dz_ldsc[i].rcve = 0; /* clr rcv enb */ + } +return SCPE_OK; +} + +t_stat dz_reset (DEVICE *dptr) +{ +int32 i; + +if (sys_model) { /* VAXstation? */ + dz_func[0] = DZ_KEYBOARD; + dz_func[1] = DZ_MOUSE; + dz_func[2] = DZ_TMXR; + dz_func[3] = DZ_TMXR; + dz_lnorder[0] = 2; + dz_lnorder[1] = 3; + dz_lnorder[2] = 2; /* only 2 connections */ + dz_lnorder[3] = 3; + } +else if (DZ_L3C) { /* no, MicroVAX */ + dz_func[0] = DZ_TMXR; + dz_func[1] = DZ_TMXR; + dz_func[2] = DZ_TMXR; + dz_func[3] = DZ_CONSOLE; + dz_lnorder[0] = 0; + dz_lnorder[1] = 1; + dz_lnorder[2] = 2; + dz_lnorder[3] = 0; /* only 3 connections */ + } +else { /* Infoserver */ + dz_func[0] = DZ_CONSOLE; + dz_func[1] = DZ_TMXR; + dz_func[2] = DZ_TMXR; + dz_func[3] = DZ_TMXR; + dz_lnorder[0] = 1; + dz_lnorder[1] = 2; + dz_lnorder[2] = 3; + dz_lnorder[3] = 1; /* only 3 connections */ + } +if (dz_ldsc != NULL) { + for (i = 0; i < DZ_LINES; i++) { + if (dz_func[i] != DZ_TMXR) { + if (dz_ldsc[i].conn) { + tmxr_linemsg (&dz_ldsc[i], "\r\nOperator disconnected line\r\n"); + tmxr_send_buffered_data (&dz_ldsc[i]); + } + tmxr_detach_ln (&dz_ldsc[i]); /* completely reset line */ + } + } + } +else + dz_desc.ldsc = dz_ldsc = (TMLN *)calloc (DZ_LINES, sizeof(*dz_ldsc)); +dz_clear (TRUE); /* init mux */ +CLR_INT (DZRX); +CLR_INT (DZTX); +sim_cancel (&dz_unit[0]); /* stop poll */ +for (i = 0; i < DZ_LINES; i++) + dz_char[i] = 0; +return SCPE_OK; +} + +/* Attach */ + +t_stat dz_attach (UNIT *uptr, CONST char *cptr) +{ +int32 muxln; +t_stat r; + +if (sim_switches & SWMASK ('M')) /* modem control? */ + tmxr_set_modem_control_passthru (&dz_desc); +r = tmxr_attach (&dz_desc, uptr, cptr); /* attach mux */ +if (r != SCPE_OK) { /* error? */ + tmxr_clear_modem_control_passthru (&dz_desc); + return r; + } +if (sim_switches & SWMASK ('M')) { /* modem control? */ + dz_mctl = 1; + sim_printf ("Modem control activated\n"); + if (sim_switches & SWMASK ('A')) { /* autodisconnect? */ + dz_auto = 1; + sim_printf ("Auto disconnect activated\n"); + } + } + +if (!dz_mctl || (0 == (dz_csr & CSR_MSE))) /* enabled? */ + return SCPE_OK; +for (muxln = 0; muxln < DZ_LINES; muxln++) { + if (dz_tcr & (1 << (muxln + TCR_V_DTR2))) { + TMLN *lp = &dz_ldsc[muxln]; + + tmxr_set_get_modem_bits (lp, TMXR_MDM_DTR|TMXR_MDM_RTS, 0, NULL); + } + } +return SCPE_OK; +} + +/* Detach */ + +t_stat dz_detach (UNIT *uptr) +{ +dz_mctl = dz_auto = 0; /* modem ctl off */ +return tmxr_detach (&dz_desc, uptr); +} + +/* SET LOG processor */ + +t_stat dz_set_log (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +t_stat r; +char gbuf[CBUFSIZE]; +int32 ln; + +if (cptr == NULL) + return SCPE_ARG; +cptr = get_glyph (cptr, gbuf, '='); +if ((cptr == NULL) || (*cptr == 0) || (gbuf[0] == 0)) + return SCPE_ARG; +ln = (int32) get_uint (gbuf, 10, dz_desc.lines, &r); +if ((r != SCPE_OK) || (ln >= dz_desc.lines)) + return SCPE_ARG; +return tmxr_set_log (NULL, ln, cptr, desc); +} + +/* SET NOLOG processor */ + +t_stat dz_set_nolog (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +t_stat r; +int32 ln; + +if (cptr == NULL) + return SCPE_ARG; +ln = (int32) get_uint (cptr, 10, dz_desc.lines, &r); +if ((r != SCPE_OK) || (ln >= dz_desc.lines)) + return SCPE_ARG; +return tmxr_set_nolog (NULL, ln, NULL, desc); +} + +/* SHOW LOG processor */ + +t_stat dz_show_log (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ +int32 i; + +for (i = 0; i < dz_desc.lines; i++) { + fprintf (st, "line %d: ", i); + tmxr_show_log (st, NULL, i, desc); + fprintf (st, "\n"); + } +return SCPE_OK; +} + +t_stat dz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "DZ Terminal Multiplexer (DZ)\n\n"); +fprintf (st, "The DZ is a %d line terminal multiplexor.\n", DZ_LINES); +fprintf (st, "For the MicroVAX, one of these lines is dedicated to the console and\n"); +fprintf (st, "cannot be used with the Telnet multiplexer. For the VAXstation, two\n"); +fprintf (st, "ports are dedicated to the keyboard and mouse.\n"); +fprintf (st, "The DZ supports three character processing modes, 7P, 7B, and 8B:\n\n"); +fprintf (st, " mode input characters output characters\n"); +fprintf (st, " =============================================\n"); +fprintf (st, " 7P high-order bit cleared high-order bit cleared,\n"); +fprintf (st, " non-printing characters suppressed\n"); +fprintf (st, " 7B high-order bit cleared high-order bit cleared\n"); +fprintf (st, " 8B no changes no changes\n\n"); +fprintf (st, "The default is 8B.\n\n"); +fprintf (st, "The DZ supports logging on a per-line basis. The command\n\n"); +fprintf (st, " sim> SET %s LOG=n=filename\n\n", dptr->name); +fprintf (st, "enables logging for the specified line(n) to the indicated file. The command\n\n"); +fprintf (st, " sim> SET %s NOLOG=line\n\n", dptr->name); +fprintf (st, "disables logging for the specified line and closes any open log file. Finally,\n"); +fprintf (st, "the command:\n\n"); +fprintf (st, " sim> SHOW %s LOG\n\n", dptr->name); +fprintf (st, "displays logging information for all %s lines.\n\n", dptr->name); +fprintf (st, "Once the DZ is attached and the simulator is running, the DZ will listen for\n"); +fprintf (st, "connections on the specified port. It assumes that the incoming connections\n"); +fprintf (st, "are Telnet connections. The connection remains open until disconnected by the\n"); +fprintf (st, "simulated program, the Telnet client, a SET %s DISCONNECT command, or a\n", dptr->name); +fprintf (st, "DETACH %s command.\n\n", dptr->name); +fprintf (st, "Other special %s commands:\n\n", dptr->name); +fprintf (st, " sim> SHOW %s CONNECTIONS show current connections\n", dptr->name); +fprintf (st, " sim> SHOW %s STATISTICS show statistics for active connections\n", dptr->name); +fprintf (st, " sim> SET %s DISCONNECT=linenumber disconnects the specified line.\n\n\n", dptr->name); +fprintf (st, "All open connections are lost when the simulator shuts down or the %s is\n", dptr->name); +fprintf (st, "detached.\n"); +return SCPE_OK; +} + +t_stat dz_help_attach (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +tmxr_attach_help (st, dptr, uptr, flag, cptr); +fprintf (st, "The terminal lines perform input and output through Telnet sessions connected\n"); +fprintf (st, "to a user-specified port. The ATTACH command specifies the port to be used:\n\n"); +fprintf (st, " sim> ATTACH {-am} %s {interface:}port set up listening port\n\n", dptr->name); +fprintf (st, "where port is a decimal number between 1 and 65535 that is not being used for\n"); +fprintf (st, "other TCP/IP activities. The optional switch -m turns on the DZ's modem\n"); +fprintf (st, "controls; the optional switch -a turns on active disconnects (disconnect\n"); +fprintf (st, "session if computer clears Data Terminal Ready). Without modem control, the\n"); +fprintf (st, "DZ behaves as though terminals were directly connected; disconnecting the\n"); +fprintf (st, "Telnet session does not cause any operating system-visible change in line\n"); +fprintf (st, "status.\n\n"); +return SCPE_OK; +} + +const char *dz_description (DEVICE *dptr) +{ +return "DZ 4-line terminal multiplexer"; +} diff --git a/VAX/vax4xx_rd.c b/VAX/vax4xx_rd.c new file mode 100644 index 00000000..1c885821 --- /dev/null +++ b/VAX/vax4xx_rd.c @@ -0,0 +1,936 @@ +/* vax4xx_rd.c: HDC9224 hard disk simulator + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + rd HDC9224 Hard Disk Controller +*/ + +#include "vax_defs.h" +#include "sim_disk.h" + +#if defined(VAX_420) +#include "vax_ka420_rdrz_bin.h" +#else +#define BOOT_CODE_ARRAY NULL +#define BOOT_CODE_SIZE 0 +#endif + +#define RD_NUMDR 3 +#define RD_RMV(u) ((drv_tab[GET_DTYPE (u->flags)].flgs & RDDF_RMV)? \ + UF_RMV: 0) +#define RDDF_RMV 01 /* removable */ +#define RD_NUMBY 512 /* bytes/sector */ + +#define RD_MAXFR (1 << 14) /* max transfer */ + +/* HDC commands */ + +#define CMD_RESET 1 +#define CMD_SETREG 2 +#define CMD_DESELECT 3 +#define CMD_DRVSEL 4 +#define CMD_RESTORE 5 +#define CMD_STEP 6 +#define CMD_POLL 7 +#define CMD_RDID 8 +#define CMD_FORMAT 9 +#define CMD_RDTRK 10 +#define CMD_RDPHY 11 +#define CMD_RDLOG 12 +#define CMD_WRPHY 13 +#define CMD_WRLOG 14 +#define CMD_UNKNOWN 15 + +/* drive status */ + +#define DST_WRF 0x01 /* write fault */ +#define DST_RDY 0x02 /* ready */ +#define DST_WPT 0x04 /* write protect */ +#define DST_DS3 0x08 /* drive status 3 */ +#define DST_TRK0 0x10 /* track 0 */ +#define DST_SCOM 0x20 /* seek complete */ +#define DST_IDX 0x40 /* index */ +#define DST_SELA 0x80 /* sel ack */ + +/* chip status */ + +#define CST_SDRV 0x03 /* selected drive */ +#define CST_CMPE 0x04 /* compare error */ +#define CST_SYNCE 0x08 /* sync error */ +#define CST_DELD 0x10 /* deleted data mark */ +#define CST_ECCE 0x20 /* ECC error */ +#define CST_ECCC 0x40 /* ECC correction attepted */ +#define CST_RETR 0x80 /* retry required */ + +/* interrupt status port */ + +#define STAT_V_BAD 0 /* bad sect */ +#define STAT_V_OVR 1 /* overrun */ +#define STAT_V_RDYC 2 /* ready chng */ +#define STAT_V_TRMC 3 /* term code */ +#define STAT_M_TRMC 0x3 +#define STAT_V_DONE 5 /* done */ +#define STAT_V_DMARQ 6 /* dmareq */ +#define STAT_V_INT 7 /* intpend */ +#define STAT_BAD (1u << STAT_V_BAD) +#define STAT_OVR (1u << STAT_V_OVR) +#define STAT_RDYC (1u << STAT_V_RDYC) +#define STAT_TRMC (STAT_M_TRMC << STAT_V_TRMC) +#define STAT_DONE (1u << STAT_V_DONE) +#define STAT_DMARQ (1u << STAT_V_DMARQ) +#define STAT_INT (1u << STAT_V_INT) + +/* termination codes */ + +#define TRM_OK 0 /* Success completion */ +#define TRM_ERR_RD 1 /* Error in READ ID sequence */ +#define TRM_ERR_VER 2 /* Error in VERIFY sequence */ +#define TRM_ERR_TRAN 3 /* Error in DATA TRANSFER sequence */ + +#define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE) + +#define DBG_REG 0x0001 /* registers */ +#define DBG_CMD 0x0002 /* commands */ +#define DBG_RD 0x0004 /* disk reads */ +#define DBG_WR 0x0008 /* disk writes */ +#define DBG_REQ 0x0010 /* display transfer requests */ +#define DBG_DSK 0x0020 /* display sim_disk activities */ +#define DBG_DAT 0x0040 /* display transfer data */ + +#define CYL u3 /* current cylinder */ +#define HEAD u4 /* current head */ +#define STAT u5 /* drive status */ +#define CMD u6 /* current command */ + +#define CUR_DRV (rd_cstat & CST_SDRV) /* currently selected drive */ + +#define GET_SPT(u) (drv_tab[GET_DTYPE (u->flags)].sect) +#define GET_SURF(u) (drv_tab[GET_DTYPE (u->flags)].surf) +#define GET_DA(u,c,h,s) ((c * (GET_SPT(u) * GET_SURF(u))) \ + + (h * GET_SPT(u)) + s) + +/* The HDC9224 supports multiple disk drive types: + + type sec surf cyl tpg gpc RCT LBNs + + RX33 15 2 80 2 1 - 2400 + RD31 17 4 615 4 1 3*8 41584 + RD32 17 6 820 6 1 ? 83236 + RD53 17 7 1024 7 1 5*8 138712 + RD54 17 15 1225 15 1 7*8 311256 +*/ + +#define RX33_DTYPE 0 +#define RX33_SECT 15 +#define RX33_SURF 2 +#define RX33_CYL 80 +#define RX33_TPG 2 +#define RX33_XBN 0 +#define RX33_DBN 0 +#define RX33_LBN 2400 +#define RX33_RCTS 0 +#define RX33_RCTC 0 +#define RX33_RBN 0 +#define RX33_CYLP 0 +#define RX33_CYLR 0 +#define RX33_CCS 0 +#define RX33_MED 0x25658021 +#define RX33_FLGS RDDF_RMV + +#define RD31_DTYPE 1 +#define RD31_SECT 17 +#define RD31_SURF 4 +#define RD31_CYL 616 /* last unused */ +#define RD31_TPG RD31_SURF +#define RD31_XBN 54 +#define RD31_DBN 14 +#define RD31_LBN 41584 +#define RD31_RCTS 3 +#define RD31_RCTC 8 +#define RD31_RBN 100 +#define RD31_CYLP 256 +#define RD31_CYLR 615 +#define RD31_CCS 9 +#define RD31_MED 0x2564401F +#define RD31_FLGS 0 + +#define RD32_DTYPE 2 +#define RD32_SECT 17 +#define RD32_SURF 6 +#define RD32_CYL 821 /* last unused */ +#define RD32_TPG RD32_SURF +#define RD32_XBN 54 +#define RD32_DBN 48 +#define RD32_LBN 83236 +#define RD32_RCTS 4 +#define RD32_RCTC 8 +#define RD32_RBN 200 +#define RD32_CYLP 821 +#define RD32_CYLR 821 +#define RD32_CCS 14 +#define RD32_MED 0x25644020 +#define RD32_FLGS 0 + +#define RD53_DTYPE 3 +#define RD53_SECT 17 +#define RD53_SURF 8 +#define RD53_CYL 1024 /* last unused */ +#define RD53_TPG RD53_SURF +#define RD53_XBN 54 +#define RD53_DBN 82 +#define RD53_LBN 138712 +#define RD53_RCTS 5 +#define RD53_RCTC 8 +#define RD53_RBN 280 +#define RD53_CYLP 1024 +#define RD53_CYLR 1024 +#define RD53_CCS 13 +#define RD53_MED 0x25644035 +#define RD53_FLGS 0 + +#define RD54_DTYPE 4 +#define RD54_SECT 17 +#define RD54_SURF 15 +#define RD54_CYL 1225 /* last unused */ +#define RD54_TPG RD54_SURF +#define RD54_XBN 54 +#define RD54_DBN 201 +#define RD54_LBN 311256 +#define RD54_RCTS 7 +#define RD54_RCTC 8 +#define RD54_RBN 609 +#define RD54_CYLP 1225 +#define RD54_CYLR 1225 +#define RD54_CCS 14 +#define RD54_MED 0x25644036 +#define RD54_FLGS 0 + +#define UNIT_V_WLK (DKUF_V_UF + 0) /* hwre write lock */ +#define UNIT_V_DTYPE (DKUF_V_UF + 1) /* drive type */ +#define UNIT_M_DTYPE 0xF +#define UNIT_WLK (1u << UNIT_V_WLK) +#define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protected */ +#define UNIT_DTYPE (UNIT_M_DTYPE << UNIT_V_DTYPE) + +struct drvtyp { + int32 sect; /* sectors */ + int32 surf; /* surfaces */ + int32 cyl; /* cylinders */ + int32 tpg; /* trk/grp */ + int32 xbn; /* XBN size */ + int32 dbn; /* DBN size */ + uint32 lbn; /* LBN size */ + int32 rcts; /* RCT size */ + int32 rctc; /* RCT copies */ + int32 rbn; /* RBNs */ + int32 cylp; /* first cyl for write precomp */ + int32 cylr; /* first cyl for reduced write current */ + int32 ccs; /* cyl/cyl skew */ + int32 med; /* MSCP media */ + int32 flgs; /* flags */ + const char *name; /* name */ + }; + +#define RD_DRV(d) \ + d##_SECT, d##_SURF, d##_CYL, d##_TPG, \ + d##_XBN, d##_DBN, d##_LBN, d##_RCTS, \ + d##_RCTC, d##_RBN, d##_CYLP, d##_CYLR, \ + d##_CCS, d##_MED, d##_FLGS +#define RD_SIZE(d) (d##_LBN * RD_NUMBY) + +static struct drvtyp drv_tab[] = { + { RD_DRV (RX33), "RX33" },{ RD_DRV (RD31), "RD31" }, + { RD_DRV (RD32), "RD32" },{ RD_DRV (RD53), "RD53" }, + { RD_DRV (RD54), "RD54" }, + { 0 } + }; + +int32 rd_cwait = 20; /* command wait time */ +int32 rd_dwait = 20; /* data trasfer wait time */ + +int32 rd_rg_p = 0; /* register pointer */ +int32 rd_stat = 0; /* interrupt status port */ + +int32 rd_dma = 0; /* DMA address */ +int32 rd_dsect = 0; /* desired sector */ +int32 rd_dhead = 0; /* desired head */ +int32 rd_dcyl = 0; /* desired cylinder */ +int32 rd_scnt = 0; /* sector count */ +int32 rd_rtcnt = 0; /* retry count */ +int32 rd_mode = 0; /* operating mode */ +int32 rd_cstat = 0; /* chip status */ +int32 rd_term = 0; /* termination conditions */ +int32 rd_data = 0; + +uint16 *rd_xb = NULL; /* xfer buffer */ + +t_stat rd_svc (UNIT *uptr); +t_stat rd_reset (DEVICE *dptr); +void rd_set_dstat (UNIT *uptr); +void rd_done (int32 term_code, t_bool setint); +void rd_cmd (int32 data); +int32 rd_decode_cmd (int32 data); +t_stat rd_set_type (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat rd_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +t_stat rd_attach (UNIT *uptr, CONST char *cptr); +t_stat rd_detach (UNIT *uptr); +t_stat rd_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *rd_description (DEVICE *dptr); + +/* RD data structures + + rd_dev RD device descriptor + rd_unit RD unit list + rd_reg RD register list + rd_mod RD modifier list +*/ + +DIB rd_dib = { + RD_ROM_INDEX, BOOT_CODE_ARRAY, BOOT_CODE_SIZE + }; + +UNIT rd_unit[] = { + { UDATA (&rd_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RD54_DTYPE << UNIT_V_DTYPE), RD_SIZE (RD54)) }, + { UDATA (&rd_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RD54_DTYPE << UNIT_V_DTYPE), RD_SIZE (RD54)) }, + { UDATA (&rd_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RX33_DTYPE << UNIT_V_DTYPE), RD_SIZE (RX33)) } + }; + +REG rd_reg[] = { + { DRDATA (RPTR, rd_rg_p, 4), REG_HRO }, + { HRDATAD (STAT, rd_stat, 8, "Interrupt Status") }, + { HRDATAD (DMA, rd_dma, 24, "DMA Address") }, + { DRDATAD (DSECT, rd_dsect, 8, "Desired Sector") }, + { DRDATAD (DHEAD, rd_dhead, 4, "Desired Head") }, + { DRDATAD (DCYL, rd_dcyl, 11, "Desired Cylinder") }, + { URDATAD (CHEAD, rd_unit[0].HEAD, 10, 4, 0, RD_NUMDR, 0, "Current Head") }, + { URDATAD (CCYL, rd_unit[0].CYL, 10, 11, 0, RD_NUMDR, 0, "Current Cylinder") }, + { URDATAD (DSTAT, rd_unit[0].STAT, 16, 8, 0, RD_NUMDR, 0, "Drive Status") }, + { URDATAD (CMD, rd_unit[0].CMD, 10, 8, 0, RD_NUMDR, 0, "Current Command") }, + { DRDATAD (SCNT, rd_scnt, 8, "Sector Count") }, + { DRDATAD (RCNT, rd_rtcnt, 8, "Retry Count") }, + { HRDATAD (MODE, rd_mode, 8, "Operating Mode") }, + { HRDATAD (CSTAT, rd_cstat, 8, "Chip Status") }, + { HRDATAD (TCON, rd_term, 8, "Termination Conditions") }, + { DRDATAD (CWAIT, rd_cwait, 24, "Command wait time"), PV_LEFT + REG_NZ }, + { DRDATAD (DWAIT, rd_dwait, 24, "Data wait time"), PV_LEFT + REG_NZ }, + { URDATA (CAPAC, rd_unit[0].capac, 10, T_ADDR_W, 0, RD_NUMDR, REG_HRO | PV_LEFT) }, + { FLDATAD (INT, int_req[IPL_SCA], INT_V_SCA, "Interrupt pending flag") }, + { NULL } + }; + +DEBTAB rd_debug[] = { + { "REG", DBG_REG, "trace read/write registers" }, + { "CMD", DBG_CMD, "display commands" }, + { "RD", DBG_RD, "display disk reads" }, + { "WR", DBG_WR, "display disk writes" }, + { "REQ", DBG_REQ, "display transfer requests" }, + { "DISK", DBG_DSK, "display sim_disk activities" }, + { "DATA", DBG_DAT, "display transfer data" }, + { 0 } + }; + +MTAB rd_mod[] = { + { UNIT_WLK, 0, "write enabled", "WRITEENABLED", + NULL, NULL, NULL, "Write enable disk drive" }, + { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", + NULL, NULL, NULL, "Write lock disk drive" }, + { MTAB_XTD|MTAB_VUN, RX33_DTYPE, NULL, "RX33", + &rd_set_type, NULL, NULL, "Set RX33 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RD31_DTYPE, NULL, "RD31", + &rd_set_type, NULL, NULL, "Set RD31 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RD32_DTYPE, NULL, "RD32", + &rd_set_type, NULL, NULL, "Set RD32 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RD53_DTYPE, NULL, "RD53", + &rd_set_type, NULL, NULL, "Set RD53 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RD54_DTYPE, NULL, "RD54", + &rd_set_type, NULL, NULL, "Set RD54 Disk Type" }, + { MTAB_XTD|MTAB_VUN, 0, "TYPE", NULL, + NULL, &rd_show_type, NULL, "Display device type" }, + { MTAB_XTD|MTAB_VUN | MTAB_VALR, 0, "FORMAT", "FORMAT={SIMH|VHD|RAW}", + &sim_disk_set_fmt, &sim_disk_show_fmt, NULL, "Display disk format" }, + { 0 } + }; + +DEVICE rd_dev = { + "RD", rd_unit, rd_reg, rd_mod, + RD_NUMDR, DEV_RDX, 20, 1, DEV_RDX, 8, + NULL, NULL, &rd_reset, + NULL, &rd_attach, &rd_detach, + &rd_dib, DEV_DEBUG | RD_FLAGS, 0, + rd_debug, NULL, NULL, &rd_help, NULL, NULL, + &rd_description + }; + +/* RD read + + 200C0000 register data access + 200C0004 interrupt status +*/ + +int32 rd_rd (int32 pa) +{ +int32 rg = (pa >> 2) & 3; +int32 data = 0; +UNIT *uptr = &rd_unit[CUR_DRV]; + +if (rd_dev.flags & DEV_DIS) /* disabled? */ + return 0; + +switch (rg) { + + case 0: /* DKC_REG */ + switch (rd_rg_p) { + + case 0: /* UDC_DMA7 */ + data = rd_dma & BMASK; + break; + + case 1: /* UDC_DMA15 */ + data = (rd_dma >> 8) & BMASK; + break; + + case 2: /* UDC_DMA23 */ + data = (rd_dma >> 16) & BMASK; + break; + + case 3: /* UDC_DSECT */ + data = rd_dsect & BMASK; + break; + + case 4: /* UDC_CHEAD */ + data = ((uptr->CYL & 0x700) >> 4) | \ + (uptr->HEAD & 0xF); + break; + + case 5: /* UDC_CCYL */ + data = uptr->CYL & BMASK; + break; + + case 6: /* temporary store */ + data = 0; + break; + + case 7: /* temporary store */ + data = 0; + break; + + case 8: /* UDC_CSTAT */ + data = rd_cstat & BMASK; + break; + + case 9: /* UDC_DSTAT */ + data = uptr->STAT & BMASK; + break; + + case 10: /* UDC_DATA */ + data = rd_data & BMASK; + break; + } + sim_debug (DBG_REG, &rd_dev, "reg %d read, value = %X\n", rd_rg_p, data); + if (rd_rg_p < 10) + rd_rg_p++; /* Advance to next register */ + break; + + case 1: /* DKC_STAT */ + data = rd_stat & BMASK; + rd_stat = rd_stat & ~(STAT_INT | STAT_RDYC); + sim_debug (DBG_REG, &rd_dev, "int status read, value = %X\n", data); + break; + } +return data; +} + +/* RD write + + 200C0000 register data access + 200C0004 controller command +*/ + +void rd_wr (int32 pa, int32 data, int32 access) +{ +int32 rg = (pa >> 2) & 3; + +if (rd_dev.flags & DEV_DIS) /* disabled? */ + return; + +switch (rg) { + + case 0: /* DKC_REG */ + switch (rd_rg_p) { + + case 0: /* UDC_DMA7 */ + rd_dma = (rd_dma & ~BMASK) | (data & BMASK); + break; + + case 1: /* UDC_DMA15 */ + rd_dma = (rd_dma & ~(BMASK << 8)) | ((data & BMASK) << 8); + break; + + case 2: /* UDC_DMA23 */ + rd_dma = (rd_dma & ~(BMASK << 16)) | ((data & BMASK) << 16); + break; + + case 3: /* UDC_DSECT */ + rd_dsect = data & BMASK; + break; + + case 4: /* UDC_DHEAD */ + rd_dhead = data & 0xF; /* head # in data <04:00> */ + rd_dcyl = (rd_dcyl & ~(0x700)) | /* cyl <10:08> in data <06:04> */ + ((data & 0x70) << 4); + break; + + case 5: /* UDC_DCYL */ + rd_dcyl = (rd_dcyl & ~BMASK) | /* cyl <07:00> */ + (data & BMASK); + break; + + case 6: /* UDC_SCNT */ + rd_scnt = data & BMASK; + break; + + case 7: /* UDC_RTCNT */ + rd_rtcnt = data & BMASK; + break; + + case 8: /* UDC_MODE */ + rd_mode = data & BMASK; + break; + + case 9: /* UDC_TERM */ + rd_term = data & BMASK; + break; + + case 10: /* UDC_DATA */ + rd_data = data & BMASK; + break; + } + sim_debug (DBG_REG, &rd_dev, "reg %d write, value = %X\n", rd_rg_p, data); + if (rd_rg_p < 10) + rd_rg_p++; /* Advance to next register */ + break; + + case 1: /* DKC_CMD */ + rd_cmd (data); + break; + } +SET_IRQL; +} + +void rd_cmd (int32 data) +{ +int32 max_cyl; +UNIT *uptr = &rd_unit[CUR_DRV]; + +/* put command in unit */ +uptr->CMD = rd_decode_cmd (data); + +switch (uptr->CMD) { + case CMD_RESET: + rd_rg_p = 0; + rd_term = 0; + rd_dsect = 0; + rd_dhead = 0; + rd_dcyl = 0; + uptr->CYL = 0; + sim_debug (DBG_CMD, &rd_dev, "RESET\n"); + rd_done (TRM_OK, FALSE); + break; + + case CMD_SETREG: + rd_rg_p = data & 0xF; + sim_debug (DBG_CMD, &rd_dev, "SETREG, reg = %d\n", rd_rg_p); + break; + + case CMD_DESELECT: + sim_debug (DBG_CMD, &rd_dev, "DESELECT\n"); + rd_done (TRM_OK, TRUE); + break; + + case CMD_DRVSEL: + rd_cstat = (rd_cstat & ~CST_SDRV) | (data & CST_SDRV); + uptr = &rd_unit[CUR_DRV]; /* get new unit */ + if ((uptr->flags & (UNIT_DIS + UNIT_ATT)) == UNIT_ATT) { + rd_done (TRM_OK, TRUE); /* drive installed */ + uptr->HEAD = rd_dhead; + uptr->CYL = 0; + rd_set_dstat (uptr); + sim_debug (DBG_CMD, &rd_dev, "DRVSEL, drive = %d\n", CUR_DRV); + } + else { + rd_done (TRM_ERR_TRAN, TRUE); /* drive not installed */ + rd_set_dstat (uptr); + sim_debug (DBG_CMD, &rd_dev, "DRVSEL, drive = %d (not present)\n", CUR_DRV); + } + break; + + case CMD_STEP: + sim_debug (DBG_CMD, &rd_dev, "STEP\n"); + + if (data & 0x2) /* direction */ + uptr->CYL--; /* in */ + else + uptr->CYL++; /* out */ + + max_cyl = drv_tab[GET_DTYPE (uptr->flags)].cyl; + if (uptr->CYL == max_cyl) /* check for wrap */ + uptr->CYL = 0; + if (uptr->CYL == -1) + uptr->CYL = (max_cyl - 1); + + rd_set_dstat (uptr); + rd_done (TRM_OK, TRUE); + break; + + default: + sim_activate (uptr, rd_cwait); + break; + } +} + +int32 rd_decode_cmd (int32 data) +{ +if (data == 0) return CMD_RESET; /* 00000000 Reset */ +if (data & 0x80) { + if (data & 0x20) return CMD_WRPHY; /* 1x0xxxxx Write Physical */ + else return CMD_WRLOG; /* 1x1xxxxx Write Logical */ + } +if (data & 0x40) { + if(data & 0x20) return CMD_FORMAT; /* 011xx_x_ Format Track */ + else if (!(data & 0x10)) return CMD_SETREG; /* 0100xxxx Set Register pointer */ + else if (!(data & 0x8)) return CMD_RDID; /* 01010xxx Seek/Read ID */ + else if (data & 0x4) return CMD_RDLOG; /* 010111xx Read Logical */ + else if (data & 0x2) return CMD_RDTRK; /* 0101101x Read Track */ + else return CMD_RDPHY; /* 0101100x Read Physical */ + } +if (data & 0x20) return CMD_DRVSEL; /* 001xxxxx Drive Select */ +else if (data & 0x10) return CMD_POLL; /* 0001xxxx Poll Drives */ +else if (data & 0x4) return CMD_STEP; /* 000001xx Step */ +else if (data & 0x2) return CMD_RESTORE; /* 0000001x Restore Drive */ +else if (data & 0x1) return CMD_DESELECT; /* 00000001 Deselect Drive */ +return CMD_UNKNOWN; +} + +/* read cylinder 0 - simulate special formatting */ + +t_stat rd_rdcyl0 (int32 hd, int32 dtype) +{ +uint32 i; +uint16 c; + +if (hd <= 2) { + memset (&rd_xb[0], 0, 8); /* 8 bytes of zero */ + rd_xb[4] = 0x3600; + rd_xb[5] = drv_tab[dtype].xbn & WMASK; /* number of XBNs */ + rd_xb[6] = (drv_tab[dtype].xbn >> 16) & WMASK; + rd_xb[7] = drv_tab[dtype].dbn & WMASK; /* number of DBNs */ + rd_xb[8] = (drv_tab[dtype].dbn >> 16) & WMASK; + rd_xb[9] = drv_tab[dtype].lbn & WMASK; /* number of LBNs (Logical-Block-Numbers) */ + rd_xb[10] = (drv_tab[dtype].lbn >> 16) & WMASK; + rd_xb[11] = drv_tab[dtype].rbn & WMASK; /* number of RBNs (Replacement-Block-Numbers) */ + rd_xb[12] = (drv_tab[dtype].rbn >> 16) & WMASK; + rd_xb[13] = drv_tab[dtype].sect; /* number of sectors per track */ + rd_xb[14] = drv_tab[dtype].tpg; /* number of tracks */ + rd_xb[15] = drv_tab[dtype].cyl; /* number of cylinders */ + rd_xb[16] = drv_tab[dtype].cylp; /* first cylinder for write precompensation */ + rd_xb[17] = drv_tab[dtype].cylr; /* first cylinder for reduced write current */ + rd_xb[18] = 0; /* seek rate or zero for buffered seeks */ + rd_xb[19] = 1; /* 0 if CRC, 1 if ECC is being used */ + rd_xb[20] = drv_tab[dtype].rcts; /* "replacement control table" (RCT) */ + rd_xb[21] = drv_tab[dtype].rctc; /* number of copies of the RCT */ + rd_xb[22] = drv_tab[dtype].med & WMASK; /* media identifier */ + rd_xb[23] = (drv_tab[dtype].med >> 16) & WMASK; + rd_xb[24] = 1; /* sector-to-sector interleave */ + rd_xb[25] = 7; /* head-to-head skew */ + rd_xb[26] = drv_tab[dtype].ccs; /* cylinder-to-cylinder skew */ + rd_xb[27] = 16; /* size of GAP 0 in the MFM format */ + rd_xb[28] = 16; /* size of GAP 1 in the MFM format */ + rd_xb[29] = 5; /* size of GAP 2 in the MFM format */ + rd_xb[30] = 40; /* size of GAP 3 in the MFM format */ + rd_xb[31] = 13; /* sync value used when formatting */ + memset (&rd_xb[32], 0, 32); /* reserved for use by the RQDX formatter */ + rd_xb[48] = 0x3039; /* serial number */ + memset (&rd_xb[49], 0, 414); /* Filler bytes to the end of the block */ + for (i = c = 0; i < 256; i++) + c = c + rd_xb[i]; + rd_xb[255] = c; /* checksum */ + } +else + memset (&rd_xb[0], 0, RD_NUMBY); +return SCPE_OK; +} + +t_stat rd_rddata (UNIT *uptr, t_lba lba, t_seccnt sects) +{ +t_seccnt sectsread; +t_stat r; + +r = sim_disk_rdsect (uptr, lba, (uint8 *)rd_xb, §sread, sects); +sim_disk_data_trace (uptr, (uint8 *)rd_xb, lba, sectsread*RD_NUMBY, "sim_disk_rdsect", DBG_DAT & rd_dev.dctrl, DBG_REQ); +return r; +} + +t_stat rd_wrdata (UNIT *uptr, t_lba lba, t_seccnt sects) +{ +t_seccnt sectswritten; + +sim_disk_data_trace (uptr, (uint8 *)rd_xb, lba, sects*RD_NUMBY, "sim_disk_wrsect", DBG_DAT & rd_dev.dctrl, DBG_REQ); +return sim_disk_wrsect (uptr, lba, (uint8 *)rd_xb, §swritten, sects); +} + +/* Unit service */ + +t_stat rd_svc (UNIT *uptr) +{ +t_lba lba; +int32 dtype = GET_DTYPE (uptr->flags); + +switch (uptr->CMD) { + case CMD_RDPHY: + case CMD_RDLOG: + uptr->CYL = rd_dcyl; + uptr->HEAD = rd_dhead; + if (dtype >= RD31_DTYPE) { + if (rd_dcyl == 0) { + lba = 0; + sim_debug (DBG_RD, &rd_dev, "cyl=%04d, hd=%d, sect=%02d, lba=%08X\n", rd_dcyl, rd_dhead, rd_dsect, lba); + rd_rdcyl0 (rd_dhead, dtype); + } + else { + lba = GET_DA (uptr, (rd_dcyl - 1), rd_dhead, rd_dsect); + sim_debug (DBG_RD, &rd_dev, "cyl=%04d, hd=%d, sect=%02d, lba=%08X\n", rd_dcyl, rd_dhead, rd_dsect, lba); + rd_rddata (uptr, lba, rd_scnt); + } + } + else { + if (rd_rtcnt & 0x1) { + rd_cstat |= CST_SYNCE; + rd_done (TRM_ERR_RD, TRUE); + return SCPE_OK; + } + lba = GET_DA (uptr, rd_dcyl, rd_dhead, (rd_dsect - 1)); + sim_debug (DBG_RD, &rd_dev, "cyl=%04d, hd=%d, sect=%02d, lba=%08X\n", rd_dcyl, rd_dhead, rd_dsect, lba); + rd_rddata (uptr, lba, rd_scnt); + } + + ddb_WriteW (rd_dma, (rd_scnt * RD_NUMBY), rd_xb); + rd_dma = (rd_dma + (rd_scnt * RD_NUMBY)) & 0xFFFFFF; + rd_dsect = rd_dsect + rd_scnt - 1; + rd_scnt = 0; + rd_done (TRM_OK, TRUE); + break; + + case CMD_WRPHY: + case CMD_WRLOG: + uptr->CYL = rd_dcyl; + uptr->HEAD = rd_dhead; + ddb_ReadW (rd_dma, (rd_scnt * RD_NUMBY), rd_xb); + rd_dma = (rd_dma + (rd_scnt * RD_NUMBY)) & 0xFFFFFF; + if (dtype >= RD31_DTYPE) { + if (rd_dcyl == 0) { + lba = 0; + sim_debug (DBG_WR, &rd_dev, "cyl=%04d, hd=%d, sect=%02d, lba=%08X (ignored)\n", rd_dcyl, rd_dhead, rd_dsect, lba); + } + else { + lba = GET_DA (uptr, (rd_dcyl - 1), rd_dhead, rd_dsect); + sim_debug (DBG_WR, &rd_dev, "cyl=%04d, hd=%d, sect=%02d, lba=%08X\n", rd_dcyl, rd_dhead, rd_dsect, lba); + rd_wrdata (uptr, lba, rd_scnt); + } + } + else { + if (rd_rtcnt & 0x1) { + rd_cstat |= 0x8; + rd_done (TRM_ERR_RD, TRUE); + return SCPE_OK; + } + lba = GET_DA (uptr, rd_dcyl, rd_dhead, (rd_dsect - 1)); + sim_debug (DBG_WR, &rd_dev, "cyl=%04d, hd=%d, sect=%02d, lba=%08X\n", rd_dcyl, rd_dhead, rd_dsect, lba); + rd_wrdata (uptr, lba, rd_scnt); + } + rd_dsect = rd_dsect + rd_scnt - 1; + rd_scnt = 0; + rd_done (TRM_OK, TRUE); + break; + + case CMD_RESTORE: + sim_debug (DBG_CMD, &rd_dev, "RESTORE\n"); + uptr->CYL = 0; + rd_set_dstat (uptr); + rd_done (TRM_OK, TRUE); + break; + + case CMD_RDID: + sim_debug (DBG_CMD, &rd_dev, "RD ID\n"); + if (uptr->CMD & 0x4) { /* step to new position? */ + uptr->CYL = rd_dcyl; + uptr->HEAD = rd_dhead; + } + rd_done (TRM_OK, TRUE); + break; + + case CMD_RDTRK: /* not implemented */ + sim_debug (DBG_CMD, &rd_dev, "RD TRK\n"); + rd_done (TRM_OK, TRUE); + break; + + case CMD_POLL: /* not implemented */ + sim_debug (DBG_CMD, &rd_dev, "POLL\n"); + rd_done (TRM_OK, TRUE); + break; + + case CMD_FORMAT: /* not implemented */ + sim_debug (DBG_CMD, &rd_dev, "FORMAT\n"); + rd_done (TRM_OK, TRUE); + break; + + default: + rd_done (TRM_OK, TRUE); + } + +return SCPE_OK; +} + +/* Update the drive status register to reflect the current unit state */ + +void rd_set_dstat (UNIT *uptr) +{ +if ((uptr->flags & (UNIT_DIS + UNIT_ATT)) == UNIT_ATT) { /* drive present? */ + uptr->STAT = (DST_SCOM | DST_RDY); + if (uptr->flags & UNIT_WPRT) /* write protected? */ + uptr->STAT |= DST_WPT; + if (CUR_DRV != 2) /* not fdd? */ + uptr->STAT |= DST_SELA; + if (uptr->CYL == 0) /* at cyl 0? */ + uptr->STAT |= DST_TRK0; + } +else /* drive not present */ + uptr->STAT = 0; +} + +/* Command complete. Set done and put final value in interface register, + request interrupt if needed, return to IDLE state. +*/ + +void rd_done (int32 term_code, t_bool setint) +{ +rd_stat = ((term_code & STAT_M_TRMC) << STAT_V_TRMC) | STAT_DONE; +if ((rd_term & 0x20) && setint) { + SET_INT (SCA); + rd_stat = rd_stat | STAT_INT; + } +} + +/* Device initialization. */ + +t_stat rd_reset (DEVICE *dptr) +{ +rd_rg_p = 0; +CLR_INT (SCA); /* clear int req */ +rd_done (TRM_OK, FALSE); +sim_cancel (&rd_unit[0]); /* cancel drive 0 */ +sim_cancel (&rd_unit[1]); /* cancel drive 1 */ +sim_cancel (&rd_unit[2]); /* cancel drive 2 */ +if (rd_xb == NULL) + rd_xb = (uint16 *) calloc (RD_MAXFR, sizeof (uint8)); +if (rd_xb == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +/* Attach routine */ + +t_stat rd_attach (UNIT *uptr, CONST char *cptr) +{ +return sim_disk_attach (uptr, cptr, RD_NUMBY, + sizeof (uint8), TRUE, DBG_DSK, + drv_tab[GET_DTYPE (uptr->flags)].name, 0, 0); +} + +/* Detach routine */ + +t_stat rd_detach (UNIT *uptr) +{ +sim_cancel (uptr); +return sim_disk_detach (uptr); +} + +/* Set unit type */ + +t_stat rd_set_type (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +if (uptr->flags & UNIT_ATT) + return SCPE_ALATT; + +if ((uptr == &rd_unit[0]) || (uptr == &rd_unit[1])) { /* hard disk only */ + if (val < RD31_DTYPE) + return SCPE_ARG; + uptr->flags = (uptr->flags & ~UNIT_DTYPE) | (val << UNIT_V_DTYPE); + } +if (uptr == &rd_unit[2]) { /* floppy disk only */ + if (val > RX33_DTYPE) + return SCPE_ARG; + uptr->flags = (uptr->flags & ~UNIT_DTYPE) | (val << UNIT_V_DTYPE); + } +uptr->capac = ((t_addr) drv_tab[val].lbn) * RD_NUMBY; + +return SCPE_OK; +} + +/* Show unit type */ + +t_stat rd_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ +fprintf (st, "%s", drv_tab[GET_DTYPE (uptr->flags)].name); +return SCPE_OK; +} + +t_stat rd_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "HDC9224 Disk Controller (RD)\n\n"); +fprintf (st, "The RD controller simulates the HDC9224 Universal Disk Controller\n"); +fprintf (st, "chip with up to two hard drives and one floppy drive.\n"); +if (dptr->flags & DEV_DISABLE) + fprintf (st, "Initially the RD controller is disabled.\n"); +else + fprintf (st, "The RD controller cannot be disabled.\n"); +fprintf (st, "Each unit can be set to one of several drive types:\n"); +fprint_set_help (st, dptr); +fprintf (st, "\nUnit RD0 and RD1 only support hard disk types (RDxx) and unit RD2\n"); +fprintf (st, "only supports a floppy disk type (RX33)\n"); +fprintf (st, "Configured options can be displayed with:\n\n"); +fprint_show_help (st, dptr); +fprint_reg_help (st, dptr); +fprintf (st, "\nDisk drives on the RD device can be attached to simulated storage in the\n"); +fprintf (st, "following ways:\n\n"); +sim_disk_attach_help (st, dptr, uptr, flag, cptr); +return SCPE_OK; +} + +const char *rd_description (DEVICE *dptr) +{ +return "HDC9224 disk controller"; +} diff --git a/VAX/vax4xx_rz80.c b/VAX/vax4xx_rz80.c new file mode 100644 index 00000000..28a5a72c --- /dev/null +++ b/VAX/vax4xx_rz80.c @@ -0,0 +1,864 @@ +/* vax4xx_rz80.c: NCR 5380 SCSI controller + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + rz SCSI controller +*/ + +#include "vax_defs.h" +#include "sim_scsi.h" +#include "vax_rzdev.h" + +#if defined(VAX_420) +#include "vax_ka420_rzrz_bin.h" +#else +#define BOOT_CODE_ARRAY NULL +#define BOOT_CODE_SIZE 0 +#endif + +#define RZ_NUMCT 2 +#define RZ_NUMDR 8 +#define RZ_CTLR (RZ_NUMDR) + +#define iflgs u3 +#define cnum u4 + +/* Mode Register */ + +#define MODE_BLOCK 0x80 /* DMA block mode */ +#define MODE_TARG 0x40 /* Target role */ +#define MODE_PARCK 0x20 /* Parity check enable */ +#define MODE_INTPAR 0x10 /* Interrupt on parity error */ +#define MODE_INTEOP 0x08 /* Interrupt on DMA end */ +#define MODE_MONBSY 0x04 /* Monitor BSY */ +#define MODE_DMA 0x02 /* Enable DMA transfer */ +#define MODE_ARB 0x01 /* Start arbitration */ + +/* Initiator Command Register */ + +#define ICMD_RST 0x80 /* Assert RST */ +#define ICMD_AIP 0x40 /* Arbitration in progress */ +#define ICMD_TEST 0x40 /* Test mode */ +#define ICMD_LA 0x20 /* Lost arbitration */ +#define ICMD_DIFF 0x20 /* Differential enable */ +#define ICMD_ACK 0x10 /* Assert ACK */ +#define ICMD_BSY 0x08 /* Assert BSY */ +#define ICMD_SEL 0x04 /* Assert SEL */ +#define ICMD_ATN 0x02 /* Assert ATN */ +#define ICMD_ENOUT 0x01 /* Enable output */ + +/* Target Command Register */ + +#define TCMD_REQ 0x08 /* Assert REQ */ +#define TCMD_MSG 0x04 /* Assert MSG */ +#define TCMD_CD 0x02 /* Assert C/D */ +#define TCMD_IO 0x01 /* Assert I/O */ +#define TCMD_PHASE 0x07 /* Phase bits */ + +/* Bus and Status Register */ + +#define STS_DMAEND 0x80 /* DMA end */ +#define STS_DMAREQ 0x40 /* DMA request */ +#define STS_PARERR 0x20 /* Parity error */ +#define STS_INTREQ 0x10 /* Interrupt request */ +#define STS_MATCH 0x08 /* Phase match */ +#define STS_BSYERR 0x04 /* Busy error */ +#define STS_ATN 0x02 /* ATN asserted */ +#define STS_ACK 0x01 /* ACK asserted */ + +/* Current Bus Status Register */ + +#define CSTAT_RST 0x80 /* RST asserted */ +#define CSTAT_BSY 0x40 /* BSY asserted */ +#define CSTAT_REQ 0x20 /* REQ asserted */ +#define CSTAT_MSG 0x10 /* MSG asserted */ +#define CSTAT_CD 0x08 /* C/D asserted */ +#define CSTAT_IO 0x04 /* I/O asserted */ +#define CSTAT_SEL 0x02 /* SEL asserted */ +#define CSTAT_DBP 0x01 /* Databus parity */ +#define CSTAT_V_PHASE 2 +#define CSTAT_M_PHASE 0x07 /* Phase bits */ + +#define DBG_REG 0x0001 /* registers */ +#define DBG_CMD 0x0002 /* display commands */ +#define DBG_INT 0x0004 /* display transfer requests */ +#define DBG_DSK 0x0008 /* display sim_disk activities */ + +#define PH_DATA_OUT 0 +#define PH_DATA_IN 1 +#define PH_COMMAND 2 +#define PH_STATUS 3 +#define PH_MSG_OUT 6 +#define PH_MSG_IN 7 + +#define UA_SELECT 0 + +#define UNIT_V_DTYPE (SCSI_V_UF + 0) /* drive type */ +#define UNIT_M_DTYPE 0x1F +#define UNIT_DTYPE (UNIT_M_DTYPE << UNIT_V_DTYPE) +#define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE) + +typedef struct { + uint32 cnum; /* ctrl number */ + uint8 odata; /* output data */ + uint8 cdata; /* current data */ + uint32 mode; /* mode reg */ + uint32 icmd; /* initiator cmd reg */ + uint32 tcmd; /* target cmd reg */ + uint32 status; /* status reg */ + uint32 cstat; + uint32 selen; /* select enable reg */ + uint32 dcount; /* DMA count reg */ + uint32 daddr; /* DMA addr reg */ + t_bool daddr_low; /* DMA addr flag */ + uint32 ddir; /* DMA dir */ + uint8 *buf; /* unit buffer */ + int32 buf_ptr; /* current buffer pointer */ + int32 buf_len; /* current buffer length */ + SCSI_BUS bus; /* SCSI bus state */ + } CTLR; + +t_stat rz_svc (UNIT *uptr); +t_stat rz_isvc (UNIT *uptr); +t_stat rz_reset (DEVICE *dptr); +t_stat rz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +t_stat rz_set_type (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat rz_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +void rz_update_status (CTLR *rz); +void rz_setint (CTLR *rz, uint32 flags); +void rz_clrint (CTLR *rz); +void rz_sw_reset (CTLR *rz); +void rz_ack (CTLR *rz); +int32 rz_parity (int32 val, int32 odd); +const char *rz_description (DEVICE *dptr); + +/* RZ data structures + + rz_dev RZ device descriptor + rz_unit RZ unit descriptor + rz_reg RZ register list +*/ + +CTLR rz_ctx = { 0 }; + +UNIT rz_unit[] = { + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_isvc, UNIT_DIS, 0) } + }; + +REG rz_reg[] = { + { FLDATAD ( INT, int_req[IPL_SCA], INT_V_SCA, "interrupt pending flag") }, + { NULL } + }; + +DEBTAB rz_debug[] = { + { "REG", DBG_REG, "Register activity" }, + { "CMD", DBG_CMD, "Chip commands" }, + { "INT", DBG_INT, "Interrupts" }, + { "SCMD", SCSI_DBG_CMD, "SCSI commands" }, + { "SMSG", SCSI_DBG_MSG, "SCSI messages" }, + { "SBUS", SCSI_DBG_BUS, "SCSI bus activity" }, + { "SDSK", SCSI_DBG_DSK, "SCSI disk activity" }, + { 0 } +}; + +MTAB rz_mod[] = { + { SCSI_WLK, 0, NULL, "WRITEENABLED", + &scsi_set_wlk, NULL, NULL, "Write enable disk drive" }, + { SCSI_WLK, SCSI_WLK, NULL, "LOCKED", + &scsi_set_wlk, NULL, NULL, "Write lock disk drive" }, + { MTAB_XTD|MTAB_VUN, 0, "WRITE", NULL, + NULL, &scsi_show_wlk, NULL, "Display drive writelock status" }, + { MTAB_XTD|MTAB_VUN, RZ23_DTYPE, NULL, "RZ23", + &rz_set_type, NULL, NULL, "Set RZ23 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ23L_DTYPE, NULL, "RZ23L", + &rz_set_type, NULL, NULL, "Set RZ23L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ24_DTYPE, NULL, "RZ24", + &rz_set_type, NULL, NULL, "Set RZ24 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ24L_DTYPE, NULL, "RZ24L", + &rz_set_type, NULL, NULL, "Set RZ24L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ25_DTYPE, NULL, "RZ25", + &rz_set_type, NULL, NULL, "Set RZ25 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ25L_DTYPE, NULL, "RZ25L", + &rz_set_type, NULL, NULL, "Set RZ25L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ26_DTYPE, NULL, "RZ26", + &rz_set_type, NULL, NULL, "Set RZ26 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ26L_DTYPE, NULL, "RZ26L", + &rz_set_type, NULL, NULL, "Set RZ26L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ55_DTYPE, NULL, "RZ55", + &rz_set_type, NULL, NULL, "Set RZ55 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RRD40_DTYPE, NULL, "CDROM", + &rz_set_type, NULL, NULL, "Set RRD40 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RRD40_DTYPE, NULL, "RRD40", + &rz_set_type, NULL, NULL, "Set RRD40 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RRD42_DTYPE, NULL, "RRD42", + &rz_set_type, NULL, NULL, "Set RRD42 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RRW11_DTYPE, NULL, "RRW11", + &rz_set_type, NULL, NULL, "Set RRW11 Disk Type" }, + { MTAB_XTD|MTAB_VUN, CDW900_DTYPE, NULL, "CDW900", + &rz_set_type, NULL, NULL, "Set SONY CDW-900E Disk Type" }, + { MTAB_XTD|MTAB_VUN, XR1001_DTYPE, NULL, "XR1001", + &rz_set_type, NULL, NULL, "Set JVC XR-W1001 Disk Type" }, + { MTAB_XTD|MTAB_VUN, TZK50_DTYPE, NULL, "TZK50", + &rz_set_type, NULL, NULL, "Set DEC TZK50 Tape Type" }, + { MTAB_XTD|MTAB_VUN, TZ30_DTYPE, NULL, "TZ30", + &rz_set_type, NULL, NULL, "Set DEC TZ30 Tape Type" }, + { MTAB_XTD|MTAB_VUN|MTAB_VALR, RZU_DTYPE, NULL, "RZUSER", + &rz_set_type, NULL, NULL, "Set RZUSER=size Disk Type" }, + { MTAB_XTD|MTAB_VUN, 0, "TYPE", NULL, + NULL, &rz_show_type, NULL, "Display device type" }, + { SCSI_NOAUTO, SCSI_NOAUTO, "noautosize", "NOAUTOSIZE", NULL, NULL, NULL, "Disables disk autosize on attach" }, + { SCSI_NOAUTO, 0, "autosize", "AUTOSIZE", NULL, NULL, NULL, "Enables disk autosize on attach" }, + { MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT", + &scsi_set_fmt, &scsi_show_fmt, NULL, "Set/Display unit format" }, + { 0 } + }; + +DEVICE rz_dev = { + "RZ", rz_unit, rz_reg, rz_mod, + RZ_NUMDR + 1, DEV_RDX, 31, 1, DEV_RDX, 8, + NULL, NULL, &rz_reset, + NULL, &scsi_attach, &scsi_detach, + NULL, DEV_DEBUG | DEV_DISK | DEV_SECTORS | RZ_FLAGS, + 0, rz_debug, NULL, NULL, &rz_help, NULL, NULL, + &rz_description + }; + +/* RZB data structures + + rzb_dev RZB device descriptor + rzb_unit RZB unit descriptor + rzb_reg RZB register list +*/ + +CTLR rzb_ctx = { 1 }; + +DIB rzb_dib = { + RZ_ROM_INDEX, BOOT_CODE_ARRAY, BOOT_CODE_SIZE + }; + +UNIT rzb_unit[] = { + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_isvc, UNIT_DIS, 0) } + }; + +REG rzb_reg[] = { + { FLDATAD ( INT, int_req[IPL_SCB], INT_V_SCB, "interrupt pending flag") }, + { NULL } + }; + +DEVICE rzb_dev = { + "RZB", rzb_unit, rzb_reg, rz_mod, + RZ_NUMDR + 1, DEV_RDX, 31, 1, DEV_RDX, 8, + NULL, NULL, &rz_reset, + NULL, &scsi_attach, &scsi_detach, + &rzb_dib, DEV_DEBUG | DEV_DISK | DEV_SECTORS | RZB_FLAGS, + 0, rz_debug, NULL, NULL, + &rz_help, NULL /* help and attach_help routines */ + }; + +static DEVICE *rz_devmap[RZ_NUMCT] = { + &rz_dev, &rzb_dev + }; + +static CTLR *rz_ctxmap[RZ_NUMCT] = { + &rz_ctx, &rzb_ctx + }; + +/* RZ routines + + rz_rd I/O page read + rz_wr I/O page write + rz_svc process event + rz_reset process reset +*/ + +int32 rz_rd (int32 pa) +{ +int32 ctlr = (pa >> 8) & 1; +CTLR *rz = rz_ctxmap[ctlr]; +DEVICE *dptr = rz_devmap[ctlr]; +UNIT *uptr = dptr->units + RZ_CTLR; +int32 rg = (pa >> 2) & 0x1F; +int32 data = 0; +int32 len; + +if (dptr->flags & DEV_DIS) /* disabled? */ + return 0; + +switch (rg) { + + case 0: /* SCS_CUR_DATA */ + if ((rz->icmd & ICMD_ENOUT) || (rz->icmd & ICMD_AIP)) /* initiator controlling bus */ + data = rz->odata; + else if (rz->bus.target >= 0) { + len = scsi_read (&rz->bus, &rz->cdata, 0); /* receive current byte */ + data = rz->cdata; + } + else { /* bus idle */ + data = 0; + if (rz->mode & MODE_PARCK) { /* parity checking enabled? */ + if (rz->mode & MODE_INTPAR) { /* interrupt too? */ + sim_debug (DBG_INT, dptr, "Delayed: Parity Error\n"); + rz_setint (rz, STS_PARERR); + } + else + rz->status = rz->status | STS_PARERR; /* signal parity error */ + } + } + break; + + case 1: /* SCS_INI_CMD */ + data = rz->icmd; + break; + + case 2: /* SCS_MODE */ + data = rz->mode; + break; + + case 3: /* SCS_TAR_CMD */ + data = rz->tcmd; + break; + + case 4: /* SCS_CUR_STAT */ + if (rz->icmd & ICMD_RST) + data = CSTAT_RST; + else { + if (rz->mode & MODE_TARG) /* target mode? */ + data = ((rz->tcmd & 0xF) << CSTAT_V_PHASE); + else { /* initiator mode? */ + data = (rz->bus.phase << CSTAT_V_PHASE); + if (rz->icmd & ICMD_SEL) + data = data | CSTAT_SEL; + if (rz->bus.target >= 0) /* target selected? */ + data = data | CSTAT_BSY; + if ((rz->bus.req) && ((rz->icmd & ICMD_ACK) == 0)) + data = data | CSTAT_REQ; + } + if (rz->icmd & ICMD_ENOUT) + data = data | (rz_parity (rz->odata, 1)); + else if (rz->bus.target >= 0) { + len = scsi_read (&rz->bus, &rz->cdata, 0); /* receive current byte */ + data = data | (rz_parity (rz->cdata, 1)); + } + } + break; + + case 5: /* SCS_STATUS */ + rz->status = rz->status & ~(STS_ACK | STS_ATN | STS_MATCH); + if ((rz->icmd & ICMD_RST) == 0) { + if ((rz->mode & MODE_TARG) == 0) { /* initiator mode */ + if (rz->icmd & ICMD_ACK) + rz->status = rz->status | STS_ACK; + if (rz->bus.atn) + rz->status = rz->status | STS_ATN; + if ((rz->tcmd & TCMD_PHASE) == rz->bus.phase) /* bus phase match? */ + rz->status = rz->status | STS_MATCH; + } + } + data = rz->status; + break; + + case 6: /* SCS_IN_DATA */ + if (rz->bus.target >= 0) { /* target selected? */ + len = scsi_read (&rz->bus, &rz->cdata, 0); /* receive current byte */ + data = rz->cdata; + } + else data = 0; + break; + + case 7: /* SCS_RESET */ + rz->status = rz->status & ~(STS_INTREQ | STS_PARERR | STS_BSYERR); + rz_clrint (rz); + data = 0; + break; + + case 8: /* SCD_ADR */ + data = rz->daddr & DCNT_MASK; + break; + + case 16: /* SCD_CNT */ + data = rz->dcount & DCNT_MASK; + break; + + case 17: /* SCD_DIR */ + data = rz->ddir; + break; + + default: + data = 0; + break; + } + +sim_debug (DBG_REG, dptr, "reg %d read, value = %X, PC = %08X\n", rg, data, fault_PC); +return data; +} + +void rz_wr (int32 pa, int32 data, int32 access) +{ +int32 ctlr = (pa >> 8) & 1; +CTLR *rz = rz_ctxmap[ctlr]; +DEVICE *dptr = rz_devmap[ctlr]; +UNIT *uptr = dptr->units + RZ_CTLR; +int32 rg = (pa >> 2) & 0x1F; +int32 i; + +if (dptr->flags & DEV_DIS) /* disabled? */ + return; + +switch (rg) { + + case 0: /* SCS_OUT_DATA */ + rz->odata = data; + break; + + case 1: /* SCS_INI_CMD */ + if ((rz->mode & MODE_TARG) == 0) { /* initiator mode */ + if ((data ^ rz->icmd) & ICMD_ATN) { + if (data & ICMD_ATN) /* setting ATN */ + scsi_set_atn (&rz->bus); + else /* clearing ATN */ + scsi_release_atn (&rz->bus); + } + if ((data ^ rz->icmd) & ICMD_ACK) { + if (data & ICMD_ACK) { /* setting ACK */ + if (rz->bus.target >= 0) + rz_ack (rz); + } + } + } + if (data & ICMD_ENOUT) { + if ((data & ICMD_SEL) && (rz->bus.target < 0)) { /* setting SEL */ + if ((rz->odata == rz->selen) && (rz->selen != 0)) { + rz_setint (rz, 0); /* selecting ourselves */ + break; + } + for (i = 0; i < RZ_NUMDR; i++) { + if ((rz->odata & (1u << i)) && (i != RZ_SCSI_ID)) { + scsi_select (&rz->bus, i); + break; + } + } + } + } +#if 0 + if ((data ^ rz->icmd) & ICMD_SEL) { + if ((data & ICMD_SEL) == 0) { /* clearing SEL */ + if (rz->bus.target < 0) + scsi_release (&rz->bus); + } + } +#endif + if ((data ^ rz->icmd) & ICMD_RST) { + if (data & ICMD_RST) { /* setting RST */ + rz_sw_reset (rz); + rz->icmd = ICMD_RST; + rz->status = STS_INTREQ; + sim_debug (DBG_INT, dptr, "Delayed: Bus reset asserted\n"); + rz_setint (rz, 0); + } + else { /* clearing RST */ + rz->icmd = data; + sim_debug (DBG_INT, dptr, "Delayed: Bus reset cleared\n"); + rz_setint (rz, 0); + } + } + else rz->icmd = data; + break; + + case 2: /* SCS_MODE */ + if (data & MODE_ARB) { /* start arbitration */ + rz->status = rz->status & ~(STS_INTREQ | STS_PARERR | STS_BSYERR); + rz_clrint (rz); + if (scsi_arbitrate (&rz->bus, RZ_SCSI_ID)) { + rz->icmd = rz->icmd | ICMD_AIP; + rz->icmd = rz->icmd & ~ICMD_LA; + } + else { + rz->icmd = rz->icmd & ~ICMD_AIP; + rz->icmd = rz->icmd | ICMD_LA; + } + } + if (data & MODE_MONBSY) { /* enable BSY monitor */ + if (rz->bus.target < 0) { /* BSY set? */ + sim_debug (DBG_INT, dptr, "Delayed: Busy error\n"); + rz_setint (rz, STS_BSYERR); /* no, error */ + } + } + if ((data & MODE_DMA) == 0) /* clearing DMA */ + rz->status = rz->status & ~STS_DMAEND; + rz->mode = data; + if (((rz->icmd & ICMD_BSY) == 0) && (rz->bus.target < 0)) + rz->mode = rz->mode & ~MODE_DMA; /* DMA can only be set when BSY is set */ + rz_update_status (rz); + break; + + case 3: /* SCS_TAR_CMD */ + rz->tcmd = data & 0xF; + if ((rz->mode & MODE_TARG) == 0) /* not target mode */ + rz_update_status (rz); + break; + + case 4: /* SCS_SEL_ENA */ + rz->selen = data; + break; + + case 5: /* SCS_DMA_SEND */ + uptr = dptr->units + rz->bus.target; + sim_activate (uptr, 50); + break; + + case 6: /* SCS_DMA_TRCV */ + break; + + case 7: /* SCS_DMA_IRCV */ + uptr = dptr->units + rz->bus.target; + sim_activate (uptr, 50); + break; + + case 8: /* SCD_ADR */ + if (access == L_BYTE) { + if (rz->daddr_low) { + rz->daddr = rz->daddr | (data & BMASK); + rz->daddr_low = FALSE; + } + else { + rz->daddr = ((data & 0x3F) << 8); + rz->daddr_low = TRUE; + } + } + else rz->daddr = data & DCNT_MASK; + break; + + case 16: /* SCD_CNT */ + rz->dcount = data & DCNT_MASK; + break; + + case 17: /* SCD_DIR */ + rz->ddir = data; + break; + } + +sim_debug (DBG_REG, dptr, "reg %d write, value = %X, PC = %08X\n", rg, data, fault_PC); +SET_IRQL; +} + +int32 rz_parity (int32 val, int32 odd) +{ +for ( ; val != 0; val = val >> 1) { + if (val & 1) + odd = odd ^ 1; + } +return odd; +} + +void rz_ack (CTLR *rz) +{ +uint32 len; +uint32 old_phase; + +old_phase = rz->bus.phase; +switch (rz->bus.phase) { + + case PH_MSG_OUT: + case PH_COMMAND: + case PH_DATA_OUT: + if (rz->bus.phase == PH_DATA_OUT) + rz->buf_ptr = 0; /* TODO: fix this in sim_scsi.c */ + rz->buf[rz->buf_ptr++] = rz->odata; + scsi_write (&rz->bus, &rz->buf[0], rz->buf_ptr); /* send next byte */ + break; + + case PH_DATA_IN: + case PH_STATUS: + case PH_MSG_IN: + len = scsi_read (&rz->bus, &rz->cdata, 1); /* receive next byte */ + break; + } +if (old_phase != rz->bus.phase) /* new phase? */ + rz->buf_ptr = 0; /* reset buffer */ +if (old_phase == PH_MSG_IN) /* message in just processed? */ + scsi_release (&rz->bus); /* accept message */ +rz_update_status (rz); +} + +void rz_update_status (CTLR *rz) +{ +DEVICE *dptr = rz_devmap[rz->cnum]; + +if ((rz->tcmd & TCMD_PHASE) == rz->bus.phase) + rz->status = rz->status | STS_MATCH; +else { + rz->status = rz->status & ~STS_MATCH; + if ((rz->mode & MODE_DMA) && (rz->bus.req)) { + sim_debug (DBG_INT, dptr, "Immediate: Phase mismatch\n"); + if (rz->cnum == 0) + SET_INT (SCB); + else + SET_INT (SCA); + rz->status = rz->status | STS_INTREQ; + } + } +if ((rz->mode & MODE_MONBSY) && (rz->bus.target < 0)) { /* monitoring BSY? */ + sim_debug (DBG_INT, dptr, "Delayed: Busy error\n"); + rz_setint (rz, STS_BSYERR); + } +} + +t_stat rz_svc (UNIT *uptr) +{ +CTLR *rz = rz_ctxmap[uptr->cnum]; +DEVICE *dptr = rz_devmap[uptr->cnum]; +int32 dma_len; +uint32 old_phase; + +old_phase = rz->bus.phase; +if (rz->dcount == 0) + dma_len = DMA_SIZE; /* full buffer */ +else + dma_len = ((rz->dcount ^ DCNT_MASK) + 1) & DCNT_MASK; /* 2's complement */ +if (rz->ddir == 1) { /* DMA in */ + dma_len = scsi_read (&rz->bus, &rz->buf[0], dma_len); + ddb_WriteB (rz->daddr, dma_len, &rz->buf[0]); + } +else { /* DMA out */ + ddb_ReadB (rz->daddr, dma_len, &rz->buf[0]); + dma_len = scsi_write (&rz->bus, &rz->buf[0], dma_len); + } +rz->buf_len = 0; +rz->dcount = (rz->dcount + dma_len) & DCNT_MASK; /* increment toward zero */ +dma_len = ((rz->dcount ^ DCNT_MASK) + 1) & DCNT_MASK; /* 2's complement */ +if (rz->ddir == 1) { /* DMA in */ + if (old_phase == PH_MSG_IN) /* message in just processed? */ + scsi_release (&rz->bus); /* accept message */ + } +else { + if ((rz->bus.phase == SCSI_STS) && (dma_len == 2)) { /* VMS driver expects this */ + rz->dcount = (rz->dcount + 1) & DCNT_MASK; /* increment toward zero */ + dma_len--; /* decrement remaining xfer */ + } + } +if (dma_len == 0) { + sim_debug (DBG_INT, dptr, "Service: DMA done\n"); + if (rz->cnum == 0) + SET_INT (SCB); + else + SET_INT (SCA); + rz->status = rz->status | STS_INTREQ | STS_DMAEND; + } +rz_update_status (rz); +return SCPE_OK; +} + +t_stat rz_isvc (UNIT *uptr) +{ +CTLR *rz = rz_ctxmap[uptr->cnum]; +DEVICE *dptr = rz_devmap[uptr->cnum]; + +sim_debug (DBG_INT, dptr, "Service: flags = %X\n", uptr->iflgs); +if (rz->cnum == 0) + SET_INT (SCB); +else + SET_INT (SCA); +rz->status = rz->status | STS_INTREQ | uptr->iflgs; +uptr->iflgs = 0; +return SCPE_OK; +} + +void rz_setint (CTLR *rz, uint32 flags) +{ +DEVICE *dptr = rz_devmap[rz->cnum]; +UNIT *uptr = dptr->units + RZ_CTLR; + +uptr->iflgs |= flags; +if (!sim_is_active (uptr)) + sim_activate (uptr, 50); +} + +void rz_clrint (CTLR *rz) +{ +DEVICE *dptr = rz_devmap[rz->cnum]; + +sim_debug (DBG_INT, dptr, "Immediate: Clear int\n"); +if (rz->cnum == 0) + CLR_INT (SCB); +else + CLR_INT (SCA); +rz->status = rz->status & ~STS_INTREQ; +} + +void rz_sw_reset (CTLR *rz) +{ +DEVICE *dptr; +UNIT *uptr; +uint32 i; + +dptr = rz_devmap[rz->cnum]; +for (i = 0; i < (RZ_NUMDR + 1); i++) { + uptr = dptr->units + i; + sim_cancel (uptr); + uptr->iflgs = 0; + } +rz_clrint (rz); +rz->cdata = 0; +rz->mode = 0; +rz->icmd = 0; +rz->tcmd = 0; +rz->status = 0; +rz->cstat = 0; +rz->selen = 0; +rz->dcount = 0; +rz->daddr = 0; +rz->daddr_low = FALSE; +rz->ddir = 0; +rz->buf_ptr = 0; +scsi_reset (&rz->bus); +} + +t_stat rz_reset (DEVICE *dptr) +{ +int32 ctlr, i; +uint32 dtyp; +CTLR *rz; +UNIT *uptr; +t_stat r; + +for (i = 0, ctlr = -1; i < RZ_NUMCT; i++) { /* find ctrl num */ + if (rz_devmap[i] == dptr) + ctlr = i; + } +if (ctlr < 0) /* not found??? */ + return SCPE_IERR; +rz = rz_ctxmap[ctlr]; +if (rz->buf == NULL) + rz->buf = (uint8 *)calloc (DMA_SIZE, sizeof(uint8)); +if (rz->buf == NULL) + return SCPE_MEM; +r = scsi_init (&rz->bus, DMA_SIZE); /* init SCSI bus */ +if (r != SCPE_OK) + return r; +rz->bus.dptr = dptr; /* set bus device */ +for (i = 0; i < (RZ_NUMDR + 1); i++) { /* init units */ + uptr = dptr->units + i; + uptr->cnum = ctlr; /* set ctrl index */ + if (i == RZ_SCSI_ID) /* initiator ID? */ + uptr->flags = UNIT_DIS; /* disable unit */ + if (i < RZ_NUMDR) { + scsi_add_unit (&rz->bus, i, uptr); + dtyp = GET_DTYPE (uptr->flags); + scsi_set_unit (&rz->bus, uptr, &rzdev_tab[dtyp]); + scsi_reset_unit (uptr); + } + } +rz_sw_reset (rz); +return SCPE_OK; +} + +/* Set unit type (and capacity if user defined) */ + +t_stat rz_set_type (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +uint32 cap; +uint32 max = sim_toffset_64? RZU_EMAXC: RZU_MAXC; +t_stat r; + +if ((val < 0) || ((val != RZU_DTYPE) && cptr)) + return SCPE_ARG; +if (uptr->flags & UNIT_ATT) + return SCPE_ALATT; +if (cptr) { + cap = (uint32) get_uint (cptr, 10, 0xFFFFFFFF, &r); + if ((sim_switches & SWMASK ('L')) == 0) + cap = cap * 1954; + if ((r != SCPE_OK) || (cap < RZU_MINC) || (cap > max)) + return SCPE_ARG; + rzdev_tab[val].lbn = cap; + } +uptr->flags = (uptr->flags & ~UNIT_DTYPE) | (val << UNIT_V_DTYPE); +uptr->capac = (t_addr)rzdev_tab[val].lbn; +return SCPE_OK; +} + +/* Show unit type */ + +t_stat rz_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ +fprintf (st, "%s", rzdev_tab[GET_DTYPE (uptr->flags)].name); +return SCPE_OK; +} + +t_stat rz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "NCR 5380 SCSI Controller (%s)\n\n", dptr->name); +fprintf (st, "The %s controller simulates the NCR 5380 SCSI controller connected\n", dptr->name); +fprintf (st, "to a bus with up to 7 target devices.\n"); +if (dptr->flags & DEV_DISABLE) + fprintf (st, "Initially the %s controller is disabled.\n", dptr->name); +else + fprintf (st, "The %s controller cannot be disabled.\n", dptr->name); +fprintf (st, "SCSI target device %s%d is reserved for the initiator and cannot\n", dptr->name, RZ_SCSI_ID); +fprintf (st, "be enabled\n"); +fprintf (st, "Each target on the SCSI bus can be set to one of several types:\n"); +fprint_set_help (st, dptr); +fprintf (st, "Configured options can be displayed with:\n\n"); +fprint_show_help (st, dptr); +fprint_reg_help (st, dptr); +scsi_help (st, dptr, uptr, flag, cptr); +return SCPE_OK; +} + +const char *rz_description (DEVICE *dptr) +{ +return "NCR 5380 SCSI controller"; +} diff --git a/VAX/vax4xx_rz94.c b/VAX/vax4xx_rz94.c new file mode 100644 index 00000000..8dc280cb --- /dev/null +++ b/VAX/vax4xx_rz94.c @@ -0,0 +1,860 @@ +/* vax4xx_rz94.c: NCR 53C94 SCSI controller + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + rz SCSI controller +*/ + +#include "vax_defs.h" +#include "sim_scsi.h" +#include "vax_rzdev.h" + +/* command groups */ + +#define CMD_DISC 0x40 /* disconnected state group */ +#define CMD_TARG 0x20 /* target state group */ +#define CMD_INIT 0x10 /* initiator state group */ + +/* status register */ + +#define STS_INT 0x80 /* interrupt */ +#define STS_GE 0x40 /* gross error */ +#define STS_PE 0x20 /* parity error */ +#define STS_TC 0x10 /* terminal count */ +#define STS_VGC 0x08 /* valid group code */ +#define STS_PH 0x07 /* SCSI phase */ +#define STS_CLR 0x10 + +/* interrupt register */ + +#define INT_SCSIRST 0x80 /* SCSI reset */ +#define INT_ILLCMD 0x40 /* illegal command */ +#define INT_DIS 0x20 /* disconnect */ +#define INT_BUSSV 0x10 /* bus service */ +#define INT_FC 0x08 /* function complete */ +#define INT_RSEL 0x04 /* reselected */ +#define INT_SELA 0x02 /* selected with ATN */ +#define INT_SEL 0x01 /* selected */ + +/* configuration register 1 */ + +#define CFG1_SLOW 0x80 /* slow cable mode */ +#define CFG1_SRD 0x40 /* disable SCSI reset int */ +#define CFG1_PTST 0x20 /* parity test */ +#define CFG1_PEN 0x10 /* parity enable */ +#define CFG1_TEST 0x08 /* chip test */ +#define CFG1_MYID 0x07 /* my bus id */ + +#define UNIT_V_DTYPE (SCSI_V_UF + 0) /* drive type */ +#define UNIT_M_DTYPE 0x1F +#define UNIT_DTYPE (UNIT_M_DTYPE << UNIT_V_DTYPE) +#define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE) + +#define RZ_MAXFR (1u << 16) /* max transfer */ + +uint32 rz_last_cmd = 0; +uint32 rz_txi = 0; /* transfer count */ +uint32 rz_txc = 0; /* transfer counter */ +uint8 rz_cfg1 = 0; /* config 1 */ +uint8 rz_cfg2 = 0; /* config 2 */ +uint8 rz_cfg3 = 0; /* config 3 */ +uint8 rz_int = 0; /* interrupt */ +uint8 rz_stat = 0; /* status */ +uint32 rz_seq = 0; +uint32 rz_dest = 1; +uint8 rz_fifo[16] = { 0 }; +uint32 rz_fifo_t = 0; +uint32 rz_fifo_b = 0; +uint32 rz_fifo_c = 0; +uint32 rz_dma = 0; +uint32 rz_dir = 0; +uint8 *rz_buf; +SCSI_BUS rz_bus; + +/* debugging bitmaps */ + +#define DBG_REG 0x0001 /* trace read/write registers */ +#define DBG_CMD 0x0002 /* display commands */ +#define DBG_INT 0x0004 /* display transfer requests */ + +DEBTAB rz_debug[] = { + { "REG", DBG_REG, "Register activity" }, + { "CMD", DBG_CMD, "Chip commands" }, + { "INT", DBG_INT, "Interrupts" }, + { "SCMD", SCSI_DBG_CMD, "SCSI commands" }, + { "SMSG", SCSI_DBG_MSG, "SCSI messages" }, + { "SBUS", SCSI_DBG_BUS, "SCSI bus activity" }, + { "SDSK", SCSI_DBG_DSK, "SCSI disk activity" }, + { 0 } +}; + +t_stat rz_svc (UNIT *uptr); +t_stat rz_reset (DEVICE *dptr); +void rz_sw_reset (void); +t_stat rz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +void rz_cmd (uint32 cmd); +t_stat rz_set_type (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat rz_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +const char *rz_description (DEVICE *dptr); + + +/* RZ data structures + + rz_dev RZ device descriptor + rz_unit RZ unit list + rz_reg RZ register list +*/ + +UNIT rz_unit[] = { + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+UNIT_ROABLE+ + (RZ23_DTYPE << UNIT_V_DTYPE), RZ_SIZE (RZ23)) }, + { UDATA (&rz_svc, UNIT_DIS, 0) } + }; + +REG rz_reg[] = { + { FLDATAD (INT, int_req[IPL_SC], INT_V_SC, "interrupt pending flag") }, + { NULL } + }; + +MTAB rz_mod[] = { + { SCSI_WLK, 0, NULL, "WRITEENABLED", + &scsi_set_wlk, NULL, NULL, "Write enable disk drive" }, + { SCSI_WLK, SCSI_WLK, NULL, "LOCKED", + &scsi_set_wlk, NULL, NULL, "Write lock disk drive" }, + { MTAB_XTD|MTAB_VUN, 0, "WRITE", NULL, + NULL, &scsi_show_wlk, NULL, "Display drive writelock status" }, + { MTAB_XTD|MTAB_VUN, RZ23_DTYPE, NULL, "RZ23", + &rz_set_type, NULL, NULL, "Set RZ23 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ23L_DTYPE, NULL, "RZ23L", + &rz_set_type, NULL, NULL, "Set RZ23L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ24_DTYPE, NULL, "RZ24", + &rz_set_type, NULL, NULL, "Set RZ24 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ24L_DTYPE, NULL, "RZ24L", + &rz_set_type, NULL, NULL, "Set RZ24L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ25_DTYPE, NULL, "RZ25", + &rz_set_type, NULL, NULL, "Set RZ25 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ25L_DTYPE, NULL, "RZ25L", + &rz_set_type, NULL, NULL, "Set RZ25L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ26_DTYPE, NULL, "RZ26", + &rz_set_type, NULL, NULL, "Set RZ26 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ26L_DTYPE, NULL, "RZ26L", + &rz_set_type, NULL, NULL, "Set RZ26L Disk Type" }, + { MTAB_XTD|MTAB_VUN, RZ55_DTYPE, NULL, "RZ55", + &rz_set_type, NULL, NULL, "Set RZ55 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RRD40_DTYPE, NULL, "CDROM", + &rz_set_type, NULL, NULL, "Set RRD40 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RRD40_DTYPE, NULL, "RRD40", + &rz_set_type, NULL, NULL, "Set RRD40 Disk Type" }, + { MTAB_XTD|MTAB_VUN, RRD42_DTYPE, NULL, "RRD42", + &rz_set_type, NULL, NULL, "Set RRD42 Disk Type" }, + { MTAB_XTD|MTAB_VUN|MTAB_VALR, RZU_DTYPE, NULL, "RZUSER", + &rz_set_type, NULL, NULL, "Set RZUSER=size Disk Type" }, + { MTAB_XTD|MTAB_VUN, 0, "TYPE", NULL, + NULL, &rz_show_type, NULL, "Display device type" }, + { SCSI_NOAUTO, SCSI_NOAUTO, "noautosize", "NOAUTOSIZE", NULL, NULL, NULL, "Disables disk autosize on attach" }, + { SCSI_NOAUTO, 0, "autosize", "AUTOSIZE", NULL, NULL, NULL, "Enables disk autosize on attach" }, + { MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT", + &scsi_set_fmt, &scsi_show_fmt, NULL, "Set/Display unit format" }, + { 0 } + }; + +DEVICE rz_dev = { + "RZ", rz_unit, rz_reg, rz_mod, + 9, DEV_RDX, 8, 1, DEV_RDX, 8, + NULL, NULL, &rz_reset, + NULL, &scsi_attach, &scsi_detach, + NULL, DEV_DISABLE | DEV_DEBUG | DEV_DISK | DEV_SECTORS, + 0, rz_debug, NULL, NULL, &rz_help, NULL, NULL, + &rz_description + }; + +/* Register names for Debug tracing */ +static const char *rz_rd_regs[] = + {"TX L", "TX H", "FIFO", "CMD ", + "STAT", "INT ", "SEQ ", "FFLG", + "CFG1", "RSVD", "RSVD", "CFG2", + "CFG3", "RSVD", "RSVD", "RSVD" }; +static const char *rz_wr_regs[] = + {"TX L", "TX H", "FIFO", "CMD ", + "DST ", "TMO ", "SYNP", "SYNO", + "CFG1", "CLK ", "TEST", "CFG2", + "CFG3", "RSVD", "RSVD", "FFOB" }; + +uint8 rz_fifo_rd (void) +{ +if (rz_fifo_c) { + rz_fifo_t &= 0xF; + rz_fifo_c--; + return rz_fifo[rz_fifo_t++]; + } +else + return rz_fifo[rz_fifo_b]; +} + +void rz_fifo_wr (uint8 data) +{ +if (rz_fifo_c < 16) { + rz_fifo[rz_fifo_b++] = data; + rz_fifo_b &= 0xF; + rz_fifo_c++; + } +else { + rz_fifo[rz_fifo_b] = data; + rz_stat |= STS_GE; /* gross error */ + } +} + +void rz_fifo_reset (void) +{ +rz_fifo_c = 0; +rz_fifo_t = rz_fifo_b = 0; +rz_fifo[rz_fifo_b] = 0; +} + +/* IO dispatch routines, I/O addresses 177601x0 - 177601x7 */ + +int32 rz_rd (int32 pa) +{ +int32 data = 0; + +if (pa == 0x200C0000) { + return rz_dma; + } +if (pa == 0x200C000C) { + return rz_dir; + } + +switch ((pa >> 2) & 0xF) { /* case on PA<2:1> */ + + case 0: /* transfer counter LSB */ + data = rz_txc & 0xFF; + break; + + case 1: /* transfer counter MSB */ + data = (rz_txc >> 8) & 0xFF; + break; + + case 2: /* FIFO */ + data = rz_fifo_rd (); + break; + + case 3: /* command */ + data = rz_last_cmd; + break; + + case 4: /* status */ + data = rz_stat | rz_bus.phase; + break; + + case 5: /* interrupt */ + data = rz_int; + if (rz_stat & STS_INT) { + rz_stat &= STS_CLR; + rz_int = 0; + } + break; + + case 6: /* sequence step */ + data = rz_seq; + break; + + case 7: /* FIFO flags/seq step */ + data = (rz_seq << 5) | rz_fifo_c; + break; + + case 8: /* config 1 */ + data = rz_cfg1; + break; + + case 11: /* config 2 */ + data = rz_cfg2; + break; + + case 12: /* config 3 */ + data = rz_cfg3; + break; + + default: /* NCR reserved */ + data = 0; + break; + } + +sim_debug (DBG_REG, &rz_dev, "rz_rd(PA=0x%08X [%s], data=0x%X) at %08X\n", pa, rz_rd_regs[(pa >> 2) & 0xF], data, fault_PC); + +SET_IRQL; +return data; +} + +void rz_wr (int32 pa, int32 data, int32 access) +{ +sim_debug (DBG_REG, &rz_dev, "rz_wr(PA=0x%08X [%s], access=%d, data=0x%X) at %08X\n", pa, rz_wr_regs[(pa >> 2) & 0xF], access, data, fault_PC); + +if (pa == 0x200C0000) { + rz_dma = data; + return; + } +if (pa == 0x200C000C) { + rz_dir = data; + return; + } + +switch ((pa >> 2) & 0xF) { /* case on PA<2:1> */ + + case 0: /* transfer count LSB */ + rz_txi = (rz_txi & ~0xFF) | (data & 0xFF); + break; + + case 1: /* transfer count MSB */ + rz_txi = (rz_txi & ~0xFF00) | ((data << 8) & 0xFF00); + break; + + case 2: /* FIFO */ + rz_fifo_wr (data); + break; + + case 3: /* command */ + rz_cmd (data); + break; + + case 4: /* destination bus ID */ + rz_dest = data & 0x7; + break; + + case 5: /* select timeout - NI */ + break; + + case 6: /* sync period - NI*/ + break; + + case 7: /* sync offset - NI? */ + break; + + case 8: /* config 1 */ + rz_cfg1 = data; + break; + + case 9: /* clock conversion - NI */ + break; + + case 10: /* test - NI? */ + break; + + case 11: /* config 2 */ + rz_cfg2 = data; + break; + + case 12: /* config 3 */ + rz_cfg3 = data; + break; + + case 15: /* FIFO bottom */ + break; + + default: /* NCR reserved */ + break; + } + +SET_IRQL; +} + +/* Unit service routine */ + +t_stat rz_svc (UNIT *uptr) +{ +rz_stat |= STS_INT; +SET_INT (SC); +return SCPE_OK; +} + +void rz_setint (uint32 flag) +{ +rz_int |= flag; +sim_activate (&rz_unit[8], 50); +} + +void rz_cmd (uint32 cmd) +{ +uint32 ini = (rz_cfg1 & CFG1_MYID); +uint32 tgt = rz_dest; +uint32 state = scsi_state (&rz_bus, ini); +uint32 txc, i, old_phase; + +if ((cmd & CMD_DISC) && (state != SCSI_DISC)) { /* check cmd validity */ + sim_debug (DBG_CMD, &rz_dev, "disconnected cmd when not disconnected\n"); + rz_setint (INT_ILLCMD); + return; + } +if ((cmd & CMD_TARG) && (state != SCSI_TARG)) { + sim_debug (DBG_CMD, &rz_dev, "target cmd when not target\n"); + rz_setint (INT_ILLCMD); + return; + } +if ((cmd & CMD_INIT) && (state != SCSI_INIT)) { + sim_debug (DBG_CMD, &rz_dev, "initiator cmd when not initiator\n"); + rz_setint (INT_ILLCMD); + return; + } + +switch (cmd & 0x7f) { + + case 0: /* NOP */ + sim_debug (DBG_CMD, &rz_dev, "NOP\n"); + if (cmd & 0x80) { /* DMA */ + rz_stat &= ~STS_TC; + rz_txc = (rz_txi == 0) ? RZ_MAXFR : rz_txi; + } + break; + + case 1: /* flush FIFO */ + sim_debug (DBG_CMD, &rz_dev, "flush fifo\n"); + rz_fifo_reset (); + rz_int |= INT_FC; + break; + + case 2: /* reset chip */ + sim_debug (DBG_CMD, &rz_dev, "sw reset\n"); + rz_sw_reset (); + break; + + case 3: /* reset SCSI */ + sim_debug (DBG_CMD, &rz_dev, "SCSI reset\n"); + scsi_reset (&rz_bus); + if ((rz_cfg1 & CFG1_SRD) == 0) { + rz_setint (INT_SCSIRST); + } + break; + + case 0x20: /* send message */ + sim_debug (DBG_CMD, &rz_dev, "send message\n"); + break; + + case 0x21: /* send status */ + sim_debug (DBG_CMD, &rz_dev, "send status\n"); + break; + + case 0x22: /* send data */ + sim_debug (DBG_CMD, &rz_dev, "send data\n"); + break; + + case 0x23: /* disconnect sequence */ + sim_debug (DBG_CMD, &rz_dev, "disconnect sequence\n"); + break; + + case 0x24: /* terminate sequence */ + sim_debug (DBG_CMD, &rz_dev, "terminate sequence\n"); + break; + + case 0x25: /* target cmd complete sequence */ + sim_debug (DBG_CMD, &rz_dev, "target cmd complete sequence\n"); + break; + + case 0x27: /* disconnect */ + sim_debug (DBG_CMD, &rz_dev, "disconnect\n"); + break; + + case 0x28: /* rcv message seq */ + sim_debug (DBG_CMD, &rz_dev, "rcv message seq\n"); + break; + + case 0x29: /* rcv cmd */ + sim_debug (DBG_CMD, &rz_dev, "rcv cmd\n"); + break; + + case 0x30: /* rcv data */ + sim_debug (DBG_CMD, &rz_dev, "rcv data\n"); + break; + + case 0x31: /* rcv cmd seq */ + sim_debug (DBG_CMD, &rz_dev, "rcv cmd seq\n"); + break; + + case 0x40: /* reselect */ + sim_debug (DBG_CMD, &rz_dev, "reselect\n"); + break; + + case 0x41: /* select without ATN */ + sim_debug (DBG_CMD, &rz_dev, "select without atn\n"); + rz_seq = 0; + if (!scsi_arbitrate (&rz_bus, ini)) { + rz_seq = 0; + rz_int |= INT_DIS; /* disconnect */ + sim_activate (&rz_unit[8], 100); + break; + } + if (!scsi_select (&rz_bus, tgt)) { + rz_seq = 0; + rz_int |= INT_DIS; /* disconnect */ + scsi_release (&rz_bus); + sim_activate (&rz_unit[8], 100); + break; + } + rz_seq = 2; + for (i = 0; rz_fifo_c > 0; i++) + rz_buf[i] = rz_fifo_rd (); + scsi_write (&rz_bus, &rz_buf[0], i); + if (scsi_state (&rz_bus, tgt) == SCSI_DISC) { + rz_seq = 3; + rz_int |= INT_DIS; + } + else { + rz_seq = 4; + rz_int |= (INT_BUSSV | INT_FC); + } + sim_activate (&rz_unit[8], 50); + break; + + case 0x42: /* select with ATN */ + sim_debug (DBG_CMD, &rz_dev, "select with atn\n"); + rz_seq = 0; + if (!scsi_arbitrate (&rz_bus, ini)) { + rz_int |= INT_DIS; /* disconnect */ + sim_activate (&rz_unit[8], 100); + break; + } + scsi_set_atn (&rz_bus); + if (!scsi_select (&rz_bus, tgt)) { + rz_seq = 0; + rz_int |= INT_DIS; /* disconnect */ + scsi_release (&rz_bus); + sim_activate (&rz_unit[8], 100); + break; + } + for (i = 0; rz_fifo_c > 0; i++) + rz_buf[i] = rz_fifo_rd (); + scsi_write (&rz_bus, &rz_buf[0], i); + rz_seq = 2; + if (scsi_state (&rz_bus, tgt) == SCSI_DISC) { + rz_seq = 3; + rz_int |= INT_DIS; + } + else { + rz_seq = 4; + rz_int |= (INT_BUSSV | INT_FC); + } + sim_activate (&rz_unit[8], 50); + break; + + case 0x43: /* select with ATN and stop */ + sim_debug (DBG_CMD, &rz_dev, "select with atn and stop\n"); + if (!scsi_arbitrate (&rz_bus, ini)) { + rz_seq = 0; + rz_int |= INT_DIS; /* disconnect */ + sim_activate (&rz_unit[8], 100); + break; + } + scsi_set_atn (&rz_bus); + if (!scsi_select (&rz_bus, tgt)) { + rz_seq = 0; + rz_int |= INT_DIS; /* disconnect */ + scsi_release (&rz_bus); + sim_activate (&rz_unit[8], 100); + break; + } + rz_buf[0] = rz_fifo_rd (); + scsi_write (&rz_bus, &rz_buf[0], 1); /* send one message byte */ + if (scsi_state (&rz_bus, tgt) == SCSI_DISC) { /* disconnected? */ + rz_seq = 0; + rz_int |= INT_DIS; + } + else { + scsi_set_atn (&rz_bus); /* keep ATN asserted */ + rz_seq = 1; + rz_int |= (INT_BUSSV | INT_FC); /* continue */ + } + sim_activate (&rz_unit[8], 50); + break; + + case 0x44: /* enable selection/reselection */ + sim_debug (DBG_CMD, &rz_dev, "enable selection/reselection\n"); + break; + + case 0x46: /* select with ATN3 */ + sim_debug (DBG_CMD, &rz_dev, "select with atn3\n"); + scsi_set_atn (&rz_bus); + if (!scsi_select (&rz_bus, tgt)) { + rz_int |= INT_DIS; /* disconnect */ + scsi_release (&rz_bus); + } + sim_activate (&rz_unit[8], 50); + break; + + case 0x1A: /* set ATN */ + sim_debug (DBG_CMD, &rz_dev, "set atn\n"); + scsi_set_atn (&rz_bus); + if (rz_bus.phase == 6) { /* TODO: check this */ + rz_int |= (INT_BUSSV | INT_FC); + sim_activate (&rz_unit[8], 50); + } + break; + + case 0x1B: /* reset ATN */ + sim_debug (DBG_CMD, &rz_dev, "reset atn\n"); + scsi_release_atn (&rz_bus); + break; + + case 0x10: + sim_debug (DBG_CMD, &rz_dev, "transfer information\n"); + if (cmd & 0x80) { /* DMA */ + rz_stat &= ~STS_TC; + rz_txc = (rz_txi == 0) ? RZ_MAXFR : rz_txi; + } + old_phase = rz_bus.phase; + switch (rz_bus.phase) { + case SCSI_DATO: /* data out */ + case SCSI_CMD: /* command */ + case SCSI_MSGO: /* message out */ + if (rz_bus.phase == 6) + scsi_release_atn (&rz_bus); + if (cmd & 0x80) { /* DMA */ + RZ_READB (rz_dma, rz_txc, &rz_buf[0]); + txc = scsi_write (&rz_bus, &rz_buf[0], rz_txc); + rz_txc -= txc; + if (rz_txc == 0) + rz_stat |= STS_TC; + } + else { + for (txc = 0; rz_fifo_c > 0; txc++) + rz_buf[txc] = rz_fifo_rd (); + txc = scsi_write (&rz_bus, &rz_buf[0], txc); + } + break; + + case SCSI_DATI: /* data in */ + case SCSI_STS: /* status */ + case SCSI_MSGI: /* message in */ + if (cmd & 0x80) { /* DMA */ + while ((rz_bus.phase == old_phase) && (rz_txc != 0)) { + txc = scsi_read (&rz_bus, &rz_buf[0], rz_txc); + RZ_WRITEB (rz_dma, txc, &rz_buf[0]); + rz_txc -= txc; + } + if (rz_txc == 0) + rz_stat |= STS_TC; + } + else { + txc = scsi_read (&rz_bus, &rz_buf[0], 1); + rz_fifo_wr (rz_buf[0]); + } + break; + } + rz_seq = 0; + if (scsi_state (&rz_bus, tgt) == SCSI_DISC) { + rz_int |= INT_DIS; + } + else { + if (rz_bus.req) + rz_int |= INT_BUSSV; + if (rz_bus.phase == SCSI_MSGI) + rz_int |= INT_FC; + } + sim_activate (&rz_unit[8], 50); + break; + + case 0x11: + sim_debug (DBG_CMD, &rz_dev, "initiator command complete\n"); + txc = 0; + txc += scsi_read (&rz_bus, &rz_buf[0], 1); + txc += scsi_read (&rz_bus, &rz_buf[1], 1); + rz_fifo_wr (rz_buf[0]); + rz_fifo_wr (rz_buf[1]); + rz_seq = 0; + rz_int |= INT_FC; + sim_activate (&rz_unit[8], 50); + break; + + case 0x12: + sim_debug (DBG_CMD, &rz_dev, "message accepted\n"); + scsi_release (&rz_bus); + rz_seq = 0; + rz_int |= INT_DIS; + sim_activate (&rz_unit[8], 50); + break; + + case 0x18: + sim_debug (DBG_CMD, &rz_dev, "transfer pad\n"); + if (cmd & 0x80) { /* DMA */ + rz_stat &= ~STS_TC; + rz_txc = (rz_txi == 0) ? RZ_MAXFR : rz_txi; + } + old_phase = rz_bus.phase; + switch (rz_bus.phase) { + case SCSI_DATO: /* data out */ + case SCSI_CMD: /* command */ + case SCSI_MSGO: /* message out */ + if (rz_bus.phase == 6) + scsi_release_atn (&rz_bus); + rz_buf[0] = 0; + for (; ((rz_bus.phase == old_phase) && (rz_txc > 0)); rz_txc--) + scsi_write (&rz_bus, &rz_buf[0], 1); + if (rz_txc == 0) + rz_stat |= STS_TC; + break; + + case SCSI_DATI: /* data in */ + case SCSI_STS: /* status */ + case SCSI_MSGI: /* message in */ + for (; ((rz_bus.phase == old_phase) && (rz_txc > 0)); rz_txc--) + txc = scsi_read (&rz_bus, &rz_buf[0], 1); + if (rz_txc == 0) + rz_stat |= STS_TC; + break; + } + rz_seq = 0; + if (scsi_state (&rz_bus, tgt) == SCSI_DISC) + rz_int |= INT_DIS; + else { + if (rz_bus.req) + rz_int |= INT_BUSSV; + /* if (rz_bus.phase == SCSI_MSGI) */ + rz_int |= INT_FC; + } + sim_activate (&rz_unit[8], 50); + break; + + default: + sim_debug (DBG_CMD, &rz_dev, "unknown command %X\n", cmd); + break; + } +if (cmd > 0) + rz_last_cmd = cmd; +} + +void rz_sw_reset () +{ +uint32 i; + +for (i = 0; i < 9; i++) + sim_cancel (&rz_unit[i]); +rz_txc = 0; +rz_cfg1 = rz_cfg1 & 0x7; +rz_cfg2 = 0; +rz_cfg3 = 0; +rz_stat = 0; +rz_seq = 0; +rz_int = 0; +rz_dest = 0; +rz_fifo_reset (); +CLR_INT (SC); +scsi_reset (&rz_bus); +} + +t_stat rz_reset (DEVICE *dptr) +{ +uint32 i; +uint32 dtyp; +UNIT *uptr; +t_stat r; + +if (rz_buf == NULL) + rz_buf = (uint8 *)calloc (RZ_MAXFR, sizeof(uint8)); +if (rz_buf == NULL) + return SCPE_MEM; +r = scsi_init (&rz_bus, RZ_MAXFR); /* init SCSI bus */ +if (r != SCPE_OK) + return r; +rz_bus.dptr = dptr; /* set bus device */ +for (i = 0; i < 8; i++) { + uptr = dptr->units + i; + if (i == RZ_SCSI_ID) /* initiator ID? */ + uptr->flags = UNIT_DIS; /* disable unit */ + scsi_add_unit (&rz_bus, i, &rz_unit[i]); + dtyp = GET_DTYPE (rz_unit[i].flags); + scsi_set_unit (&rz_bus, &rz_unit[i], &rzdev_tab[dtyp]); + scsi_reset_unit (&rz_unit[i]); + } +rz_sw_reset (); +return SCPE_OK; +} + +/* Set unit type (and capacity if user defined) */ + +t_stat rz_set_type (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +uint32 cap; +uint32 max = sim_toffset_64? RZU_EMAXC: RZU_MAXC; +t_stat r; + +if ((val < 0) || ((val != RZU_DTYPE) && cptr)) + return SCPE_ARG; +if (uptr->flags & UNIT_ATT) + return SCPE_ALATT; +if (cptr) { + cap = (uint32) get_uint (cptr, 10, 0xFFFFFFFF, &r); + if ((sim_switches & SWMASK ('L')) == 0) + cap = cap * 1954; + if ((r != SCPE_OK) || (cap < RZU_MINC) || (cap > max)) + return SCPE_ARG; + rzdev_tab[val].lbn = cap; + } +uptr->flags = (uptr->flags & ~UNIT_DTYPE) | (val << UNIT_V_DTYPE); +uptr->capac = (t_addr)rzdev_tab[val].lbn; +return SCPE_OK; +} + +/* Show unit type */ + +t_stat rz_show_type (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ +fprintf (st, "%s", rzdev_tab[GET_DTYPE (uptr->flags)].name); +return SCPE_OK; +} + +t_stat rz_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "NCR 53C94 SCSI Controller (%s)\n\n", dptr->name); +fprintf (st, "The %s controller simulates the NCR 53C94 SCSI controller connected\n", dptr->name); +fprintf (st, "to a bus with up to 7 target devices.\n"); +if (dptr->flags & DEV_DISABLE) + fprintf (st, "Initially the %s controller is disabled.\n", dptr->name); +else + fprintf (st, "The %s controller cannot be disabled.\n", dptr->name); +fprintf (st, "SCSI target device %s%d is reserved for the initiator and cannot\n", dptr->name, RZ_SCSI_ID); +fprintf (st, "be enabled\n"); +fprintf (st, "Each target on the SCSI bus can be set to one of several types:\n"); +fprint_set_help (st, dptr); +fprintf (st, "Configured options can be displayed with:\n\n"); +fprint_show_help (st, dptr); +fprint_reg_help (st, dptr); +scsi_help (st, dptr, uptr, flag, cptr); +return SCPE_OK; +} + +const char *rz_description (DEVICE *dptr) +{ +return "NCR 53C94 SCSI controller"; +} diff --git a/VAX/vax4xx_stddev.c b/VAX/vax4xx_stddev.c new file mode 100644 index 00000000..b17d8eed --- /dev/null +++ b/VAX/vax4xx_stddev.c @@ -0,0 +1,563 @@ +/* vax4xx_stddev.c: KA4xx standard devices + + Copyright (c) 2019, Matt Burke + This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + rom bootstrap ROM (no registers) + nvr non-volatile ROM (no registers) + or option ROMs (no registers) + clk 100Hz and TODR clock +*/ + +#include "vax_defs.h" +#include + +#define UNIT_V_NODELAY (UNIT_V_UF + 0) /* ROM access equal to RAM access */ +#define UNIT_NODELAY (1u << UNIT_V_NODELAY) + +#define CLKCSR_IMP (CSR_IE) /* real-time clock */ +#define CLKCSR_RW (CSR_IE) +#define CLK_DELAY 5000 /* 100 Hz */ +#define TMXR_MULT 1 /* 100 Hz */ + +uint32 *rom = NULL; /* boot ROM */ +uint32 *nvr = NULL; /* non-volatile mem */ +int32 clk_csr = 0; /* control/status */ +int32 clk_tps = 100; /* ticks/second */ +int32 tmr_int = 0; /* interrupt */ +int32 tmxr_poll = CLK_DELAY * TMXR_MULT; /* term mux poll */ +int32 tmr_poll = CLK_DELAY; /* pgm timer poll */ + +t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat rom_reset (DEVICE *dptr); +t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *rom_description (DEVICE *dptr); +t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat nvr_reset (DEVICE *dptr); +t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +t_stat nvr_attach (UNIT *uptr, CONST char *cptr); +t_stat nvr_detach (UNIT *uptr); +const char *nvr_description (DEVICE *dptr); +t_stat or_reset (DEVICE *dptr); +t_stat or_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *or_description (DEVICE *dptr); +t_stat clk_svc (UNIT *uptr); +t_stat clk_reset (DEVICE *dptr); +const char *clk_description (DEVICE *dptr); + +extern int32 sysd_hlt_enb (void); +extern int32 wtc_rd (int32 rg); +extern void wtc_wr (int32 rg, int32 val); +extern void wtc_set_valid (void); +extern void wtc_set_invalid (void); + +/* ROM data structures + + rom_dev ROM device descriptor + rom_unit ROM units + rom_reg ROM register list +*/ + +UNIT rom_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, ROMSIZE) }; + +REG rom_reg[] = { + { NULL } + }; + +MTAB rom_mod[] = { + { UNIT_NODELAY, UNIT_NODELAY, "fast access", "NODELAY", NULL, NULL, NULL, "Disable calibrated ROM access speed" }, + { UNIT_NODELAY, 0, "1usec calibrated access", "DELAY", NULL, NULL, NULL, "Enable calibrated ROM access speed" }, + { 0 } + }; + +DEVICE rom_dev = { + "ROM", &rom_unit, rom_reg, rom_mod, + 1, 16, ROMAWIDTH, 4, 16, 32, + &rom_ex, &rom_dep, &rom_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, &rom_help, NULL, NULL, + &rom_description + }; + +/* NVR data structures + + nvr_dev NVR device descriptor + nvr_unit NVR units + nvr_reg NVR register list +*/ + +UNIT nvr_unit = + { UDATA (NULL, UNIT_FIX+UNIT_BINK, NVRSIZE) }; + +REG nvr_reg[] = { + { NULL } + }; + +DEVICE nvr_dev = { + "NVR", &nvr_unit, nvr_reg, NULL, + 1, 16, NVRAWIDTH, 4, 16, 32, + &nvr_ex, &nvr_dep, &nvr_reset, + NULL, &nvr_attach, &nvr_detach, + NULL, 0, 0, NULL, NULL, NULL, &nvr_help, NULL, NULL, + &nvr_description + }; + +/* OR data structures + + or_dev OR device descriptor + or_unit OR unit descriptor + or_reg OR register list +*/ + +UNIT or_unit[] = { + { UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) }, + { UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) }, + { UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) }, + { UDATA (NULL, UNIT_FIX+UNIT_RO+UNIT_BINK, ORSIZE) } + }; + +REG or_reg[] = { + { NULL } + }; + +DEVICE or_dev = { + "OR", or_unit, or_reg, NULL, + OR_COUNT, 16, ORAWIDTH, 4, 16, 32, + NULL, NULL, &or_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, &or_help, NULL, NULL, + &or_description + }; + +/* CLK data structures + + clk_dev CLK device descriptor + clk_unit CLK unit descriptor + clk_reg CLK register list +*/ + +UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY }; + +REG clk_reg[] = { + { HRDATAD (CSR, clk_csr, 16, "control/status register") }, + { FLDATAD (INT, tmr_int, 0, "interrupt request") }, + { FLDATAD (IE, clk_csr, CSR_V_IE, "interrupt enable flag (CSR<6>)") }, + { DRDATAD (TIME, clk_unit.wait, 24, "initial poll interval"), REG_NZ + PV_LEFT }, + { DRDATAD (POLL, tmr_poll, 24, "calibrated poll interval"), REG_NZ + PV_LEFT + REG_HRO }, + { DRDATAD (TPS, clk_tps, 8, "ticks per second (100)"), REG_NZ + PV_LEFT }, +#if defined (SIM_ASYNCH_IO) + { DRDATAD (ASYNCH, sim_asynch_enabled, 1, "asynch I/O enabled flag"), PV_LEFT }, + { DRDATAD (LATENCY, sim_asynch_latency, 32, "desired asynch interrupt latency"), PV_LEFT }, + { DRDATAD (INST_LATENCY, sim_asynch_inst_latency, 32, "calibrated instruction latency"), PV_LEFT }, +#endif + { NULL } + }; + +DEVICE clk_dev = { + "CLK", &clk_unit, clk_reg, NULL, + 1, 0, 0, 0, 0, 0, + NULL, NULL, &clk_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, + &clk_description + }; + +/* ROM: read only memory - stored in a buffered file + Register space access routines see ROM twice + + ROM access has been 'regulated' to about 1Mhz to avoid issues + with testing the interval timers in self-test. Specifically, + the VAX boot ROM (ka4xx.bin) contains code which presumes that + the VAX runs at a particular slower speed when code is running + from ROM (which is not cached). These assumptions are built + into instruction based timing loops. As the host platform gets + much faster than the original VAX, the assumptions embedded in + these code loops are no longer valid. + + Code has been added to the ROM implementation to limit CPU speed + to about 500K instructions per second. This heads off any future + issues with the embedded timing loops. +*/ + +int32 rom_rd (int32 pa) +{ +int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2; +int32 val = rom[rg]; + +if (rom_unit.flags & UNIT_NODELAY) + return val; + +return sim_rom_read_with_delay (val); +} + +void rom_wr_B (int32 pa, int32 val) +{ +int32 rg = ((pa - ROMBASE) & ROMAMASK) >> 2; +int32 sc = (pa & 3) << 3; + +rom[rg] = ((val & 0xFF) << sc) | (rom[rg] & ~(0xFF << sc)); +return; +} + +/* ROM examine */ + +t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if ((vptr == NULL) || (addr & 03)) + return SCPE_ARG; +if (addr >= ROMSIZE) + return SCPE_NXM; +*vptr = rom[addr >> 2]; +return SCPE_OK; +} + +/* ROM deposit */ + +t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if (addr & 03) + return SCPE_ARG; +if (addr >= ROMSIZE) + return SCPE_NXM; +rom[addr >> 2] = (uint32) val; +return SCPE_OK; +} + +/* ROM reset */ + +t_stat rom_reset (DEVICE *dptr) +{ +if (rom == NULL) + rom = (uint32 *) calloc (ROMSIZE >> 2, sizeof (uint32)); +if (rom == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +t_stat rom_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Read-only memory (ROM)\n\n"); +fprintf (st, "The boot ROM consists of a single unit, simulating the 256KB boot ROM. It has\n"); +fprintf (st, "no registers. The boot ROM is loaded with a binary byte stream using the \n"); +fprintf (st, "LOAD -r command:\n\n"); +fprintf (st, " LOAD -r KA410.BIN load ROM image KA410.BIN\n\n"); +fprintf (st, "When the simulator starts running (via the BOOT command), if the ROM has\n"); +fprintf (st, "not yet been loaded, an attempt will be made to automatically load the\n"); +fprintf (st, "ROM image from the file ka410.bin in the current working directory.\n"); +fprintf (st, "If that load attempt fails, then a copy of the missing ROM file is\n"); +fprintf (st, "written to the current directory and the load attempt is retried.\n\n"); +fprintf (st, "ROM accesses a use a calibrated delay that slows ROM-based execution to\n"); +fprintf (st, "about 500K instructions per second. This delay is required to make the\n"); +fprintf (st, "power-up self-test routines run correctly on very fast hosts.\n"); +fprint_set_help (st, dptr); +return SCPE_OK; +} + +const char *rom_description (DEVICE *dptr) +{ +return "read-only memory"; +} + +/* NVR: non-volatile RAM - stored in a buffered file */ + +int32 nvr_rd (int32 pa) +{ +int32 rg = (pa - NVRBASE) >> 2; +int32 val; + +if (rg < 14) /* watch chip */ + val = wtc_rd (rg); +else + val = nvr[rg]; +return (val << 2); +} + +void nvr_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa - NVRBASE) >> 2; +val = val >> 2; +if (rg < 14) /* watch chip */ + wtc_wr (rg, val); +else { + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = 0xFF; + nvr[rg] = ((val & mask) << sc) | (nvr[rg] & ~(mask << sc)); + } +} + +/* NVR examine */ + +t_stat nvr_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if ((vptr == NULL) || (addr & 03)) + return SCPE_ARG; +if (addr >= NVRSIZE) + return SCPE_NXM; +*vptr = nvr[addr >> 2]; +return SCPE_OK; +} + +/* NVR deposit */ + +t_stat nvr_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if (addr & 03) + return SCPE_ARG; +if (addr >= NVRSIZE) + return SCPE_NXM; +nvr[addr >> 2] = (uint32) val; +return SCPE_OK; +} + +/* NVR reset */ + +t_stat nvr_reset (DEVICE *dptr) +{ +if (nvr == NULL) { + nvr = (uint32 *) calloc (NVRSIZE >> 2, sizeof (uint32)); + nvr_unit.filebuf = nvr; + } +if (nvr == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +t_stat nvr_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Non-volatile Memory (NVR)\n\n"); +fprintf (st, "The NVR simulates %d bytes of battery-backed up memory.\n", NVRSIZE); +fprintf (st, "When the simulator starts, NVR is cleared to 0, and the battery-low indicator\n"); +fprintf (st, "is set. Alternately, NVR can be attached to a file. This allows the NVR\n"); +fprintf (st, "state to be preserved across simulator runs. Successfully attaching an NVR\n"); +fprintf (st, "image clears the battery-low indicator.\n\n"); +return SCPE_OK; +} + +/* NVR attach */ + +t_stat nvr_attach (UNIT *uptr, CONST char *cptr) +{ +t_stat r; + +uptr->flags = uptr->flags | (UNIT_ATTABLE | UNIT_BUFABLE); +r = attach_unit (uptr, cptr); +if (r != SCPE_OK) + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); +else { + uptr->hwmark = (uint32) uptr->capac; + wtc_set_valid (); + } +return r; +} + +/* NVR detach */ + +t_stat nvr_detach (UNIT *uptr) +{ +t_stat r; + +r = detach_unit (uptr); +if ((uptr->flags & UNIT_ATT) == 0) { + uptr->flags = uptr->flags & ~(UNIT_ATTABLE | UNIT_BUFABLE); + wtc_set_invalid (); + } +return r; +} + +const char *nvr_description (DEVICE *dptr) +{ +return "non-volatile memory"; +} + +/* OR routines + + or_rd I/O page read + or_reset process reset +*/ + +int32 or_rd (int32 pa) +{ +uint32 off = (pa - ORBASE); /* offset from start of option roms */ +uint32 rn = ((off >> 18) & 0x3); /* rom number (0 - 3) */ +UNIT *uptr = &or_dev.units[rn]; /* get unit */ +uint8 *opr = (uint8*) uptr->filebuf; +int32 data = 0; +uint32 rg; + +if ((uptr->flags & UNIT_ATT) && (opr != NULL)) { + switch (opr[0]) { /* number of ROM chips */ + case 1: + rg = (off >> 2) & (uptr->capac - 1); + data = (0xFFFFFF00 | (opr[rg] & 0xFF)); + return sim_rom_read_with_delay (data); + + case 2: + rg = (off >> 1) & (uptr->capac - 1); + data = data | opr[rg++]; + data = data | (opr[rg] << 8); + data = (0xFFFF0000 | data); + return sim_rom_read_with_delay (data); + + case 4: + rg = off & (uptr->capac - 1); + data = data | opr[rg++]; + data = data | (opr[rg++] << 8); + data = data | (opr[rg++] << 16); + data = data | (opr[rg++] << 24); + return sim_rom_read_with_delay (data); + } + } +return sim_rom_read_with_delay (0xFFFFFFFF); +} + +t_stat or_reset (DEVICE *dptr) +{ +return SCPE_OK; +} + +t_stat or_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Option ROMs (OR)\n\n"); +fprintf (st, "The OR simulates the read only memory present on option boards.\n"); +fprintf (st, "These ROMs contain the self-test code that is called by the main\n"); +fprintf (st, "ROM during system power up. The system uses these ROMs to determine\n"); +fprintf (st, "which option boards are present.\n"); +return SCPE_OK; +} + +t_stat or_map (uint32 index, uint8 *rom, t_addr size) +{ +UNIT *uptr = &or_unit[index]; +uptr->filebuf = (void *)rom; +uptr->capac = size; +uptr->flags |= UNIT_ATT; +return SCPE_OK; +} + +t_stat or_unmap (uint32 index) +{ +UNIT *uptr = &or_unit[index]; +uptr->filebuf = NULL; +uptr->capac = 0; +uptr->flags &= ~UNIT_ATT; +return SCPE_OK; +} + +const char *or_description (DEVICE *dptr) +{ +return "option ROMs"; +} + +/* Clock MxPR routines + + iccs_rd/wr interval timer +*/ + +int32 iccs_rd (void) +{ +return (clk_csr & CLKCSR_IMP); +} + +void iccs_wr (int32 data) +{ +if ((data & CSR_IE) == 0) + tmr_int = 0; +if (data & CSR_DONE) + sim_rtcn_tick_ack (20, TMR_CLK); +clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW); +return; +} + +/* Clock routines + + clk_svc process event (clock tick) + clk_reset process reset + clk_description return device description +*/ + +t_stat clk_svc (UNIT *uptr) +{ +int32 t; + +if (clk_csr & CSR_IE) + tmr_int = 1; +t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */ +sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */ +return SCPE_OK; +} + +/* Reset routine */ + +t_stat clk_reset (DEVICE *dptr) +{ +int32 t; + +clk_csr = 0; +tmr_int = 0; +t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */ +sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */ +tmr_poll = t; /* set tmr poll */ +tmxr_poll = t * TMXR_MULT; /* set mux poll */ +return SCPE_OK; +} + +const char *clk_description (DEVICE *dptr) +{ +return "100hz clock tick"; +} + +/* Dummy I/O space functions */ + +int32 ReadIO (uint32 pa, int32 lnt) +{ +return 0; +} + +void WriteIO (uint32 pa, int32 val, int32 lnt) +{ +return; +} + +int32 ReadIOU (uint32 pa, int32 lnt) +{ +return 0; +} + +void WriteIOU (uint32 pa, int32 val, int32 lnt) +{ +return; +} diff --git a/VAX/vax4xx_va.c b/VAX/vax4xx_va.c new file mode 100644 index 00000000..b6e58333 --- /dev/null +++ b/VAX/vax4xx_va.c @@ -0,0 +1,1415 @@ +/* vax4xx_va.c: GPX video simulator + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + va GPX colour video +*/ + +#include "vax_defs.h" +#include "sim_video.h" +#include "vax_gpx.h" +#include "vax_lk.h" +#include "vax_vs.h" + +#if VA_PLANES == 4 +#include "vax_ka4xx_4pln_bin.h" +#else +#include "vax_ka4xx_8pln_bin.h" +#define BT458 1 +#endif + +#define VA_ADP_OF 0x0000 /* address processor */ +#define VA_FCC_OF 0x0100 /* FIFO compression chip */ +#define VA_DAC_OF 0x0180 /* D/A converter */ +#define VA_CCR_OF 0x0200 /* cursor chip */ +#define VA_CBR_OF 0x0280 /* colour board readback */ +#define VA_FFW_OF 0x4000 /* FIFO window */ + +#define VA_TMP_OF 0x40 + +#define INT_FCC 1 + +#define CUR_X_OF 216 +#define CUR_Y_OF 33 + +#define CMD_TEST 0x8000 +#define CMD_HSHI 0x4000 +#define CMD_VBHI 0x2000 +#define CMD_LODSA 0x1000 +#define CMD_FORG2 0x0800 +#define CMD_ENRG2 0x0400 +#define CMD_FORG1 0x0200 +#define CMD_ENRG1 0x0100 +#define CMD_XHWID 0x0080 +#define CMD_XHCL1 0x0040 +#define CMD_XHCLP 0x0020 +#define CMD_XHAIR 0x0010 +#define CMD_FOPB 0x0008 +#define CMD_ENPB 0x0004 +#define CMD_FOPA 0x0002 +#define CMD_ENPA 0x0001 + +#define CUR_X ((va_xpos < CUR_X_OF) ? 0 : (va_xpos - CUR_X_OF)) +#define CUR_Y ((va_ypos < CUR_Y_OF) ? 0 : (va_ypos - CUR_Y_OF)) +#define CUR_V ((va_ccmd & CMD_LODSA) == 0) +#define CUR_F (0) + +#define CUR_PLNA 0 +#define CUR_PLNB 16 + +#if defined(BT458) +#define CUR_COL 4 +#define CUR_HOT (VA_BPP + 1) +#define CUR_BG (VA_BPP + 2) +#define CUR_FG (VA_BPP + 3) +#else +#define CUR_COL 8 +#define CUR_HOT (VA_BPP + VA_BPP + 1) +#define CUR_BG (VA_BPP + VA_BPP + 2) +#define CUR_FG (VA_BPP + VA_BPP + 3) +#endif + +#define RAM_SIZE (1u << 16) /* FIFO RAM */ + +#define FCCCSR_PACK 0x0100 /* byte/word */ +#define FCCCSR_WR 0x5F83 +#define FCCCSR_V_MODE 9 +#define FCCCSR_M_MODE 0x3 +#define GET_MODE(x) ((x >> FCCCSR_V_MODE) & FCCCSR_M_MODE) + +#define MODE_HALT 0 +#define MODE_DL 1 +#define MODE_BTP 2 +#define MODE_PTB 3 + +/* Debugging Bitmaps */ + +#define DBG_FCC 0x0001 /* fifo compression chip activity */ +#define DBG_CURSOR 0x0002 /* Cursor content, function and visibility activity */ + +/* FIFO compression chip registers */ + +#define FCC_CCSR 0x0 /* colour board CSR */ +#define FCC_ICSR 0x1 /* interrupt CSR */ +#define FCC_FCSR 0x2 /* FIFO CSR */ +#define FCC_FWU 0x3 /* FIFO words used */ +#define FCC_FT 0x4 /* FIFO threshold */ +#define FCC_RSVD 0x5 /* reserved */ +#define FCC_PUT 0x6 /* FIFO put pointer */ +#define FCC_GET 0x7 /* FIFO get pointer */ +#define FCC_DIAG 0x8 /* diag */ +#define FCC_CMPA 0x9 /* CMPA */ +#define FCC_CMPB 0xA /* CMPB */ +#define FCC_CMPC 0xB /* CPMC - PLA address */ +#define FCC_MAXREG 0xB + +extern int32 int_req[IPL_HLVL]; +extern int32 tmxr_poll; /* calibrated delay */ +extern int32 fault_PC; +extern int32 trpirq; + +uint16 va_ram[RAM_SIZE]; + +uint32 va_fcc_csr = 0; +uint32 va_fcc_int = 0; +uint32 va_fcc_fcsr = 0; +uint32 va_fcc_data = 0; +uint32 va_fcc_sc = 0; +int32 va_fcc_fifo_sz = 0; /* data size */ +int32 va_fcc_fifo_th = 0; /* threshold */ +uint32 va_fcc_fifo_wp = 0; /* write pointer */ +uint32 va_fcc_fifo_rp = 0; /* read pointer */ + +uint32 va_ccmd = 0; /* cursor command reg */ +uint32 va_xpos = 0; /* cursor x position */ +uint32 va_ypos = 0; /* cursor y position */ +uint32 va_xmin1 = 0; /* region 1 left edge */ +uint32 va_xmax1 = 0; /* region 1 right edge */ +uint32 va_ymin1 = 0; /* region 1 top edge */ +uint32 va_ymax1 = 0; /* region 1 bottom edge */ +uint32 va_xmin2 = 0; /* region 2 left edge */ +uint32 va_xmax2 = 0; /* region 2 right edge */ +uint32 va_ymin2 = 0; /* region 2 top edge */ +uint32 va_ymax2 = 0; /* region 2 bottom edge */ +uint16 va_cur[32]; /* cursor image data */ +uint32 va_cur_p = 0; /* cursor image pointer */ + +uint32 va_cur_x = 0; /* Last cursor X-position */ +uint32 va_cur_y = 0; /* Last cursor Y-position */ +uint32 va_cur_f = 0; /* Last cursor function */ +t_bool va_cur_v = FALSE; /* Last cursor visible */ + +t_bool va_active = FALSE; +t_bool va_updated[2048]; +t_bool va_input_captured = FALSE; /* Mouse and Keyboard input captured in video window */ +uint32 *va_buf = NULL; /* Video memory */ +uint32 *va_lines = NULL; /* Video Display Lines */ +#if defined(BT458) +uint32 va_palette[VA_BPP + CUR_COL]; /* Colour palette (screen, cursor)*/ +uint32 va_cmap2[VA_BPP + CUR_COL]; /* Colour palette (screen, cursor)*/ +#else +uint32 va_palette[VA_BPP + VA_BPP + CUR_COL]; /* Colour palette (fg, bg, cursor)*/ +#endif + +uint32 va_dla = 0; /* display list addr */ +int32 va_yoff = 0; +int32 va_dpln = 0; +uint32 va_white = 0; +uint32 va_black = 0; + +uint32 va_bt458_addr = 0; +uint32 va_cmap_p = 0; +uint32 va_cmap[3]; + +const char *va_fcc_rgd[] = { /* FIFO compression chip registers */ + "Colour Board CSR", + "Interrupt CSR", + "FIFO CSR", + "FIFO Words Used", + "FIFO Threshold", + "Reserved", + "FIFO Put Pointer", + "FIFO Get Pointer", + "Diag", + "CMPA", + "CMPB", + "CMPC - PLA Address" + }; + +const char *va_dac_rgd[] = { /* D/A converter registers */ + "Active Region Colour 0", + "Active Region Colour 1", + "Active Region Colour 2", + "Active Region Colour 3", + "Active Region Colour 4", + "Active Region Colour 5", + "Active Region Colour 6", + "Active Region Colour 7", + "Active Region Colour 8", + "Active Region Colour 9", + "Active Region Colour 10", + "Active Region Colour 11", + "Active Region Colour 12", + "Active Region Colour 13", + "Active Region Colour 14", + "Active Region Colour 15", + "Background Colour 0", + "Background Colour 1", + "Background Colour 2", + "Background Colour 3", + "Background Colour 4", + "Background Colour 5", + "Background Colour 6", + "Background Colour 7", + "Background Colour 8", + "Background Colour 9", + "Background Colour 10", + "Background Colour 11", + "Background Colour 12", + "Background Colour 13", + "Background Colour 14", + "Background Colour 15", + "Reserved", + "Active Cursor Colour A", + "Active Cursor Colour B", + "Active Cursor Colour C", + "Reserved", + "Background Cursor Colour A", + "Background Cursor Colour B", + "Background Cursor Colour C", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Mode", + "Delay Adjust - Sync", + "Delay Adjust - Blank", + "Delay Adjust - Active Region" + }; + +const char *va_ccr_rgd[] = { /* cusror chip registers */ + "Command Register", + "X Position", + "Y Position", + "X Minimum 1", + "X Maximum 1", + "Y Minimum 1", + "Y Maximum 1", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "X Minimum 2", + "X Maximum 2", + "Y Minimum 2", + "Y Maximum 2", + "Cursor Bitmap" + }; + +t_stat va_svc (UNIT *uptr); +t_stat va_dmasvc (UNIT *uptr); +t_stat va_reset (DEVICE *dptr); +t_stat va_attach (UNIT *uptr, CONST char *cptr); +t_stat va_detach (UNIT *uptr); +t_stat va_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat va_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat va_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc); +t_stat va_set_yoff (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat va_show_yoff (FILE* st, UNIT* uptr, int32 val, CONST void* desc); +t_stat va_set_dpln (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat va_show_dpln (FILE* st, UNIT* uptr, int32 val, CONST void* desc); +t_stat va_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *va_description (DEVICE *dptr); +void va_dlist (void); + +extern int32 eval_int (void); + +/* GPX data structures + + va_dev GPX device descriptor + va_unit GPX unit list + va_reg GPX register list + va_mod GPX modifier list +*/ + +DIB va_dib = { + VA_ROM_INDEX, BOOT_CODE_ARRAY, BOOT_CODE_SIZE + }; + +UNIT va_unit[] = { + { UDATA (&va_svc, UNIT_IDLE, 0) }, + { UDATA (&va_dmasvc, UNIT_IDLE+UNIT_DIS, 0) }, + }; + +REG va_reg[] = { + { HRDATAD (AADCT, va_adp[ADP_ADCT], 16, "address counter") }, + { HRDATAD (AREQ, va_adp[ADP_REQ], 16, "request enable") }, + { HRDATAD (AINT, va_adp[ADP_INT], 16, "interrupt enable") }, + { HRDATAD (ASTAT, va_adp[ADP_STAT], 16, "status") }, + { HRDATAD (AMDE, va_adp[ADP_MDE], 16, "mode") }, + { NULL } + }; + +MTAB va_mod[] = { + { MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLE", + &va_set_enable, NULL, NULL, "Enable GPX" }, + { MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLE", + &va_set_enable, NULL, NULL, "Disable GPX" }, + { MTAB_XTD|MTAB_VDV, TRUE, NULL, "CAPTURE", + &va_set_capture, &va_show_capture, NULL, "Enable Captured Input Mode" }, + { MTAB_XTD|MTAB_VDV, FALSE, NULL, "NOCAPTURE", + &va_set_capture, NULL, NULL, "Disable Captured Input Mode" }, + { MTAB_XTD|MTAB_VDV, TRUE, "OSCURSOR", NULL, + NULL, &va_show_capture, NULL, "Display Input Capture mode" }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "VIDEO", NULL, + NULL, &vid_show_video, NULL, "Display the host system video capabilities" }, + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "OFFSET", "OFFSET=n", + &va_set_yoff, &va_show_yoff, NULL, "Display the Y offset" }, + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "DPLANE", "DPLANE=n", + &va_set_dpln, &va_show_dpln, NULL, "Display the debug plane" }, + { 0 } + }; + +DEVICE va_dev = { + "VA", va_unit, va_reg, va_mod, + 2, DEV_RDX, 20, 1, DEV_RDX, 8, + NULL, NULL, &va_reset, + NULL, NULL, &va_detach, + &va_dib, DEV_DIS, 0, + NULL, NULL, NULL, &va_help, NULL, NULL, + &va_description + }; + +void va_fcc_fifo_clr (void) +{ +sim_debug (DBG_FCC, &va_dev, "fcc_fifo_clr\n"); +va_fcc_fifo_wp = 0; /* reset pointers */ +va_fcc_fifo_rp = 0; +va_fcc_fifo_sz = 0; /* empty */ +} + +void va_fcc_fifo_wr (uint32 val) +{ +sim_debug (DBG_FCC, &va_dev, "fcc_fifo_wr: %d, %X (%d) at %08X\n", va_fcc_fifo_wp, val, (va_fcc_fifo_sz + 1), fault_PC); +if (va_fcc_fifo_sz == RAM_SIZE) { /* writing full fifo? */ + sim_debug (DBG_FCC, &va_dev, "fcc fifo overflow\n"); + return; /* should not get here */ + } +va_ram[va_fcc_fifo_wp++] = val; /* store value */ +if (va_fcc_fifo_wp == RAM_SIZE) /* pointer wrap? */ + va_fcc_fifo_wp = 0; +va_fcc_fifo_sz++; +} + +uint32 va_fcc_fifo_rd (void) +{ +uint32 val; + +if (va_fcc_fifo_sz == 0) { /* reading empty fifo */ + sim_debug (DBG_FCC, &va_dev, "fcc fifo underflow\n"); + return 0; /* should not get here */ + } +val = va_ram[va_fcc_fifo_rp++]; /* get value */ +sim_debug (DBG_FCC, &va_dev, "fcc_fifo_rd: %d, %X (%d) at %08X\n", (va_fcc_fifo_rp - 1), val, va_fcc_fifo_sz, fault_PC); +if (va_fcc_fifo_rp == RAM_SIZE) /* pointer wrap? */ + va_fcc_fifo_rp = 0; +va_fcc_fifo_sz--; +if (va_fcc_fifo_sz == 0) + va_fcc_fifo_clr (); +return val; +} + +void va_ccr_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = (pa >> 1) & 0x1F; + +if (rg <= 0xF) + sim_debug (DBG_REG, &va_dev, "ccr_wr: %s, %X at %08X\n", va_ccr_rgd[rg], val, fault_PC); +else + sim_debug (DBG_REG, &va_dev, "ccr_wr: %X, %X at %08X\n", rg, val, fault_PC); + +switch (rg) { + + case 0: /* CUR_CMD */ +#if 0 + if ((val & CMD_TEST) == 0) { + if (val & (CMD_ENRG2|CMD_FORG2|CMD_ENRG1|CMD_FORG1|CMD_FOPB|CMD_FOPA)) + ka_cfgtst = ka_cfgtst & ~(1 << 4); + else ka_cfgtst = ka_cfgtst | (1 << 4); + } + else ka_cfgtst = ka_cfgtst | (1 << 4); +#endif + if ((va_ccmd ^ val) & CMD_LODSA) /* toggle sprite display? */ + va_cur_p = 0; /* reset array ptr */ + va_ccmd = val; + break; + + case 1: /* CUR_XPOS */ + va_xpos = val; + break; + + case 2: /* CUR_YPOS */ + va_ypos = val; + break; + + case 3: /* CUR_XMIN_1 */ + va_xmin1 = val; + break; + + case 4: /* CUR_XMAX_1 */ + va_xmax1 = val; + break; + + case 5: /* CUR_YMIN_1 */ + va_ymin1 = val; + break; + + case 6: /* CUR_YMAX_1 */ + va_ymax1 = val; + break; + + case 11: /* CUR_XMIN_2 */ + va_xmin2 = val; + break; + + case 12: /* CUR_XMAX_2 */ + va_xmax2 = val; + break; + + case 13: /* CUR_YMIN_2 */ + va_ymin2 = val; + break; + + case 14: /* CUR_YMAX_2 */ + va_ymax2 = val; + break; + + case 15: /* CUR_LOAD */ + va_cur[va_cur_p++] = val; + if (va_cur_p == 32) + va_cur_p--; + break; + } +} + +#if defined(BT458) +int32 va_dac_rd (int32 pa) +{ +uint32 rg = (pa >> 1) & 0x3F; +uint32 data = 0; + +switch (rg) { + case 0: /* address */ + data = va_bt458_addr; + break; + + case 1: /* colour map */ + if (va_cmap_p == 0) { + va_cmap[0] = va_cmap2[va_bt458_addr] & 0xFF; + va_cmap[1] = (va_cmap2[va_bt458_addr] >> 8) & 0xFF; + va_cmap[2] = (va_cmap2[va_bt458_addr] >> 16) & 0xFF; + } + data = va_cmap[va_cmap_p++]; + if (va_cmap_p == 3) { + va_cmap_p = 0; + va_bt458_addr++; + va_bt458_addr = va_bt458_addr & 0xFF; + } + break; + + case 2: /* control */ + va_bt458_addr++; + va_bt458_addr = va_bt458_addr & 0x7; + break; + + case 3: /* overlay map */ + if (va_cmap_p == 0) { + va_cmap[0] = va_cmap2[VA_BPP + va_bt458_addr] & 0xFF; + va_cmap[1] = (va_cmap2[VA_BPP + va_bt458_addr] >> 8) & 0xFF; + va_cmap[2] = (va_cmap2[VA_BPP + va_bt458_addr] >> 16) & 0xFF; + } + data = va_cmap[va_cmap_p++]; + if (va_cmap_p == 3) { + va_cmap_p = 0; + va_bt458_addr++; + va_bt458_addr = va_bt458_addr & 0x7; + } + break; + } + +return data; +} + +void va_dac_wr (int32 pa, int32 val, int32 lnt) +{ +uint32 rg = (pa >> 1) & 0x3F; +int32 i; + +switch (rg) { + case 0: /* address */ + va_bt458_addr = val & 0xFF; + va_cmap_p = 0; + break; + + case 1: /* colour map */ + va_cmap[va_cmap_p++] = val; + if (va_cmap_p == 3) { + va_cmap_p = 0; + va_palette[va_bt458_addr] = vid_map_rgb (va_cmap[0], va_cmap[1], va_cmap[2]); + va_cmap2[va_bt458_addr] = va_cmap[0]; + va_cmap2[va_bt458_addr] |= (va_cmap[1] << 8); + va_cmap2[va_bt458_addr] |= (va_cmap[2] << 16); + for (i = 0; i < VA_YSIZE; i++) + va_updated[i] = TRUE; + va_bt458_addr++; + va_bt458_addr = va_bt458_addr & 0xFF; + } + break; + + case 2: /* control */ + va_bt458_addr++; + va_bt458_addr = va_bt458_addr & 0x7; + break; + + case 3: /* overlay map */ + va_cmap[va_cmap_p++] = val; + if (va_cmap_p == 3) { + va_cmap_p = 0; + va_palette[VA_BPP + va_bt458_addr] = vid_map_rgb (va_cmap[0], va_cmap[1], va_cmap[2]); + va_cmap2[VA_BPP + va_bt458_addr] = va_cmap[0]; + va_cmap2[VA_BPP + va_bt458_addr] |= (va_cmap[1] << 8); + va_cmap2[VA_BPP + va_bt458_addr] |= (va_cmap[2] << 16); + for (i = 0; i < VA_YSIZE; i++) + va_updated[i] = TRUE; + va_bt458_addr++; + va_bt458_addr = va_bt458_addr & 0x7; + } + break; + } +} +#else +int32 va_dac_rd (int32 pa) +{ +uint32 rg = (pa >> 1) & 0x3F; +uint32 data = 0; + +if (rg <= 0x33) + sim_debug (DBG_REG, &va_dev, "dac_rd: %s, %X at %08X\n", va_dac_rgd[rg], data, fault_PC); +else + sim_debug (DBG_REG, &va_dev, "dac_rd: %X, %X at %08X\n", rg, data, fault_PC); + +return data; +} + +void va_dac_wr (int32 pa, int32 val, int32 lnt) +{ +uint32 rg = (pa >> 1) & 0x3F; +int32 red, grn, blu, i; + +if (rg <= 0x33) + sim_debug (DBG_REG, &va_dev, "dac_wr: %s, %X at %08X\n", va_dac_rgd[rg], val, fault_PC); +else + sim_debug (DBG_REG, &va_dev, "dac_wr: %X, %X at %08X\n", rg, val, fault_PC); + +if (rg < 0x28) { /* active colour map? */ + rg = rg & 0xF; + red = val & 0xF; + blu = (val >> 4) & 0xF; + grn = (val >> 8) & 0xF; + red = red | (red << 4); /* 12 bit to 24 bit */ + blu = blu | (blu << 4); + grn = grn | (grn << 4); + va_palette[rg] = vid_map_rgb (red, grn, blu); + for (i = 0; i < VA_YSIZE; i++) + va_updated[i] = TRUE; + } +} +#endif + +int32 va_fcc_rd (int32 pa) +{ +uint32 rg = (pa >> 1) & 0xF; +uint32 data = 0; + +switch (rg) { + case FCC_CCSR: /* colour board CSR */ + data = va_fcc_csr; + if (va_adp[ADP_REQ] & va_adp[ADP_STAT]) + data = data | 0x2000; /* Adder requesting I/O */ + break; + + case FCC_ICSR: /* interrupt CSR */ + data = va_fcc_int; + break; + + case FCC_FCSR: /* FIFO CSR */ + data = va_fcc_fcsr; + if (va_fcc_fifo_sz == RAM_SIZE) + data = data | 0x8000; /* FIFO full */ + else if (va_fcc_fifo_sz == 0) + data = data | 0x80; /* FIFO empty */ + else if (va_fcc_fifo_sz < 0) + data = data | 0x4; /* FIFO data is wrapping around */ + switch (GET_MODE (va_fcc_csr)) { + case MODE_BTP: + if (va_fcc_fifo_wp == va_fcc_fifo_th) + data = data | 0x4000; /* FIFO pointers at threshold */ + break; + case MODE_PTB: + case MODE_DL: + if (va_fcc_fifo_rp == va_fcc_fifo_th) + data = data | 0x4000; /* FIFO pointers at threshold */ + break; + } + break; + + case FCC_FWU: /* FIFO words used */ + if (va_fcc_fifo_sz < 0) + data = 0xC000 - (va_fcc_fifo_rp - va_fcc_fifo_wp); + else + data = va_fcc_fifo_sz; + break; + + case FCC_FT: /* threshold */ + data = va_fcc_fifo_th; + break; + + case FCC_PUT: /* put pointer */ + data = va_fcc_fifo_wp; + break; + + case FCC_GET: /* get pointer */ + data = va_fcc_fifo_rp; + break; + + default: + data = 0; + break; + } + +if (rg <= FCC_MAXREG) + sim_debug (DBG_REG, &va_dev, "fcc_rd: %s, %X at %08X\n", va_fcc_rgd[rg], data, fault_PC); +else + sim_debug (DBG_REG, &va_dev, "fcc_rd: %X, %X at %08X\n", rg, data, fault_PC); + +return data; +} + +void va_fcc_wr (int32 pa, int32 val, int32 lnt) +{ +uint32 rg = (pa >> 1) & 0xF; + +if (rg <= FCC_MAXREG) + sim_debug (DBG_REG, &va_dev, "fcc_wr: %s, %X at %08X\n", va_fcc_rgd[rg], val, fault_PC); +else + sim_debug (DBG_REG, &va_dev, "fcc_wr: %X, %X at %08X\n", rg, val, fault_PC); + +switch (rg) { + case FCC_CCSR: /* colour board CSR */ + if (GET_MODE (val) != MODE_DL) + va_dla = 0; + va_fcc_csr = (va_fcc_csr & ~FCCCSR_WR); + va_fcc_csr = va_fcc_csr | (val & FCCCSR_WR); + if (val & 0x4000) { /* flush FIFO? */ +#if 0 + va_fcc_fifo_wp = 0; + va_fcc_fifo_rp = 0; + va_fcc_fifo_sz = 0; + if (va_fcc_fifo_sz < va_fcc_fifo_th) +#endif + va_fcc_int |= 0x80; /* interrupt */ + } + if (GET_MODE (va_fcc_csr) != MODE_HALT) + va_dmasvc (&va_unit[1]); + break; + + case FCC_ICSR: /* interrupt CSR */ + if ((val & 0x42) == 0) + CLR_INT (VC2); + else if ((va_fcc_int & 0x3) == 0x1) /* pixel interrupt */ + SET_INT (VC2); + else if ((va_fcc_int & 0xC0) == 0x80) /* threshold interrupt */ + SET_INT (VC2); + va_fcc_int = va_fcc_int & ~(val & 0x81); /* W1C */ + va_fcc_int = va_fcc_int & ~(0x42); /* WR */ + va_fcc_int = va_fcc_int | (val & 0x42); + break; + + case FCC_FCSR: /* FIFO CSR */ + va_fcc_fcsr = val & 0xFFFF; + break; + + case FCC_FWU: /* FIFO words used */ + break; + + case FCC_FT: /* threshold */ + va_fcc_fifo_th = val; + break; + + case FCC_PUT: /* put pointer */ + va_fcc_fifo_wp = val; + va_fcc_fifo_sz = va_fcc_fifo_wp - va_fcc_fifo_rp; + sim_debug (DBG_FCC, &va_dev, "Put pointer wr: mode = %d\n", GET_MODE (va_fcc_csr)); + if ((GET_MODE (va_fcc_csr) != MODE_HALT) && (va_fcc_fifo_sz > 0)) + va_dmasvc (&va_unit[1]); + break; + + case FCC_GET: /* get pointer */ + va_fcc_fifo_rp = val; + va_fcc_fifo_sz = va_fcc_fifo_wp - va_fcc_fifo_rp; + sim_debug (DBG_FCC, &va_dev, "Get pointer wr: mode = %d\n", GET_MODE (va_fcc_csr)); + if ((GET_MODE (va_fcc_csr) != MODE_HALT) && (va_fcc_fifo_sz > 0)) + va_dmasvc (&va_unit[1]); + break; + + default: + break; + } +} + +int32 va_rd (int32 pa) +{ +int32 rg = (pa >> 1) & 0x7FFF; +int32 data; + +if (rg >= VA_FFW_OF) { + rg = rg & 0x3FFF; + rg = rg | ((va_fcc_csr & 0x3) << 14); /* add A15,A16 */ + data = va_ram[rg]; + sim_debug (DBG_REG, &va_dev, "ffw_rd: %X, %X at %08X\n", rg, data, fault_PC); + return data; + } +if (rg >= VA_CBR_OF) { +#if defined(BT458) + data = (VA_PLANES << 4); /* Brooktree 4 or 8-plane */ +#else + data = 0x00F0; /* original 4-plane */ +#endif + return data; + } +if (rg >= VA_CCR_OF) { + data = 0; + sim_debug (DBG_REG, &va_dev, "ccr_rd: %X, %X at %08X\n", pa, data, fault_PC); + return data; + } +if (rg >= VA_DAC_OF) { + data = va_dac_rd (pa); + return data; + } +if (rg >= VA_FCC_OF) { + data = va_fcc_rd (pa); + return data; + } +if (rg >= VA_ADP_OF) { /* address processor */ + data = va_adp_rd (rg); + SET_IRQL; + return data; + } +return 0; +} + +void va_wr (int32 pa, int32 val, int32 lnt) +{ +int32 nval; +int32 rg = (pa >> 1) & 0x7FFF; +int32 sc; + +if (rg >= VA_FFW_OF) { + rg = rg & 0x3FFF; + rg = rg | ((va_fcc_csr & 0x3) << 14); /* add A15,A16 */ + if (lnt < L_WORD) { + int32 t = va_ram[rg]; + sc = (pa & 1) << 3; + nval = ((val & BMASK) << sc) | (t & ~(BMASK << sc)); + } + else nval = val; + va_ram[rg] = nval; + sim_debug (DBG_REG, &va_dev, "ffw_wr: %X, %X at %08X\n", rg, val, fault_PC); + return; + } +if (rg >= VA_CBR_OF) { + sim_debug (DBG_REG, &va_dev, "cbr_wr: %X, %X at %08X\n", pa, val, fault_PC); + return; + } +if (rg >= VA_CCR_OF) { + va_ccr_wr (pa, val, lnt); + return; + } +if (rg >= VA_DAC_OF) { + va_dac_wr (pa, val, lnt); + return; + } +if (rg >= VA_FCC_OF) { + va_fcc_wr (pa, val, lnt); + return; + } +if (rg >= VA_ADP_OF) { /* address processor */ + va_adp_wr (rg, val); + SET_IRQL; + return; + } +} + +void va_dlist () +{ +t_bool nodec = FALSE; +uint32 inst, saved_inst; +int32 val; + +saved_inst = (va_dla >> 16) & 0xFFFF; /* get saved instruction */ +va_dla = va_dla & 0x0000FFFF; /* get saved address */ +if ((va_dla < VA_TMP_OF) || (saved_inst & 0x2000)) { + if (va_fcc_fifo_sz == 0) + return; + inst = va_fcc_fifo_rd (); + } +else + inst = va_ram[va_dla++]; +if (saved_inst & 0x1000) /* saved decode flag */ + nodec = TRUE; + +sim_debug (DBG_ROP, &va_dev, "Begin display list\n"); +sim_debug (DBG_ROP, &va_dev, "DLIST: %04X = %04X ", (va_dla == 0) ? 0 : (va_dla - 1), inst); +for (;;) { + if (nodec) { /* decode disabled? */ + sim_debug (DBG_ROP, &va_dev, "(data - full word)\n"); + va_adp_wr (ADP_ADCT, inst); /* write to adder (full word) */ + nodec = FALSE; /* enable decode */ + } + else if (inst & 0x8000) { /* command? */ + if (inst & 0x800) { + if (va_dla < VA_TMP_OF) { + if (va_fcc_fifo_sz == 0) + break; + va_dla = va_fcc_fifo_rd (); + } + else + va_dla = va_ram[va_dla]; + va_dla = va_dla & 0x1FFF; + if (va_dla >= VA_TMP_OF) + va_dla = va_dla | 0xC000; + sim_debug (DBG_ROP, &va_dev, "(JMPTD @ %X)\n", va_dla); + } + else { + sim_debug (DBG_ROP, &va_dev, "(command"); + if (inst & 0x4000) + sim_debug (DBG_ROP, &va_dev, ", write disable"); + if (inst & 0x2000) /* read fifo? */ + sim_debug (DBG_ROP, &va_dev, ", read fifo"); + if (inst & 0x1000) /* decode disable? */ + sim_debug (DBG_ROP, &va_dev, ", decode disable"); + sim_debug (DBG_ROP, &va_dev, ")\n"); + if ((inst & 0x4000) == 0) /* write enabled? */ + va_adp_wr (ADP_ADCT, (0x8000 | (inst & 0xFFF))); /* update counter */ + if (inst & 0x1000) /* decode disable? */ + nodec = TRUE; + if (inst & 0x2000) { /* read fifo? */ + if (va_fcc_fifo_sz == 0) { + va_dla = va_dla | (inst << 16); /* save current instruction */ + break; + } + inst = va_fcc_fifo_rd (); + sim_debug (DBG_ROP, &va_dev, "DLIST: fifo = %04X\n", inst); + continue; + } + } + } + else if (inst & 0x4000) { /* write disable? */ + if (inst & 0x2000) { /* read fifo? */ + val = inst & 0x1FFF; + val = 0x2000 - val; /* FIXME: # words is negative? */ + sim_debug (DBG_ROP, &va_dev, "(PTB %d words)\n", val); + for (; val > 0; val--) { + if (va_fcc_fifo_sz == 0) + break; + inst = va_fcc_fifo_rd (); + va_adp_wr (ADP_IDD, inst); + } + va_dla = 0; /* always returns to FIFO */ + } + else { + va_dla = inst & 0x1FFF; + if (va_dla >= VA_TMP_OF) + va_dla = va_dla | 0xC000; + sim_debug (DBG_ROP, &va_dev, "(JMPT @ %X)\n", va_dla); + } + } + else { + sim_debug (DBG_ROP, &va_dev, "(data)\n"); + va_adp_wr (ADP_ADCT, (inst & 0x3FFF)); /* write to adder */ + } + if (va_dla < VA_TMP_OF) { + if (va_fcc_fifo_sz == 0) + break; + inst = va_fcc_fifo_rd (); + } + else + inst = va_ram[va_dla++]; + sim_debug (DBG_ROP, &va_dev, "DLIST: %04X = %04X ", (va_dla == 0) ? 0 : (va_dla - 1), inst); + } +sim_debug (DBG_ROP, &va_dev, "Display list complete\n"); +} + +void va_setint (int32 src) +{ +switch (src) { + case INT_FCC: /* DMA IRQ */ + SET_INT (VC2); + break; + case INT_ADP: /* ADP IRQ */ + SET_INT (VC1); + break; + } +} + +static SIM_INLINE void va_invalidate (uint32 y1, uint32 y2) +{ +uint32 ln; + +for (ln = y1; ln < y2; ln++) + va_updated[ln] = TRUE; /* flag as updated */ +} + +t_stat va_svc (UNIT *uptr) +{ +SIM_MOUSE_EVENT mev; +SIM_KEY_EVENT kev; +t_bool updated = FALSE; /* flag for refresh */ +uint32 lines; +uint32 ln, col, off; +uint16 *plna, *plnb; +uint16 bita, bitb; +uint32 c; + +va_adp_svc (uptr); + +if (va_cur_v != CUR_V) { /* visibility changed? */ + if (CUR_V) /* visible? */ + va_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */ + else + va_invalidate (va_cur_y, (va_cur_y + 16)); /* invalidate old pos */ + } +else if (va_cur_y != CUR_Y) { /* moved (Y)? */ + va_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */ + va_invalidate (va_cur_y, (va_cur_y + 16)); /* invalidate old pos */ + } +else if (va_cur_x != CUR_X) { /* moved (X)? */ + va_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */ + } + +va_cur_x = CUR_X; /* store cursor data */ +va_cur_y = CUR_Y; +va_cur_v = CUR_V; +va_cur_f = CUR_F; + +if (vid_poll_kb (&kev) == SCPE_OK) /* poll keyboard */ + lk_event (&kev); /* push event */ +if (vid_poll_mouse (&mev) == SCPE_OK) /* poll mouse */ + vs_event (&mev); /* push event */ + +lines = 0; +for (ln = 0; ln < VA_YSIZE; ln++) { + if (va_updated[ln + va_yoff]) { /* line updated? */ + off = (ln + va_yoff) * VA_XSIZE; /* get video buf offet */ + if (va_dpln > 0) { + for (col = 0; col < VA_XSIZE; col++) + va_lines[ln*VA_XSIZE + col] = (va_buf[off + col] & va_dpln) ? va_white : va_black; + } + else { + for (col = 0; col < VA_XSIZE; col++) + va_lines[ln*VA_XSIZE + col] = va_palette[va_buf[off + col] & VA_PLANE_MASK]; + } + + if (CUR_V && /* cursor visible && need to draw cursor? */ + (va_input_captured || (va_dev.dctrl & DBG_CURSOR))) { + if ((ln >= CUR_Y) && (ln < (CUR_Y + 16))) { /* cursor on this line? */ + plna = &va_cur[(CUR_PLNA + ln - CUR_Y)];/* get plane A base */ + plnb = &va_cur[(CUR_PLNB + ln - CUR_Y)];/* get plane B base */ + for (col = 0; col < 16; col++) { + if ((CUR_X + col) >= VA_XSIZE) /* Part of cursor off screen? */ + continue; /* Skip */ + if (va_ccmd & CMD_FOPA) /* force plane A to 1? */ + bita = 1; + else if (va_ccmd & CMD_ENPA) /* plane A enabled? */ + bita = (*plna >> col) & 1; + else bita = 0; + if (va_ccmd & CMD_FOPB) /* force plane B to 1? */ + bitb = 1; + else if (va_ccmd & CMD_ENPB) /* plane B enabled? */ + bitb = (*plnb >> col) & 1; + else bitb = 0; + if (bita & bitb) + va_lines[ln*VA_XSIZE + CUR_X + col] = va_palette[CUR_FG]; + else if (bita ^ bitb) + va_lines[ln*VA_XSIZE + CUR_X + col] = va_palette[CUR_BG]; + } + } + } + va_updated[ln + va_yoff] = FALSE; /* set valid */ + if ((ln == (VA_YSIZE-1)) || /* if end of window OR */ + (va_updated[ln+va_yoff+1] == FALSE)) { /* next is already valid? */ + vid_draw (0, ln-lines, VA_XSIZE, lines+1, va_lines+(ln-lines)*VA_XSIZE); /* update region */ + lines = 0; + } + else + lines++; + updated = TRUE; + } + } + +if (updated) /* video updated? */ + vid_refresh (); /* put to screen */ + +sim_activate (uptr, tmxr_poll); /* reactivate */ +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +return SCPE_OK; +} + +t_bool va_fcc_rdn (uint32 *data, uint32 bits) +{ +int32 mask = (1u << bits) - 1; +if (va_fcc_sc == 0) { /* need to read FIFO? */ + if (va_fcc_fifo_sz == 0) /* empty? */ + return FALSE; /* no more data to read */ + va_fcc_data = va_fcc_fifo_rd (); + } +*data = (va_fcc_data >> va_fcc_sc) & mask; /* extract bits */ +va_fcc_sc = (va_fcc_sc + bits) & 0xF; +return TRUE; +} + +t_bool va_fcc_wrn (uint32 data, uint32 bits) +{ +int32 mask = (1u << bits) - 1; +mask = mask << va_fcc_sc; +va_fcc_data = va_fcc_data & ~mask; /* clear bits */ +va_fcc_data = va_fcc_data | ((data << va_fcc_sc) & mask); /* insert bits */ +va_fcc_sc = (va_fcc_sc + bits) & 0xF; +if (va_fcc_sc == 0) { /* need to write FIFO? */ + if (va_fcc_fifo_sz == RAM_SIZE) /* full? */ + return FALSE; /* no more space to write */ + va_fcc_fifo_wr (va_fcc_data); + va_fcc_data = 0; + } +return TRUE; +} + +void va_fcc_decomp (UNIT *uptr) +{ +uint32 pix, last_pix, len1, len2, i, sc, temp; + +last_pix = 0xFF; +for (;uptr->CMD != 0;) { + if (!va_fcc_rdn (&pix, 4)) /* read pixel from FIFO */ + return; + va_fifo_wr (pix); /* output pixel */ + if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0) + va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ)); + if (pix == last_pix) { /* same as previous? */ + if (!va_fcc_rdn (&len1, 4)) /* get run length */ + return; + len2 = 0; + if (len1 & 0x8) { /* deferred? */ + for (i = 0, sc = 0; i < (len1 & 0x7); i++) { + if (!va_fcc_rdn (&temp, 4)) + return; + len2 = len2 | (temp << sc); + sc = sc + 4; + } + } + else + len2 = len1 & 0x7; /* immediate */ + for (i = 0; i < len2; i++) { + va_fifo_wr (pix); /* output pixel */ + if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0) + va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ)); + } + } + last_pix = pix; + } +} + +void va_fcc_comp (UNIT *uptr) +{ +uint32 pix, last_pix, len1, len2, temp; + +va_fcc_sc = 0; +va_fcc_data = 0; +if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) { + va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ)); + if (va_adp[ADP_STAT] & ADPSTAT_AC) + return; + } +last_pix = va_fifo_rd (); +for (;;) { + va_fcc_wrn (last_pix, 4); + if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) { + va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ)); + if (va_adp[ADP_STAT] & ADPSTAT_AC) + return; + } + pix = va_fifo_rd (); + va_fcc_wrn (pix, 4); + len1 = 0; + while (pix == last_pix) { + if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) { + va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ)); + if (va_adp[ADP_STAT] & ADPSTAT_AC) + return; + } + pix = va_fifo_rd (); + len1++; + } + if (len1 > 0) { + len1--; + if (len1 > 0x7) { + temp = len1; + for (len2 = 0; temp != 0; len2++) + temp = temp >> 4; + len2 = len2 | 0x8; + va_fcc_wrn (len2, 4); + for (;len1 != 0;) { + va_fcc_wrn (len1 & 0xF, 4); + len1 = len1 >> 4; + } + } + else + va_fcc_wrn (len1, 4); + } + last_pix = pix; + } +} + +int32 debug_flag = 0; + +t_stat va_dmasvc (UNIT *uptr) +{ +uint16 data; + +if (GET_MODE (va_fcc_csr) == MODE_HALT) + return SCPE_OK; + +sim_debug (DBG_FCC, &va_dev, "DMA service\n"); +switch (GET_MODE (va_fcc_csr)) { + + case MODE_PTB: + sim_debug (DBG_FCC, &va_dev, "DMA mode PTB\n"); + if (va_fcc_csr & 0x1800) { /* compressed? */ + va_fcc_decomp (uptr); + } + else if (va_fcc_csr & FCCCSR_PACK) { + for (;uptr->CMD != 0;) { + if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0) + va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ)); + if (va_fcc_fifo_sz == 0) + break; + data = va_fcc_fifo_rd (); + va_fifo_wr (data & BMASK); + if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0) + va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ)); + va_fifo_wr ((data >> 8) & BMASK); + } + } + else { + for (;uptr->CMD != 0;) { + if ((va_adp[ADP_STAT] & ADPSTAT_ITR) == 0) + va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ)); + if (va_fcc_fifo_sz == 0) + break; + data = va_fcc_fifo_rd (); + va_fifo_wr (data); + } + } + va_ptb (&va_unit[1], (va_unit[1].CMD == CMD_PTBZ)); + if (va_fcc_fifo_sz < va_fcc_fifo_th) + va_fcc_int |= 0x80; + if (uptr->CMD == 0) + va_fcc_int |= 0x1; + break; + + case MODE_BTP: + sim_debug (DBG_FCC, &va_dev, "DMA mode BTP\n"); + if ((va_fcc_csr & 0x1880) == 0x1800) { /* compressed, not diag? */ + va_fcc_comp (uptr); + } + else if (va_fcc_csr & FCCCSR_PACK) { + for (;;) { + if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) { + va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ)); + if (va_adp[ADP_STAT] & ADPSTAT_AC) + break; + } + data = (va_fifo_rd () & BMASK); + if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) { + va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ)); + if (va_adp[ADP_STAT] & ADPSTAT_AC) + break; + } + data |= ((va_fifo_rd () & BMASK) << 8); + va_fcc_fifo_wr (data); + } + } + else { + for (;;) { + if ((va_adp[ADP_STAT] & ADPSTAT_IRR) == 0) { + va_btp (&va_unit[1], (va_unit[1].CMD == CMD_BTPZ)); + if (va_adp[ADP_STAT] & ADPSTAT_AC) + break; + } + data = va_fifo_rd (); + va_fcc_fifo_wr (data); + } + } + if (va_fcc_fifo_sz > va_fcc_fifo_th) + va_fcc_int |= 0x80; + if (uptr->CMD == 0) + va_fcc_int |= 0x1; + break; + + case MODE_DL: + sim_debug (DBG_FCC, &va_dev, "DMA mode DL\n"); + va_dlist (); + if (va_fcc_fifo_sz < va_fcc_fifo_th) + va_fcc_int |= 0x80; + break; + + default: + sim_debug (DBG_FCC, &va_dev, "DMA mode %X\n", GET_MODE(va_fcc_csr)); + break; + } + +sim_debug (DBG_FCC, &va_dev, "DMA service complete\n"); +if ((va_fcc_int & 0x3) == 0x3) /* pixel interrupt */ + va_setint (INT_FCC); +else if ((va_fcc_int & 0xC0) == 0xC0) /* threshold interrupt */ + va_setint (INT_FCC); +return SCPE_OK; +} + +t_stat va_reset (DEVICE *dptr) +{ +int32 i; +t_stat r; + +CLR_INT (VC2); /* clear int req */ +sim_cancel (&va_unit[0]); /* stop poll */ +sim_cancel (&va_unit[1]); +va_adp_reset (dptr); + +va_fcc_fifo_clr (); +va_fcc_csr = 0x8000; +va_dla = 0; + +va_bt458_addr = 0; +va_cmap_p = 0; + +for (i = 0; i < VA_YSIZE; i++) + va_updated[i] = TRUE; + +if (dptr->flags & DEV_DIS) { + if (va_active) { + free (va_buf); + va_buf = NULL; + free (va_lines); + va_lines = NULL; + va_active = FALSE; + return vid_close (); + } + else + return SCPE_OK; + } + +if (!vid_active) { + r = vid_open (dptr, NULL, VA_XSIZE, VA_YSIZE, va_input_captured ? SIM_VID_INPUTCAPTURED : 0);/* display size & capture mode */ + if (r != SCPE_OK) + return r; + va_buf = (uint32 *) calloc (VA_BUFSIZE, sizeof (uint32)); + if (va_buf == NULL) { + vid_close (); + return SCPE_MEM; + } + va_lines = (uint32 *) calloc (VA_XSIZE * VA_YSIZE, sizeof (uint32)); + if (va_lines == NULL) { + free (va_buf); + vid_close (); + return SCPE_MEM; + } +#if defined (BT458) + for (i = 0; i < (VA_BPP + CUR_COL); i++) + va_palette[i] = vid_map_rgb (0x00, 0x00, 0x00); /* black */ + va_palette[VA_BPP - 1] = vid_map_rgb (0xFF, 0xFF, 0xFF); /* white */ + va_palette[CUR_FG] = vid_map_rgb (0xFF, 0xFF, 0xFF); +#else + for (i = 0; i < (VA_BPP + VA_BPP + CUR_COL); i++) + va_palette[i] = vid_map_rgb (0x00, 0x00, 0x00); /* black */ + va_palette[CUR_FG] = vid_map_rgb (0xFF, 0xFF, 0xFF); +#endif + va_black = vid_map_rgb (0x00, 0x00, 0x00); /* black */ + va_white = vid_map_rgb (0xFF, 0xFF, 0xFF); /* white */ + sim_printf ("GPX Display Created. "); + va_show_capture (stdout, NULL, 0, NULL); + if (sim_log) + va_show_capture (sim_log, NULL, 0, NULL); + sim_printf ("\n"); + va_active = TRUE; + } +sim_activate_abs (&va_unit[0], tmxr_poll); +return SCPE_OK; +} + +t_stat va_detach (UNIT *uptr) +{ +if ((va_dev.flags & DEV_DIS) == 0) { + va_dev.flags |= DEV_DIS; + va_reset(&va_dev); + } +return SCPE_OK; +} + +t_stat va_set_yoff (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +int32 i; +t_stat r; + +if (cptr == NULL) + return SCPE_ARG; +va_yoff = (int32) get_uint (cptr, 10, 2048, &r); +for (i = 0; i < VA_YSIZE; i++) + va_updated[i + va_yoff] = TRUE; +return r; +} + +t_stat va_show_yoff (FILE* st, UNIT* uptr, int32 val, CONST void* desc) +{ +fprintf (st, "%d", va_yoff); +return SCPE_OK; +} + +t_stat va_set_dpln (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +int32 i; +t_stat r; + +if (cptr == NULL) + return SCPE_ARG; +va_dpln = (int32) get_uint (cptr, 10, VA_PLANES, &r); +if (va_dpln > 0) { + va_dpln = va_dpln - 1; + va_dpln = (1u << va_dpln); + } +for (i = 0; i < VA_YSIZE; i++) + va_updated[i + va_yoff] = TRUE; +return r; +} + +t_stat va_show_dpln (FILE* st, UNIT* uptr, int32 val, CONST void* desc) +{ +fprintf (st, "%d", va_dpln); +return SCPE_OK; +} + +t_stat va_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +return cpu_set_model (NULL, 0, (val ? "VAXSTATIONGPX" : "MICROVAX"), NULL); +} + +t_stat va_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +if (vid_active) + return sim_messagef (SCPE_ALATT, "Capture Mode Can't be changed with device enabled\n"); +va_input_captured = val; +return SCPE_OK; +} + +t_stat va_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc) +{ +if (va_input_captured) { + fprintf (st, "Captured Input Mode, "); + vid_show_release_key (st, uptr, val, desc); + } +else + fprintf (st, "Uncaptured Input Mode"); +return SCPE_OK; +} + +t_stat va_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "GPX 8-Bit Colour Video Subsystem (%s)\n\n", dptr->name); +fprintf (st, "Use the Control-Right-Shift key combination to regain focus from the simulated\n"); +fprintf (st, "video display\n"); +fprint_set_help (st, dptr); +fprint_show_help (st, dptr); +fprint_reg_help (st, dptr); +return SCPE_OK; +} + +const char *va_description (DEVICE *dptr) +{ +return "GPX Colour Graphics Adapter"; +} diff --git a/VAX/vax4xx_vc.c b/VAX/vax4xx_vc.c new file mode 100644 index 00000000..fa4f78f9 --- /dev/null +++ b/VAX/vax4xx_vc.c @@ -0,0 +1,575 @@ +/* vax4xx_vc.c: Monochrome video simulator + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + vc Monochrome video +*/ + +#include "vax_defs.h" +#include "sim_video.h" +#include "vax_lk.h" +#include "vax_vs.h" + +#define VC_XSIZE 1024 /* visible width */ +#define VC_YSIZE 864 /* visible height */ + +#define VC_BXSIZE 1024 /* buffer width */ +#define VC_BUFMASK (VC_BUFSIZE - 1) + +#define CUR_X_OF 216 +#define CUR_Y_OF 33 + +#define CMD_TEST 0x8000 +#define CMD_HSHI 0x4000 +#define CMD_VBHI 0x2000 +#define CMD_LODSA 0x1000 +#define CMD_FORG2 0x0800 +#define CMD_ENRG2 0x0400 +#define CMD_FORG1 0x0200 +#define CMD_ENRG1 0x0100 +#define CMD_XHWID 0x0080 +#define CMD_XHCL1 0x0040 +#define CMD_XHCLP 0x0020 +#define CMD_XHAIR 0x0010 +#define CMD_FOPB 0x0008 +#define CMD_ENPB 0x0004 +#define CMD_FOPA 0x0002 +#define CMD_ENPA 0x0001 + +#define CUR_X ((vc_xpos < CUR_X_OF) ? 0 : (vc_xpos - CUR_X_OF)) +#define CUR_Y ((vc_ypos < CUR_Y_OF) ? 0 : (vc_ypos - CUR_Y_OF)) +#define CUR_V ((vc_cmd & CMD_LODSA) == 0) +#define CUR_F (0) + +#define CUR_PLNA 0 +#define CUR_PLNB 16 + +/* Debugging Bitmaps */ + +#define DBG_REG 0x0001 /* registers */ +#define DBG_CURSOR 0x0002 /* Cursor content, function and visibility activity */ +#define DBG_TCURSOR 0x0800 /* Cursor content, function and visibility activity */ + +extern int32 tmxr_poll; +extern int32 ka_cfgtst; + +uint32 vc_cmd = 0; /* cursor command reg */ +uint32 vc_xpos = 0; /* cursor x position */ +uint32 vc_ypos = 0; /* cursor y position */ +uint32 vc_xmin1 = 0; /* region 1 left edge */ +uint32 vc_xmax1 = 0; /* region 1 right edge */ +uint32 vc_ymin1 = 0; /* region 1 top edge */ +uint32 vc_ymax1 = 0; /* region 1 bottom edge */ +uint32 vc_xmin2 = 0; /* region 2 left edge */ +uint32 vc_xmax2 = 0; /* region 2 right edge */ +uint32 vc_ymin2 = 0; /* region 2 top edge */ +uint32 vc_ymax2 = 0; /* region 2 bottom edge */ +uint16 vc_cur[32]; /* cursor image data */ +uint32 vc_cur_p = 0; /* cursor image pointer */ +t_bool vc_updated[VC_YSIZE]; +t_bool vc_cur_new_data = FALSE; /* New Cursor image data */ +t_bool vc_input_captured = FALSE; /* Mouse and Keyboard input captured in video window */ +uint32 vc_cur_x = 0; /* Last cursor X-position */ +uint32 vc_cur_y = 0; /* Last cursor Y-position */ +uint32 vc_cur_f = 0; /* Last cursor function */ +t_bool vc_cur_v = FALSE; /* Last cursor visible */ +uint32 vc_org = 0; /* display origin */ +uint32 vc_last_org = 0; /* display last origin */ +uint32 vc_sel = 0; /* interrupt select */ +uint32 *vc_buf = NULL; /* Video memory */ +uint32 *vc_lines = NULL; /* Video Display Lines */ +uint32 vc_palette[2]; /* Monochrome palette */ +t_bool vc_active = FALSE; + +t_stat vc_svc (UNIT *uptr); +t_stat vc_reset (DEVICE *dptr); +t_stat vc_detach (UNIT *dptr); +t_stat vc_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat vc_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat vc_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc); +t_stat vc_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *vc_description (DEVICE *dptr); + +/* VC data structures + + vc_dev VC device descriptor + vc_unit VC unit descriptor + vc_reg VC register list +*/ + +UNIT vc_unit = { + UDATA ( &vc_svc, UNIT_IDLE, 0 ) + }; + +REG vc_reg[] = { + { HRDATAD (CMD, vc_cmd, 16, "Cursor command register") }, + { DRDATAD (XPOS, vc_xpos, 16, "Cursor X position") }, + { DRDATAD (YPOS, vc_ypos, 16, "Cursor Y position") }, + { DRDATAD (XMIN1, vc_xmin1, 16, "Region 1 left edge") }, + { DRDATAD (XMAX1, vc_xmax1, 16, "Region 1 right edge") }, + { DRDATAD (YMIN1, vc_ymin1, 16, "Region 1 top edge") }, + { DRDATAD (YMAX1, vc_ymax1, 16, "Region 1 bottom edge") }, + { DRDATAD (XMIN2, vc_xmin2, 16, "Region 2 left edge") }, + { DRDATAD (XMAX2, vc_xmax2, 16, "Region 2 right edge") }, + { DRDATAD (YMIN2, vc_ymin2, 16, "Region 2 top edge") }, + { DRDATAD (YMAX2, vc_ymax2, 16, "Region 2 bottom edge") }, + { DRDATAD (ORG, vc_org, 8, "Display origin") }, + { DRDATAD (ISEL, vc_sel, 1, "Interrupt select") }, + { HRDATA (CURP, vc_cur_p, 5), REG_HRO }, + { NULL } + }; + +DEBTAB vc_debug[] = { + { "REG", DBG_REG, "Register activity" }, + { "CURSOR", DBG_CURSOR, "Cursor content, function and visibility activity" }, + { "TCURSOR", DBG_TCURSOR, "Cursor content, function and visibility activity" }, + { 0 } + }; + +MTAB vc_mod[] = { + { MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLE", + &vc_set_enable, NULL, NULL, "Enable Monochrome Video" }, + { MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLE", + &vc_set_enable, NULL, NULL, "Disable Monochrome Video" }, + { MTAB_XTD|MTAB_VDV, TRUE, NULL, "CAPTURE", + &vc_set_capture, &vc_show_capture, NULL, "Enable Captured Input Mode" }, + { MTAB_XTD|MTAB_VDV, FALSE, NULL, "NOCAPTURE", + &vc_set_capture, NULL, NULL, "Disable Captured Input Mode" }, + { MTAB_XTD|MTAB_VDV, TRUE, "OSCURSOR", NULL, + NULL, &vc_show_capture, NULL, "Display Input Capture mode" }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "VIDEO", NULL, + NULL, &vid_show_video, NULL, "Display the host system video capabilities" }, + { 0 } + }; + +DEVICE vc_dev = { + "VC", &vc_unit, vc_reg, vc_mod, + 1, 10, 31, 1, DEV_RDX, 8, + NULL, NULL, &vc_reset, + NULL, NULL, &vc_detach, + NULL, DEV_DEBUG | DEV_DIS, 0, + vc_debug, NULL, NULL, &vc_help, NULL, NULL, + &vc_description + }; + +/* VC routines + + vc_wr I/O page write + vc_svc process event + vc_reset process reset +*/ + +void vc_wr (int32 pa, int32 data, int32 access) +{ +int32 rg = (pa >> 2) & 0x1F; + +if (vc_dev.flags & DEV_DIS) /* disabled? */ + return; + +switch (rg) { + + case 0: /* CUR_CMD */ + if ((data & CMD_TEST) == 0) { + if (data & (CMD_ENRG2|CMD_FORG2|CMD_ENRG1|CMD_FORG1|CMD_FOPB|CMD_FOPA)) + ka_cfgtst = ka_cfgtst & ~(1 << 4); + else ka_cfgtst = ka_cfgtst | (1 << 4); + } + else ka_cfgtst = ka_cfgtst | (1 << 4); + if ((vc_cmd ^ data) & CMD_LODSA) /* toggle sprite display? */ + vc_cur_p = 0; /* reset array ptr */ + vc_cmd = data; + break; + + case 1: /* CUR_XPOS */ + vc_xpos = data; + vid_set_cursor_position (CUR_X, CUR_Y); + break; + + case 2: /* CUR_YPOS */ + vc_ypos = data; + vid_set_cursor_position (CUR_X, CUR_Y); + break; + + case 3: /* CUR_XMIN_1 */ + vc_xmin1 = data; + break; + + case 4: /* CUR_XMAX_1 */ + vc_xmax1 = data; + break; + + case 5: /* CUR_YMIN_1 */ + vc_ymin1 = data; + break; + + case 6: /* CUR_YMAX_1 */ + vc_ymax1 = data; + break; + + case 11: /* CUR_XMIN_2 */ + vc_xmin2 = data; + break; + + case 12: /* CUR_XMAX_2 */ + vc_xmax2 = data; + break; + + case 13: /* CUR_YMIN_2 */ + vc_ymin2 = data; + break; + + case 14: /* CUR_YMAX_2 */ + vc_ymax2 = data; + break; + + case 15: /* CUR_LOAD */ + vc_cur[vc_cur_p++] = data; + if (vc_cur_p == 32) + vc_cur_p--; + vc_cur_new_data = TRUE; + break; + } + +sim_debug (DBG_REG, &vc_dev, "reg %d write, value = %X\n", rg, data); +return; +} + +int32 vc_mem_rd (int32 pa) +{ +int32 rg = ((pa - 0x30000000) >> 2); + +if (!vc_buf) /* MONO disabled? */ + return 0; /* Invalid memory reference */ + +return vc_buf[rg]; +} + +void vc_mem_wr (int32 pa, int32 val, int32 lnt) +{ +int32 nval; +int32 rg = ((pa - 0x30000000) >> 2); +uint32 scrln; + +if (!vc_buf) /* MONO disabled? */ + return; /* Invalid memory reference */ + +if (lnt < L_LONG) { /* byte or word? */ + int32 sc = (pa & 3) << 3; /* merge */ + int32 mask = (lnt == L_WORD)? 0xFFFF: 0xFF; + int32 t = vc_buf[rg]; + nval = ((val & mask) << sc) | (t & ~(mask << sc)); + } +else nval = val; +vc_buf[rg] = nval; /* update buffer */ +scrln = ((rg >> 5) + VC_BYSIZE - (vc_org << VC_ORSC)) & (VC_BYSIZE - 1); +if (scrln < VC_YSIZE) + vc_updated[scrln] = TRUE; /* flag as updated */ +return; +} + +static void vc_set_vid_cursor (t_bool visible) +{ +uint8 data[2*16]; +uint8 mask[2*16]; +uint32 ln, col; +uint16 *plna, *plnb; +uint16 bita, bitb; +int i, d, m; + +sim_debug (DBG_CURSOR, &vc_dev, "vc_set_vid_cursor(%s)\n", visible ? "Visible" : "Invisible"); +memset (data, 0, sizeof(data)); +memset (mask, 0, sizeof(mask)); +for (ln = 0; ln < 16; ln++) { + plna = &vc_cur[(CUR_PLNA + ln)]; /* get plane A base */ + plnb = &vc_cur[(CUR_PLNB + ln)]; /* get plane B base */ + for (col = 0; col < 16; col++) { + if (vc_cmd & CMD_FOPA) /* force plane A to 1? */ + bita = 1; + else if (vc_cmd & CMD_ENPA) /* plane A enabled? */ + bita = (*plna >> col) & 1; + else bita = 0; + if (vc_cmd & CMD_FOPB) /* force plane B to 1? */ + bitb = 1; + else if (vc_cmd & CMD_ENPB) /* plane B enabled? */ + bitb = (*plnb >> col) & 1; + else bitb = 0; + + if (bita) { + if (bitb) { + d = 0; m = 1; /* white */ + } + else { + d = 1; m = 0; /* inverted */ + } + } + else { + if (bitb) { + d = 1; m = 1; /* black */ + } + else { + d = 0; m = 0; /* transparent */ + } + } + i = (ln * 16) + col; + data[i>>3] |= d<<(7-(i&7)); + mask[i>>3] |= m<<(7-(i&7)); + } + } +if ((vc_dev.dctrl & DBG_CURSOR) && (vc_dev.dctrl & DBG_TCURSOR)) { + /* box the cursor image */ + for (i=0; i<16*16; i++) { + if ((0 == i>>4) || (0xF == i>>4) || (0 == (i&0xF)) || (0xF == (i&0xF))) { + data[i>>3] |= 1<<(7-(i&7)); + mask[i>>3] |= 1<<(7-(i&7)); + } + if ((1 == i>>4) || (0xE == i>>4) || (1 == (i&0xF)) || (0xE == (i&0xF))) { + data[i>>3] &= ~(1<<(7-(i&7))); + mask[i>>3] |= 1<<(7-(i&7)); + } + } + } +vid_set_cursor (visible, 16, 16, data, mask, 0, 0); +} + +static SIM_INLINE void vc_invalidate (uint32 y1, uint32 y2) +{ +uint32 ln; + +for (ln = y1; ln < y2; ln++) + vc_updated[ln] = TRUE; /* flag as updated */ +} + +t_stat vc_svc (UNIT *uptr) +{ +SIM_MOUSE_EVENT mev; +SIM_KEY_EVENT kev; +t_bool updated = FALSE; /* flag for refresh */ +uint32 lines; +uint32 ln, col, off; +uint16 *plna, *plnb; +uint16 bita, bitb; +uint32 c; + +if (vc_cur_v != CUR_V) { /* visibility changed? */ + if (CUR_V) /* visible? */ + vc_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */ + else + vc_invalidate (vc_cur_y, (vc_cur_y + 16)); /* invalidate old pos */ + } +else if (vc_cur_y != CUR_Y) { /* moved (Y)? */ + vc_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */ + vc_invalidate (vc_cur_y, (vc_cur_y + 16)); /* invalidate old pos */ + } +else if ((vc_cur_x != CUR_X) || /* moved (X)? */ + (vc_cur_new_data)) { /* cursor image changed? */ + vc_invalidate (CUR_Y, (CUR_Y + 16)); /* invalidate new pos */ + } + +if ((!vc_input_captured) && /* OS cursor? AND */ + ((vc_cur_new_data) || /* cursor image changed? OR */ + (vc_cur_v != CUR_V))) { /* visibility changed? */ + vc_set_vid_cursor (CUR_V); + } + +vc_cur_x = CUR_X; /* store cursor data */ +vc_cur_y = CUR_Y; +vid_set_cursor_position (vc_cur_x, vc_cur_y); +vc_cur_v = CUR_V; +vc_cur_f = CUR_F; +vc_cur_new_data = FALSE; + +if (vid_poll_kb (&kev) == SCPE_OK) /* poll keyboard */ + lk_event (&kev); /* push event */ +if (vid_poll_mouse (&mev) == SCPE_OK) /* poll mouse */ + vs_event (&mev); /* push event */ + +if (vc_org != vc_last_org) /* origin moved? */ + vc_invalidate (0, (VC_YSIZE - 1)); /* redraw whole screen */ + +vc_last_org = vc_org; /* store video origin */ + +lines = 0; +for (ln = 0; ln < VC_YSIZE; ln++) { + if (vc_updated[ln]) { /* line invalid? */ + off = ((ln + (vc_org << VC_ORSC)) << 5) & VC_BUFMASK; /* get video buf offet */ + for (col = 0; col < VC_XSIZE; col++) + vc_lines[ln*VC_XSIZE + col] = vc_palette[(vc_buf[off + (col >> 5)] >> (col & 0x1F)) & 1]; + /* 1bpp to 32bpp */ + if (CUR_V && /* cursor visible && need to draw cursor? */ + (vc_input_captured || (vc_dev.dctrl & DBG_CURSOR))) { + if ((ln >= CUR_Y) && (ln < (CUR_Y + 16))) { /* cursor on this line? */ + plna = &vc_cur[(CUR_PLNA + ln - CUR_Y)];/* get plane A base */ + plnb = &vc_cur[(CUR_PLNB + ln - CUR_Y)];/* get plane B base */ + for (col = 0; col < 16; col++) { + if ((CUR_X + col) >= VC_XSIZE) /* Part of cursor off screen? */ + continue; /* Skip */ + if (vc_cmd & CMD_FOPA) /* force plane A to 1? */ + bita = 1; + else if (vc_cmd & CMD_ENPA) /* plane A enabled? */ + bita = (*plna >> col) & 1; + else bita = 0; + if (vc_cmd & CMD_FOPB) /* force plane B to 1? */ + bitb = 1; + else if (vc_cmd & CMD_ENPB) /* plane B enabled? */ + bitb = (*plnb >> col) & 1; + else bitb = 0; + vc_lines[ln*VC_XSIZE + CUR_X + col] = vc_palette[((vc_lines[ln*VC_XSIZE + CUR_X + col] == vc_palette[1]) & ~bitb) ^ bita]; + } + } + } + vc_updated[ln] = FALSE; /* set valid */ + if ((ln == (VC_YSIZE-1)) || /* if end of window OR */ + (vc_updated[ln+1] == FALSE)) { /* next is already valid? */ + vid_draw (0, ln-lines, VC_XSIZE, lines+1, vc_lines+(ln-lines)*VC_XSIZE); /* update region */ + lines = 0; + } + else + lines++; + updated = TRUE; + } + } + +if (updated) /* video updated? */ + vid_refresh (); /* put to screen */ + +SET_INT (VC1); /* VSYNC int */ +sim_activate (uptr, tmxr_poll); +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +return SCPE_OK; +} + +t_stat vc_reset (DEVICE *dptr) +{ +t_stat r; +uint32 i; + +CLR_INT (VC1); +sim_cancel (&vc_unit); /* deactivate unit */ + +vc_cmd = 0; +vc_xpos = 0; +vc_ypos = 0; +vc_xmin1 = 0; +vc_xmax1 = 0; +vc_ymin1 = 0; +vc_ymax1 = 0; +vc_xmin2 = 0; +vc_xmax2 = 0; +vc_ymin2 = 0; +vc_ymax2 = 0; +vc_cur_p = 0; + +for (i = 0; i < VC_YSIZE; i++) + vc_updated[i] = FALSE; + +if (dptr->flags & DEV_DIS) { + if (vc_active) { + free (vc_buf); + vc_buf = NULL; + free (vc_lines); + vc_lines = NULL; + vc_active = FALSE; + return vid_close (); + } + else + return SCPE_OK; + } + +if (!vid_active && !vc_active) { + r = vid_open (dptr, NULL, VC_XSIZE, VC_YSIZE, vc_input_captured ? SIM_VID_INPUTCAPTURED : 0); /* display size */ + if (r != SCPE_OK) + return r; + vc_buf = (uint32 *) calloc (VC_BUFSIZE, sizeof (uint32)); + if (vc_buf == NULL) { + vid_close (); + return SCPE_MEM; + } + vc_lines = (uint32 *) calloc (VC_XSIZE * VC_YSIZE, sizeof (uint32)); + if (vc_lines == NULL) { + free (vc_buf); + vid_close (); + return SCPE_MEM; + } + vc_palette[0] = vid_map_rgb (0x00, 0x00, 0x00); /* black */ + vc_palette[1] = vid_map_rgb (0xFF, 0xFF, 0xFF); /* white */ + sim_printf ("Monochrome Video Display Created. "); + vc_show_capture (stdout, NULL, 0, NULL); + if (sim_log) + vc_show_capture (sim_log, NULL, 0, NULL); + sim_printf ("\n"); + vc_active = TRUE; + } +sim_activate_abs (&vc_unit, tmxr_poll); +return SCPE_OK; +} + +t_stat vc_detach (UNIT *uptr) +{ +if ((vc_dev.flags & DEV_DIS) == 0) { + vc_dev.flags |= DEV_DIS; + vc_reset(&vc_dev); + } +return SCPE_OK; +} + +t_stat vc_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +return cpu_set_model (NULL, 0, (val ? "VAXSTATION" : "MICROVAX"), NULL); +} + +t_stat vc_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +if (vid_active) + return sim_messagef (SCPE_ALATT, "Capture Mode Can't be changed with device enabled\n"); +vc_input_captured = val; +return SCPE_OK; +} + +t_stat vc_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc) +{ +if (vc_input_captured) { + fprintf (st, "Captured Input Mode, "); + vid_show_release_key (st, uptr, val, desc); + } +else + fprintf (st, "Uncaptured Input Mode"); +return SCPE_OK; +} + +t_stat vc_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Monochrome Video Subsystem (%s)\n\n", dptr->name); +fprintf (st, "Use the Control-Right-Shift key combination to regain focus from the simulated\n"); +fprintf (st, "video display\n"); +fprint_set_help (st, dptr); +fprint_show_help (st, dptr); +fprint_reg_help (st, dptr); +return SCPE_OK; +} + +const char *vc_description (DEVICE *dptr) +{ +return "Monochrome Graphics Adapter"; +} diff --git a/VAX/vax4xx_ve.c b/VAX/vax4xx_ve.c new file mode 100644 index 00000000..fcdf526c --- /dev/null +++ b/VAX/vax4xx_ve.c @@ -0,0 +1,1522 @@ +/* vax4xx_ve.c: SPX video simulator + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + ve SPX colour video +*/ + +#include "vax_defs.h" +#include "sim_video.h" +#include "vax_lk.h" +#include "vax_vs.h" + +#include "vax_ka4xx_spx_bin.h" + +#define VE_XSIZE 1280 /* visible width */ +#define VE_YSIZE 1024 /* visible height */ + +#define VE_BXSIZE 1280 /* buffer width */ +#define VE_BYSIZE 2048 /* buffer height */ +#define VE_BUFSIZE 0x280000 /* number of bytes */ +#define VE_ORSC 3 /* screen origin multiplier */ + +#define PUTL(b,x,v) b[x+3] = (v >> 24) & 0xFF; \ + b[x+2] = (v >> 16) & 0xFF; \ + b[x+1] = (v >> 8) & 0xFF; \ + b[x] = v & 0xFF +#define PUTW(b,x,v) b[x+1] = (v >> 8) & 0xFF; \ + b[x] = v & 0xFF +#define GETL(b,x) ((b[x+3] << 24) | \ + (b[x+2] << 16) | \ + (b[x+1] << 8) | \ + b[x]) +#define GETW(b,x) ((b[x+1] << 8)|b[x]) + +#define CURSOR_X_OFFSET 216 +#define CURSOR_Y_OFFSET 33 + +#define CMD_TEST 0x8000 +#define CMD_HSHI 0x4000 +#define CMD_VBHI 0x2000 +#define CMD_LODSA 0x1000 +#define CMD_FORG2 0x0800 +#define CMD_ENRG2 0x0400 +#define CMD_FORG1 0x0200 +#define CMD_ENRG1 0x0100 +#define CMD_XHWID 0x0080 +#define CMD_XHCL1 0x0040 +#define CMD_XHCLP 0x0020 +#define CMD_XHAIR 0x0010 +#define CMD_FOPB 0x0008 +#define CMD_ENPB 0x0004 +#define CMD_FOPA 0x0002 +#define CMD_ENPA 0x0001 + +#define TBC_CMD_F0EN 0x00000001 +#define TBC_CMD_F0DS 0x00000002 +#define TBC_CMD_F0OP 0x00000004 +#define TBC_CMD_F0IN 0x00000008 + +#define TBC_CMD_FIFOEN(x) (TBC_CMD_F0EN << ((x * 5) + ((x == 3) ? 1 : 0))) +#define TBC_CMD_FIFODIS(x) (TBC_CMD_F0DS << ((x * 5) + ((x == 3) ? 1 : 0))) +#define TBC_CMD_FIFOOUT(x) (TBC_CMD_F0OP << ((x * 5) + ((x == 3) ? 1 : 0))) +#define TBC_CMD_FIFOIN(x) (TBC_CMD_F0IN << ((x * 5) + ((x == 3) ? 1 : 0))) + +#define TBC_CMD_F1EN 0x00000020 +#define TBC_CMD_F1DS 0x00000040 +#define TBC_CMD_F2EN 0x00000400 +#define TBC_CMD_F2DS 0x00000800 +#define TBC_CMD_F3EN 0x00010000 +#define TBC_CMD_F3DS 0x00020000 +#define TBC_CMD_F3IN 0x00080000 +#define TBC_CMD_STRW 0x40000000 +#define TBC_CMD_STRR 0x80000000 + +#define TBC_CSR_F0DR 0x00100000 +#define TBC_CSR_F1DR 0x00200000 +#define TBC_CSR_F2DR 0x00400000 +#define TBC_CSR_F3DR 0x00800000 +#define TBC_CSR_F0EN 0x00010000 +#define TBC_CSR_F1EN 0x00020000 +#define TBC_CSR_F2EN 0x00040000 +#define TBC_CSR_F3EN 0x00080000 + +#define TBC_CSR_FIFODIR(x) (TBC_CSR_F0DR << x) +#define TBC_CSR_FIFOEN(x) (TBC_CSR_F0EN << x) +#define TBC_CSR_STRDIR 0x00000400 +#define TBC_CSR_STRSTAT 0x00000800 + +#define INTSTS_F0_GE_THRSH 0x00000100 +#define INTSTS_F0_LT_THRSH 0x00000200 + +#define GET_FIFO(x) ((x >> 3) - 2) +#define FIFO_LEN 0x4000 + +extern int32 tmxr_poll; +extern int32 ka_cfgtst; +extern uint32 vc_org; +extern uint32 vc_last_org; + +struct fifo_reg_t { + uint32 buf[FIFO_LEN >> 2]; + uint32 put_ptr; + uint32 get_ptr; + uint32 count; + uint32 threshold; + uint32 semaphore; + }; + +typedef struct fifo_reg_t FIFO_REG; + +uint32 bt459_addr = 0; +uint32 bt459_cmap_p = 0; +uint32 bt459_cmap[3]; +uint32 cp_fb_format = 0; +uint32 cp_int_status = 0; +uint32 cp_int_mask = 0; +uint32 gf_fb_format = 0; +uint32 spx_xstart = 0; +uint32 spx_ystart = 0; +uint32 spx_xend = 0; +uint32 spx_yend = 0; +uint32 spx_dstpix = 0; +uint32 spx_srcpix = 0; +uint32 spx_fg = 0; +uint32 spx_cmd = 0; +uint32 spx_rmask = 0; +uint32 spx_wmask = 0; +uint32 spx_smask = 0; +uint32 spx_dmask = 0; +uint32 spx_strx = 0; +uint32 spx_stry = 0; +uint32 spx_destloop = 0; +uint32 spx_upc = 0; /* micro pc */ +uint32 spx_status = 0; +uint32 tbc_csr = 0; +FIFO_REG tbc_fifo[4]; +uint32 tbc_table = 0; +uint32 tbc_timing_setup = 0; +uint32 spx_timing_csr = 0; +uint32 tbc_ltrr = 0; +uint32 tbc_timing = 0; +t_bool ve_input_captured = FALSE; /* Mouse and Keyboard input captured in video window */ +uint8 *ve_buf = NULL; /* Video memory */ +uint32 *ve_lines = NULL; /* Video Display Lines */ +uint32 ve_palette[256]; +t_bool ve_updated[VE_YSIZE]; +t_bool ve_active = FALSE; + +t_stat ve_svc (UNIT *uptr); +t_stat ve_micro_svc (UNIT *uptr); +t_stat ve_reset (DEVICE *dptr); +t_stat ve_detach (UNIT *dptr); +t_stat ve_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat ve_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat ve_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc); +t_stat ve_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *ve_description (DEVICE *dptr); +int32 tbc_rd (int32 rg); +void tbc_wr (int32 rg, int32 val, int32 lnt); +int32 scn_rd (int32 rg); +void scn_wr (int32 rg, int32 val, int32 lnt); + + +/* VE data structures + + ve_dev VE device descriptor + ve_unit VE unit descriptor + ve_reg VE register list +*/ + +DIB ve_dib = { + VE_ROM_INDEX, BOOT_CODE_ARRAY, BOOT_CODE_SIZE + }; + +UNIT ve_unit[] = { + { UDATA (&ve_svc, UNIT_IDLE, 0) }, + { UDATA (&ve_micro_svc, UNIT_IDLE+UNIT_DIS, 0) } + }; + +REG ve_reg[] = { + { NULL } + }; + +/* Debugging Bitmaps */ + +#define DBG_REG 0x0100 /* register activity */ +#define DBG_ROP 0x0200 /* raster operations */ + +DEBTAB ve_debug[] = { + {"REG", DBG_REG, "Register activity"}, + {"ROP", DBG_ROP, "Raster operations"}, + {"VMOUSE", SIM_VID_DBG_MOUSE, "Video Mouse"}, + {"VCURSOR", SIM_VID_DBG_CURSOR, "Video Cursor"}, + {"VKEY", SIM_VID_DBG_KEY, "Video Key"}, + {"VVIDEO", SIM_VID_DBG_VIDEO, "Video Video"}, + { 0 } + }; + +MTAB ve_mod[] = { + { MTAB_XTD|MTAB_VDV, 1, NULL, "ENABLE", + &ve_set_enable, NULL, NULL, "Enable VCB01 (QVSS)" }, + { MTAB_XTD|MTAB_VDV, 0, NULL, "DISABLE", + &ve_set_enable, NULL, NULL, "Disable VCB01 (QVSS)" }, + { MTAB_XTD|MTAB_VDV, TRUE, NULL, "CAPTURE", + &ve_set_capture, &ve_show_capture, NULL, "Enable Captured Input Mode" }, + { MTAB_XTD|MTAB_VDV, FALSE, NULL, "NOCAPTURE", + &ve_set_capture, NULL, NULL, "Disable Captured Input Mode" }, + { MTAB_XTD|MTAB_VDV, TRUE, "OSCURSOR", NULL, + NULL, &ve_show_capture, NULL, "Display Input Capture mode" }, + { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "VIDEO", NULL, + NULL, &vid_show_video, NULL, "Display the host system video capabilities" }, + { 0 } + }; + +DEVICE ve_dev = { + "VE", ve_unit, ve_reg, ve_mod, + 2, 10, 31, 1, DEV_RDX, 8, + NULL, NULL, &ve_reset, + NULL, NULL, &ve_detach, + &ve_dib, DEV_DIS | DEV_DEBUG, 0, + ve_debug, NULL, NULL, &ve_help, NULL, NULL, + &ve_description + }; + +/* VE routines + + ve_rd I/O page read + ve_wr I/O page write + ve_svc process event + ve_reset process reset + ve_detach process detach +*/ + +int32 ve_rd (int32 pa) +{ +int32 rg = ((pa - 0x38000000) >> 2); +uint32 data = 0; + +if (pa >= 0x39bc0000) { /* ROMCFG */ + data = 0xC0000202; /* from real hardware */ + sim_debug (DBG_REG, &ve_dev, "rom_cfg %X rd %X at %08X\n", pa, data, fault_PC); + return data; + } +if (pa >= 0x39b20000) { + rg = rg & 0xFFF; + if (pa >= 0x39b23000) { + sim_debug (DBG_REG, &ve_dev, "direct_fifo 3 %X rd at %08X\n", pa, fault_PC); + return 0; + } + else if (pa >= 0x39b22000) { + sim_debug (DBG_REG, &ve_dev, "direct_fifo 2 %X rd at %08X\n", pa, fault_PC); + return 0; + } + else if (pa >= 0x39b21000) { + sim_debug (DBG_REG, &ve_dev, "direct_fifo 1 %X rd at %08X\n", pa, fault_PC); + return 0; + } + else { + data = tbc_fifo[0].buf[rg]; + sim_debug (DBG_REG, &ve_dev, "direct_fifo 0 %X rd %X at %08X\n", pa, data, fault_PC); + return data; + } + } +if (pa >= 0x39b1c000) { + sim_debug (DBG_REG, &ve_dev, "bt459 cmap %X rd\n", (bt459_addr & 0xFF)); + return 0; + } +if (pa >= 0x39b18000) { + sim_debug (DBG_REG, &ve_dev, "bt459 reg %X rd\n", bt459_addr); + return 0; + } +if (pa == 0x39b14000) { + /* sim_debug (DBG_REG, &ve_dev, "bt459 adrh %08X rd %X\n", pa); */ + return (bt459_addr >> 8) & 0xFF; + } +if (pa == 0x39b10000) { + /* sim_debug (DBG_REG, &ve_dev, "bt459 adrl %08X rd %X\n", pa); */ + return bt459_addr & 0xFF; + } +if (pa >= 0x39b00000) { + /* sim_debug (DBG_REG, &ve_dev, "spx reg1 %08X rd %X\n", pa); */ + rg = rg & 0xFF; + data = tbc_rd (rg); + return data; + } +/* if (pa >= 0x39300000) { */ +if ((pa & 0xFF000000) >= 0x39000000) { + /* sim_debug (DBG_REG, &ve_dev, "spx reg2 %08X rd %X\n", pa); */ + rg = rg & 0xFF; + /* if (pa >= 0x39303000) { */ + if ((pa & 0xFF00FFFF) > 0x39003000) { + switch (rg) { + case 0x5B: /* STATUS */ + sim_debug (DBG_REG, &ve_dev, "scanproc cmdalt rd at %08X\n", fault_PC); + break; + + case 0x5C: + sim_debug (DBG_REG, &ve_dev, "scanproc write_mask rd at %08X\n", fault_PC); + break; + + case 0x5D: + sim_debug (DBG_REG, &ve_dev, "scanproc read_mask rd at %08X\n", fault_PC); + break; + + default: + sim_debug (DBG_REG, &ve_dev, "scanproc %08X rd\n", pa); + break; + } + } + /* else if (pa >= 0x39302000) { */ + else if ((pa & 0xFF00FFFF) > 0x39002000) { + return scn_rd (rg); + } + else { + sim_debug (DBG_REG, &ve_dev, "scanproc %08X rd at %08X\n", pa, fault_PC); + } + return data; + } + +rg = pa & 0x3FFFFF; +return (GETL (ve_buf, rg) & spx_rmask); +} + +void ve_wr (int32 pa, int32 val, int32 lnt) +{ +int32 rg = ((pa - 0x38000000) >> 2); +uint32 scrln; + +if (pa >= 0x39b20000) { + rg = rg & 0xFFF; + if (pa >= 0x39b23000) { + sim_debug (DBG_REG, &ve_dev, "direct_fifo 3 %X wr %X\n", pa, val); + return; + } + else if (pa >= 0x39b22000) { + sim_debug (DBG_REG, &ve_dev, "direct_fifo 2 %X wr %X\n", pa, val); + return; + } + else if (pa >= 0x39b21000) { + sim_debug (DBG_REG, &ve_dev, "direct_fifo 1 %X wr %X\n", pa, val); + return; + } + else { + sim_debug (DBG_REG, &ve_dev, "direct_fifo 0 %X wr %X\n", pa, val); + tbc_fifo[0].buf[rg] = val; + return; + } + } +if (pa >= 0x39b1c000) { + /* sim_debug (DBG_REG, &ve_dev, "bt459 cmap %X wr %X\n", bt459_addr, val); */ + bt459_cmap[bt459_cmap_p++] = val; + if (bt459_cmap_p == 3) { + bt459_cmap_p = 0; + sim_debug (DBG_REG, &ve_dev, "bt459 cmap %X wr %X, %X, %X at %08X\n", (bt459_addr & 0xFF), bt459_cmap[0], bt459_cmap[1], bt459_cmap[2], fault_PC); + ve_palette[(bt459_addr & 0xFF)] = vid_map_rgb (bt459_cmap[0], bt459_cmap[1], bt459_cmap[2]); + sim_debug (DBG_REG, &ve_dev, "ve_palette[%d] = 0x%08X\n", (bt459_addr & 0xFF), ve_palette[(bt459_addr & 0xFF)]); + bt459_addr++; + if (bt459_addr == 0x100) bt459_addr = 0; + } + return; + } +if (pa >= 0x39b18000) { + sim_debug (DBG_REG, &ve_dev, "bt459 reg %X wr %X\n", bt459_addr, val); + return; + } +if (pa == 0x39b14000) { + bt459_addr = (bt459_addr & 0xFF) | ((val & 0xFF) << 8); + /* sim_debug (DBG_REG, &ve_dev, "bt459 adrh %08X wr %X (%X)\n", pa, val, bt459_addr); */ + return; + } +if (pa == 0x39b10000) { + bt459_addr = (bt459_addr & ~0xFF) | (val & 0xFF); + /* sim_debug (DBG_REG, &ve_dev, "bt459 adrl %08X wr %X (%X)\n", pa, val, bt459_addr); */ + return; + } +if (pa >= 0x39b00000) { + /* sim_debug (DBG_REG, &ve_dev, "tbc reg %X wr %X (%08X)\n", rg, val, pa); */ + rg = rg & 0xFF; + tbc_wr (rg, val, lnt); + return; + } +if (pa >= 0x39300000) { + /* sim_debug (DBG_REG, &ve_dev, "spx reg %X wr %X (%08X)\n", rg, val, pa); */ + rg = rg & 0xFF; + if (pa > 0x39303000) { + switch (rg) { + case 0x5B: /* STATUS */ + sim_debug (DBG_REG, &ve_dev, "scanproc cmdalt wr %X at %08X\n", val, fault_PC); + break; + + case 0x5C: + sim_debug (DBG_REG, &ve_dev, "scanproc write_mask wr %X at %08X\n", val, fault_PC); + spx_wmask = val; + break; + + case 0x5D: + sim_debug (DBG_REG, &ve_dev, "scanproc read_mask wr %X at %08X\n", val, fault_PC); + spx_rmask = val; + break; + + default: + sim_debug (DBG_REG, &ve_dev, "tbc %08X wr %X\n", pa, val); + break; + } + } + else { + scn_wr (rg, val, lnt); + return; + } + return; + } +if (pa >= 0x39000000) { + /* sim_debug (DBG_REG, &ve_dev, "spx reg %X wr %X (%08X)\n", rg, val, pa); */ + rg = rg & 0xFF; + scn_wr (rg, val, lnt); + return; + } + +rg = pa & 0x3FFFFF; + +if (lnt > L_WORD) { + PUTL (ve_buf, rg, (val & spx_wmask)); + } +else if (lnt > L_BYTE) { + PUTW (ve_buf, rg, (val & ((pa & 2) ? (spx_wmask >> 16) : spx_wmask))); + } +else + ve_buf[rg] = (val & (spx_wmask >> ((pa & 3) << 3))); + +scrln = ((rg / VE_BXSIZE) + (vc_org << VE_ORSC)); +if (scrln < VE_YSIZE) + ve_updated[scrln] = TRUE; /* flag as updated */ +return; +} + +void ve_put_fifo (uint32 id, uint32 data) +{ +if (tbc_fifo[id].count > 0) { + tbc_fifo[id].buf[tbc_fifo[id].put_ptr++] = data; + if (tbc_fifo[id].put_ptr == FIFO_LEN) + tbc_fifo[id].put_ptr = 0; + tbc_fifo[id].count = tbc_fifo[id].count - 4; + if (tbc_fifo[id].count >= tbc_fifo[id].threshold) { + } + } +} + +void ve_get_fifo (uint32 id, uint32 *data) +{ +if (tbc_fifo[id].count < FIFO_LEN) { + *data = tbc_fifo[id].buf[tbc_fifo[id].get_ptr++]; + if (tbc_fifo[id].get_ptr == FIFO_LEN) + tbc_fifo[id].get_ptr = 0; + tbc_fifo[id].count = tbc_fifo[id].count + 4; + } +} + +void ve_clear_fifo (uint32 id) +{ +tbc_fifo[id].put_ptr = 0; +tbc_fifo[id].get_ptr = 0; +tbc_fifo[id].count = FIFO_LEN; +} + +int32 tbc_rd (int32 rg) +{ +uint32 data = 0; + +switch (rg) { + case 0x0: + data = tbc_csr; + sim_debug (DBG_REG, &ve_dev, "tbc csr rd %X at %08X\n", data, fault_PC); + break; + + case 0x1: + sim_debug (DBG_REG, &ve_dev, "tbc cmd rd at %08X\n", fault_PC); /* no read? */ + break; + + case 0x3: + sim_debug (DBG_REG, &ve_dev, "tbc diag rd at %08X\n", fault_PC); + break; + + case 0x4: + /* sim_debug (DBG_REG, &ve_dev, "tbc cp_fb_format rd at %08X\n", fault_PC); */ + data = cp_fb_format; + break; + + case 0x5: + /* sim_debug (DBG_REG, &ve_dev, "tbc cp_int_mask rd at %08X\n", fault_PC); */ + data = cp_int_mask; + break; + + case 0x6: + /* sim_debug (DBG_REG, &ve_dev, "tbc cp_int_status rd at %08X\n", fault_PC); */ + data = cp_int_status; + break; + + case 0x8: + /* sim_debug (DBG_REG, &ve_dev, "tbc gf_fb_format rd at %08X\n", fault_PC); */ + data = gf_fb_format; + break; + + case 0x9: + sim_debug (DBG_REG, &ve_dev, "tbc gf_int_mask rd at %08X\n", fault_PC); + break; + + case 0xA: + sim_debug (DBG_REG, &ve_dev, "tbc gf_int_status rd at %08X\n", fault_PC); + break; + + case 0x10: /* FIFO0 Data */ + case 0x18: + case 0x20: + case 0x28: + ve_get_fifo (GET_FIFO(rg), &data); + if (tbc_csr & TBC_CSR_STRSTAT) { /* stream in progress? */ + if (tbc_fifo[GET_FIFO(rg)].count >= tbc_fifo[GET_FIFO(rg)].threshold) + sim_activate (&ve_unit[1], 200); /* get more data */ + } + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d data rd %X at %08X\n", GET_FIFO(rg), data, fault_PC); + break; + + case 0x11: + case 0x19: + case 0x21: + case 0x29: + data = tbc_fifo[GET_FIFO(rg)].put_ptr; + break; + + case 0x12: + case 0x1A: + case 0x22: + case 0x2A: + data = tbc_fifo[GET_FIFO(rg)].get_ptr; + break; + + case 0x13: /* FIFO0 Count */ + case 0x1B: + case 0x23: + case 0x2B: + data = tbc_fifo[GET_FIFO(rg)].count; + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d count rd %X at %08X\n", GET_FIFO(rg), data, fault_PC); + break; + + case 0x14: + case 0x1C: + case 0x24: + case 0x2C: + data = tbc_fifo[GET_FIFO(rg)].threshold; + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d threshold rd %X at %08X\n", GET_FIFO(rg), data, fault_PC); + break; + + case 0x15: + case 0x1D: + case 0x25: + case 0x2D: + data = tbc_fifo[GET_FIFO(rg)].semaphore; + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d semaphore rd %X at %08X\n", GET_FIFO(rg), data, fault_PC); + break; + + case 0x40: + tbc_timing = tbc_timing ^ 0x14000; + data = tbc_timing; + sim_debug (DBG_REG, &ve_dev, "tbc timing_csr rd %X at %08X\n", data, fault_PC); + break; + + case 0x41: + sim_debug (DBG_REG, &ve_dev, "tbc hsync rd at %08X\n", fault_PC); + break; + + case 0x42: + sim_debug (DBG_REG, &ve_dev, "tbc hsync2 rd at %08X\n", fault_PC); + break; + + case 0x43: + sim_debug (DBG_REG, &ve_dev, "tbc early_hblank rd at %08X\n", fault_PC); + break; + + case 0x44: + sim_debug (DBG_REG, &ve_dev, "tbc vsync rd at %08X\n", fault_PC); + break; + + case 0x45: + sim_debug (DBG_REG, &ve_dev, "tbc vblank rd at %08X\n", fault_PC); + break; + + case 0x46: + data = tbc_table; + sim_debug (DBG_REG, &ve_dev, "tbc table rd %X at %08X\n", data, fault_PC); + break; + + case 0x47: + data = tbc_timing_setup; + sim_debug (DBG_REG, &ve_dev, "tbc timing_setup rd %X at %08X\n", data, fault_PC); + break; + + case 0x48: + data = tbc_ltrr; + tbc_ltrr++; + if (tbc_ltrr == 5) tbc_ltrr = 0; + sim_debug (DBG_REG, &ve_dev, "tbc ltrr rd %X at %08X\n", data, fault_PC); + break; + + case 0x50: + sim_debug (DBG_REG, &ve_dev, "tbc sp_bus_loop rd at %08X\n", fault_PC); + break; + + default: + sim_debug (DBG_REG, &ve_dev, "tbc %X rd at %08X\n", rg, fault_PC); + break; + } +return data; +} + +void tbc_wr (int32 rg, int32 val, int32 lnt) +{ +uint32 i; + +switch (rg) { + case 0x0: + sim_debug (DBG_REG, &ve_dev, "tbc csr wr %X at %08X\n", val, fault_PC); + break; + + case 0x1: + sim_debug (DBG_REG, &ve_dev, "tbc cmd wr %X at %08X\n", val, fault_PC); + for (i = 0; i < 4; i++) { + if (val & TBC_CMD_FIFOEN(i)) { + tbc_csr |= TBC_CSR_FIFOEN(i); + sim_debug (DBG_REG, &ve_dev, "fifo %d enable\n", i); + } + else if (val & TBC_CMD_FIFODIS(i)) { + tbc_csr &= ~TBC_CSR_FIFOEN(i); + sim_debug (DBG_REG, &ve_dev, "fifo %d disable\n", i); + } + if (val & TBC_CMD_FIFOOUT(i)) { + tbc_csr |= TBC_CSR_FIFODIR(i); + sim_debug (DBG_REG, &ve_dev, "fifo %d output\n", i); + } + else if (val & TBC_CMD_FIFOIN(i)) { + tbc_csr &= ~TBC_CSR_FIFODIR(i); + sim_debug (DBG_REG, &ve_dev, "fifo %d input\n", i); + } + } + if (val & 0x800000) { /* Input FIFO Load */ + tbc_csr = (tbc_csr & ~0x3) | ((val >> 21) & 0x3); + } + if (val & 0x4000000) { /* Output FIFO Load */ + tbc_csr = (tbc_csr & ~0x300) | ((val >> 16) & 0x300); + } + /* NOTE: + * Set STREAM_STATUS and STREAM direction for the + * following commands. + * 0 = INPUT (to card) + * 1 = OUTPUT (from card) + */ + if (val & TBC_CMD_STRW) { + sim_debug (DBG_REG, &ve_dev, "stream write\n"); + tbc_csr |= TBC_CSR_STRDIR; /* stream write */ + tbc_csr |= TBC_CSR_STRSTAT; /* stream active */ + } + else if (val & TBC_CMD_STRR) { + sim_debug (DBG_REG, &ve_dev, "stream read\n"); + tbc_csr &= ~TBC_CSR_STRDIR; /* stream read */ + tbc_csr |= TBC_CSR_STRSTAT; /* stream active */ + } + else { + sim_debug (DBG_REG, &ve_dev, "stream disable\n"); + tbc_csr &= ~TBC_CSR_STRDIR; + tbc_csr &= ~TBC_CSR_STRSTAT; /* stream inactive */ + } + break; + + case 0x3: + sim_debug (DBG_REG, &ve_dev, "tbc diag wr %X at %08X\n", val, fault_PC); + if (val & 0x10) { /* synchronous reset */ + for (i = 0; i < 4; i++) { + ve_clear_fifo (i); + } + sim_debug (DBG_REG, &ve_dev, "tbc reset\n"); + bt459_cmap_p = 0; + } + else if (val & 0x1) { + ve_clear_fifo (0); + sim_debug (DBG_REG, &ve_dev, "fifo0 reset\n"); + } + else if (val & 0x2) { + ve_clear_fifo (1); + sim_debug (DBG_REG, &ve_dev, "fifo1 reset\n"); + } + else if (val & 0x4) { + ve_clear_fifo (2); + sim_debug (DBG_REG, &ve_dev, "fifo2 reset\n"); + } + else if (val & 0x8) { + ve_clear_fifo (3); + sim_debug (DBG_REG, &ve_dev, "fifo3 reset\n"); + } + break; + + case 0x4: + /* sim_debug (DBG_REG, &ve_dev, "tbc cp_fb_format wr %X at %08X\n", val, fault_PC); */ + cp_fb_format = val; + break; + + case 0x5: + sim_debug (DBG_REG, &ve_dev, "tbc cp_int_mask wr %X at %08X\n", val, fault_PC); + cp_int_mask = val; + break; + + case 0x6: + /* sim_debug (DBG_REG, &ve_dev, "tbc cp_int_status wr %X at %08X\n", val, fault_PC); */ + cp_int_status = (cp_int_status & ~val); + break; + + case 0x8: + /* sim_debug (DBG_REG, &ve_dev, "tbc gf_fb_format wr %X at %08X\n", val, fault_PC); */ + gf_fb_format = val; + break; + + case 0x9: + sim_debug (DBG_REG, &ve_dev, "tbc gf_int_mask wr %X at %08X\n", val, fault_PC); + break; + + case 0xA: + sim_debug (DBG_REG, &ve_dev, "tbc gf_int_status wr %X at %08X\n", val, fault_PC); + break; + + case 0x10: /* FIFO0 Data */ + case 0x18: + case 0x20: + case 0x28: + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d data wr %X at %08X (ptr = %d)\n", GET_FIFO(rg), val, fault_PC, tbc_fifo[GET_FIFO(rg)].put_ptr); + ve_put_fifo (GET_FIFO(rg), val); + if (tbc_csr & TBC_CSR_STRSTAT) { /* stream in progress? */ + if (tbc_fifo[GET_FIFO(rg)].count < tbc_fifo[GET_FIFO(rg)].threshold) + sim_activate (&ve_unit[1], 200); /* flush data */ + } + break; + + case 0x11: + case 0x19: + case 0x21: + case 0x29: + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d put_ptr wr %X at %08X\n", GET_FIFO(rg), val, fault_PC); + tbc_fifo[GET_FIFO(rg)].put_ptr = val; + break; + + case 0x12: + case 0x1A: + case 0x22: + case 0x2A: + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d get_ptr wr %X at %08X\n", GET_FIFO(rg), val, fault_PC); + /* tbc_fifo[GET_FIFO(rg)].get_ptr = val; */ + break; + + case 0x13: /* FIFO0 Count */ + case 0x1B: + case 0x23: + case 0x2B: + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d count wr %X at %08X\n", GET_FIFO(rg), val, fault_PC); + tbc_fifo[GET_FIFO(rg)].count = val; + break; + + case 0x14: + case 0x1C: + case 0x24: + case 0x2C: + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d threshold wr %X at %08X\n", GET_FIFO(rg), val, fault_PC); + tbc_fifo[GET_FIFO(rg)].threshold = val; + break; + + case 0x15: + case 0x1D: + case 0x25: + case 0x2D: + sim_debug (DBG_REG, &ve_dev, "tbc fifo%d semaphore wr %X at %08X\n", GET_FIFO(rg), val, fault_PC); + tbc_fifo[GET_FIFO(rg)].semaphore = val; + break; + + case 0x40: + sim_debug (DBG_REG, &ve_dev, "tbc timing_csr wr %X at %08X\n", val, fault_PC); + tbc_timing = val; + break; + + case 0x41: + sim_debug (DBG_REG, &ve_dev, "tbc hsync wr %X at %08X\n", val, fault_PC); + break; + + case 0x42: + sim_debug (DBG_REG, &ve_dev, "tbc hsync2 wr %X at %08X\n", val, fault_PC); + break; + + case 0x43: + sim_debug (DBG_REG, &ve_dev, "tbc early_hblank wr %X at %08X\n", val, fault_PC); + break; + + case 0x44: + sim_debug (DBG_REG, &ve_dev, "tbc vsync wr %X at %08X\n", val, fault_PC); + break; + + case 0x45: + sim_debug (DBG_REG, &ve_dev, "tbc vblank wr %X at %08X\n", val, fault_PC); + break; + + case 0x46: + sim_debug (DBG_REG, &ve_dev, "tbc table wr %X at %08X\n", val, fault_PC); + tbc_table = val; + break; + + case 0x47: + sim_debug (DBG_REG, &ve_dev, "tbc timing_setup wr %X at %08X\n", val, fault_PC); + tbc_timing_setup = val; + break; + + case 0x48: + sim_debug (DBG_REG, &ve_dev, "tbc ltrr wr %X at %08X\n", val, fault_PC); + break; + + case 0x50: + sim_debug (DBG_REG, &ve_dev, "tbc sp_bus_loop wr %X at %08X\n", val, fault_PC); + break; + + default: + sim_debug (DBG_REG, &ve_dev, "tbc %X wr %X at %08X\n", rg, val, fault_PC); + break; + } +} + +int32 scn_rd (int32 rg) +{ +uint32 data = 0; + +switch (rg) { + case 0x40: /* STATUS */ + data = spx_status; + sim_debug (DBG_REG, &ve_dev, "scanproc status rd %X at %08X\n", data, fault_PC); + break; + + case 0x46: + sim_debug (DBG_REG, &ve_dev, "scanproc config rd at %08X\n", fault_PC); + break; + + case 0x7F: + sim_debug (DBG_REG, &ve_dev, "scanproc micropc rd at %08X\n", fault_PC); + break; + + case 0xFE: + /* sim_debug (DBG_REG, &ve_dev, "scanproc microlo rd at %08X\n", fault_PC); */ + break; + + case 0x4B: + /* sim_debug (DBG_REG, &ve_dev, "scanproc microhi rd at %08X\n", fault_PC); */ + break; + + case 0x80: + sim_debug (DBG_REG, &ve_dev, "scanproc rowframe rd at %08X\n", fault_PC); + break; + + case 0x0: + sim_debug (DBG_REG, &ve_dev, "scanproc rowframe_mask rd at %08X\n", fault_PC); + break; + + case 0x64: + sim_debug (DBG_REG, &ve_dev, "scanproc maingreg0 rd at %08X\n", fault_PC); + break; + + case 0x24: + sim_debug (DBG_REG, &ve_dev, "scanproc mainreg0_mask rd at %08X\n", fault_PC); + break; + + case 0x82: + sim_debug (DBG_REG, &ve_dev, "scanproc winoffset rd at %08X\n", fault_PC); + break; + + case 0x7B: + sim_debug (DBG_REG, &ve_dev, "scanproc command rd at %08X\n", fault_PC); + break; + + case 0x74: + sim_debug (DBG_REG, &ve_dev, "scanproc xstart rd at %08X\n", fault_PC); + break; + + case 0x75: + sim_debug (DBG_REG, &ve_dev, "scanproc ystart rd at %08X\n", fault_PC); + break; + + case 0x76: + sim_debug (DBG_REG, &ve_dev, "scanproc xend rd at %08X\n", fault_PC); + break; + + case 0x77: + sim_debug (DBG_REG, &ve_dev, "scanproc yend rd at %08X\n", fault_PC); + break; + + case 0x78: + sim_debug (DBG_REG, &ve_dev, "scanproc dstpix rd at %08X\n", fault_PC); + break; + + case 0x38: + sim_debug (DBG_REG, &ve_dev, "scanproc dstpix1 rd at %08X\n", fault_PC); + break; + + case 0x79: + sim_debug (DBG_REG, &ve_dev, "scanproc srcpix rd at %08X\n", fault_PC); + break; + + case 0x39: + sim_debug (DBG_REG, &ve_dev, "scanproc srcpix1 rd at %08X\n", fault_PC); + break; + + case 0x67: + sim_debug (DBG_REG, &ve_dev, "scanproc main3 rd at %08X\n", fault_PC); + break; + + case 0x7A: + sim_debug (DBG_REG, &ve_dev, "scanproc stride rd at %08X\n", fault_PC); + break; + + case 0x7C: + sim_debug (DBG_REG, &ve_dev, "scanproc srcmask rd at %08X\n", fault_PC); + break; + + case 0x7D: + sim_debug (DBG_REG, &ve_dev, "scanproc dstmask rd at %08X\n", fault_PC); + break; + + case 0x98: + sim_debug (DBG_REG, &ve_dev, "scanproc fg rd at %08X\n", fault_PC); + break; + + case 0x99: + sim_debug (DBG_REG, &ve_dev, "scanproc bg rd at %08X\n", fault_PC); + break; + + case 0x9C: + sim_debug (DBG_REG, &ve_dev, "scanproc destloop rd at %08X\n", fault_PC); + break; + + default: + sim_debug (DBG_REG, &ve_dev, "scanproc %X rd at %08X\n", rg, fault_PC); + break; + } +return data; +} + +void scn_wr (int32 rg, int32 val, int32 lnt) +{ +switch (rg) { + case 0x40: /* STATUS */ + sim_debug (DBG_REG, &ve_dev, "scanproc status wr %X at %08X\n", val, fault_PC); + spx_status = (spx_status & ~val); + break; + + case 0x46: + sim_debug (DBG_REG, &ve_dev, "scanproc config wr %X at %08X\n", val, fault_PC); + break; + + case 0x7F: + sim_debug (DBG_REG, &ve_dev, "scanproc micropc wr %X at %08X\n", val, fault_PC); + spx_upc = val & 0xFFFF; + sim_activate (&ve_unit[1], 200); + break; + + case 0xFE: + /* sim_debug (DBG_REG, &ve_dev, "scanproc microlo wr %X at %08X\n", val, fault_PC); */ + break; + + case 0x4B: + /* sim_debug (DBG_REG, &ve_dev, "scanproc microhi wr %X at %08X\n", val, fault_PC); */ + break; + + case 0x80: + sim_debug (DBG_REG, &ve_dev, "scanproc rowframe wr %X at %08X\n", val, fault_PC); + break; + + case 0x0: + sim_debug (DBG_REG, &ve_dev, "scanproc rowframe_mask wr %X at %08X\n", val, fault_PC); + break; + + case 0x64: + sim_debug (DBG_REG, &ve_dev, "scanproc maingreg0 wr %X at %08X\n", val, fault_PC); + break; + + case 0x24: + sim_debug (DBG_REG, &ve_dev, "scanproc mainreg0_mask wr %X at %08X\n", val, fault_PC); + break; + + case 0x82: + sim_debug (DBG_REG, &ve_dev, "scanproc winoffset wr %X at %08X\n", val, fault_PC); + break; + + case 0x7B: + sim_debug (DBG_REG, &ve_dev, "scanproc command wr %X at %08X\n", val, fault_PC); + spx_cmd = val; + break; + + case 0xF4: + case 0x74: + sim_debug (DBG_REG, &ve_dev, "scanproc xstart wr %X at %08X\n", val, fault_PC); + spx_xstart = val; + break; + + case 0xF5: + case 0x75: + sim_debug (DBG_REG, &ve_dev, "scanproc ystart wr %X at %08X\n", val, fault_PC); + spx_ystart = val; + break; + + case 0xF6: + case 0x76: + sim_debug (DBG_REG, &ve_dev, "scanproc xend wr %X at %08X\n", val, fault_PC); + spx_xend = val; + break; + + case 0xF7: + case 0x77: + sim_debug (DBG_REG, &ve_dev, "scanproc yend wr %X at %08X\n", val, fault_PC); + spx_yend = val; + break; + + case 0x78: + sim_debug (DBG_REG, &ve_dev, "scanproc dstpix wr %X at %08X\n", val, fault_PC); + spx_dstpix = val; + break; + + case 0x38: + sim_debug (DBG_REG, &ve_dev, "scanproc dstpix1 wr %X at %08X\n", val, fault_PC); + break; + + case 0x79: + sim_debug (DBG_REG, &ve_dev, "scanproc srcpix wr %X at %08X\n", val, fault_PC); + spx_srcpix = val; + break; + + case 0x39: + sim_debug (DBG_REG, &ve_dev, "scanproc srcpix1 wr %X at %08X\n", val, fault_PC); + break; + + case 0x67: + sim_debug (DBG_REG, &ve_dev, "scanproc main3 wr %X at %08X\n", val, fault_PC); + break; + + case 0xFA: + case 0x7A: + sim_debug (DBG_REG, &ve_dev, "scanproc stride wr %X at %08X\n", val, fault_PC); + break; + + case 0x7C: + sim_debug (DBG_REG, &ve_dev, "scanproc srcmask wr %X at %08X\n", val, fault_PC); + spx_smask = val; + break; + + case 0x7D: + sim_debug (DBG_REG, &ve_dev, "scanproc dstmask wr %X at %08X\n", val, fault_PC); + spx_dmask = val; + break; + + case 0xD8: + case 0x98: + sim_debug (DBG_REG, &ve_dev, "scanproc fg wr %X at %08X\n", val, fault_PC); + spx_fg = val; + break; + + case 0x99: + sim_debug (DBG_REG, &ve_dev, "scanproc bg wr %X at %08X\n", val, fault_PC); + break; + + case 0x9C: + sim_debug (DBG_REG, &ve_dev, "scanproc destloop wr %X at %08X\n", val, fault_PC); + spx_destloop = val; + break; + + default: + sim_debug (DBG_REG, &ve_dev, "scanproc %X wr %X\n", rg, val); + break; + } +} + +void spx_fill_rect (void) +{ +uint32 xstart, xend, ystart, yend; +uint32 dstpix; +uint32 x, y; + +xstart = (spx_xstart >> 16); +ystart = (spx_ystart >> 16); +xend = (spx_xend >> 16); +yend = (spx_yend >> 16); +if (spx_cmd & 0x400) /* absolute coordinates */ + dstpix = 0; +else + dstpix = spx_dstpix & 0xFFFFFF; + +sim_debug (DBG_ROP, &ve_dev, "fill_rect: xs = %d, xe = %d, ys = %d, ye = %d, dx = %d, dy = %d, fg = %X\n", + xstart, xend, ystart, yend, (dstpix % 1280), (dstpix / 1280), (spx_fg & 0xFF)); + +if (xend > VE_BXSIZE) /* clip X */ + xend = VE_BXSIZE; +if (yend > VE_BYSIZE) /* clip Y */ + yend = VE_BYSIZE; + +if ((spx_destloop & 0xFFFF) != 0x2006) { + for (y = ystart; y < yend; y++) { + for (x = xstart; x < xend; x++) { + ve_buf[((y * 1280) + x + dstpix)] = (spx_fg & 0xFF); + } + if (y < VE_YSIZE) + ve_updated[y] = TRUE; /* FIXME: map to screen line */ + } + } +cp_int_status |= 0x2; +} + +void spx_copy_rect (void) +{ +uint32 xstart, xend, ystart, yend; +uint32 srcpix, dstpix; +uint32 x, y; + +xstart = (spx_xstart >> 16); +ystart = (spx_ystart >> 16); +xend = (spx_xend >> 16); +yend = (spx_yend >> 16); +srcpix = spx_srcpix & 0xFFFFFF; +if (spx_cmd & 0x400) /* absolute coordinates */ + dstpix = 0; +else + dstpix = spx_dstpix & 0xFFFFFF; + +sim_debug (DBG_ROP, &ve_dev, "copy_rect: xs = %d, xe = %d, ys = %d, ye = %d, sx = %d, sy = %d, dx = %d, dy = %d\n", + xstart, xend, ystart, yend, (srcpix % 1280), (srcpix / 1280), (dstpix % 1280), (dstpix / 1280)); + +if (xend > VE_BXSIZE) /* clip X */ + xend = VE_BXSIZE; +if (yend > VE_BYSIZE) /* clip Y */ + yend = VE_BYSIZE; + +for (y = ystart; y < yend; y++) { + for (x = xstart; x < xend; x++) { + ve_buf[((y * 1280) + x + dstpix)] = \ + (ve_buf[((y * 1280) + x + dstpix)] & ~spx_dmask) | \ + (ve_buf[(((y - ystart) * 1280) + (x - xstart) + srcpix)] & spx_smask); + } + if (y < VE_YSIZE) + ve_updated[y] = TRUE; /* FIXME: map to screen line */ + } +cp_int_status |= 0x2; +} + +void spx_stream_data () +{ +uint32 xstart, xend, ystart, yend; +uint32 dstpix; +uint32 data, i; + +xstart = (spx_xstart >> 16); +ystart = (spx_ystart >> 16); +xend = (spx_xend >> 16); +yend = (spx_yend >> 16); + +if (spx_cmd & 0x400) /* absolute coordinates */ + dstpix = 0; +else + dstpix = spx_dstpix & 0xFFFFFF; +spx_strx = xstart; +spx_stry = ystart; + +sim_debug (DBG_ROP, &ve_dev, "stream_data: xs = %d, xe = %d, ys = %d, ye = %d, dx = %d, dy = %d\n", + xstart, xend, ystart, yend, (dstpix % 1280), (dstpix / 1280)); + +if (tbc_csr & TBC_CSR_STRDIR) { /* write */ + while (tbc_fifo[0].count < FIFO_LEN) { + ve_get_fifo (0, &data); + sim_debug (DBG_REG, &ve_dev, "buffer[%X] = %X\n", ((spx_stry * 1280) + spx_strx + dstpix), ((data >> (i << 3)) & 0xFF)); + for (i = 0; i < 4; i++) { + ve_buf[((spx_stry * 1280) + spx_strx + dstpix)] = ((data >> (i << 3)) & 0xFF); + spx_strx++; + if (spx_stry < VE_YSIZE) + ve_updated[spx_stry] = TRUE; + if (spx_strx > xend) { + spx_strx = xstart; + spx_stry++; + } + if (spx_stry > yend) { + cp_int_status |= 0x2; /* Done */ + spx_status |= 0x100; /* Done */ + tbc_csr &= ~TBC_CSR_STRSTAT; + sim_debug (DBG_REG, &ve_dev, "stream done\n"); + return; + } + } + } + } +else { /* read */ + while (tbc_fifo[0].count > 0) { + data = 0; + for (i = 0; i < 4; i++) { + if (spx_strx > xend) { + spx_strx = xstart; + spx_stry++; + } + if (spx_stry > yend) break; + /* sim_debug (DBG_REG, &ve_dev, "buffer[%X] = %X\n", ((spx_stry * 1280) + spx_strx + dstpix), ((val >> (i << 3)) & spx_wmask & 0xFF)); */ + data |= (((ve_buf[((spx_stry * 1280) + spx_strx + dstpix)]) & spx_rmask & 0xFF) << (i << 3)); + spx_strx++; + + if (spx_stry > yend) { + cp_int_status |= 0x2; + return; + } + } + ve_put_fifo (0, data); + } + } +} + +t_stat ve_micro_svc (UNIT *uptr) +{ +switch (spx_upc) { + + case 0x23AE: + case 0x2019: + spx_fill_rect (); + break; + + case 0x1F: + case 0x239C: /* Read? */ + case 0x23A2: /* Bitmap write? */ + case 0x53: + spx_stream_data (); + break; + + case 0x23CB: + case 0xA9: + spx_copy_rect (); + break; + + case 0x2153: /* Load microcode? */ + break; + + default: + sim_debug (DBG_REG, &ve_dev, "unknown scanproc micropc %X\n", spx_upc); + } +return SCPE_OK; +} + +static SIM_INLINE void ve_invalidate (uint32 y1, uint32 y2) +{ +uint32 ln; + +for (ln = y1; ln < y2; ln++) + ve_updated[ln] = TRUE; /* flag as updated */ +} + +t_stat ve_svc (UNIT *uptr) +{ +SIM_MOUSE_EVENT mev; +SIM_KEY_EVENT kev; +t_bool updated = FALSE; /* flag for refresh */ +uint32 lines; +uint32 ln, col, off; +uint32 i, c; +uint32 rg, val; + +for (i = 0; i < 4; i++) { + if (tbc_csr & TBC_CSR_FIFOEN(i)) { + if (tbc_fifo[i].count >= tbc_fifo[i].threshold) + cp_int_status |= (INTSTS_F0_GE_THRSH << (4 * i)); + else + cp_int_status |= (INTSTS_F0_LT_THRSH << (4 * i)); + if ((tbc_fifo[i].count & 1) == 0) { + while (tbc_fifo[i].count < FIFO_LEN) { /* while fifo not empty */ + /* NOTE: + * if ((tbc_csr & STREAM_STATUS) && ((tbc_csr & STREAM_DIRECTION) == INPUT)) + * stream to bitmap + * else if ((tbc_csr & STREAM_STATUS) && ((tbc_csr & STREAM_DIRECTION) == OUTPUT)) + * stream from bitmap + * else + * register writes + */ + sim_debug (DBG_REG, &ve_dev, "get_ptr = %d, put_ptr = %d\n", tbc_fifo[i].get_ptr, tbc_fifo[i].put_ptr); + if ((tbc_csr & TBC_CSR_STRSTAT) == 0) { + ve_get_fifo (i, &rg); + switch ((rg >> 20) & 0x3) { + case 0: /* SCN reg SWZ=0 */ + case 1: /* SCN reg SWZ=1 */ + rg = (rg >> 2) & 0xFF; + ve_get_fifo (i, &val); + sim_debug (DBG_REG, &ve_dev, "scn_wr(%X, %X)\n", rg, val); + scn_wr (rg, val, L_LONG); + break; + + case 2: /* TBC reg */ + rg = (rg >> 2) & 0xFF; + ve_get_fifo (i, &val); + sim_debug (DBG_REG, &ve_dev, "tbc_wr(%X, %X)\n", rg, val); + tbc_wr (rg, val, L_LONG); + break; + } + } + } + } + } + } +cp_int_status |= 0x10; /* VBLANK Finish */ +cp_int_status |= 0x1; /* Ready */ +spx_status |= 0x200; /* Ready */ + +if (vid_poll_kb (&kev) == SCPE_OK) /* poll keyboard */ + lk_event (&kev); /* push event */ +if (vid_poll_mouse (&mev) == SCPE_OK) /* poll mouse */ + vs_event (&mev); /* push event */ + +if (vc_org != vc_last_org) /* origin moved? */ + ve_invalidate (0, (VE_YSIZE - 1)); /* redraw whole screen */ + +vc_last_org = vc_org; /* store video origin */ + +lines = 0; +for (ln = 0; ln < VE_YSIZE; ln++) { + if (ve_updated[ln]) { /* line invalid? */ + off = ((ln + (vc_org << VE_ORSC)) * VE_BXSIZE); /* get video buf offet */ + for (col = 0; col < VE_XSIZE; col++) + ve_lines[ln*VE_XSIZE + col] = ve_palette[ve_buf[off + col]]; + /* 8bpp to 32bpp */ +#if 0 + if (CUR_V) { /* cursor visible? */ + if ((ln >= CUR_Y) && (ln < (CUR_Y + 16))) { /* cursor on this line? */ + plna = &vc_cur[(CUR_PLNA + ln - CUR_Y)];/* get plane A base */ + plnb = &vc_cur[(CUR_PLNB + ln - CUR_Y)];/* get plane B base */ + for (col = 0; col < 16; col++) { + if ((CUR_X + col) >= VC_XSIZE) /* Part of cursor off screen? */ + continue; /* Skip */ + if (vc_cmd & CMD_FOPA) /* force plane A to 1? */ + bita = 1; + else if (vc_cmd & CMD_ENPA) /* plane A enabled? */ + bita = (*plna >> col) & 1; + else bita = 0; + if (vc_cmd & CMD_FOPB) /* force plane B to 1? */ + bitb = 1; + else if (vc_cmd & CMD_ENPB) /* plane B enabled? */ + bitb = (*plnb >> col) & 1; + else bitb = 0; + line[CUR_X + col] = ve_palette[((line[CUR_X + col] == ve_palette[1]) & ~bitb) ^ bita]; + } + } + } +#endif + ve_updated[ln] = FALSE; /* set valid */ + if ((ln == (VE_YSIZE-1)) || /* if end of window OR */ + (ve_updated[ln+1] == FALSE)) { /* next is already valid? */ + vid_draw (0, ln-lines, VE_XSIZE, lines+1, ve_lines+(ln-lines)*VE_XSIZE); /* update region */ + lines = 0; + } + else + lines++; + updated = TRUE; + } + } + +if (updated) /* video updated? */ + vid_refresh (); /* put to screen */ + +if (cp_int_status & cp_int_mask) + SET_INT (VC2); +sim_activate (uptr, tmxr_poll); +if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */ + return c; +return SCPE_OK; +} + +t_stat ve_reset (DEVICE *dptr) +{ +t_stat r; +uint32 i; + +CLR_INT (VC2); +sim_cancel (&ve_unit[0]); /* deactivate units */ +sim_cancel (&ve_unit[1]); + +bt459_addr = 0; +cp_fb_format = 0; +cp_int_status = 0; +cp_int_mask = 0; +gf_fb_format = 0; +spx_xstart = 0; +spx_ystart = 0; +spx_xend = 0; +spx_yend = 0; +spx_dstpix = 0; +spx_srcpix = 0; +bt459_cmap_p = 0; +bt459_cmap[0] = 0; +bt459_cmap[1] = 0; +bt459_cmap[2] = 0; +spx_fg = 0; +tbc_csr = 0; +spx_cmd = 0; +spx_rmask = 0; +spx_wmask = 0; +spx_smask = 0; +spx_dmask = 0; +spx_strx = 0; +spx_stry = 0; +spx_destloop = 0; +tbc_timing = 0; +spx_status = 0; + +for (i = 0; i < 4; i++) + ve_clear_fifo (i); + +for (i = 0; i < VE_YSIZE; i++) + ve_updated[i] = FALSE; + +if (dptr->flags & DEV_DIS) { + if (ve_active) { + free (ve_buf); + ve_buf = NULL; + free (ve_lines); + ve_lines = NULL; + ve_active = FALSE; + return vid_close (); + } + else + return SCPE_OK; + } + +if (!vid_active && !ve_active) { + r = vid_open (dptr, NULL, VE_XSIZE, VE_YSIZE, ve_input_captured ? SIM_VID_INPUTCAPTURED : 0);/* display size & capture mode */ + if (r != SCPE_OK) + return r; + ve_buf = (uint8 *) calloc (VE_BUFSIZE, sizeof (uint8)); + if (ve_buf == NULL) { + vid_close (); + return SCPE_MEM; + } + ve_lines = (uint32 *) calloc (VE_XSIZE*VE_YSIZE, sizeof (uint32)); + if (ve_lines == NULL) { + free (ve_buf); + vid_close (); + return SCPE_MEM; + } + sim_printf ("SPX Video Display Created. "); + ve_show_capture (stdout, NULL, 0, NULL); + if (sim_log) + ve_show_capture (sim_log, NULL, 0, NULL); + sim_printf ("\n"); + ve_active = TRUE; + } +sim_activate_abs (&ve_unit[0], tmxr_poll); +return SCPE_OK; +} + +t_stat ve_detach (UNIT *uptr) +{ +if ((ve_dev.flags & DEV_DIS) == 0) { + ve_dev.flags |= DEV_DIS; + ve_reset(&ve_dev); + } +return SCPE_OK; +} + +t_stat ve_set_enable (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +return cpu_set_model (NULL, 0, (val ? "VAXSTATIONSPX" : "MICROVAX"), NULL); +} + +t_stat ve_set_capture (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +if (vid_active) + return sim_messagef (SCPE_ALATT, "Capture Mode Can't be changed with device enabled\n"); +ve_input_captured = val; +return SCPE_OK; +} + +t_stat ve_show_capture (FILE* st, UNIT* uptr, int32 val, CONST void* desc) +{ +if (ve_input_captured) { + fprintf (st, "Captured Input Mode, "); + vid_show_release_key (st, uptr, val, desc); + } +else + fprintf (st, "Uncaptured Input Mode"); +return SCPE_OK; +} + +t_stat ve_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "SPX Colour Video Subsystem (%s)\n\n", dptr->name); +fprintf (st, "Use the Control-Right-Shift key combination to regain focus from the simulated\n"); +fprintf (st, "video display\n"); +fprint_set_help (st, dptr); +fprint_show_help (st, dptr); +fprint_reg_help (st, dptr); +return SCPE_OK; +} + +const char *ve_description (DEVICE *dptr) +{ +return "SPX Colour Graphics Adapter"; +} diff --git a/VAX/vax630_sysdev.c b/VAX/vax630_sysdev.c index 18d13eb1..b5bf3ddb 100644 --- a/VAX/vax630_sysdev.c +++ b/VAX/vax630_sysdev.c @@ -390,8 +390,11 @@ int32 nvr_rd (int32 pa) int32 rg = (pa + 1 - NVRBASE) >> 1; int32 result; -if (rg < 14) /* watch chip */ - result = wtc_rd (pa); +if (rg < 14) { /* watch chip */ + result = wtc_rd (rg); + if (rg & 1) + result = (result << 16); /* word aligned */ + } else { result = (nvr[rg] & WMASK) | (((uint32)nvr[rg]) << 16); if (pa & 1) @@ -408,7 +411,7 @@ void nvr_wr (int32 pa, int32 val, int32 lnt) int32 rg = (pa + 1 - NVRBASE) >> 1; if (rg < 14) /* watch chip */ - wtc_wr (pa, val, lnt); + wtc_wr (rg, val, lnt); else { int32 orig_nvr = (int32)nvr[rg]; diff --git a/VAX/vax_defs.h b/VAX/vax_defs.h index e7a56634..d451bd2c 100644 --- a/VAX/vax_defs.h +++ b/VAX/vax_defs.h @@ -909,6 +909,16 @@ extern void rom_wr_B (int32 pa, int32 val); #include "vax750_defs.h" #elif defined (VAX_730) #include "vax730_defs.h" +#elif defined (VAX_410) +#include "vax410_defs.h" +#elif defined (VAX_420) +#include "vax420_defs.h" +#elif defined (VAX_43) +#include "vax43_defs.h" +#elif defined (VAX_440) +#include "vax440_defs.h" +#elif defined (IS_1000) +#include "is1000_defs.h" #elif defined (VAX_610) #include "vax610_defs.h" #elif defined (VAX_620) || defined (VAX_630) diff --git a/VAX/vax_gpx.c b/VAX/vax_gpx.c index 4682bd26..d739229a 100644 --- a/VAX/vax_gpx.c +++ b/VAX/vax_gpx.c @@ -1802,8 +1802,12 @@ for (val = 0;;) { sim_debug (DBG_ROP, gpx_dev, "BTP Complete\n"); /* FIXME - This is a temporary workaround for the QDSS. Address output complete should not be set until the FIFO is empty */ +#if defined(VAX_630) uptr->CMD = 0; va_adpstat (ADPSTAT_AC | ADPSTAT_RC, 0); +#else +va_adpstat (ADPSTAT_RC, 0); +#endif return SCPE_OK; } diff --git a/VAX/vax_gpx.h b/VAX/vax_gpx.h index f4408f8d..9598ab47 100644 --- a/VAX/vax_gpx.h +++ b/VAX/vax_gpx.h @@ -31,7 +31,9 @@ /* FIXME - Some or all of these should be dynamic */ +#ifndef VA_PLANES #define VA_PLANES 4 +#endif #define VA_BPP (1u << VA_PLANES) #define VA_PLANE_MASK (VA_BPP - 1) diff --git a/VAX/vax_is1000_bin.h b/VAX/vax_is1000_bin.h new file mode 100644 index 00000000..d9684cd6 --- /dev/null +++ b/VAX/vax_is1000_bin.h @@ -0,0 +1,32781 @@ +#ifndef ROM_vax_is1000_bin_H +#define ROM_vax_is1000_bin_H 0 +/* + VAX/vax_is1000_bin.h produced at Wed Apr 17 01:08:39 2019 + from VAX/is1000.bin which was last modified at Wed Apr 17 01:05:07 2019 + file size: 524288 (0x80000) - checksum: 0xFCBCD74A + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x80000 +#define BOOT_CODE_FILENAME "is1000.bin" +#define BOOT_CODE_ARRAY vax_is1000_bin +unsigned char vax_is1000_bin[] = { +0x31,0xE1,0x12,0x00,0x01,0x06,0x01,0x08,0x01,0x01,0x01,0x01,0x00,0x01,0x02,0x03, +0x55,0x55,0x55,0x55,0xAA,0xAA,0xAA,0xAA,0x33,0x33,0x33,0x33,0x04,0x04,0x04,0x04, +0x00,0x00,0x00,0x00,0xFC,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0xF8,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x02,0x00,0x00,0x50,0x02,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x31,0xD5,0x01,0x00,0x31,0xD7,0x01,0x00,0x31,0xD9,0x01,0x00,0x31,0xDB,0x01,0x00, +0x31,0xDD,0x01,0x00,0x31,0xDF,0x01,0x00,0x31,0xE1,0x01,0x00,0x31,0xE3,0x01,0x00, +0x31,0xE5,0x01,0x00,0x31,0x10,0x02,0x00,0x00,0x00,0x00,0x11,0xFE,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x01,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x90,0x51,0x60,0x95,0x51,0x01,0x01,0x01, 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+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,}; +#endif /* ROM_vax_is1000_bin_H */ diff --git a/VAX/vax_ka410_bin.h b/VAX/vax_ka410_bin.h new file mode 100644 index 00000000..8032ced8 --- /dev/null +++ b/VAX/vax_ka410_bin.h @@ -0,0 +1,16397 @@ +#ifndef ROM_vax_ka410_bin_H +#define ROM_vax_ka410_bin_H 0 +/* + VAX/vax_ka410_bin.h produced at Sun Apr 7 17:47:23 2019 + from VAX/ka410.bin which was last modified at Sun Apr 7 17:44:20 2019 + file size: 262144 (0x40000) - checksum: 0xFEDA0B61 + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x40000 +#define BOOT_CODE_FILENAME "ka410.bin" +#define BOOT_CODE_ARRAY vax_ka410_bin +unsigned char vax_ka410_bin[] = { +0x31,0xB8,0x00,0x00,0x02,0x00,0x04,0x04,0x7F,0x7F,0x7F,0x7F,0x00,0x01,0x02,0x03, +0x55,0x55,0x55,0x55,0xAA,0xAA,0xAA,0xAA,0x33,0x33,0x33,0x33,0x40,0x40,0x40,0x40, +0xFC,0x03,0x00,0x00,0xF8,0x03,0x00,0x00,0x48,0x02,0x00,0x00,0x44,0x02,0x00,0x00, +0x54,0x02,0x00,0x00,0x50,0x02,0x00,0x00,0xC4,0x02,0x00,0x00,0xC0,0x02,0x00,0x00, +0x11,0x46,0x00,0x00,0x11,0x48,0x00,0x00,0x11,0x4A,0x00,0x00,0x11,0x4C,0x00,0x00, +0x11,0x4E,0x00,0x00,0x11,0x50,0x00,0x00,0x11,0x52,0x00,0x00,0x11,0x54,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x34,0x0B,0x00,0x00,0x9C,0x08,0x05,0x20,0x7F,0x01,0xDB,0x00,0x00,0x9C,0x05,0x20, +0x00,0x06,0x05,0x20,0x28,0x33,0x05,0x20,0x9F,0xCF,0x55,0x60,0x11,0x2A,0x9F,0xCF, +0xC9,0x77,0x11,0x24,0x9F,0xCF,0x99,0x76,0x11,0x1E,0x9F,0xCF,0xA7,0x76,0x11,0x18, +0x9F,0xCF,0xC0,0x76,0x11,0x12,0x9F,0xCF,0xD3,0x76,0x11,0x0C,0x9F,0xCF,0x0B,0x77, +0x11,0x06,0x9F,0xCF,0x9C,0x5F,0x11,0x00,0x31,0x0D,0x5F,0xDB,0x2B,0x9F,0x00,0x00, +0x08,0x20,0xED,0x08,0x05,0x9F,0x00,0x00,0x08,0x20,0x03,0x13,0x03,0x31,0x90,0x07, +0xDA,0x00,0x0B,0xD0,0x8F,0x00,0x00,0x0A,0x20,0x52,0xB0,0x10,0x62,0xD0,0x0A,0x50, +0xF5,0x50,0xFD,0xD0,0x8F,0x60,0xF0,0xFF,0xFF,0x50,0xD7,0x50,0x13,0x19,0xE0,0x04, +0x62,0xF8,0x9E,0xCF,0x34,0x22,0x50,0xD4,0x51,0xB0,0x20,0x62,0xB0,0x41,0x60,0xA2, +0x04,0xF3,0x03,0x51,0xF7,0x11,0x00,0xB0,0x8F,0x08,0xC0,0x9F,0x00,0x00,0x0F,0x20, +0xDA,0x00,0x18,0x94,0x9F,0x0C,0x00,0x08,0x20,0x94,0x9F,0x00,0x00,0x02,0x20,0xAA, +0x8F,0xFC,0x00,0x9F,0x3C,0x00,0x0B,0x20,0xAA,0x30,0x9F,0x38,0x00,0x0B,0x20,0xB0, +0x8F,0xFC,0x03,0x9F,0x48,0x00,0x0B,0x20,0xB0,0x8F,0xFC,0x03,0x9F,0x4C,0x00,0x0B, +0x20,0x3C,0x8F,0x00,0xFF,0x50,0xF5,0x50,0xFD,0xEF,0x00,0x03,0xEF,0xAF,0xFE,0xFD, +0xFF,0x50,0xC1,0x02,0x40,0xEF,0x23,0x13,0x00,0x00,0x57,0x7C,0x53,0xD0,0x01,0x55, +0xD4,0x56,0xD4,0x58,0xD4,0x50,0xD0,0x01,0x51,0xD0,0x01,0x52,0xD0,0x51,0x64,0xD1, +0x64,0x51,0x12,0x19,0xD2,0x51,0x51,0xD0,0x51,0x64,0xD1,0x64,0x51,0x12,0x0E,0xD2, +0x51,0x51,0x9C,0x01,0x51,0x51,0xF3,0x20,0x52,0xE2,0x3C,0x01,0x50,0xF0,0x50,0x56, +0x01,0x58,0xC1,0x55,0x56,0x64,0xC0,0x8F,0x00,0x00,0x01,0x00,0x54,0xF2,0x10,0x56, +0xC3,0xB5,0x58,0x13,0x03,0xD0,0x55,0x53,0xF3,0x57,0x55,0xB4,0xD0,0x53,0x57,0x78, +0x14,0x57,0x50,0x13,0x02,0x11,0x03,0x31,0x4D,0xFF,0xD0,0x50,0x5C,0xEF,0x0C,0x13, +0x5C,0x56,0xC0,0x8F,0xFF,0x01,0x00,0x00,0x56,0xCA,0x8F,0xFF,0x01,0x00,0x00,0x56, +0xC0,0x56,0x56,0xEF,0x09,0x16,0x56,0x5B,0xC1,0x8F,0x0C,0x02,0x00,0x00,0x5B,0x57, +0xD0,0x57,0x5B,0x78,0x09,0x57,0x57,0xC3,0x57,0x5C,0x5A,0xD0,0x01,0x59,0xC1,0x04, +0x5A,0x58,0x7D,0x8F,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0xA8,0xFC,0xD0,0x8F, +0xD8,0xB2,0x17,0xD6,0xA8,0xFC,0xD1,0x8F,0xD8,0xB2,0x17,0xD6,0xA8,0xFC,0x12,0x57, +0xD1,0x8F,0x33,0x33,0x33,0x33,0x68,0x12,0x4E,0x7D,0x8F,0x33,0x33,0x33,0x33,0x33, +0x33,0x33,0x33,0xA8,0xFC,0xD0,0x8F,0xD8,0xB2,0x17,0xD6,0xA8,0xFD,0xD1,0x8F,0x33, +0xD8,0xB2,0x17,0xA8,0xFC,0x12,0x30,0xD1,0x8F,0xD6,0x33,0x33,0x33,0x68,0x12,0x27, +0x7D,0x8F,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0xA8,0xFC,0xD0,0x8F,0xD8,0xB2, +0x17,0xD6,0xA8,0xFE,0xD1,0x8F,0x33,0x33,0xD8,0xB2,0xA8,0xFC,0x12,0x09,0xD1,0x8F, +0x17,0xD6,0x33,0x33,0x68,0x13,0x03,0x31,0xE2,0x00,0x7D,0x8F,0x33,0x33,0x33,0x33, +0x33,0x33,0x33,0x33,0xA8,0xFC,0xD0,0x8F,0xD8,0xB2,0x17,0xD6,0xA8,0xFF,0xD1,0x8F, +0x33,0x33,0x33,0xD8,0xA8,0xFC,0x12,0xDF,0xD1,0x8F,0xB2,0x17,0xD6,0x33,0x68,0x12, +0xD6,0x7D,0x8F,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0x33,0xA8,0xFC,0xB0,0x8F,0x17, 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b/VAX/vax_ka410_xs_bin.h @@ -0,0 +1,2061 @@ +#ifndef ROM_vax_ka410_xs_bin_H +#define ROM_vax_ka410_xs_bin_H 0 +/* + VAX/vax_ka410_xs_bin.h produced at Sun Apr 7 13:22:58 2019 + from VAX/ka410_xs.bin which was last modified at Sun Apr 7 11:12:27 2019 + file size: 32768 (0x8000) - checksum: 0xFFD8BD83 + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x8000 +#define BOOT_CODE_FILENAME "ka410_xs.bin" +#define BOOT_CODE_ARRAY vax_ka410_xs_bin +unsigned char vax_ka410_xs_bin[] = { +0x01,0x00,0x01,0x00,0x55,0xAA,0x33,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x03,0x00, +0x03,0x00,0xC0,0x00,0x4E,0x49,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00, 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vax_ka420_rdrz_bin +unsigned char vax_ka420_rdrz_bin[] = { +0x02,0x02,0x00,0x00,0x02,0x02,0x00,0x01,0x55,0x55,0xAA,0xAA,0x33,0x33,0x40,0x40, +0x01,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0x00,0x30,0x00,0x01,0x00,0x90,0x00,0x53,0x54,0x52,0x47, +0x2D,0x31,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00, +0x02,0x00,0x00,0x40,0x00,0x8A,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00, +0x02,0x00,0x00,0x00,0x00,0x2C,0x00,0x00,0x29,0x5C,0x00,0x00,0x08,0x03,0x00,0x00, +0x02,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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ROM_vax_ka420_rzrz_bin_H 0 +/* + VAX/vax_ka420_rzrz_bin.h produced at Sun Apr 7 13:22:58 2019 + from VAX/ka420_rzrz.bin which was last modified at Sun Apr 7 11:12:27 2019 + file size: 131072 (0x20000) - checksum: 0xFF7A9A51 + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x20000 +#define BOOT_CODE_FILENAME "ka420_rzrz.bin" +#define BOOT_CODE_ARRAY vax_ka420_rzrz_bin +unsigned char vax_ka420_rzrz_bin[] = { +0x02,0x02,0x00,0x00,0x02,0x02,0x00,0x01,0x55,0x55,0xAA,0xAA,0x33,0x33,0x40,0x40, +0x01,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0x00,0x58,0x00,0x01,0x00,0xA0,0x80,0x53,0x43,0x53,0x49, +0x2D,0x41,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x41,0x1C,0x00,0x00,0x00,0x00,0x00,0x00, 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vax_ka4xx_8pln_bin +unsigned char vax_ka4xx_8pln_bin[] = { +0x01,0x00,0x01,0x00,0x55,0xAA,0x33,0x40,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x03,0x00, +0x01,0x00,0xD0,0x00,0x38,0x50,0x4C,0x4E,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xAC,0x00,0x00,0x00, +0xA2,0x5E,0x00,0x00,0xFC,0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x68,0x00,0x00, +0x00,0x76,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0xE8,0x4C,0x00,0x00, +0x66,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x38,0x53,0x00,0x00, +0x43,0x14,0x00,0x00,0x18,0x0C,0x00,0x00,0x01,0x00,0x00,0x80,0x38,0x53,0x00,0x00, +0x16,0x0C,0x00,0x00,0x40,0x0B,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0xDE,0x00,0x00, +0x00,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x20,0x43,0x6F,0x70, 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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x61,}; +#endif /* ROM_vax_ka4xx_8pln_bin_H */ diff --git a/VAX/vax_ka4xx_dz_bin.h b/VAX/vax_ka4xx_dz_bin.h new file mode 100644 index 00000000..b0b0280a --- /dev/null +++ b/VAX/vax_ka4xx_dz_bin.h @@ -0,0 +1,2061 @@ +#ifndef ROM_vax_ka4xx_dz_bin_H +#define ROM_vax_ka4xx_dz_bin_H 0 +/* + VAX/vax_ka4xx_dz_bin.h produced at Sun Apr 7 13:22:58 2019 + from VAX/ka4xx_dz.bin which was last modified at Sun Apr 7 13:06:20 2019 + file size: 32768 (0x8000) - checksum: 0xFFD84C02 + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x8000 +#define BOOT_CODE_FILENAME "ka4xx_dz.bin" +#define BOOT_CODE_ARRAY vax_ka4xx_dz_bin +unsigned char vax_ka4xx_dz_bin[] = { +0x01,0x00,0x02,0x00,0x55,0xAA,0x33,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, +0x00,0x00,0xF0,0x00,0x53,0x4C,0x55,0x20,0x20,0x20,0x20,0x20,0x20,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00, +0x00,0x0E,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x40,0x00,0x10,0x00,0x00, +0x00,0x5C,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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b/VAX/vax_ka4xx_spx_bin.h @@ -0,0 +1,8205 @@ +#ifndef ROM_vax_ka4xx_spx_bin_H +#define ROM_vax_ka4xx_spx_bin_H 0 +/* + VAX/vax_ka4xx_spx_bin.h produced at Sun Apr 7 13:22:58 2019 + from VAX/ka4xx_spx.bin which was last modified at Sun Apr 7 13:05:52 2019 + file size: 131072 (0x20000) - checksum: 0xFF765752 + This file is a generated file and should NOT be edited or changed by hand. +*/ +#define BOOT_CODE_SIZE 0x20000 +#define BOOT_CODE_FILENAME "ka4xx_spx.bin" +#define BOOT_CODE_ARRAY vax_ka4xx_spx_bin +unsigned char vax_ka4xx_spx_bin[] = { +0x02,0x02,0x00,0x00,0x02,0x02,0x00,0x01,0x55,0x55,0xAA,0xAA,0x33,0x33,0x40,0x40, +0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x01,0x00,0x03,0x00,0x01,0x00,0xD4,0x00,0x53,0x50,0x47,0x46, +0x58,0x20,0x20,0x20,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x35,}; +#endif /* ROM_vax_ka4xx_spx_bin_H */ diff --git a/VAX/vax_nar.c b/VAX/vax_nar.c new file mode 100644 index 00000000..837fa59d --- /dev/null +++ b/VAX/vax_nar.c @@ -0,0 +1,202 @@ +/* vax_nar.c: Network address ROM simulator + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. + + nar Network address ROM +*/ + +#include "vax_defs.h" +#include "sim_ether.h" + +uint32 nar[NARSIZE]; /* network address ROM */ +ETH_MAC nar_mac = {0x08, 0x00, 0x2B, 0xCC, 0xDD, 0xEE}; +t_bool nar_init = FALSE; + +t_stat nar_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw); +t_stat nar_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw); +t_stat nar_reset (DEVICE *dptr); +t_stat nar_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *nar_description (DEVICE *dptr); +t_stat nar_showmac (FILE* st, UNIT* uptr, int32 val, CONST void* desc); +t_stat nar_setmac (UNIT* uptr, int32 val, CONST char* cptr, void* desc); + +/* NAR data structures + + nar_dev NAR device descriptor + nar_unit NAR units + nar_reg NAR register list +*/ + +UNIT nar_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK, NARSIZE) }; + +REG nar_reg[] = { + { NULL } + }; + +MTAB nar_mod[] = { + { MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "MAC", "MAC=xx:xx:xx:xx:xx:xx", + &nar_setmac, &nar_showmac, NULL, "MAC address" }, + { 0 } + }; + +DEVICE nar_dev = { + "NAR", &nar_unit, nar_reg, nar_mod, + 1, 16, NARAWIDTH, 4, 16, 32, + &nar_ex, &nar_dep, &nar_reset, + NULL, NULL, NULL, + NULL, 0, 0, NULL, NULL, NULL, &nar_help, NULL, NULL, + &nar_description + }; + +/* NAR read */ + +int32 nar_rd (int32 pa) +{ +int32 rg = (pa >> 2) & 0x1F; +return nar[rg]; +} + +t_stat nar_showmac (FILE* st, UNIT* uptr, int32 val, CONST void* desc) +{ +char buffer[20]; + +eth_mac_fmt ((ETH_MAC*)nar_mac, buffer); +fprintf (st, "MAC=%s", buffer); +return SCPE_OK; +} + +t_stat nar_setmac (UNIT* uptr, int32 val, CONST char* cptr, void* desc) +{ +t_stat status; + +if (!cptr) + return SCPE_IERR; +status = eth_mac_scan (&nar_mac, cptr); +if (status != SCPE_OK) + return status; +nar_reset (&nar_dev); +return SCPE_OK; +} + +/* NAR examine */ + +t_stat nar_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if ((vptr == NULL) || (addr & 03)) + return SCPE_ARG; +if (addr >= NARSIZE) + return SCPE_NXM; +*vptr = nar[addr]; +return SCPE_OK; +} + +/* NAR deposit */ + +t_stat nar_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw) +{ +uint32 addr = (uint32) exta; + +if (addr & 03) + return SCPE_ARG; +if (addr >= NARSIZE) + return SCPE_NXM; +nar[addr] = (uint32) val; +return SCPE_OK; +} + +/* NAR reset */ + +t_stat nar_reset (DEVICE *dptr) +{ +uint16 i, c, w; +t_stat r; + +if (!nar_init) { /* set initial MAC */ + nar_init = TRUE; + r = eth_mac_scan (&nar_mac, "08:00:2B:00:00:00/24"); + if (r != SCPE_OK) + return r; + } + +for (i = c = 0; i < 6; i += 2) { + c = c + c + ((uint32)((uint32)c + (uint32)c) > 0xFFFF ? 1 : 0); + w = (nar_mac[i] << 8) | nar_mac[i + 1]; + c = c + w + ((uint32)((uint32)c + (uint32)w) > 0xFFFF ? 1 : 0); + } +nar[0] = nar_mac[0]; /* MAC Address */ +nar[1] = nar_mac[1]; +nar[2] = nar_mac[2]; +nar[3] = nar_mac[3]; +nar[4] = nar_mac[4]; +nar[5] = nar_mac[5]; +nar[6] = (c >> 8) & 0xFF; /* checksum */ +nar[7] = c & 0xFF; +nar[8] = c & 0xFF; /* same in reverse */ +nar[9] = (c >> 8) & 0xFF; +nar[10] = nar_mac[5]; +nar[11] = nar_mac[4]; +nar[12] = nar_mac[3]; +nar[13] = nar_mac[2]; +nar[14] = nar_mac[1]; +nar[15] = nar_mac[0]; +nar[16] = nar_mac[0]; /* same again forwards */ +nar[17] = nar_mac[1]; +nar[18] = nar_mac[2]; +nar[19] = nar_mac[3]; +nar[20] = nar_mac[4]; +nar[21] = nar_mac[5]; +nar[22] = (c >> 8) & 0xFF; +nar[23] = c & 0xFF; +nar[24] = 0xFF; /* manufacturing check data */ +nar[25] = 0x0; +nar[26] = 0x55; +nar[27] = 0xAA; +nar[28] = 0xFF; +nar[29] = 0x0; +nar[30] = 0x55; +nar[31] = 0xAA; +return SCPE_OK; +} + +t_stat nar_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "Network address ROM\n\n"); +fprintf (st, "The ROM consists of a single unit, simulating the 32 byte\n"); +fprintf (st, "network address ROM.\n"); +fprint_set_help (st, dptr); +fprint_show_help (st, dptr); +fprintf (st, "\nMAC address octets must be delimited by dashes, colons or periods.\n"); +fprintf (st, "The controller defaults to a relatively unique MAC address in the range\n"); +fprintf (st, "08-00-2B-00-00-00 thru 08-00-2B-FF-FF-FF, which should be sufficient\n"); +fprintf (st, "for most network environments. If desired, the simulated MAC address\n"); +fprintf (st, "can be directly set.\n"); +return SCPE_OK; +} + +const char *nar_description (DEVICE *dptr) +{ +return "network address ROM"; +} diff --git a/VAX/vax_rzdev.h b/VAX/vax_rzdev.h new file mode 100644 index 00000000..1a205e69 --- /dev/null +++ b/VAX/vax_rzdev.h @@ -0,0 +1,248 @@ +/* vax_rzdev.h: DEC SCSI devices + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. +*/ + +#ifndef _VAX_RZDEV_H_ +#define _VAX_RZDEV_H_ + +#include "sim_scsi.h" + +#define RZ23_DTYPE 0 +#define RZ23_TYPE SCSI_DISK +#define RZ23_PQUAL 0 +#define RZ23_SCSI 1 +#define RZ23_RM FALSE +#define RZ23_BLK 512 +#define RZ23_LBN 204863 +#define RZ23_MANU "DEC" +#define RZ23_DESC "RZ23 (C) DEC" +#define RZ23_REV "0A18" + +#define RZ23L_DTYPE 1 +#define RZ23L_TYPE SCSI_DISK +#define RZ23L_PQUAL 0 +#define RZ23L_SCSI 1 +#define RZ23L_RM FALSE +#define RZ23L_BLK 512 +#define RZ23L_LBN 237587 +#define RZ23L_MANU "DEC" +#define RZ23L_DESC "RZ23L (C) DEC" +#define RZ23L_REV "2528" + +#define RZ24_DTYPE 2 +#define RZ24_TYPE SCSI_DISK +#define RZ24_PQUAL 0 +#define RZ24_SCSI 1 +#define RZ24_RM FALSE +#define RZ24_BLK 512 +#define RZ24_LBN 409791 +#define RZ24_MANU "DEC" +#define RZ24_DESC "RZ24 (C) DEC" +#define RZ24_REV "4041" + +#define RZ24L_DTYPE 3 +#define RZ24L_TYPE SCSI_DISK +#define RZ24L_PQUAL 0 +#define RZ24L_SCSI 2 +#define RZ24L_RM FALSE +#define RZ24L_BLK 512 +#define RZ24L_LBN 479349 +#define RZ24L_MANU "DEC" +#define RZ24L_DESC "RZ24L (C) DEC" +#define RZ24L_REV "4766" + +#define RZ25_DTYPE 4 +#define RZ25_TYPE SCSI_DISK +#define RZ25_PQUAL 0 +#define RZ25_SCSI 2 +#define RZ25_RM FALSE +#define RZ25_BLK 512 +#define RZ25_LBN 832526 +#define RZ25_MANU "DEC" +#define RZ25_DESC "RZ25 (C) DEC" +#define RZ25_REV "0700" + +#define RZ25L_DTYPE 5 +#define RZ25L_TYPE SCSI_DISK +#define RZ25L_PQUAL 0 +#define RZ25L_SCSI 2 +#define RZ25L_RM FALSE +#define RZ25L_BLK 512 +#define RZ25L_LBN 1046205 +#define RZ25L_MANU "DEC" +#define RZ25L_DESC "RZ25L (C) DEC" +#define RZ25L_REV "0008" + +#define RZ26_DTYPE 6 +#define RZ26_TYPE SCSI_DISK +#define RZ26_PQUAL 0 +#define RZ26_SCSI 2 +#define RZ26_RM FALSE +#define RZ26_BLK 512 +#define RZ26_LBN 2050859 +#define RZ26_MANU "DEC" +#define RZ26_DESC "RZ26 (C) DEC" +#define RZ26_REV "0700" + +#define RZ26L_DTYPE 7 +#define RZ26L_TYPE SCSI_DISK +#define RZ26L_PQUAL 0 +#define RZ26L_SCSI 2 +#define RZ26L_RM FALSE +#define RZ26L_BLK 512 +#define RZ26L_LBN 2050859 +#define RZ26L_MANU "DEC" +#define RZ26L_DESC "RZ26L (C) DEC" +#define RZ26L_REV "0008" + +#define RZ55_DTYPE 8 +#define RZ55_TYPE SCSI_DISK +#define RZ55_PQUAL 0 +#define RZ55_SCSI 1 +#define RZ55_RM FALSE +#define RZ55_BLK 512 +#define RZ55_LBN 648437 +#define RZ55_MANU "DEC" +#define RZ55_DESC "RZ55" +#define RZ55_REV "0900" + +#define RRD40_DTYPE 9 +#define RRD40_TYPE SCSI_CDROM +#define RRD40_PQUAL 0 +#define RRD40_SCSI 1 +#define RRD40_RM TRUE +#define RRD40_BLK 512 +#define RRD40_LBN 1160156 +#define RRD40_MANU "DEC" +#define RRD40_DESC "RRD40" +#define RRD40_REV "250D" + +#define RRD42_DTYPE 10 +#define RRD42_TYPE SCSI_CDROM +#define RRD42_PQUAL 0 +#define RRD42_SCSI 1 +#define RRD42_RM TRUE +#define RRD42_BLK 512 +#define RRD42_LBN 1160156 +#define RRD42_MANU "DEC" +#define RRD42_DESC "RRD42" +#define RRD42_REV "1.1A" + +#define RRW11_DTYPE 11 +#define RRW11_TYPE SCSI_WORM +#define RRW11_PQUAL 0 +#define RRW11_SCSI 1 +#define RRW11_RM TRUE +#define RRW11_BLK 512 +#define RRW11_LBN 1160156 +#define RRW11_MANU "DEC" +#define RRW11_DESC "RRW11" +#define RRW11_REV "1.1A" + +#define CDW900_DTYPE 12 +#define CDW900_TYPE SCSI_WORM +#define CDW900_PQUAL 0 +#define CDW900_SCSI 1 +#define CDW900_RM TRUE +#define CDW900_BLK 512 +#define CDW900_LBN 1160156 +#define CDW900_MANU "SONY" +#define CDW900_DESC "CDW-900E" +#define CDW900_REV "1.13" + +#define XR1001_DTYPE 13 +#define XR1001_TYPE SCSI_WORM +#define XR1001_PQUAL 0 +#define XR1001_SCSI 1 +#define XR1001_RM TRUE +#define XR1001_BLK 512 +#define XR1001_LBN 1160156 +#define XR1001_MANU "JVC" +#define XR1001_DESC "XR-W1001" +#define XR1001_REV "1.1A" + +#define TZK50_DTYPE 14 +#define TZK50_TYPE SCSI_TAPE +#define TZK50_PQUAL 0x50 +#define TZK50_SCSI 1 +#define TZK50_RM TRUE +#define TZK50_BLK 512 +#define TZK50_LBN 1160156 +#define TZK50_MANU "DEC" +#define TZK50_DESC "TZK50" +#define TZK50_REV "1.1A" + +#define TZ30_DTYPE 15 +#define TZ30_TYPE SCSI_TAPE +#define TZ30_PQUAL 0x30 +#define TZ30_SCSI 1 +#define TZ30_RM TRUE +#define TZ30_BLK 512 +#define TZ30_LBN 1160156 +#define TZ30_MANU "DEC" +#define TZ30_DESC "TZK50" +#define TZ30_REV "1.1A" + +#define RZU_DTYPE 16 /* user defined */ +#define RZU_TYPE SCSI_DISK +#define RZU_PQUAL 0 +#define RZU_SCSI 2 +#define RZU_RM TRUE +#define RZU_BLK 512 +#define RZU_LBN 236328 /* from RZ23 */ +#define RZU_MANU "SIMH" +#define RZU_DESC "RZUSER" +#define RZU_REV "0001" +#define RZU_MINC 10000 /* min cap LBNs */ +#define RZU_MAXC 4194303 /* max cap LBNs */ +#define RZU_EMAXC 2147483647 /* ext max cap */ + +#define RZ_DEV(d) \ + { d##_TYPE, d##_PQUAL, d##_SCSI, d##_RM, d##_BLK, \ + d##_LBN, d##_MANU, d##_DESC, d##_REV, #d } +#define RZ_SIZE(d) d##_LBN + +static struct scsi_dev_t rzdev_tab[] = { + RZ_DEV (RZ23), + RZ_DEV (RZ23L), + RZ_DEV (RZ24), + RZ_DEV (RZ24L), + RZ_DEV (RZ25), + RZ_DEV (RZ25L), + RZ_DEV (RZ26), + RZ_DEV (RZ26L), + RZ_DEV (RZ55), + RZ_DEV (RRD40), + RZ_DEV (RRD42), + RZ_DEV (RRW11), + RZ_DEV (CDW900), + RZ_DEV (XR1001), + RZ_DEV (TZK50), + RZ_DEV (TZ30), + RZ_DEV (RZU), + { 0 } + }; + +#endif diff --git a/VAX/vax_watch.c b/VAX/vax_watch.c index afbb1660..5598c55b 100644 --- a/VAX/vax_watch.c +++ b/VAX/vax_watch.c @@ -157,9 +157,8 @@ static const char *wtc_regs[] = -int32 wtc_rd (int32 pa) +int32 wtc_rd (int32 rg) { -int32 rg = (pa >> 1) & 0xF; int32 val = 0; time_t curr; struct timespec now; @@ -239,21 +238,18 @@ switch(rg) { case 13: /* CSR D */ val = wtc_csrd & WTC_CSRD_RD; + wtc_set_valid (); break; } -sim_debug(DBG_REG, &wtc_dev, "wtc_rd(pa=0x%08X [%s], data=0x%X) ", pa, wtc_regs[rg], val); +sim_debug(DBG_REG, &wtc_dev, "wtc_rd(rg=%d [%s], data=0x%X) ", rg, wtc_regs[rg], val); sim_debug_bits(DBG_REG, &wtc_dev, wtc_bitdefs[rg], (uint32)val, (uint32)val, TRUE); -if (rg & 1) - val = (val << 16); /* word aligned? */ - return val; } -void wtc_wr (int32 pa, int32 val, int32 lnt) +void wtc_wr (int32 rg, int32 val) { -int32 rg = (pa >> 1) & 0xF; int32 new_val = val; val = val & 0xFF; @@ -279,7 +275,7 @@ switch(rg) { break; } -sim_debug(DBG_REG, &wtc_dev, "wtc_wr(pa=0x%08X [%s], data=0x%X) ", pa, wtc_regs[rg], val); +sim_debug(DBG_REG, &wtc_dev, "wtc_wr(rg=%d [%s], data=0x%X) ", rg, wtc_regs[rg], val); sim_debug_bits(DBG_REG, &wtc_dev, wtc_bitdefs[rg], (uint32)new_val, (uint32)new_val, TRUE); } diff --git a/VAX/vax_xs.c b/VAX/vax_xs.c new file mode 100644 index 00000000..a7d6f414 --- /dev/null +++ b/VAX/vax_xs.c @@ -0,0 +1,826 @@ +/* vax_xs.c: LANCE ethernet simulator + + Copyright (c) 2019, Matt Burke + This module is partly based on the DEUNA simulator, Copyright (c) 2003-2011, David T. Hittner + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + xs LANCE Ethernet Controller +*/ + +#include "vax_xs.h" + +#if defined(VAX_410) +#include "vax_ka410_xs_bin.h" +#else +#define BOOT_CODE_ARRAY NULL +#define BOOT_CODE_SIZE 0 +#endif + +#define GETB(p,x) (p[x]) +#define GETW(p,x) ((p[(x + 1)] << 8) | p[x]) +#define GETL(p,x) ((p[(x + 3)] << 24) | (p[(x + 2)] << 16) | (p[(x + 1)] << 8) | p[x]) + +extern int32 tmxr_poll; + +t_stat xs_svc (UNIT *uptr); +void xs_process_receive(CTLR* xs); +void xs_process_transmit (CTLR* xs); +void xs_dump_rxring(CTLR* xs); +void xs_dump_txring(CTLR* xs); +t_stat xs_init (CTLR* xs); +void xs_updateint(CTLR* xs); +void xs_setint (CTLR* xs); +void xs_clrint (CTLR* xs); +void xs_read_callback (int status); +void xs_write_callback (int status); +t_stat xs_reset (DEVICE *dptr); +t_stat xs_attach (UNIT *uptr, CONST char *cptr); +t_stat xs_detach (UNIT* uptr); +t_stat xs_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); +const char *xs_description (DEVICE *dptr); + +/* XS data structures + + xs_dev XS device descriptor + xs_unit XS unit list + xs_reg XS register list + xs_mod XS modifier list +*/ + +struct xs_device xs_var = { + xs_read_callback, /* read callback routine */ + xs_write_callback, /* write callback routine */ + }; + +DIB xs_dib = { + XS_ROM_INDEX, BOOT_CODE_ARRAY, BOOT_CODE_SIZE + }; + +UNIT xs_unit = { + UDATA (&xs_svc, UNIT_IDLE | UNIT_ATTABLE | UNIT_DISABLE, 0) + }; + +REG xs_reg[] = { + { GRDATA ( SA0, xs_var.mac[0], 16, 8, 0), REG_RO|REG_FIT }, + { GRDATA ( SA1, xs_var.mac[1], 16, 8, 0), REG_RO|REG_FIT }, + { GRDATA ( SA2, xs_var.mac[2], 16, 8, 0), REG_RO|REG_FIT }, + { GRDATA ( SA3, xs_var.mac[3], 16, 8, 0), REG_RO|REG_FIT }, + { GRDATA ( SA4, xs_var.mac[4], 16, 8, 0), REG_RO|REG_FIT }, + { GRDATA ( SA5, xs_var.mac[5], 16, 8, 0), REG_RO|REG_FIT }, + { FLDATA ( INT, xs_var.irq, 0) }, + { BRDATA ( SETUP, &xs_var.setup, DEV_RDX, 8, sizeof(xs_var.setup)), REG_HRO }, + { GRDATA ( CSR0, xs_var.csr0, DEV_RDX, 16, 0), REG_FIT }, + { GRDATA ( CSR1, xs_var.csr1, DEV_RDX, 16, 0), REG_FIT }, + { GRDATA ( CSR2, xs_var.csr2, DEV_RDX, 16, 0), REG_FIT }, + { GRDATA ( CSR3, xs_var.csr3, DEV_RDX, 16, 0), REG_FIT }, + { GRDATA ( MODE, xs_var.mode, DEV_RDX, 16, 0), REG_FIT }, + { GRDATA ( RPTR, xs_var.rptr, DEV_RDX, 16, 0), REG_FIT }, + { GRDATA ( INBB, xs_var.inbb, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( TDRB, xs_var.tdrb, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( TELEN, xs_var.telen, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( TRLEN, xs_var.trlen, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( TXNEXT, xs_var.txnext, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( RDRB, xs_var.rdrb, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( RELEN, xs_var.relen, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( RRLEN, xs_var.rrlen, DEV_RDX, 32, 0), REG_FIT }, + { GRDATA ( RXNEXT, xs_var.rxnext, DEV_RDX, 32, 0), REG_FIT }, + { BRDATA ( RXHDR, xs_var.rxhdr, DEV_RDX, 16, 4), REG_HRO }, + { BRDATA ( TXHDR, xs_var.txhdr, DEV_RDX, 16, 4), REG_HRO }, + { FLDATAD ( INT, int_req[IPL_XS1], INT_V_XS1, "interrupt pending flag") }, + }; + +DEBTAB xs_debug[] = { + {"TRACE", DBG_TRC, "trace routine calls"}, + {"REG", DBG_REG, "read/write registers"}, + {"PACKET", DBG_PCK, "packet headers"}, + {"DATA", DBG_DAT, "packet data"}, + {"ETH", DBG_ETH, "ethernet device"}, + { 0 } +}; + +MTAB xs_mod[] = { + { MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "ETH", NULL, + NULL, ð_show, NULL, "Display attachable devices" }, + { 0 } + }; + +DEVICE xs_dev = { + "XS", &xs_unit, xs_reg, xs_mod, + 1, DEV_RDX, 20, 1, DEV_RDX, 8, + NULL, NULL, &xs_reset, + NULL, &xs_attach, &xs_detach, + &xs_dib, DEV_DEBUG | XS_FLAGS, 0, + xs_debug, NULL, NULL, &xs_help, NULL, NULL, + &xs_description + }; + +CTLR xs_ctrl[] = { + {&xs_dev, &xs_unit, NULL, &xs_var} /* XS controller */ + }; + +/* XS read + + 200E0000 register data port + 200E0004 register address port +*/ + +int32 xs_rd (int32 pa) +{ +CTLR *xs = &xs_ctrl[0]; +int32 rg = (pa >> 2) & 3; +int32 data = 0; + +switch (rg) { + + case 0: /* NI_RDP */ + switch (xs->var->rptr) { + + case 0: /* NI_CSR0 */ + data = xs->var->csr0; + if (data & CSR0_ERR) + data |= CSR0_ESUM; /* error bits set */ + break; + + case 1: /* NI_CSR1 */ + data = xs->var->csr1; + break; + + case 2: /* NI_CSR2 */ + data = xs->var->csr2; + break; + + case 3: /* NI_CSR3 */ + data = xs->var->csr3; + break; + } + sim_debug(DBG_REG, &xs_dev, "reg %d read, value = %X, PC = %08X\n", xs->var->rptr, data, fault_PC); + break; + + case 1: /* NI_RAP */ + data = xs->var->rptr; + /* sim_debug(DBG_REG, &xs_dev, "reg ptr read, value = %X\n", data); */ + break; + } + +return data; +} + +/* XS write + + 200E0000 register data port + 200E0004 register address port +*/ + +void xs_wr (int32 pa, int32 data, int32 access) +{ +CTLR *xs = &xs_ctrl[0]; +int32 rg = (pa >> 2) & 3; + +switch (rg) { + + case 0: /* NI_RDP */ + switch (xs->var->rptr) { + + case 0: /* NI_CSR0 */ + xs->var->csr0 = (xs->var->csr0 & ~CSR0_RW) | (data & CSR0_RW); + xs->var->csr0 = xs->var->csr0 & ~(data & CSR0_W1C); + + if (data & CSR0_STOP) { /* STOP */ + xs->var->csr0 = xs->var->csr0 | CSR0_STOP; + xs->var->csr0 = xs->var->csr0 & ~(CSR0_STRT | CSR0_INIT | CSR0_IDON | CSR0_TXON | CSR0_RXON); + xs->var->csr0 = xs->var->csr0 & ~(CSR0_ERR | CSR0_ESUM); + sim_cancel (&xs_unit); + } + else if ((data & CSR0_INIT) && (!(xs->var->csr0 & CSR0_INIT))) /* INIT */ + xs_init(xs); + else if ((data & CSR0_STRT) && (!(xs->var->csr0 & CSR0_STRT))) { /* START */ + xs->var->csr0 = xs->var->csr0 | CSR0_STRT; + xs->var->csr0 = xs->var->csr0 & ~CSR0_STOP; + if ((xs->var->mode & MODE_DRX) == 0) + xs->var->csr0 = xs->var->csr0 | CSR0_RXON; + if ((xs->var->mode & MODE_DTX) == 0) + xs->var->csr0 = xs->var->csr0 | CSR0_TXON; + sim_clock_coschedule (&xs_unit, tmxr_poll); + } + else if (data & CSR0_TDMD) { /* TDMD */ + xs_process_transmit(xs); + } + + xs_updateint (xs); + + if ((data & CSR_IE) == 0) + CLR_INT (XS1); + else if ((xs->var->csr0 & (CSR0_INTR + CSR_IE)) == CSR0_INTR) + SET_INT (XS1); + break; + + case 1: /* NI_CSR1 */ + xs->var->csr1 = (data & 0xFFFF); + break; + + case 2: /* NI_CSR2 */ + xs->var->csr2 = (data & 0xFFFF); + break; + + case 3: /* NI_CSR3 */ + xs->var->csr3 = data; + break; + } + sim_debug(DBG_REG, &xs_dev, "reg %d write, value = %X, PC = %08X\n", xs->var->rptr, data, fault_PC); + break; + + case 1: /* NI_RAP */ + xs->var->rptr = data; + /* sim_debug(DBG_REG, &xs_dev, "reg ptr write, value = %X\n", data); */ + break; + } + +return; +} + +/* Unit service */ + +t_stat xs_svc (UNIT *uptr) +{ +int32 queue_size; +CTLR *xs = &xs_ctrl[0]; + +if ((xs->var->csr0 & (CSR0_STRT | CSR0_INIT)) == CSR0_INIT) { + /* Init done */ + xs->var->csr0 = xs->var->csr0 | (CSR0_IDON | CSR0_INTR); + if (xs->var->csr0 & CSR_IE) + SET_INT (XS1); + return SCPE_OK; + } + +if (!(xs->var->mode & MODE_DRX)) { + /* First pump any queued packets into the system */ + if (xs->var->ReadQ.count > 0) + xs_process_receive(xs); + + /* Now read and queue packets that have arrived */ + /* This is repeated as long as they are available and we have room */ + do { + queue_size = xs->var->ReadQ.count; + /* read a packet from the ethernet - processing is via the callback */ + eth_read (xs->var->etherface, &xs->var->read_buffer, xs->var->rcallback); + } while (queue_size != xs->var->ReadQ.count); + + /* Now pump any still queued packets into the system */ + if (xs->var->ReadQ.count > 0) + xs_process_receive(xs); + } + +if (!(xs->var->mode & MODE_DTX)) + xs_process_transmit(xs); + +sim_clock_coschedule (uptr, tmxr_poll); +return SCPE_OK; +} + +/* Transfer received packets into receive ring. */ +void xs_process_receive(CTLR* xs) +{ +uint8 b0, b1, b2, b3; +uint32 segb, ba; +int slen, wlen, off; +t_stat rstatus, wstatus; +ETH_ITEM* item = 0; +int no_buffers = xs->var->csr0 & CSR0_MISS; + +sim_debug(DBG_TRC, xs->dev, "xs_process_receive(), buffers: %d\n", xs->var->rrlen); + +// xs_dump_rxring(xs); /* debug receive ring */ + +/* process only when in the running state, and host buffers are available */ +if (no_buffers) + return; + +/* check read queue for buffer loss */ +if (xs->var->ReadQ.loss) { + xs->var->ReadQ.loss = 0; + } + +/* while there are still packets left to process in the queue */ +while (xs->var->ReadQ.count > 0) { + + /* get next receive buffer */ + ba = xs->var->rdrb + (xs->var->relen * 2) * xs->var->rxnext; + rstatus = XS_READW (ba, 8, xs->var->rxhdr); + if (rstatus) { + /* tell host bus read failed */ + xs->var->csr0 |= CSR0_MERR; + break; + } + + /* if buffer not owned by controller, exit [at end of ring] */ + if (!(xs->var->rxhdr[1] & RXR_OWN)) { + /* tell the host there are no more buffers */ + /* xs->var->csr0 |= CSR0_MISS; */ /* I don't think this is correct 08-dec-2005 dth */ + sim_debug(DBG_TRC, xs->dev, "Stopping input processing - Not Owned receive descriptor=0x%X, ", ba); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w2, xs->var->rxhdr[2], xs->var->rxhdr[2], 0); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w3, xs->var->rxhdr[3], xs->var->rxhdr[3], 1); + break; + } + + /* set buffer length and address */ + slen = (uint16)(xs->var->rxhdr[2] * -1); /* 2s Complement */ + segb = xs->var->rxhdr[0] + ((xs->var->rxhdr[1] & RXR_HADR) << 16); + + /* get first packet from receive queue */ + if (!item) { + item = &xs->var->ReadQ.item[xs->var->ReadQ.head]; + /* Pad the packet to minimum size */ + if (item->packet.len < ETH_MIN_PACKET) { + int len = item->packet.len; + memset (&item->packet.msg[len], 0, ETH_MIN_PACKET - len); + item->packet.len = ETH_MIN_PACKET; + } + } + + /* is this the start of frame? */ + if (item->packet.used == 0) { + xs->var->rxhdr[1] |= RXR_STF; + off = 0; + } + + /* figure out chained packet size */ + wlen = item->packet.crc_len - item->packet.used; + if (wlen > slen) + wlen = slen; + + sim_debug(DBG_TRC, xs->dev, "Using receive descriptor=0x%X, slen=0x%04X(%d), segb=0x%04X, ", ba, slen, slen, segb); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w1, xs->var->rxhdr[1], xs->var->rxhdr[1], 0); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w2, xs->var->rxhdr[2], xs->var->rxhdr[2], 0); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w3, xs->var->rxhdr[3], xs->var->rxhdr[3], 0); + sim_debug(DBG_TRC, xs->dev, ", pktlen=0x%X(%d), used=0x%X, wlen=0x%X\n", item->packet.len, item->packet.len, item->packet.used, wlen); + + /* Is this the end-of-frame? */ + if ((item->packet.used + wlen) == item->packet.crc_len) { + b0 = item->packet.msg[item->packet.crc_len - 4]; + b1 = item->packet.msg[item->packet.crc_len - 3]; + b2 = item->packet.msg[item->packet.crc_len - 2]; + b3 = item->packet.msg[item->packet.crc_len - 1]; + item->packet.msg[item->packet.crc_len - 4] = b3; + item->packet.msg[item->packet.crc_len - 3] = b2; + item->packet.msg[item->packet.crc_len - 2] = b1; + item->packet.msg[item->packet.crc_len - 1] = b0; + } + + /* transfer chained packet to host buffer */ + wstatus = XS_WRITEB (segb, wlen, &item->packet.msg[off]); + if (wstatus) { + /* error during write */ + xs->var->csr0 |= CSR0_MERR; + break; + } + + /* update chained counts */ + item->packet.used += wlen; + off += wlen; + + /* Is this the end-of-frame? */ + if (item->packet.used == item->packet.crc_len) { + /* mark end-of-frame */ + xs->var->rxhdr[1] |= RXR_ENF; + + /* Fill in the Received Message Length field */ + xs->var->rxhdr[3] &= ~RXR_MLEN; + xs->var->rxhdr[3] |= (item->packet.crc_len); + + /* remove processed packet from the receive queue */ + ethq_remove (&xs->var->ReadQ); + item = 0; + + /* tell host we received a packet */ + xs->var->csr0 |= CSR0_RINT; + } /* if end-of-frame */ + + /* give buffer back to host */ + xs->var->rxhdr[1] &= ~RXR_OWN; /* clear ownership flag */ + + sim_debug(DBG_TRC, xs->dev, "Updating receive descriptor=0x%X, slen=0x%04X, segb=0x%04X, ", ba, slen, segb); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w1, xs->var->rxhdr[1], xs->var->rxhdr[1], 0); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w2, xs->var->rxhdr[2], xs->var->rxhdr[2], 0); + sim_debug_bits(DBG_TRC, xs->dev, xs_rdes_w3, xs->var->rxhdr[3], xs->var->rxhdr[3], 1); + + /* update the ring entry in host memory. */ + wstatus = XS_WRITEW (ba, 8, xs->var->rxhdr); + if (wstatus) { + /* tell host bus write failed */ + xs->var->csr0 |= CSR0_MERR; + } + /* set to next receive ring buffer */ + xs->var->rxnext += 1; + if (xs->var->rxnext == xs->var->rrlen) + xs->var->rxnext = 0; + + } /* while */ + + /* if we failed to finish receiving the frame, flush the packet */ + if (item) { + ethq_remove(&xs->var->ReadQ); + xs->var->csr0 |= CSR0_MISS; + } + + /* set or clear interrupt, depending on what happened */ + xs_updateint (xs); + // xs_dump_rxring(xs); /* debug receive ring */ +} + +void xs_process_transmit (CTLR* xs) +{ +uint32 segb, ba; +int slen, wlen, off, giant, runt; +t_stat rstatus, wstatus; + +/* sim_debug(DBG_TRC, xs->dev, "xs_process_transmit()\n"); */ + +for (;;) { + + /* get next transmit buffer */ + ba = xs->var->tdrb + (xs->var->telen * 2) * xs->var->txnext; + rstatus = XS_READW (ba, 8, xs->var->txhdr); + if (rstatus) { + /* tell host bus read failed */ + xs->var->csr0 |= CSR0_MERR; + break; + } + + /* if buffer not owned by controller, exit [at end of ring] */ + if (!(xs->var->txhdr[1] & TXR_OWN)) + break; + + /* set buffer length and address */ + slen = (uint16)(xs->var->txhdr[2] * -1); /* 2s complement */ + segb = xs->var->txhdr[0] + ((xs->var->txhdr[1] & TXR_HADR) << 16); + wlen = slen; + + sim_debug(DBG_TRC, xs->dev, "Using transmit descriptor=0x%X, slen=0x%04X(%d), segb=0x%04X, ", ba, slen, slen, segb); + sim_debug_bits(DBG_TRC, xs->dev, xs_tdes_w1, xs->var->txhdr[1], xs->var->txhdr[1], 0); + sim_debug_bits(DBG_TRC, xs->dev, xs_tdes_w2, xs->var->txhdr[2], xs->var->txhdr[2], 0); + sim_debug(DBG_TRC, xs->dev, ", pktlen=0x%X(%d), used=0x%X, wlen=0x%X\n", 0, 0, 0, wlen); + + /* prepare to accumulate transmit information if start of frame */ + if (xs->var->txhdr[1] & TXR_STF) { + memset(&xs->var->write_buffer, 0, sizeof(ETH_PACK)); + off = giant = runt = 0; + } + + /* get packet data from host */ + if (xs->var->write_buffer.len + slen > ETH_MAX_PACKET) { + wlen = ETH_MAX_PACKET - xs->var->write_buffer.len; + giant = 1; + } + if (wlen > 0) { + rstatus = XS_READB(segb, wlen, &xs->var->write_buffer.msg[off]); + if (rstatus) { + /* tell host bus read failed */ + xs->var->csr0 |= CSR0_MERR; + break; + } + } + off += wlen; + xs->var->write_buffer.len += wlen; + + /* transmit packet when end-of-frame is reached */ + if (xs->var->txhdr[1] & TXR_ENF) { + + /* make sure packet is minimum length */ + if (xs->var->write_buffer.len < ETH_MIN_PACKET) { + xs->var->write_buffer.len = ETH_MIN_PACKET; /* pad packet to minimum length */ + runt = 1; + } + + /* are we in internal loopback mode ? */ + if ((xs->var->mode & MODE_LOOP) && (xs->var->mode & MODE_INTL)) { + /* just put packet in receive buffer */ + ethq_insert (&xs->var->ReadQ, 1, &xs->var->write_buffer, 0); + sim_debug(DBG_TRC, xs->dev, "loopback packet\n"); + } + else { + /* transmit packet synchronously - write callback sets status */ + wstatus = eth_write(xs->var->etherface, &xs->var->write_buffer, xs->var->wcallback); + if (wstatus) + xs->var->csr0 |= CSR0_BABL; + else if (DEBUG_PRI (xs_dev, DBG_PCK)) + eth_packet_trace_ex (xs->var->etherface, xs->var->write_buffer.msg, xs->var->write_buffer.len, "xs-write", DEBUG_PRI (xs_dev, DBG_DAT), DBG_PCK); + } + + /* update transmit status in transmit buffer */ + if (xs->var->write_buffer.status != 0) { + /* failure */ + const uint16 tdr = 100 + wlen * 8; /* arbitrary value */ + xs->var->txhdr[3] |= TXR_RTRY; + xs->var->txhdr[3] |= tdr & TXR_TDR; + xs->var->txhdr[1] |= TXR_ERRS; + } + + /* was packet too big or too small? */ + if (giant || runt) { + xs->var->txhdr[3] |= TXR_BUFL; + xs->var->txhdr[1] |= TXR_ERRS; + } + + /* tell host we transmitted a packet */ + xs->var->csr0 |= CSR0_TINT; + + } /* if end-of-frame */ + + /* give buffer ownership back to host */ + xs->var->txhdr[1] &= ~TXR_OWN; + + sim_debug(DBG_TRC, xs->dev, "Updating transmit descriptor=0x%X, slen=0x%04X, segb=0x%04X, ", ba, slen, segb); + sim_debug_bits(DBG_TRC, xs->dev, xs_tdes_w1, xs->var->txhdr[1], xs->var->txhdr[1], 0); + sim_debug_bits(DBG_TRC, xs->dev, xs_tdes_w2, xs->var->txhdr[2], xs->var->txhdr[2], 1); + + /* update transmit buffer */ + wstatus = XS_WRITEW (ba, 8, xs->var->txhdr); + if (wstatus) { + /* tell host bus write failed */ + xs->var->csr0 |= CSR0_MERR; + break; + } + + /* set to next transmit ring buffer */ + xs->var->txnext += 1; + if (xs->var->txnext == xs->var->trlen) + xs->var->txnext = 0; + + } +xs_updateint (xs); +} + +t_stat xs_init (CTLR* xs) +{ +uint16 w1, w2; +uint8 inb[0x18]; + +sim_debug (DBG_TRC, &xs_dev, "xs_init() at %08X\n", fault_PC); + +sim_cancel (&xs_unit); + +/* clear read queue */ +ethq_clear (&xs->var->ReadQ); + +/* clear setup info */ +memset (&xs->var->setup, 0, sizeof(struct xs_setup)); + +xs->var->inbb = ((xs->var->csr2 & 0xFF) << 16) | (xs->var->csr1 & 0xFFFE); +sim_debug (DBG_REG, &xs_dev, "xs_inbb = %04X\n", xs->var->inbb); + +if (XS_READB (xs->var->inbb, 0x18, &inb[0])) { + /* memory read error */ + xs->var->csr0 |= (CSR0_MERR | CSR0_IDON | CSR0_INTR); + xs->var->csr0 &= ~(CSR0_RXON | CSR0_TXON); + return SCPE_OK; + } + +xs->var->mode = GETW (inb, 0); +sim_debug(DBG_REG, &xs_dev, "xs_mode = %04X\n", xs->var->mode); + +xs->var->mac[0] = GETB (inb, 0x2); +xs->var->mac[1] = GETB (inb, 0x3); +xs->var->mac[2] = GETB (inb, 0x4); +xs->var->mac[3] = GETB (inb, 0x5); +xs->var->mac[4] = GETB (inb, 0x6); +xs->var->mac[5] = GETB (inb, 0x7); + +w1 = GETW (inb, 0x10); +w2 = GETW (inb, 0x12); + +xs->var->rdrb = ((w2 << 16) | w1) & 0xFFFFF8; +xs->var->rrlen = (w2 >> 13) & 0x7; +xs->var->rrlen = (1u << xs->var->rrlen); +xs->var->relen = 4; +xs->var->rxnext = 0; +sim_debug (DBG_REG, &xs_dev, "xs_rdrb = %08X\n", xs->var->rdrb); +sim_debug (DBG_REG, &xs_dev, "xs_rrlen = %04X\n", xs->var->rrlen); + +w1 = GETW (inb, 0x14); +w2 = GETW (inb, 0x16); + +xs->var->tdrb = ((w2 << 16) | w1) & 0xFFFFF8; +xs->var->trlen = (w2 >> 13) & 0x7; +xs->var->trlen = (1u << xs->var->trlen); +xs->var->telen = 4; +xs->var->txnext = 0; +sim_debug (DBG_REG, &xs_dev, "xs_tdrb = %08X\n", xs->var->tdrb); +sim_debug (DBG_REG, &xs_dev, "xs_trlen = %04X\n", xs->var->trlen); + +xs->var->setup.mult0 = GETL (inb, 0x8); +xs->var->setup.mult1 = GETL (inb, 0xC); + +xs->var->setup.promiscuous = (xs->var->mode & MODE_PROM) ? 1 : 0; +xs->var->setup.multicast = ((xs->var->setup.mult0 | xs->var->setup.mult1) > 0) ? 1 : 0; + +xs->var->csr0 = xs->var->csr0 | CSR0_INIT; +xs->var->csr0 = xs->var->csr0 & ~CSR0_STOP; + +/* reset ethernet interface */ +memcpy (xs->var->setup.macs[0], xs->var->mac, sizeof(ETH_MAC)); +xs->var->setup.mac_count = 1; +if (xs->var->etherface) + eth_filter (xs->var->etherface, xs->var->setup.mac_count, + &xs->var->mac, xs->var->setup.multicast, + xs->var->setup.promiscuous); + +sim_activate (&xs_unit, 50); + +return SCPE_OK; +} + +void xs_updateint(CTLR* xs) +{ +if (xs->var->csr0 & 0x5F00) /* if any interrupt bits on, */ + xs_setint (xs); +else + xs_clrint (xs); +} + +void xs_setint (CTLR* xs) +{ +if (xs->var->csr0 & CSR0_INTR) + return; +xs->var->csr0 |= CSR0_INTR; +if (xs->var->csr0 & CSR_IE) + SET_INT (XS1); +} + +void xs_clrint (CTLR* xs) +{ +xs->var->csr0 &= ~CSR0_INTR; +CLR_INT (XS1); +} + +void xs_read_callback(int status) +{ +CTLR *xs = &xs_ctrl[0]; + +if (DEBUG_PRI (xs_dev, DBG_PCK)) + eth_packet_trace_ex (xs->var->etherface, xs->var->read_buffer.msg, xs->var->read_buffer.len, "xs-recvd", DEBUG_PRI (xs_dev, DBG_DAT), DBG_PCK); + +/* add packet to read queue */ +ethq_insert(&xs->var->ReadQ, 2, &xs->var->read_buffer, 0); +} + +void xs_write_callback (int status) +{ +CTLR *xs = &xs_ctrl[0]; +xs->var->write_buffer.status = status; +} + +/* Device initialization */ + +t_stat xs_reset (DEVICE *dptr) +{ +t_stat status; +CTLR *xs = &xs_ctrl[0]; + +xs->var->csr0 = 0; +xs->var->csr1 = 0; +xs->var->csr2 = 0; +xs->var->csr3 = 0; +xs->var->rptr = 0; +xs->var->mode = 0; +xs->var->inbb = 0; +CLR_INT (XS1); /* clear int req */ +/* init read queue (first time only) */ +status = ethq_init (&xs->var->ReadQ, XS_QUE_MAX); +if (status != SCPE_OK) + return status; + +sim_cancel (&xs_unit); /* cancel unit */ +return SCPE_OK; +} + +/* Attach routine */ + +t_stat xs_attach (UNIT *uptr, CONST char *cptr) +{ +t_stat status; +char* tptr; +CTLR *xs = &xs_ctrl[0]; + +tptr = (char *) malloc(strlen(cptr) + 1); +if (tptr == NULL) + return SCPE_MEM; +strcpy(tptr, cptr); + +xs->var->etherface = (ETH_DEV *) malloc(sizeof(ETH_DEV)); +if (!xs->var->etherface) + return SCPE_MEM; + +status = eth_open(xs->var->etherface, cptr, xs->dev, DBG_ETH); +if (status != SCPE_OK) { + free(tptr); + free(xs->var->etherface); + xs->var->etherface = 0; + return status; + } +uptr->filename = tptr; +uptr->flags |= UNIT_ATT; +eth_setcrc(xs->var->etherface, 1); /* enable CRC */ + +/* reset the device with the new attach info */ +xs_reset(xs->dev); + +return SCPE_OK; +} + +t_stat xs_detach (UNIT* uptr) +{ +CTLR *xs = &xs_ctrl[0]; + +if (uptr->flags & UNIT_ATT) { + eth_close (xs->var->etherface); + free(xs->var->etherface); + xs->var->etherface = 0; + free(uptr->filename); + uptr->filename = NULL; + uptr->flags &= ~UNIT_ATT; + } +return SCPE_OK; +} + +void xs_dump_rxring (CTLR* xs) +{ +int i; +int rrlen = xs->var->rrlen; +sim_printf ("receive ring[%s]: base address: %08x headers: %d, header size: %d, current: %d\n", + xs->dev->name, xs->var->rdrb, xs->var->rrlen, xs->var->relen, xs->var->rxnext); +for (i=0; ivar->rdrb + (xs->var->relen * 2) * i; + t_stat rstatus = XS_READW (ba, 8, rxhdr); /* get rxring entry[i] */ + int own = (rxhdr[2] & RXR_OWN) >> 15; + int len = rxhdr[0]; + uint32 addr = rxhdr[1] + ((rxhdr[2] & 3) << 16); + if (rstatus == 0) + sim_printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", + i, own, len, addr, rxhdr[0], rxhdr[1], rxhdr[2], rxhdr[3]); + } +} + +void xs_dump_txring (CTLR* xs) +{ +int i; +int trlen = xs->var->trlen; +sim_printf ("transmit ring[%s]: base address: %08x headers: %d, header size: %d, current: %d\n", + xs->dev->name, xs->var->tdrb, xs->var->trlen, xs->var->telen, xs->var->txnext); +for (i=0; ivar->tdrb + (xs->var->telen * 2) * i; + t_stat tstatus = XS_READW (ba, 8, txhdr); /* get rxring entry[i] */ + int own = (txhdr[2] & RXR_OWN) >> 15; + int len = txhdr[0]; + uint32 addr = txhdr[1] + ((txhdr[2] & 3) << 16); + if (tstatus == 0) + sim_printf (" header[%d]: own:%d, len:%d, address:%08x data:{%04x,%04x,%04x,%04x}\n", + i, own, len, addr, txhdr[0], txhdr[1], txhdr[2], txhdr[3]); + } +} + +t_stat xs_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "LANCE Ethernet Controller (XS)\n\n"); +fprintf (st, "The simulator implements one LANCE Ethernet controller (XS).\n"); +if (dptr->flags & DEV_DISABLE) + fprintf (st, "Initially the XS controller is disabled.\n"); +else + fprintf (st, "The XS controller cannot be disabled.\n"); +fprintf (st, "There are no configurable options. The MAC address is controlled through\n"); +fprintf (st, "the network address ROM device (NAR).\n\n"); +fprint_set_help (st, dptr); +fprintf (st, "\nConfigured options and controller state can be displayed with:\n\n"); +fprint_show_help (st, dptr); +fprintf (st, "To access the network, the simulated Ethernet controller must be attached to a\n"); +fprintf (st, "real Ethernet interface.\n\n"); +eth_attach_help(st, dptr, uptr, flag, cptr); +return SCPE_OK; +} + +const char *xs_description (DEVICE *dptr) +{ +return "LANCE Ethernet controller"; +} diff --git a/VAX/vax_xs.h b/VAX/vax_xs.h new file mode 100644 index 00000000..0f1e2f3b --- /dev/null +++ b/VAX/vax_xs.h @@ -0,0 +1,179 @@ +/* vax_xs.h: LANCE ethernet simulator + + Copyright (c) 2019, Matt Burke + This module is partly based on the DEUNA simulator, Copyright (c) 2003-2011, David T. Hittner + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name(s) of the author(s) shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author(s). + + xs LANCE Ethernet Controller +*/ + +#include "vax_defs.h" +#include "sim_ether.h" + +#define XS_QUE_MAX 500 /* message queue array */ +#define XS_FILTER_MAX 11 /* mac + 10 multicast addrs */ + +struct xs_setup { + int32 promiscuous; /* promiscuous mode enabled */ + int32 multicast; /* enable all multicast addresses */ + uint32 mult0; + uint32 mult1; + int32 mac_count; /* number of multicast mac addresses */ + ETH_MAC macs[XS_FILTER_MAX]; /* MAC addresses to respond to */ +}; + +struct xs_device { + /*+ initialized values - DO NOT MOVE */ + ETH_PCALLBACK rcallback; /* read callback routine */ + ETH_PCALLBACK wcallback; /* write callback routine */ + /*- initialized values - DO NOT MOVE */ + + /* I/O register storage */ + uint32 irq; /* interrupt request flag */ + + ETH_MAC mac; /* MAC address */ + ETH_DEV* etherface; /* buffers, etc. */ + ETH_PACK read_buffer; + ETH_PACK write_buffer; + ETH_QUE ReadQ; + struct xs_setup setup; + + uint16 csr0; /* LANCE registers */ + uint16 csr1; + uint16 csr2; + uint16 csr3; + uint16 rptr; /* register pointer */ + uint16 mode; /* mode register */ + uint32 inbb; /* initialisation block base */ + + uint32 tdrb; /* transmit desc ring base */ + uint32 telen; /* transmit desc ring entry len */ + uint32 trlen; /* transmit desc ring length */ + uint32 txnext; /* transmit buffer pointer */ + uint32 rdrb; /* receive desc ring base */ + uint32 relen; /* receive desc ring entry len */ + uint32 rrlen; /* receive desc ring length */ + uint32 rxnext; /* receive buffer pointer */ + + uint16 rxhdr[4]; /* content of RX ring entry, during wait */ + uint16 txhdr[4]; /* content of TX ring entry, during xmit */ +}; + +struct xs_controller { + DEVICE* dev; /* device block */ + UNIT* unit; /* unit block */ + DIB* dib; /* device interface block */ + struct xs_device* var; /* controller-specific variables */ +}; + +typedef struct xs_controller CTLR; + +/* CSR definitions */ +#define CSR0_ESUM 0x8000 /* <15> error summary */ +#define CSR0_BABL 0x4000 /* <14> transmitter timeout */ +#define CSR0_CERR 0x2000 /* <13> collision error */ +#define CSR0_MISS 0x1000 /* <12> missed packet */ +#define CSR0_MERR 0x0800 /* <11> memory error */ +#define CSR0_RINT 0x0400 /* <10> receive interrupt */ +#define CSR0_TINT 0x0200 /* <09> transmit interrupt */ +#define CSR0_IDON 0x0100 /* <08> initialisation done */ +#define CSR0_INTR 0x0080 /* <07> interrupt reqest */ +#define CSR0_RXON 0x0020 /* <05> receiver on */ +#define CSR0_TXON 0x0010 /* <04> transmitter on */ +#define CSR0_TDMD 0x0008 /* <03> transmitter demand */ +#define CSR0_STOP 0x0004 /* <02> stop */ +#define CSR0_STRT 0x0002 /* <01> start */ +#define CSR0_INIT 0x0001 /* <00> initialise */ +#define CSR0_RW (CSR_IE) +#define CSR0_W1C (CSR0_IDON | CSR0_TINT | CSR0_RINT | \ + CSR0_MERR | CSR0_MISS | CSR0_CERR | \ + CSR0_BABL) +#define CSR0_ERR (CSR0_BABL | CSR0_CERR | CSR0_MISS | \ + CSR0_MERR) + +/* Mode definitions */ +#define MODE_PROM 0x8000 /* <15> Promiscuous Mode */ +#define MODE_INTL 0x0040 /* <06> Internal Loopback */ +#define MODE_DRTY 0x0020 /* <05> Disable Retry */ +#define MODE_COLL 0x0010 /* <04> Force Collision */ +#define MODE_DTCR 0x0008 /* <03> Disable Transmit CRC */ +#define MODE_LOOP 0x0004 /* <02> Loopback */ +#define MODE_DTX 0x0002 /* <01> Disable Transmitter */ +#define MODE_DRX 0x0001 /* <00> Disable Receiver */ + +/* Transmitter Ring definitions */ +#define TXR_OWN 0x8000 /* <15> we own it (1) */ +#define TXR_ERRS 0x4000 /* <14> error summary */ +#define TXR_MORE 0x1000 /* <12> Mult Retries Needed */ +#define TXR_ONE 0x0800 /* <11> One Collision */ +#define TXR_DEF 0x0400 /* <10> Deferred */ +#define TXR_STF 0x0200 /* <09> Start Of Frame */ +#define TXR_ENF 0x0100 /* <08> End Of Frame */ +#define TXR_HADR 0x00FF /* <7:0> High order buffer address */ +#define TXR_BUFL 0x8000 /* <15> Buffer Length Error */ +#define TXR_UFLO 0x4000 /* <14> Underflow Error */ +#define TXR_LCOL 0x1000 /* <12> Late Collision */ +#define TXR_LCAR 0x0800 /* <11> Lost Carrier */ +#define TXR_RTRY 0x0400 /* <10> Retry Failure (16x) */ +#define TXR_TDR 0x01FF /* <9:0> TDR value if RTRY=1 */ + +/* Receiver Ring definitions */ +#define RXR_OWN 0x8000 /* <15> we own it (1) */ +#define RXR_ERRS 0x4000 /* <14> Error Summary */ +#define RXR_FRAM 0x2000 /* <13> Frame Error */ +#define RXR_OFLO 0x1000 /* <12> Message Overflow */ +#define RXR_CRC 0x0800 /* <11> CRC Check Error */ +#define RXR_BUFL 0x0400 /* <10> Buffer Length error */ +#define RXR_STF 0x0200 /* <09> Start Of Frame */ +#define RXR_ENF 0x0100 /* <08> End Of Frame */ +#define RXR_HADR 0x00FF /* <7:0> High order buffer address */ +#define RXR_MLEN 0x0FFF /* <11:0> Message Length */ + +BITFIELD xs_tdes_w1[] = { + BITNCF(8), BIT(ENP), BIT(STP), BIT(DEF), BIT(ONE), BIT(MORE), BIT(FCS), BIT(ERR), BIT(OWN), + ENDBITS +}; +BITFIELD xs_tdes_w2[] = { + BITFFMT(mlen,12,"0x%X"), + ENDBITS +}; + +BITFIELD xs_rdes_w1[] = { + BITNCF(8), BIT(ENP), BIT(STP), BIT(BUFL), BIT(CRC), BIT(OFLO), BIT(FRAM), BIT(ERRS), BIT(OWN), + ENDBITS +}; +BITFIELD xs_rdes_w2[] = { + BITFFMT(blen,12,"0x%X"), + ENDBITS +}; +BITFIELD xs_rdes_w3[] = { + BITFFMT(mlen,12,"0x%X"), + ENDBITS +}; + +/* Debug definitions */ +#define DBG_TRC 0x0001 +#define DBG_REG 0x0002 +#define DBG_PCK 0x0004 +#define DBG_DAT 0x0008 +#define DBG_ETH 0x0010 diff --git a/Visual Studio Projects/InfoServer100.vcproj b/Visual Studio Projects/InfoServer100.vcproj new file mode 100644 index 00000000..1f98d9a8 --- /dev/null +++ b/Visual Studio Projects/InfoServer100.vcproj @@ -0,0 +1,619 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/InfoServer1000.vcproj b/Visual Studio Projects/InfoServer1000.vcproj new file mode 100644 index 00000000..68ff3154 --- /dev/null +++ b/Visual Studio Projects/InfoServer1000.vcproj @@ -0,0 +1,583 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/MicroVAX2000.vcproj b/Visual Studio Projects/MicroVAX2000.vcproj new file mode 100644 index 00000000..9725fa01 --- /dev/null +++ b/Visual Studio Projects/MicroVAX2000.vcproj @@ -0,0 +1,615 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/MicroVAX3100.vcproj b/Visual Studio Projects/MicroVAX3100.vcproj new file mode 100644 index 00000000..007c4f20 --- /dev/null +++ b/Visual Studio Projects/MicroVAX3100.vcproj @@ -0,0 +1,619 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/MicroVAX3100M76.vcproj b/Visual Studio Projects/MicroVAX3100M76.vcproj new file mode 100644 index 00000000..7d518a38 --- /dev/null +++ b/Visual Studio Projects/MicroVAX3100M76.vcproj @@ -0,0 +1,609 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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a/Visual Studio Projects/MicroVAX3100e.vcproj b/Visual Studio Projects/MicroVAX3100e.vcproj new file mode 100644 index 00000000..77b32067 --- /dev/null +++ b/Visual Studio Projects/MicroVAX3100e.vcproj @@ -0,0 +1,619 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/Simh.sln b/Visual Studio Projects/Simh.sln index 334dc8dd..f713a1b4 100644 --- a/Visual Studio Projects/Simh.sln +++ b/Visual Studio Projects/Simh.sln @@ -303,11 +303,65 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "UC15", "UC15.vcproj", "{B5E {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} EndProjectSection EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "InfoServer1000", "InfoServer1000.vcproj", "{0137B38A-30E9-4181-B0AE-419CF469A24E}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX8200", "VAX8200.vcproj", "{B9BA7B49-AFAD-4950-B8DC-2FAD61AE8B7E}" ProjectSection(ProjectDependencies) = postProject {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} EndProjectSection EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MicroVAX2000", "MicroVAX2000.vcproj", "{69B5704E-DEF6-4F11-B849-22078F212E27}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MicroVAX3100", "MicroVAX3100.vcproj", "{7C7E80AA-D2EE-4FD3-9FF8-8490DC83335C}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MicroVAX3100e", "MicroVAX3100e.vcproj", "{06407112-07C6-46E6-A96E-393C27A9F633}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "InfoServer100", "InfoServer100.vcproj", "{6C818AD1-E09C-4C08-9832-E1D95FDCA597}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "InfoServer150VTX", "InfoServer150VTX.vcproj", "{4A8AA409-A793-444E-A03B-9D91E0EE4891}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MicroVAX3100M76", "MicroVAX3100M76.vcproj", "{7F8038CE-A04D-47B3-A284-BC0D3B1A7CD7}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAXStation4000M60", "VAXStation4000M60.vcproj", "{E158012B-70C1-4186-B787-C56B4476CD49}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "MicroVAX3100M80", "MicroVAX3100M80.vcproj", "{DCC79963-1155-47ED-A5BE-B5F6882B4B22}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAXStation4000VLC", "VAXStation4000VLC.vcproj", "{1AB7B087-9D64-48EA-A235-193DF85EB763}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAXStation3100M30", "VAXStation3100M30.vcproj", "{8198BF0B-235F-41A5-A16A-22CC616878E8}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAXStation3100M38", "VAXStation3100M38.vcproj", "{7E69582F-4C1E-45F7-8E15-5CD166A78BD3}" + ProjectSection(ProjectDependencies) = postProject + {D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8} + EndProjectSection +EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution Debug|Win32 = Debug|Win32 @@ -558,10 +612,58 @@ Global {B5E9D32E-53F9-4C9B-B037-5A2D34E370CF}.Debug|Win32.Build.0 = Debug|Win32 {B5E9D32E-53F9-4C9B-B037-5A2D34E370CF}.Release|Win32.ActiveCfg = Release|Win32 {B5E9D32E-53F9-4C9B-B037-5A2D34E370CF}.Release|Win32.Build.0 = Release|Win32 + {0137B38A-30E9-4181-B0AE-419CF469A24E}.Debug|Win32.ActiveCfg = Debug|Win32 + {0137B38A-30E9-4181-B0AE-419CF469A24E}.Debug|Win32.Build.0 = Debug|Win32 + {0137B38A-30E9-4181-B0AE-419CF469A24E}.Release|Win32.ActiveCfg = Release|Win32 + {0137B38A-30E9-4181-B0AE-419CF469A24E}.Release|Win32.Build.0 = Release|Win32 {B9BA7B49-AFAD-4950-B8DC-2FAD61AE8B7E}.Debug|Win32.ActiveCfg = Debug|Win32 {B9BA7B49-AFAD-4950-B8DC-2FAD61AE8B7E}.Debug|Win32.Build.0 = Debug|Win32 {B9BA7B49-AFAD-4950-B8DC-2FAD61AE8B7E}.Release|Win32.ActiveCfg = Release|Win32 {B9BA7B49-AFAD-4950-B8DC-2FAD61AE8B7E}.Release|Win32.Build.0 = Release|Win32 + {69B5704E-DEF6-4F11-B849-22078F212E27}.Debug|Win32.ActiveCfg = Debug|Win32 + {69B5704E-DEF6-4F11-B849-22078F212E27}.Debug|Win32.Build.0 = Debug|Win32 + {69B5704E-DEF6-4F11-B849-22078F212E27}.Release|Win32.ActiveCfg = Release|Win32 + {69B5704E-DEF6-4F11-B849-22078F212E27}.Release|Win32.Build.0 = Release|Win32 + {7C7E80AA-D2EE-4FD3-9FF8-8490DC83335C}.Debug|Win32.ActiveCfg = Debug|Win32 + {7C7E80AA-D2EE-4FD3-9FF8-8490DC83335C}.Debug|Win32.Build.0 = Debug|Win32 + {7C7E80AA-D2EE-4FD3-9FF8-8490DC83335C}.Release|Win32.ActiveCfg = Release|Win32 + {7C7E80AA-D2EE-4FD3-9FF8-8490DC83335C}.Release|Win32.Build.0 = Release|Win32 + {06407112-07C6-46E6-A96E-393C27A9F633}.Debug|Win32.ActiveCfg = Debug|Win32 + {06407112-07C6-46E6-A96E-393C27A9F633}.Debug|Win32.Build.0 = Debug|Win32 + {06407112-07C6-46E6-A96E-393C27A9F633}.Release|Win32.ActiveCfg = Release|Win32 + {06407112-07C6-46E6-A96E-393C27A9F633}.Release|Win32.Build.0 = Release|Win32 + {6C818AD1-E09C-4C08-9832-E1D95FDCA597}.Debug|Win32.ActiveCfg = Debug|Win32 + {6C818AD1-E09C-4C08-9832-E1D95FDCA597}.Debug|Win32.Build.0 = Debug|Win32 + {6C818AD1-E09C-4C08-9832-E1D95FDCA597}.Release|Win32.ActiveCfg = Release|Win32 + {6C818AD1-E09C-4C08-9832-E1D95FDCA597}.Release|Win32.Build.0 = Release|Win32 + {4A8AA409-A793-444E-A03B-9D91E0EE4891}.Debug|Win32.ActiveCfg = Debug|Win32 + {4A8AA409-A793-444E-A03B-9D91E0EE4891}.Debug|Win32.Build.0 = Debug|Win32 + {4A8AA409-A793-444E-A03B-9D91E0EE4891}.Release|Win32.ActiveCfg = Release|Win32 + {4A8AA409-A793-444E-A03B-9D91E0EE4891}.Release|Win32.Build.0 = Release|Win32 + {7F8038CE-A04D-47B3-A284-BC0D3B1A7CD7}.Debug|Win32.ActiveCfg = Debug|Win32 + {7F8038CE-A04D-47B3-A284-BC0D3B1A7CD7}.Debug|Win32.Build.0 = Debug|Win32 + {7F8038CE-A04D-47B3-A284-BC0D3B1A7CD7}.Release|Win32.ActiveCfg = Release|Win32 + {7F8038CE-A04D-47B3-A284-BC0D3B1A7CD7}.Release|Win32.Build.0 = Release|Win32 + {E158012B-70C1-4186-B787-C56B4476CD49}.Debug|Win32.ActiveCfg = Debug|Win32 + {E158012B-70C1-4186-B787-C56B4476CD49}.Debug|Win32.Build.0 = Debug|Win32 + {E158012B-70C1-4186-B787-C56B4476CD49}.Release|Win32.ActiveCfg = Release|Win32 + {E158012B-70C1-4186-B787-C56B4476CD49}.Release|Win32.Build.0 = Release|Win32 + {DCC79963-1155-47ED-A5BE-B5F6882B4B22}.Debug|Win32.ActiveCfg = Debug|Win32 + {DCC79963-1155-47ED-A5BE-B5F6882B4B22}.Debug|Win32.Build.0 = Debug|Win32 + {DCC79963-1155-47ED-A5BE-B5F6882B4B22}.Release|Win32.ActiveCfg = Release|Win32 + {DCC79963-1155-47ED-A5BE-B5F6882B4B22}.Release|Win32.Build.0 = Release|Win32 + {1AB7B087-9D64-48EA-A235-193DF85EB763}.Debug|Win32.ActiveCfg = Debug|Win32 + {1AB7B087-9D64-48EA-A235-193DF85EB763}.Debug|Win32.Build.0 = Debug|Win32 + {1AB7B087-9D64-48EA-A235-193DF85EB763}.Release|Win32.ActiveCfg = Release|Win32 + {1AB7B087-9D64-48EA-A235-193DF85EB763}.Release|Win32.Build.0 = Release|Win32 + {8198BF0B-235F-41A5-A16A-22CC616878E8}.Debug|Win32.ActiveCfg = Debug|Win32 + {8198BF0B-235F-41A5-A16A-22CC616878E8}.Debug|Win32.Build.0 = Debug|Win32 + {8198BF0B-235F-41A5-A16A-22CC616878E8}.Release|Win32.ActiveCfg = Release|Win32 + {8198BF0B-235F-41A5-A16A-22CC616878E8}.Release|Win32.Build.0 = Release|Win32 + {7E69582F-4C1E-45F7-8E15-5CD166A78BD3}.Debug|Win32.ActiveCfg = Debug|Win32 + {7E69582F-4C1E-45F7-8E15-5CD166A78BD3}.Debug|Win32.Build.0 = Debug|Win32 + {7E69582F-4C1E-45F7-8E15-5CD166A78BD3}.Release|Win32.ActiveCfg = Release|Win32 + {7E69582F-4C1E-45F7-8E15-5CD166A78BD3}.Release|Win32.Build.0 = Release|Win32 EndGlobalSection GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE diff --git a/Visual Studio Projects/VAXStation3100M30.vcproj b/Visual Studio Projects/VAXStation3100M30.vcproj new file mode 100644 index 00000000..5eec33bf --- /dev/null +++ b/Visual Studio Projects/VAXStation3100M30.vcproj @@ -0,0 +1,619 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAXStation3100M38.vcproj b/Visual Studio Projects/VAXStation3100M38.vcproj new file mode 100644 index 00000000..eeea0fa8 --- /dev/null +++ b/Visual Studio Projects/VAXStation3100M38.vcproj @@ -0,0 +1,625 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAXStation4000M60.vcproj b/Visual Studio Projects/VAXStation4000M60.vcproj new file mode 100644 index 00000000..edb1c7ca --- /dev/null +++ b/Visual Studio Projects/VAXStation4000M60.vcproj @@ -0,0 +1,595 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Visual Studio Projects/VAXStation4000VLC.vcproj b/Visual Studio Projects/VAXStation4000VLC.vcproj new file mode 100644 index 00000000..ea6dbd84 --- /dev/null +++ b/Visual Studio Projects/VAXStation4000VLC.vcproj @@ -0,0 +1,601 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/descrip.mms b/descrip.mms index ce154d6b..0dd5ed8b 100644 --- a/descrip.mms +++ b/descrip.mms @@ -3,7 +3,7 @@ # Modified By: Mark Pizzolato / mark@infocomm.com # Norman Lastovica / norman.lastovica@oracle.com # Camiel Vanderhoeven / camiel@camicom.com -# Matt Burke / scope.matthew@btinternet.com +# Matt Burke / matt@9track.net # # This MMS/MMK build script is used to compile the various simulators in # the SIMH package for OpenVMS using DEC C v6.0-001(AXP), v6.5-001(AXP), @@ -15,50 +15,62 @@ # # This build script will accept the following build options. # -# ALL Just Build "Everything". -# 3B2 Just Build The AT&T 3B2. -# ALTAIR Just Build The MITS Altair. -# ALTAIRZ80 Just Build The MITS Altair Z80. -# BESM6 Just Build The BESM-6. -# B5500 Just Build The B5500. -# CDC1700 Just Build The CDC1700. -# ECLIPSE Just Build The Data General Eclipse. -# GRI Just Build The GRI Corporation GRI-909. -# LGP Just Build The Royal-McBee LGP-30. -# H316 Just Build The Honewell 316/516. -# HP2100 Just Build The Hewlett-Packard HP-2100. -# HP3000 Just Build The Hewlett-Packard HP-3000. -# I1401 Just Build The IBM 1401. -# I1620 Just Build The IBM 1620. -# I7094 Just Build The IBM 7094. -# IBM1130 Just Build The IBM 1130. -# ID16 Just Build The Interdata 16-bit CPU. -# ID32 Just Build The Interdata 32-bit CPU. -# NOVA Just Build The Data General Nova. -# PDP1 Just Build The DEC PDP-1. -# PDP4 Just Build The DEC PDP-4. -# PDP7 Just Build The DEC PDP-7. -# PDP8 Just Build The DEC PDP-8. -# PDP9 Just Build The DEC PDP-9. -# PDP10 Just Build The DEC PDP-10. -# PDP11 Just Build The DEC PDP-11. -# PDP15 Just Build The DEC PDP-15. -# S3 Just Build The IBM System 3. -# SDS Just Build The SDS 940. -# SSEM Just Build the Manchester University SSEM. -# SWTP6800MP-A Just Build The SWTP6800MP-A. -# SWTP6800MP-A2 Just Build The SWTP6800MP-A2. -# VAX Just Build The DEC MicroVAX3900 (aka VAX). -# MicroVAX3900 Just Build The DEC MicroVAX3900 (aka VAX). -# MicroVAX1 Just Build The DEC MicroVAX1 (MicroVAX I). -# rtVAX1000 Just Build The DEC rtVAX1000 (rtVAX 1000). -# MicroVAX2 Just Build The DEC MicroVAX2 (MicroVAX II). -# VAX730 Just Build The DEC VAX730. -# VAX750 Just Build The DEC VAX750. -# VAX780 Just Build The DEC VAX780. -# VAX8200 Just Build The DEC VAX8200. -# VAX8600 Just Build The DEC VAX8600. -# CLEAN Will Clean Files Back To Base Kit. +# ALL Just Build "Everything". +# 3B2 Just Build The AT&T 3B2. +# ALTAIR Just Build The MITS Altair. +# ALTAIRZ80 Just Build The MITS Altair Z80. +# BESM6 Just Build The BESM-6. +# B5500 Just Build The B5500. +# CDC1700 Just Build The CDC1700. +# ECLIPSE Just Build The Data General Eclipse. +# GRI Just Build The GRI Corporation GRI-909. +# LGP Just Build The Royal-McBee LGP-30. +# H316 Just Build The Honewell 316/516. +# HP2100 Just Build The Hewlett-Packard HP-2100. +# HP3000 Just Build The Hewlett-Packard HP-3000. +# I1401 Just Build The IBM 1401. +# I1620 Just Build The IBM 1620. +# I7094 Just Build The IBM 7094. +# IBM1130 Just Build The IBM 1130. +# ID16 Just Build The Interdata 16-bit CPU. +# ID32 Just Build The Interdata 32-bit CPU. +# INFOSERVER1000 Just Build The DEC InfoServer 1000. +# NOVA Just Build The Data General Nova. +# PDP1 Just Build The DEC PDP-1. +# PDP4 Just Build The DEC PDP-4. +# PDP7 Just Build The DEC PDP-7. +# PDP8 Just Build The DEC PDP-8. +# PDP9 Just Build The DEC PDP-9. +# PDP10 Just Build The DEC PDP-10. +# PDP11 Just Build The DEC PDP-11. +# PDP15 Just Build The DEC PDP-15. +# S3 Just Build The IBM System 3. +# SDS Just Build The SDS 940. +# SSEM Just Build the Manchester University SSEM. +# SWTP6800MP-A Just Build The SWTP6800MP-A. +# SWTP6800MP-A2 Just Build The SWTP6800MP-A2. +# VAX Just Build The DEC MicroVAX3900 (aka VAX). +# MicroVAX3900 Just Build The DEC MicroVAX3900 (aka VAX). +# MicroVAX1 Just Build The DEC MicroVAX1 (MicroVAX I). +# rtVAX1000 Just Build The DEC rtVAX1000 (rtVAX 1000). +# MicroVAX2 Just Build The DEC MicroVAX2 (MicroVAX II). +# MICROVAX2000 Just Build The DEC MicroVAX 2000. +# INFOSERVER100 Just Build The DEC InfoServer 100. +# INFOSERVER150VTX Just Build The DEC InfoServer 150 VXT. +# MICROVAX3100 Just Build The DEC MicroVAX 3100 M10/M20. +# MICROVAX3100E Just Build The DEC MicroVAX 3100 M10e/M20e. +# VAXSTATION3100M30 Just Build The DEC VAXstation 3100 M30. +# VAXSTATION3100M38 Just Build The DEC VAXstation 3100 M38. +# VAXSTATION3100M76 Just Build The DEC VAXstation 3100 M76. +# VAXSTATION4000M60 Just Build The DEC VAXstation 4000 M60. +# VAXSTATION3100M80 Just Build The DEC MicroVAX 3100 M80. +# VAXSTATION4000VLC Just Build The DEC VAXstation 4000 VLC. +# VAX730 Just Build The DEC VAX730. +# VAX750 Just Build The DEC VAX750. +# VAX780 Just Build The DEC VAX780. +# VAX8200 Just Build The DEC VAX8200. +# VAX8600 Just Build The DEC VAX8600. +# CLEAN Will Clean Files Back To Base Kit. # # To build with debugging enabled (which will also enable traceback # information) use.. @@ -208,7 +220,8 @@ SIMH_SOURCE = $(SIMH_DIR)SIM_CONSOLE.C,$(SIMH_DIR)SIM_SOCK.C,\ $(SIMH_DIR)SIM_TMXR.C,$(SIMH_DIR)SIM_ETHER.C,\ $(SIMH_DIR)SIM_TAPE.C,$(SIMH_DIR)SIM_FIO.C,\ $(SIMH_DIR)SIM_TIMER.C,$(SIMH_DIR)SIM_DISK.C,\ - $(SIMH_DIR)SIM_SERIAL.C,$(SIMH_DIR)SIM_VIDEO.C + $(SIMH_DIR)SIM_SERIAL.C,$(SIMH_DIR)SIM_VIDEO.C,\ + $(SIMH_DIR)SIM_SCSI.C SIMH_MAIN = SCP.C .IFDEF ALPHA_OR_IA64 SIMH_LIB64 = $(LIB_DIR)SIMH64-$(ARCH).OLB @@ -736,6 +749,326 @@ VAX_OPTIONS = /INCL=($(SIMH_DIR),$(VAX_DIR),$(PDP11_DIR)$(PCAP_INC))\ VAX_SIMH_LIB = $(SIMH_LIB) .ENDIF +# Digital Equipment VAX410 (MicroVAX 2000) Simulator Definitions. +# +VAX410_DIR = SYS$DISK:[.VAX] +VAX410_LIB1 = $(LIB_DIR)VAX410L1-$(ARCH).OLB +VAX410_SOURCE1 = $(VAX410_DIR)VAX_CPU.C,$(VAX410_DIR)VAX_CPU1.C,\ + $(VAX410_DIR)VAX_FPA.C,$(VAX410_DIR)VAX_CIS.C,\ + $(VAX410_DIR)VAX_OCTA.C,$(VAX410_DIR)VAX_CMODE.C,\ + $(VAX410_DIR)VAX_MMU.C,$(VAX410_DIR)VAX_SYS.C,\ + $(VAX410_DIR)VAX_SYSCM.C +VAX410_LIB2 = $(LIB_DIR)VAX410L2-$(ARCH).OLB +VAX410_SOURCE2 = $(VAX410_DIR)VAX_NAR.C,$(VAX410_DIR)VAX4XX_STDDEV.C,\ + $(VAX410_DIR)VAX410_SYSDEV.C,$(VAX410_DIR)VAX410_SYSLIST.C,\ + $(VAX410_DIR)VAX4XX_DZ.C,$(VAX410_DIR)VAX4XX_RD.C,\ + $(VAX410_DIR)VAX4XX_RZ80.C,$(VAX410_DIR)VAX_XS.C,\ + $(VAX410_DIR)VAX4XX_VA.C,$(VAX410_DIR)VAX4XX_VC.C,\ + $(VAX410_DIR)VAX_LK.C,$(VAX410_DIR)VAX_VS.C,\ + $(VAX410_DIR)VAX_GPX.C,$(VAX410_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX410_OPTIONS = /INCL=($(SIMH_DIR),$(VAX410_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_410=1") +VAX410_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX410_OPTIONS = /INCL=($(SIMH_DIR),$(VAX410_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_410=1") +VAX410_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX411 (InfoServer 100) Simulator Definitions. +# +VAX411_DIR = SYS$DISK:[.VAX] +VAX411_LIB1 = $(LIB_DIR)VAX411L1-$(ARCH).OLB +VAX411_SOURCE1 = $(VAX411_DIR)VAX_CPU.C,$(VAX411_DIR)VAX_CPU1.C,\ + $(VAX411_DIR)VAX_FPA.C,$(VAX411_DIR)VAX_CIS.C,\ + $(VAX411_DIR)VAX_OCTA.C,$(VAX411_DIR)VAX_CMODE.C,\ + $(VAX411_DIR)VAX_MMU.C,$(VAX411_DIR)VAX_SYS.C,\ + $(VAX411_DIR)VAX_SYSCM.C +VAX411_LIB2 = $(LIB_DIR)VAX411L2-$(ARCH).OLB +VAX411_SOURCE2 = $(VAX411_DIR)VAX_NAR.C,$(VAX411_DIR)VAX4XX_STDDEV.C,\ + $(VAX411_DIR)VAX420_SYSDEV.C,$(VAX411_DIR)VAX420_SYSLIST.C,\ + $(VAX411_DIR)VAX4XX_DZ.C,$(VAX411_DIR)VAX4XX_RD.C,\ + $(VAX411_DIR)VAX4XX_RZ80.C,$(VAX411_DIR)VAX_XS.C,\ + $(VAX411_DIR)VAX4XX_VA.C,$(VAX411_DIR)VAX4XX_VC.C,\ + $(VAX411_DIR)VAX4XX_VE.C,$(VAX411_DIR)VAX_LK.C,\ + $(VAX411_DIR)VAX_VS.C,$(VAX411_DIR)VAX_GPX.C,\ + $(VAX411_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX411_OPTIONS = /INCL=($(SIMH_DIR),$(VAX411_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_420=1","VAX_411=1") +VAX411_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX411_OPTIONS = /INCL=($(SIMH_DIR),$(VAX411_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_420=1","VAX_411=1") +VAX411_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX412 (InfoServer 150 VXT) Simulator Definitions. +# +VAX412_DIR = SYS$DISK:[.VAX] +VAX412_LIB1 = $(LIB_DIR)VAX412L1-$(ARCH).OLB +VAX412_SOURCE1 = $(VAX412_DIR)VAX_CPU.C,$(VAX412_DIR)VAX_CPU1.C,\ + $(VAX412_DIR)VAX_FPA.C,$(VAX412_DIR)VAX_CIS.C,\ + $(VAX412_DIR)VAX_OCTA.C,$(VAX412_DIR)VAX_CMODE.C,\ + $(VAX412_DIR)VAX_MMU.C,$(VAX412_DIR)VAX_SYS.C,\ + $(VAX412_DIR)VAX_SYSCM.C +VAX412_LIB2 = $(LIB_DIR)VAX412L2-$(ARCH).OLB +VAX412_SOURCE2 = $(VAX412_DIR)VAX_NAR.C,$(VAX412_DIR)VAX4XX_STDDEV.C,\ + $(VAX412_DIR)VAX420_SYSDEV.C,$(VAX412_DIR)VAX420_SYSLIST.C,\ + $(VAX412_DIR)VAX4XX_DZ.C,$(VAX412_DIR)VAX4XX_RD.C,\ + $(VAX412_DIR)VAX4XX_RZ80.C,$(VAX412_DIR)VAX_XS.C,\ + $(VAX412_DIR)VAX4XX_VA.C,$(VAX412_DIR)VAX4XX_VC.C,\ + $(VAX412_DIR)VAX4XX_VE.C,$(VAX412_DIR)VAX_LK.C,\ + $(VAX412_DIR)VAX_VS.C,$(VAX412_DIR)VAX_GPX.C,\ + $(VAX412_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX412_OPTIONS = /INCL=($(SIMH_DIR),$(VAX412_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_420=1","VAX_412=1") +VAX412_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX412_OPTIONS = /INCL=($(SIMH_DIR),$(VAX412_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_420=1","VAX_412=1") +VAX412_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX41A (MicroVAX 3100 M10/M20) Simulator Definitions. +# +VAX41A_DIR = SYS$DISK:[.VAX] +VAX41A_LIB1 = $(LIB_DIR)VAX41AL1-$(ARCH).OLB +VAX41A_SOURCE1 = $(VAX41A_DIR)VAX_CPU.C,$(VAX41A_DIR)VAX_CPU1.C,\ + $(VAX41A_DIR)VAX_FPA.C,$(VAX41A_DIR)VAX_CIS.C,\ + $(VAX41A_DIR)VAX_OCTA.C,$(VAX41A_DIR)VAX_CMODE.C,\ + $(VAX41A_DIR)VAX_MMU.C,$(VAX41A_DIR)VAX_SYS.C,\ + $(VAX41A_DIR)VAX_SYSCM.C +VAX41A_LIB2 = $(LIB_DIR)VAX41AL2-$(ARCH).OLB +VAX41A_SOURCE2 = $(VAX41A_DIR)VAX_NAR.C,$(VAX41A_DIR)VAX4XX_STDDEV.C,\ + $(VAX41A_DIR)VAX420_SYSDEV.C,$(VAX41A_DIR)VAX420_SYSLIST.C,\ + $(VAX41A_DIR)VAX4XX_DZ.C,$(VAX41A_DIR)VAX4XX_RD.C,\ + $(VAX41A_DIR)VAX4XX_RZ80.C,$(VAX41A_DIR)VAX_XS.C,\ + $(VAX41A_DIR)VAX4XX_VA.C,$(VAX41A_DIR)VAX4XX_VC.C,\ + $(VAX41A_DIR)VAX4XX_VE.C,$(VAX41A_DIR)VAX_LK.C,\ + $(VAX41A_DIR)VAX_VS.C,$(VAX41A_DIR)VAX_GPX.C,\ + $(VAX41A_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX41A_OPTIONS = /INCL=($(SIMH_DIR),$(VAX41A_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_420=1","VAX_41A=1") +VAX41A_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX41A_OPTIONS = /INCL=($(SIMH_DIR),$(VAX41A_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_420=1","VAX_41A=1") +VAX41A_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX41D (MicroVAX 3100 M10e/M20e) Simulator Definitions. +# +VAX41D_DIR = SYS$DISK:[.VAX] +VAX41D_LIB1 = $(LIB_DIR)VAX41DL1-$(ARCH).OLB +VAX41D_SOURCE1 = $(VAX41D_DIR)VAX_CPU.C,$(VAX41D_DIR)VAX_CPU1.C,\ + $(VAX41D_DIR)VAX_FPA.C,$(VAX41D_DIR)VAX_CIS.C,\ + $(VAX41D_DIR)VAX_OCTA.C,$(VAX41D_DIR)VAX_CMODE.C,\ + $(VAX41D_DIR)VAX_MMU.C,$(VAX41D_DIR)VAX_SYS.C,\ + $(VAX41D_DIR)VAX_SYSCM.C +VAX41D_LIB2 = $(LIB_DIR)VAX41DL2-$(ARCH).OLB +VAX41D_SOURCE2 = $(VAX41D_DIR)VAX_NAR.C,$(VAX41D_DIR)VAX4XX_STDDEV.C,\ + $(VAX41D_DIR)VAX420_SYSDEV.C,$(VAX41D_DIR)VAX420_SYSLIST.C,\ + $(VAX41D_DIR)VAX4XX_DZ.C,$(VAX41D_DIR)VAX4XX_RD.C,\ + $(VAX41D_DIR)VAX4XX_RZ80.C,$(VAX41D_DIR)VAX_XS.C,\ + $(VAX41D_DIR)VAX4XX_VA.C,$(VAX41D_DIR)VAX4XX_VC.C,\ + $(VAX41D_DIR)VAX4XX_VE.C,$(VAX41D_DIR)VAX_LK.C,\ + $(VAX41D_DIR)VAX_VS.C,$(VAX41D_DIR)VAX_GPX.C,\ + $(VAX41D_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX41D_OPTIONS = /INCL=($(SIMH_DIR),$(VAX41D_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_420=1","VAX_41D=1") +VAX41D_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX41D_OPTIONS = /INCL=($(SIMH_DIR),$(VAX41D_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_420=1","VAX_41D=1") +VAX41D_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX42A (VAXstation 3100 M30) Simulator Definitions. +# +VAX42A_DIR = SYS$DISK:[.VAX] +VAX42A_LIB1 = $(LIB_DIR)VAX42AL1-$(ARCH).OLB +VAX42A_SOURCE1 = $(VAX42A_DIR)VAX_CPU.C,$(VAX42A_DIR)VAX_CPU1.C,\ + $(VAX42A_DIR)VAX_FPA.C,$(VAX42A_DIR)VAX_CIS.C,\ + $(VAX42A_DIR)VAX_OCTA.C,$(VAX42A_DIR)VAX_CMODE.C,\ + $(VAX42A_DIR)VAX_MMU.C,$(VAX42A_DIR)VAX_SYS.C,\ + $(VAX42A_DIR)VAX_SYSCM.C +VAX42A_LIB2 = $(LIB_DIR)VAX42AL2-$(ARCH).OLB +VAX42A_SOURCE2 = $(VAX42A_DIR)VAX_NAR.C,$(VAX42A_DIR)VAX4XX_STDDEV.C,\ + $(VAX42A_DIR)VAX420_SYSDEV.C,$(VAX42A_DIR)VAX420_SYSLIST.C,\ + $(VAX42A_DIR)VAX4XX_DZ.C,$(VAX42A_DIR)VAX4XX_RD.C,\ + $(VAX42A_DIR)VAX4XX_RZ80.C,$(VAX42A_DIR)VAX_XS.C,\ + $(VAX42A_DIR)VAX4XX_VA.C,$(VAX42A_DIR)VAX4XX_VC.C,\ + $(VAX42A_DIR)VAX4XX_VE.C,$(VAX42A_DIR)VAX_LK.C,\ + $(VAX42A_DIR)VAX_VS.C,$(VAX42A_DIR)VAX_GPX.C,\ + $(VAX42A_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX42A_OPTIONS = /INCL=($(SIMH_DIR),$(VAX42A_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_420=1","VAX_42A=1") +VAX42A_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX42A_OPTIONS = /INCL=($(SIMH_DIR),$(VAX42A_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_420=1","VAX_42A=1") +VAX42A_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX42B (VAXstation 3100 M38) Simulator Definitions. +# +VAX42B_DIR = SYS$DISK:[.VAX] +VAX42B_LIB1 = $(LIB_DIR)VAX42BL1-$(ARCH).OLB +VAX42B_SOURCE1 = $(VAX42B_DIR)VAX_CPU.C,$(VAX42B_DIR)VAX_CPU1.C,\ + $(VAX42B_DIR)VAX_FPA.C,$(VAX42B_DIR)VAX_CIS.C,\ + $(VAX42B_DIR)VAX_OCTA.C,$(VAX42B_DIR)VAX_CMODE.C,\ + $(VAX42B_DIR)VAX_MMU.C,$(VAX42B_DIR)VAX_SYS.C,\ + $(VAX42B_DIR)VAX_SYSCM.C +VAX42B_LIB2 = $(LIB_DIR)VAX42BL2-$(ARCH).OLB +VAX42B_SOURCE2 = $(VAX42B_DIR)VAX_NAR.C,$(VAX42B_DIR)VAX4XX_STDDEV.C,\ + $(VAX42B_DIR)VAX420_SYSDEV.C,$(VAX42B_DIR)VAX420_SYSLIST.C,\ + $(VAX42B_DIR)VAX4XX_DZ.C,$(VAX42B_DIR)VAX4XX_RD.C,\ + $(VAX42B_DIR)VAX4XX_RZ80.C,$(VAX42B_DIR)VAX_XS.C,\ + $(VAX42B_DIR)VAX4XX_VA.C,$(VAX42B_DIR)VAX4XX_VC.C,\ + $(VAX42B_DIR)VAX4XX_VE.C,$(VAX42B_DIR)VAX_LK.C,\ + $(VAX42B_DIR)VAX_VS.C,$(VAX42B_DIR)VAX_GPX.C,\ + $(VAX42B_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX42B_OPTIONS = /INCL=($(SIMH_DIR),$(VAX42B_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_420=1","VAX_42B=1") +VAX42B_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX42B_OPTIONS = /INCL=($(SIMH_DIR),$(VAX42B_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_420=1","VAX_42B=1") +VAX42B_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX43 (VAXstation 3100 M76) Simulator Definitions. +# +VAX43_DIR = SYS$DISK:[.VAX] +VAX43_LIB1 = $(LIB_DIR)VAX43L1-$(ARCH).OLB +VAX43_SOURCE1 = $(VAX43_DIR)VAX_CPU.C,$(VAX43_DIR)VAX_CPU1.C,\ + $(VAX43_DIR)VAX_FPA.C,$(VAX43_DIR)VAX_CIS.C,\ + $(VAX43_DIR)VAX_OCTA.C,$(VAX43_DIR)VAX_CMODE.C,\ + $(VAX43_DIR)VAX_MMU.C,$(VAX43_DIR)VAX_SYS.C,\ + $(VAX43_DIR)VAX_SYSCM.C +VAX43_LIB2 = $(LIB_DIR)VAX43L2-$(ARCH).OLB +VAX43_SOURCE2 = $(VAX43_DIR)VAX_NAR.C,$(VAX43_DIR)VAX4XX_STDDEV.C,\ + $(VAX43_DIR)VAX43_SYSDEV.C,$(VAX43_DIR)VAX43_SYSLIST.C,\ + $(VAX43_DIR)VAX4XX_DZ.C,$(VAX43_DIR)VAX4XX_RZ80.C,\ + $(VAX43_DIR)VAX_XS.C,$(VAX43_DIR)VAX4XX_VC.C,\ + $(VAX43_DIR)VAX4XX_VE.C,$(VAX43_DIR)VAX_LK.C,\ + $(VAX43_DIR)VAX_VS.C,$(VAX43_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX43_OPTIONS = /INCL=($(SIMH_DIR),$(VAX43_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_43=1") +VAX43_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX43_OPTIONS = /INCL=($(SIMH_DIR),$(VAX43_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_43=1") +VAX43_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX46 (VAXstation 4000 M60) Simulator Definitions. +# +VAX46_DIR = SYS$DISK:[.VAX] +VAX46_LIB1 = $(LIB_DIR)VAX46L1-$(ARCH).OLB +VAX46_SOURCE1 = $(VAX46_DIR)VAX_CPU.C,$(VAX46_DIR)VAX_CPU1.C,\ + $(VAX46_DIR)VAX_FPA.C,$(VAX46_DIR)VAX_CIS.C,\ + $(VAX46_DIR)VAX_OCTA.C,$(VAX46_DIR)VAX_CMODE.C,\ + $(VAX46_DIR)VAX_MMU.C,$(VAX46_DIR)VAX_SYS.C,\ + $(VAX46_DIR)VAX_SYSCM.C +VAX46_LIB2 = $(LIB_DIR)VAX46L2-$(ARCH).OLB +VAX46_SOURCE2 = $(VAX46_DIR)VAX_NAR.C,$(VAX46_DIR)VAX4XX_STDDEV.C,\ + $(VAX46_DIR)VAX440_SYSDEV.C,$(VAX46_DIR)VAX440_SYSLIST.C,\ + $(VAX46_DIR)VAX4XX_DZ.C,$(VAX46_DIR)VAX4XX_RZ94.C,\ + $(VAX46_DIR)VAX_XS.C,$(VAX46_DIR)VAX_LK.C,\ + $(VAX46_DIR)VAX_VS.C,$(VAX46_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX46_OPTIONS = /INCL=($(SIMH_DIR),$(VAX46_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_440=1","VAX_46=1") +VAX46_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX46_OPTIONS = /INCL=($(SIMH_DIR),$(VAX46_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_440=1","VAX_46=1") +VAX46_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX47 (MicroVAX 3100 M80) Simulator Definitions. +# +VAX47_DIR = SYS$DISK:[.VAX] +VAX47_LIB1 = $(LIB_DIR)VAX47L1-$(ARCH).OLB +VAX47_SOURCE1 = $(VAX47_DIR)VAX_CPU.C,$(VAX47_DIR)VAX_CPU1.C,\ + $(VAX47_DIR)VAX_FPA.C,$(VAX47_DIR)VAX_CIS.C,\ + $(VAX47_DIR)VAX_OCTA.C,$(VAX47_DIR)VAX_CMODE.C,\ + $(VAX47_DIR)VAX_MMU.C,$(VAX47_DIR)VAX_SYS.C,\ + $(VAX47_DIR)VAX_SYSCM.C +VAX47_LIB2 = $(LIB_DIR)VAX47L2-$(ARCH).OLB +VAX47_SOURCE2 = $(VAX47_DIR)VAX_NAR.C,$(VAX47_DIR)VAX4XX_STDDEV.C,\ + $(VAX47_DIR)VAX440_SYSDEV.C,$(VAX47_DIR)VAX440_SYSLIST.C,\ + $(VAX47_DIR)VAX4XX_DZ.C,$(VAX47_DIR)VAX4XX_RZ94.C,\ + $(VAX47_DIR)VAX_XS.C,$(VAX47_DIR)VAX_LK.C,\ + $(VAX47_DIR)VAX_VS.C,$(VAX47_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX47_OPTIONS = /INCL=($(SIMH_DIR),$(VAX47_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_440=1","VAX_47=1") +VAX47_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX47_OPTIONS = /INCL=($(SIMH_DIR),$(VAX47_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_440=1","VAX_47=1") +VAX47_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment VAX48 (VAXstation 4000 VLC) Simulator Definitions. +# +VAX48_DIR = SYS$DISK:[.VAX] +VAX48_LIB1 = $(LIB_DIR)VAX48L1-$(ARCH).OLB +VAX48_SOURCE1 = $(VAX48_DIR)VAX_CPU.C,$(VAX48_DIR)VAX_CPU1.C,\ + $(VAX48_DIR)VAX_FPA.C,$(VAX48_DIR)VAX_CIS.C,\ + $(VAX48_DIR)VAX_OCTA.C,$(VAX48_DIR)VAX_CMODE.C,\ + $(VAX48_DIR)VAX_MMU.C,$(VAX48_DIR)VAX_SYS.C,\ + $(VAX48_DIR)VAX_SYSCM.C +VAX48_LIB2 = $(LIB_DIR)VAX48L2-$(ARCH).OLB +VAX48_SOURCE2 = $(VAX48_DIR)VAX_NAR.C,$(VAX48_DIR)VAX4XX_STDDEV.C,\ + $(VAX48_DIR)VAX440_SYSDEV.C,$(VAX48_DIR)VAX440_SYSLIST.C,\ + $(VAX48_DIR)VAX4XX_DZ.C,$(VAX48_DIR)VAX4XX_RZ94.C,\ + $(VAX48_DIR)VAX_XS.C,$(VAX48_DIR)VAX_LK.C,\ + $(VAX48_DIR)VAX_VS.C,$(VAX48_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +VAX48_OPTIONS = /INCL=($(SIMH_DIR),$(VAX48_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_440=1","VAX_48=1") +VAX48_SIMH_LIB = $(SIMH_LIB64) +.ELSE +VAX48_OPTIONS = /INCL=($(SIMH_DIR),$(VAX48_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_440=1","VAX_48=1") +VAX48_SIMH_LIB = $(SIMH_LIB) +.ENDIF + +# Digital Equipment IS1000 (InfoServer 1000) Simulator Definitions. +# +IS1000_DIR = SYS$DISK:[.VAX] +IS1000_LIB1 = $(LIB_DIR)IS1000L1-$(ARCH).OLB +IS1000_SOURCE1 = $(IS1000_DIR)VAX_CPU.C,$(IS1000_DIR)VAX_CPU1.C,\ + $(IS1000_DIR)VAX_FPA.C,$(IS1000_DIR)VAX_CIS.C,\ + $(IS1000_DIR)VAX_OCTA.C,$(IS1000_DIR)VAX_CMODE.C,\ + $(IS1000_DIR)VAX_MMU.C,$(IS1000_DIR)VAX_SYS.C,\ + $(IS1000_DIR)VAX_SYSCM.C +IS1000_LIB2 = $(LIB_DIR)IS1000L2-$(ARCH).OLB +IS1000_SOURCE2 = $(IS1000_DIR)VAX_NAR.C,$(IS1000_DIR)VAX4NN_STDDEV.C,\ + $(IS1000_DIR)IS1000_SYSDEV.C,$(IS1000_DIR)IS1000_SYSLIST.C,\ + $(IS1000_DIR)VAX4XX_RZ94.C,$(IS1000_DIR)VAX_XS.C,\ + $(IS1000_DIR)VAX_WATCH.C +.IFDEF ALPHA_OR_IA64 +IS1000_OPTIONS = /INCL=($(SIMH_DIR),$(IS1000_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"IS_1000=1") +IS1000_SIMH_LIB = $(SIMH_LIB64) +.ELSE +IS1000_OPTIONS = /INCL=($(SIMH_DIR),$(IS1000_DIR),$(PDP11_DIR)$(PCAP_INC))\ + /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"IS_1000=1") +IS1000_SIMH_LIB = $(SIMH_LIB) +.ENDIF + # Digital Equipment VAX610 (MicroVAX I) Simulator Definitions. # VAX610_DIR = SYS$DISK:[.VAX] @@ -1003,6 +1336,10 @@ I7094_OPTIONS = /INCL=($(SIMH_DIR),$(I7094_DIR))/DEF=($(CC_DEFS)) ALL : ALTAIR ALTAIRZ80 CDC1700 ECLIPSE GRI LGP H316 HP2100 HP3000 I1401 I1620 \ IBM1130 ID16 ID32 NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP10 PDP11 PDP15 S3 \ VAX MICROVAX3900 MICROVAX1 RTVAX1000 MICROVAX2 VAX730 VAX750 VAX780 \ + MICROVAX2000 INFOSERVER100 INFOSERVER150VTX \ + MICROVAX3100 MICROVAX3100E VAXSTATION3100M30 \ + VAXSTATION3100M38 VAXSTATION3100M76 VAXSTATION4000M60 \ + VAXSTATION3100M80 VAXSTATION4000VLC INFOSERVER1000 \ VAX8200 VAX8600 SDS I7094 SWTP6800MP-A SWTP6800MP-A2 SSEM BESM6 B5500 $! No further actions necessary .ELSE @@ -1011,8 +1348,11 @@ ALL : ALTAIR ALTAIRZ80 CDC1700 ECLIPSE GRI LGP H316 HP2100 HP3000 I1401 I1620 \ # ALL : ALTAIR GRI H316 HP2100 I1401 I1620 IBM1130 ID16 ID32 \ NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP11 PDP15 S3 \ - VAX MICROVAX3900 MICROVAX1 RTVAX1000 MICROVAX2 VAX730 VAX750 VAX780 \ - VAX8200 VAX8600 SDS SWTP6800MP-A SWTP6800MP-A2 SSEM + VAX MICROVAX3900 MICROVAX1 RTVAX1000 MICROVAX2 VAX730 VAX750 VAX780 VAX8600 \ + MICROVAX2000 INFOSERVER100 INFOSERVER150VTX \ + MICROVAX3100 MICROVAX3100E VAXSTATION3100M30 \ + VAXSTATION3100M38 VAXSTATION3100M76 VAXSTATION4000M60 \ + VAXSTATION3100M80 VAXSTATION4000VLC INFOSERVER1000 $! No further actions necessary .ENDIF @@ -1568,6 +1908,270 @@ $(VAX_LIB2) : $(VAX_SOURCE2) $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* +$(VAX410_LIB1) : $(VAX410_SOURCE1) + $! + $! Building The $(VAX410_LIB1) Library. + $! + $ $(CC)$(VAX410_OPTIONS)/OBJ=$(VAX410_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX410_LIB2) : $(VAX410_SOURCE2) + $! + $! Building The $(VAX410_LIB2) Library. + $! + $ $(CC)$(VAX410_OPTIONS)/OBJ=$(VAX410_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX411_LIB1) : $(VAX411_SOURCE1) + $! + $! Building The $(VAX411_LIB1) Library. + $! + $ $(CC)$(VAX411_OPTIONS)/OBJ=$(VAX411_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX411_LIB2) : $(VAX411_SOURCE2) + $! + $! Building The $(VAX411_LIB2) Library. + $! + $ $(CC)$(VAX411_OPTIONS)/OBJ=$(VAX411_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX412_LIB1) : $(VAX412_SOURCE1) + $! + $! Building The $(VAX412_LIB1) Library. + $! + $ $(CC)$(VAX412_OPTIONS)/OBJ=$(VAX412_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX412_LIB2) : $(VAX412_SOURCE2) + $! + $! Building The $(VAX412_LIB2) Library. + $! + $ $(CC)$(VAX412_OPTIONS)/OBJ=$(VAX412_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX41A_LIB1) : $(VAX41A_SOURCE1) + $! + $! Building The $(VAX41A_LIB1) Library. + $! + $ $(CC)$(VAX41A_OPTIONS)/OBJ=$(VAX41A_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX41A_LIB2) : $(VAX41A_SOURCE2) + $! + $! Building The $(VAX41A_LIB2) Library. + $! + $ $(CC)$(VAX41A_OPTIONS)/OBJ=$(VAX41A_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX41D_LIB1) : $(VAX41D_SOURCE1) + $! + $! Building The $(VAX41D_LIB1) Library. + $! + $ $(CC)$(VAX41D_OPTIONS)/OBJ=$(VAX41D_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX41D_LIB2) : $(VAX41D_SOURCE2) + $! + $! Building The $(VAX41D_LIB2) Library. + $! + $ $(CC)$(VAX41D_OPTIONS)/OBJ=$(VAX41D_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX42A_LIB1) : $(VAX42A_SOURCE1) + $! + $! Building The $(VAX42A_LIB1) Library. + $! + $ $(CC)$(VAX42A_OPTIONS)/OBJ=$(VAX42A_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX42A_LIB2) : $(VAX42A_SOURCE2) + $! + $! Building The $(VAX42A_LIB2) Library. + $! + $ $(CC)$(VAX42A_OPTIONS)/OBJ=$(VAX42A_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX42B_LIB1) : $(VAX42B_SOURCE1) + $! + $! Building The $(VAX42B_LIB1) Library. + $! + $ $(CC)$(VAX42B_OPTIONS)/OBJ=$(VAX42B_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX42B_LIB2) : $(VAX42B_SOURCE2) + $! + $! Building The $(VAX42B_LIB2) Library. + $! + $ $(CC)$(VAX42B_OPTIONS)/OBJ=$(VAX42B_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX43_LIB1) : $(VAX43_SOURCE1) + $! + $! Building The $(VAX43_LIB1) Library. + $! + $ $(CC)$(VAX43_OPTIONS)/OBJ=$(VAX43_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX43_LIB2) : $(VAX43_SOURCE2) + $! + $! Building The $(VAX43_LIB2) Library. + $! + $ $(CC)$(VAX43_OPTIONS)/OBJ=$(VAX43_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX46_LIB1) : $(VAX46_SOURCE1) + $! + $! Building The $(VAX46_LIB1) Library. + $! + $ $(CC)$(VAX46_OPTIONS)/OBJ=$(VAX46_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX46_LIB2) : $(VAX46_SOURCE2) + $! + $! Building The $(VAX46_LIB2) Library. + $! + $ $(CC)$(VAX46_OPTIONS)/OBJ=$(VAX46_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX47_LIB1) : $(VAX47_SOURCE1) + $! + $! Building The $(VAX47_LIB1) Library. + $! + $ $(CC)$(VAX47_OPTIONS)/OBJ=$(VAX47_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX47_LIB2) : $(VAX47_SOURCE2) + $! + $! Building The $(VAX47_LIB2) Library. + $! + $ $(CC)$(VAX47_OPTIONS)/OBJ=$(VAX47_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX48_LIB1) : $(VAX48_SOURCE1) + $! + $! Building The $(VAX48_LIB1) Library. + $! + $ $(CC)$(VAX48_OPTIONS)/OBJ=$(VAX48_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(VAX48_LIB2) : $(VAX48_SOURCE2) + $! + $! Building The $(VAX48_LIB2) Library. + $! + $ $(CC)$(VAX48_OPTIONS)/OBJ=$(VAX48_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(IS1000_LIB1) : $(IS1000_SOURCE1) + $! + $! Building The $(IS1000_LIB1) Library. + $! + $ $(CC)$(IS1000_OPTIONS)/OBJ=$(IS1000_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +$(IS1000_LIB2) : $(IS1000_SOURCE2) + $! + $! Building The $(IS1000_LIB2) Library. + $! + $ $(CC)$(IS1000_OPTIONS)/OBJ=$(IS1000_DIR) - + /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST) + $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN - + LIBRARY/CREATE $(MMS$TARGET) + $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + $(VAX610_LIB1) : $(VAX610_SOURCE1) $! $! Building The $(VAX610_LIB1) Library. @@ -2271,6 +2875,186 @@ $(BIN_DIR)MICROVAX3900-$(ARCH).EXE : $(SIMH_MAIN) $(VAX_SIMH_LIB) $(PCAP_LIBD) $ $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* $ COPY $(BIN_DIR)MICROVAX3900-$(ARCH).EXE $(BIN_DIR)VAX-$(ARCH).EXE +MICROVAX2000 : $(BIN_DIR)MICROVAX2000-$(ARCH).EXE + $! MICROVAX2000 done + +$(BIN_DIR)MICROVAX2000-$(ARCH).EXE : $(SIMH_MAIN) $(VAX410_SIMH_LIB) $(PCAP_LIBD) $(VAX410_LIB1) $(VAX410_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)MICROVAX2000-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX410_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)MICROVAX2000-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX410_LIB1)/LIBRARY,$(VAX410_LIB2)/LIBRARY,- + $(VAX410_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +INFOSERVER100 : $(BIN_DIR)INFOSERVER100-$(ARCH).EXE + $! INFOSERVER100 done + +$(BIN_DIR)INFOSERVER100-$(ARCH).EXE : $(SIMH_MAIN) $(VAX411_SIMH_LIB) $(PCAP_LIBD) $(VAX411_LIB1) $(VAX411_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)INFOSERVER100-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX411_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)INFOSERVER100-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX411_LIB1)/LIBRARY,$(VAX411_LIB2)/LIBRARY,- + $(VAX411_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +INFOSERVER150VTX : $(BIN_DIR)INFOSERVER150VTX-$(ARCH).EXE + $! INFOSERVER150VTX done + +$(BIN_DIR)INFOSERVER150VTX-$(ARCH).EXE : $(SIMH_MAIN) $(VAX412_SIMH_LIB) $(PCAP_LIBD) $(VAX412_LIB1) $(VAX412_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)INFOSERVER150VTX-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX412_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)INFOSERVER150VTX-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX412_LIB1)/LIBRARY,$(VAX412_LIB2)/LIBRARY,- + $(VAX412_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +MICROVAX3100 : $(BIN_DIR)MICROVAX3100-$(ARCH).EXE + $! MICROVAX3100 done + +$(BIN_DIR)MICROVAX3100-$(ARCH).EXE : $(SIMH_MAIN) $(VAX41A_SIMH_LIB) $(PCAP_LIBD) $(VAX41A_LIB1) $(VAX41A_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)MICROVAX3100-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX41A_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)MICROVAX3100-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX41A_LIB1)/LIBRARY,$(VAX41A_LIB2)/LIBRARY,- + $(VAX41A_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +MICROVAX3100E : $(BIN_DIR)MICROVAX3100E-$(ARCH).EXE + $! MICROVAX3100E done + +$(BIN_DIR)MICROVAX3100E-$(ARCH).EXE : $(SIMH_MAIN) $(VAX41D_SIMH_LIB) $(PCAP_LIBD) $(VAX41D_LIB1) $(VAX41D_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)MICROVAX3100E-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX41D_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)MICROVAX3100E-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX41D_LIB1)/LIBRARY,$(VAX41D_LIB2)/LIBRARY,- + $(VAX41D_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAXSTATION3100M30 : $(BIN_DIR)VAXSTATION3100M30-$(ARCH).EXE + $! VAXSTATION3100M30 done + +$(BIN_DIR)VAXSTATION3100M30-$(ARCH).EXE : $(SIMH_MAIN) $(VAX42A_SIMH_LIB) $(PCAP_LIBD) $(VAX42A_LIB1) $(VAX42A_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAXSTATION3100M30-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX42A_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAXSTATION3100M30-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX42A_LIB1)/LIBRARY,$(VAX42A_LIB2)/LIBRARY,- + $(VAX42A_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAXSTATION3100M38 : $(BIN_DIR)VAXSTATION3100M38-$(ARCH).EXE + $! VAXSTATION3100M38 done + +$(BIN_DIR)VAXSTATION3100M38-$(ARCH).EXE : $(SIMH_MAIN) $(VAX42B_SIMH_LIB) $(PCAP_LIBD) $(VAX42B_LIB1) $(VAX42B_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAXSTATION3100M38-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX42B_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAXSTATION3100M38-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX42B_LIB1)/LIBRARY,$(VAX42B_LIB2)/LIBRARY,- + $(VAX42B_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAXSTATION3100M76 : $(BIN_DIR)VAXSTATION3100M76-$(ARCH).EXE + $! VAXSTATION3100M76 done + +$(BIN_DIR)VAXSTATION3100M76-$(ARCH).EXE : $(SIMH_MAIN) $(VAX43_SIMH_LIB) $(PCAP_LIBD) $(VAX43_LIB1) $(VAX43_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAXSTATION3100M76-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX43_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAXSTATION3100M76-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX43_LIB1)/LIBRARY,$(VAX43_LIB2)/LIBRARY,- + $(VAX43_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAXSTATION4000M60 : $(BIN_DIR)VAXSTATION4000M60-$(ARCH).EXE + $! VAXSTATION4000M60 done + +$(BIN_DIR)VAXSTATION4000M60-$(ARCH).EXE : $(SIMH_MAIN) $(VAX46_SIMH_LIB) $(PCAP_LIBD) $(VAX46_LIB1) $(VAX46_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAXSTATION4000M60-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX46_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAXSTATION4000M60-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX46_LIB1)/LIBRARY,$(VAX46_LIB2)/LIBRARY,- + $(VAX46_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAXSTATION3100M80 : $(BIN_DIR)VAXSTATION3100M80-$(ARCH).EXE + $! VAXSTATION3100M80 done + +$(BIN_DIR)VAXSTATION3100M80-$(ARCH).EXE : $(SIMH_MAIN) $(VAX47_SIMH_LIB) $(PCAP_LIBD) $(VAX47_LIB1) $(VAX47_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAXSTATION3100M80-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX47_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAXSTATION3100M80-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX47_LIB1)/LIBRARY,$(VAX47_LIB2)/LIBRARY,- + $(VAX47_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +VAXSTATION4000VLC : $(BIN_DIR)VAXSTATION4000VLC-$(ARCH).EXE + $! VAXSTATION4000VLC done + +$(BIN_DIR)VAXSTATION4000VLC-$(ARCH).EXE : $(SIMH_MAIN) $(VAX48_SIMH_LIB) $(PCAP_LIBD) $(VAX48_LIB1) $(VAX48_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)VAXSTATION4000VLC-$(ARCH).EXE Simulator. + $! + $ $(CC)$(VAX48_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)VAXSTATION4000VLC-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(VAX48_LIB1)/LIBRARY,$(VAX48_LIB2)/LIBRARY,- + $(VAX48_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + +INFOSERVER1000 : $(BIN_DIR)INFOSERVER1000-$(ARCH).EXE + $! INFOSERVER1000 done + +$(BIN_DIR)INFOSERVER1000-$(ARCH).EXE : $(SIMH_MAIN) $(IS1000_SIMH_LIB) $(PCAP_LIBD) $(IS1000_LIB1) $(IS1000_LIB2) $(PCAP_EXECLET) + $! + $! Building The $(BIN_DIR)INFOSERVER1000-$(ARCH).EXE Simulator. + $! + $ $(CC)$(IS1000_OPTIONS)/OBJ=$(BLD_DIR) SCP.C + $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)- + /EXE=$(BIN_DIR)INFOSERVER1000-$(ARCH).EXE - + $(BLD_DIR)SCP.OBJ,- + $(IS1000_LIB1)/LIBRARY,$(IS1000_LIB2)/LIBRARY,- + $(IS1000_SIMH_LIB)/LIBRARY$(PCAP_LIBR) + $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;* + MICROVAX1 : $(BIN_DIR)MICROVAX1-$(ARCH).EXE $! MICROVAX1 done diff --git a/makefile b/makefile index 4f39f406..3fa53a5b 100644 --- a/makefile +++ b/makefile @@ -99,7 +99,7 @@ endif BUILD_SINGLE := $(MAKECMDGOALS) $(BLANK_SUFFIX) BUILD_MULTIPLE_VERB = is # building the pdp1, pdp11, tx-0, or any microvax simulator could use video support -ifneq (,$(or $(findstring XXpdp1XX,$(addsuffix XX,$(addprefix XX,$(MAKECMDGOALS)))),$(findstring pdp11,$(MAKECMDGOALS)),$(findstring tx-0,$(MAKECMDGOALS)),$(findstring microvax1,$(MAKECMDGOALS)),$(findstring microvax2,$(MAKECMDGOALS)),$(findstring microvax3900,$(MAKECMDGOALS)),$(findstring XXvaxXX,$(addsuffix XX,$(addprefix XX,$(MAKECMDGOALS)))))) +ifneq (,$(or $(findstring XXpdp1XX,$(addsuffix XX,$(addprefix XX,$(MAKECMDGOALS)))),$(findstring pdp11,$(MAKECMDGOALS)),$(findstring tx-0,$(MAKECMDGOALS)),$(findstring microvax1,$(MAKECMDGOALS)),$(findstring microvax2,$(MAKECMDGOALS)),$(findstring microvax3900,$(MAKECMDGOALS)),$(findstring vax41,$(MAKECMDGOALS)),$(findstring vax42,$(MAKECMDGOALS)),$(findstring microvax3100m76,$(MAKECMDGOALS)),$(findstring XXvaxXX,$(addsuffix XX,$(addprefix XX,$(MAKECMDGOALS)))))) VIDEO_USEFUL = true endif # building the besm6 needs both video support and fontfile support @@ -1222,7 +1222,9 @@ SIM = scp.c sim_console.c sim_fio.c sim_timer.c sim_sock.c \ sim_video.c sim_imd.c sim_card.c DISPLAYD = display - + +SCSI = sim_scsi.c + # # Emulator source files and compile time options # @@ -1308,6 +1310,65 @@ VAX = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c ${VAXD}/vax_io.c \ VAX_OPT = -DVM_VAX -DUSE_INT64 -DUSE_ADDR64 -DUSE_SIM_VIDEO -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} ${VIDEO_CCDEFS} ${VIDEO_LDFLAGS} +VAX410 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax_watch.c ${VAXD}/vax_nar.c ${VAXD}/vax4xx_stddev.c \ + ${VAXD}/vax410_sysdev.c ${VAXD}/vax410_syslist.c ${VAXD}/vax4xx_dz.c \ + ${VAXD}/vax4xx_rd.c ${VAXD}/vax4xx_rz80.c ${VAXD}/vax_xs.c \ + ${VAXD}/vax4xx_va.c ${VAXD}/vax4xx_vc.c ${VAXD}/vax_lk.c \ + ${VAXD}/vax_vs.c ${VAXD}/vax_gpx.c +VAX410_OPT = -DVM_VAX -DVAX_410 -DUSE_INT64 -DUSE_ADDR64 -DUSE_SIM_VIDEO -I ${VAXD} ${NETWORK_OPT} ${VIDEO_CCDEFS} ${VIDEO_LDFLAGS} + + +VAX420 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax_watch.c ${VAXD}/vax_nar.c ${VAXD}/vax4xx_stddev.c \ + ${VAXD}/vax420_sysdev.c ${VAXD}/vax420_syslist.c ${VAXD}/vax4xx_dz.c \ + ${VAXD}/vax4xx_rd.c ${VAXD}/vax4xx_rz80.c ${VAXD}/vax_xs.c \ + ${VAXD}/vax4xx_va.c ${VAXD}/vax4xx_vc.c ${VAXD}/vax4xx_ve.c \ + ${VAXD}/vax_lk.c ${VAXD}/vax_vs.c ${VAXD}/vax_gpx.c +VAX420_OPT = -DVM_VAX -DVAX_420 -DUSE_INT64 -DUSE_ADDR64 -DUSE_SIM_VIDEO -I ${VAXD} ${NETWORK_OPT} ${VIDEO_CCDEFS} ${VIDEO_LDFLAGS} +VAX411_OPT = ${VAX420_OPT} -DVAX_411 +VAX412_OPT = ${VAX420_OPT} -DVAX_412 +VAX41A_OPT = ${VAX420_OPT} -DVAX_41A +VAX41D_OPT = ${VAX420_OPT} -DVAX_41D +VAX42A_OPT = ${VAX420_OPT} -DVAX_42A +VAX42B_OPT = ${VAX420_OPT} -DVAX_42B + + +VAX43 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax_watch.c ${VAXD}/vax_nar.c ${VAXD}/vax4xx_stddev.c \ + ${VAXD}/vax43_sysdev.c ${VAXD}/vax43_syslist.c ${VAXD}/vax4xx_dz.c \ + ${VAXD}/vax4xx_rz80.c ${VAXD}/vax_xs.c ${VAXD}/vax4xx_vc.c \ + ${VAXD}/vax4xx_ve.c ${VAXD}/vax_lk.c ${VAXD}/vax_vs.c +VAX43_OPT = -DVM_VAX -DVAX_43 -DUSE_INT64 -DUSE_ADDR64 -DUSE_SIM_VIDEO -I ${VAXD} ${NETWORK_OPT} ${VIDEO_CCDEFS} ${VIDEO_LDFLAGS} + + +VAX440 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax_watch.c ${VAXD}/vax_nar.c ${VAXD}/vax4xx_stddev.c \ + ${VAXD}/vax440_sysdev.c ${VAXD}/vax440_syslist.c ${VAXD}/vax4xx_dz.c \ + ${VAXD}/vax_xs.c ${VAXD}/vax_lk.c ${VAXD}/vax_vs.c ${VAXD}/vax4xx_rz94.c +VAX440_OPT = -DVM_VAX -DVAX_440 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} ${NETWORK_OPT} +VAX46_OPT = ${VAX440_OPT} -DVAX_46 +VAX47_OPT = ${VAX440_OPT} -DVAX_47 +VAX48_OPT = ${VAX440_OPT} -DVAX_48 + + +IS1000 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ + ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ + ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ + ${VAXD}/vax_watch.c ${VAXD}/vax_nar.c ${VAXD}/vax_xs.c \ + ${VAXD}/vax4xx_rz94.c ${VAXD}/vax4nn_stddev.c \ + ${VAXD}/is1000_sysdev.c ${VAXD}/is1000_syslist.c +IS1000_OPT = -DVM_VAX -DIS_1000 -DUSE_INT64 -DUSE_ADDR64 -I ${VAXD} ${NETWORK_OPT} + + VAX610 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ @@ -1320,6 +1381,7 @@ VAX610 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ ${PDP11D}/pdp11_td.c ${PDP11D}/pdp11_io_lib.c VAX610_OPT = -DVM_VAX -DVAX_610 -DUSE_INT64 -DUSE_ADDR64 -DUSE_SIM_VIDEO -I ${VAXD} -I ${PDP11D} ${NETWORK_OPT} ${VIDEO_CCDEFS} ${VIDEO_LDFLAGS} + VAX630 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ @@ -1382,21 +1444,6 @@ VAX780 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ VAX780_OPT = -DVM_VAX -DVAX_780 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} -VAX8200 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ - ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ - ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ - ${VAXD}/vax_watch.c ${VAXD}/vax820_stddev.c ${VAXD}/vax820_bi.c \ - ${VAXD}/vax820_mem.c ${VAXD}/vax820_uba.c ${VAXD}/vax820_ka.c \ - ${VAXD}/vax820_syslist.c \ - ${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \ - ${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \ - ${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \ - ${PDP11D}/pdp11_hk.c ${PDP11D}/pdp11_vh.c ${PDP11D}/pdp11_dmc.c \ - ${PDP11D}/pdp11_td.c ${PDP11D}/pdp11_tc.c ${PDP11D}/pdp11_rk.c \ - ${PDP11D}/pdp11_io_lib.c ${PDP11D}/pdp11_ch.c -VAX8200_OPT = -DVM_VAX -DVAX_820 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT} - - VAX8600 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \ ${VAXD}/vax_cis.c ${VAXD}/vax_octa.c ${VAXD}/vax_cmode.c \ ${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c ${VAXD}/vax_syscm.c \ @@ -1864,8 +1911,10 @@ ATT3B2_OPT = -DUSE_INT64 -DUSE_ADDR64 -I ${ATT3B2D} ${NETWORK_OPT} # Build everything (not the unsupported/incomplete or experimental simulators) # ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 \ - vax microvax3900 microvax1 rtvax1000 microvax2 vax730 vax750 vax780 \ - vax8200 vax8600 \ + vax microvax3900 microvax1 rtvax1000 microvax2 vax730 vax750 vax780 vax8600 \ + microvax2000 infoserver100 infoserver150vtx microvax3100 microvax3100e \ + vaxstation3100m30 vaxstation3100m38 microvax3100m76 vaxstation4000m60 \ + microvax3100m80 vaxstation4000vlc infoserver1000 \ nova eclipse hp2100 hp3000 i1401 i1620 s3 altair altairz80 gri \ i7094 ibm1130 id16 id32 sds lgp h316 cdc1700 \ swtp6800mp-a swtp6800mp-a2 tx-0 ssem b5500 isys8010 isys8020 \ @@ -1901,7 +1950,7 @@ ifeq ($(WIN32),) endif else $(@D)\$(@F) - del $(@D)\$(@F) +# del $(@D)\$(@F) endif # @@ -2004,6 +2053,78 @@ ifneq (,$(call find_test,$(VAXD),vax-diag)) $@ $(call find_test,$(VAXD),vax-diag) $(TEST_ARG) endif +microvax2000 : ${BIN}BuildROMs${EXE} ${BIN}microvax2000${EXE} + +${BIN}microvax2000${EXE} : ${VAX410} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX410} ${SCSI} ${SIM} ${VAX410_OPT} -o $@ ${LDFLAGS} + +infoserver100 : ${BIN}BuildROMs${EXE} ${BIN}infoserver100${EXE} + +${BIN}infoserver100${EXE} : ${VAX420} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX420} ${SCSI} ${SIM} ${VAX411_OPT} -o $@ ${LDFLAGS} + +infoserver150vtx : ${BIN}BuildROMs${EXE} ${BIN}infoserver150vtx${EXE} + +${BIN}infoserver150vtx${EXE} : ${VAX420} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX420} ${SCSI} ${SIM} ${VAX412_OPT} -o $@ ${LDFLAGS} + +microvax3100 : ${BIN}BuildROMs${EXE} ${BIN}microvax3100${EXE} + +${BIN}microvax3100${EXE} : ${VAX420} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX420} ${SCSI} ${SIM} ${VAX41A_OPT} -o $@ ${LDFLAGS} + +microvax3100e : ${BIN}BuildROMs${EXE} ${BIN}microvax3100e${EXE} + +${BIN}microvax3100e${EXE} : ${VAX420} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX420} ${SCSI} ${SIM} ${VAX41D_OPT} -o $@ ${LDFLAGS} + +vaxstation3100m30 : ${BIN}BuildROMs${EXE} ${BIN}vaxstation3100m30${EXE} + +${BIN}vaxstation3100m30${EXE} : ${VAX420} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX420} ${SCSI} ${SIM} ${VAX42A_OPT} -o $@ ${LDFLAGS} + +vaxstation3100m38 : ${BIN}BuildROMs${EXE} ${BIN}vaxstation3100m38${EXE} + +${BIN}vaxstation3100m38${EXE} : ${VAX420} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX420} ${SCSI} ${SIM} ${VAX42B_OPT} -o $@ ${LDFLAGS} + +microvax3100m76 : ${BIN}BuildROMs${EXE} ${BIN}microvax3100m76${EXE} + +${BIN}microvax3100m76${EXE} : ${VAX43} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX43} ${SCSI} ${SIM} ${VAX43_OPT} -o $@ ${LDFLAGS} + +vaxstation4000m60 : ${BIN}BuildROMs${EXE} ${BIN}vaxstation4000m60${EXE} + +${BIN}vaxstation4000m60${EXE} : ${VAX440} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX440} ${SCSI} ${SIM} ${VAX46_OPT} -o $@ ${LDFLAGS} + +microvax3100m80 : ${BIN}BuildROMs${EXE} ${BIN}microvax3100m80${EXE} + +${BIN}microvax3100m80${EXE} : ${VAX440} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX440} ${SCSI} ${SIM} ${VAX47_OPT} -o $@ ${LDFLAGS} + +vaxstation4000vlc : ${BIN}BuildROMs${EXE} ${BIN}vaxstation4000vlc${EXE} + +${BIN}vaxstation4000vlc${EXE} : ${VAX440} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${VAX440} ${SCSI} ${SIM} ${VAX48_OPT} -o $@ ${LDFLAGS} + +infoserver1000 : ${BIN}BuildROMs${EXE} ${BIN}infoserver1000${EXE} + +${BIN}infoserver1000${EXE} : ${IS1000} ${SCSI} ${SIM} ${BUILD_ROMS} + ${MKDIRBIN} + ${CC} ${IS1000} ${SCSI} ${SIM} ${IS1000_OPT} -o $@ ${LDFLAGS} + microvax1 : ${BIN}BuildROMs${EXE} ${BIN}microvax1${EXE} ${BIN}microvax1${EXE} : ${VAX610} ${SIM} ${BUILD_ROMS} @@ -2058,15 +2179,6 @@ ifneq (,$(call find_test,$(VAXD),vax-diag)) $@ $(call find_test,$(VAXD),vax-diag) $(TEST_ARG) endif -vax8200 : ${BIN}vax8200${EXE} - -${BIN}vax8200${EXE} : ${VAX8200} ${SIM} ${BUILD_ROMS} - ${MKDIRBIN} - ${CC} ${VAX8200} ${SIM} ${VAX8200_OPT} $(CC_OUTSPEC) ${LDFLAGS} -ifneq (,$(call find_test,$(VAXD),vax-diag)) - $@ $(call find_test,$(VAXD),vax-diag) $(TEST_ARG) -endif - vax8600 : ${BIN}BuildROMs${EXE} ${BIN}vax8600${EXE} ${BIN}vax8600${EXE} : ${VAX8600} ${SIM} ${BUILD_ROMS} diff --git a/sim_BuildROMs.c b/sim_BuildROMs.c index fb654c68..ac991bb8 100644 --- a/sim_BuildROMs.c +++ b/sim_BuildROMs.c @@ -43,6 +43,25 @@ struct ROM_File_Descriptor { {"VAX/ka620.bin", "VAX/vax_ka620_bin.h", 65536, 0xFF7F930F, "vax_ka620_bin"}, {"VAX/ka630.bin", "VAX/vax_ka630_bin.h", 65536, 0xFF7F73EF, "vax_ka630_bin"}, {"VAX/ka610.bin", "VAX/vax_ka610_bin.h", 16384, 0xFFEF3312, "vax_ka610_bin"}, + {"VAX/ka410.bin", "VAX/vax_ka410_bin.h", 262144, 0xFEDA0B61, "vax_ka410_bin"}, + {"VAX/ka411.bin", "VAX/vax_ka411_bin.h", 262144, 0xFECB7EE3, "vax_ka411_bin"}, + {"VAX/ka412.bin", "VAX/vax_ka412_bin.h", 262144, 0xFED96BB4, "vax_ka412_bin"}, + {"VAX/ka41a.bin", "VAX/vax_ka41a_bin.h", 262144, 0xFECBAC7B, "vax_ka41a_bin"}, + {"VAX/ka41d.bin", "VAX/vax_ka41d_bin.h", 262144, 0xFECB8513, "vax_ka41d_bin"}, + {"VAX/ka42a.bin", "VAX/vax_ka42a_bin.h", 262144, 0xFED8967F, "vax_ka42a_bin"}, + {"VAX/ka42b.bin", "VAX/vax_ka42b_bin.h", 262144, 0xFECBB2EF, "vax_ka42b_bin"}, + {"VAX/ka43a.bin", "VAX/vax_ka43a_bin.h", 262144, 0xFEAB1DF9, "vax_ka43a_bin"}, + {"VAX/ka46a.bin", "VAX/vax_ka46a_bin.h", 262144, 0xFE8D094C, "vax_ka46a_bin"}, + {"VAX/ka47a.bin", "VAX/vax_ka47a_bin.h", 262144, 0xFE8D8DDA, "vax_ka47a_bin"}, + {"VAX/ka48a.bin", "VAX/vax_ka48a_bin.h", 262144, 0xFEBB854D, "vax_ka48a_bin"}, + {"VAX/is1000.bin", "VAX/vax_is1000_bin.h", 524288, 0xFCBCD74A, "vax_is1000_bin"}, + {"VAX/ka410_xs.bin", "VAX/vax_ka410_xs_bin.h", 32768, 0xFFD8BD83, "vax_ka410_xs_bin"}, + {"VAX/ka420_rdrz.bin", "VAX/vax_ka420_rdrz_bin.h", 131072, 0xFF747E93, "vax_ka420_rdrz_bin"}, + {"VAX/ka420_rzrz.bin", "VAX/vax_ka420_rzrz_bin.h", 131072, 0xFF7A9A51, "vax_ka420_rzrz_bin"}, + {"VAX/ka4xx_4pln.bin", "VAX/vax_ka4xx_4pln_bin.h", 65536, 0xFF9CD286, "vax_ka4xx_4pln_bin"}, + {"VAX/ka4xx_8pln.bin", "VAX/vax_ka4xx_8pln_bin.h", 65536, 0xFFA2FF59, "vax_ka4xx_8pln_bin"}, + {"VAX/ka4xx_dz.bin", "VAX/vax_ka4xx_dz_bin.h", 32768, 0xFFD84C02, "vax_ka4xx_dz_bin"}, + {"VAX/ka4xx_spx.bin" , "VAX/vax_ka4xx_spx_bin.h", 131072, 0xFF765752, "vax_ka4xx_spx_bin"}, {"VAX/ka750_new.bin", "VAX/vax_ka750_bin_new.h", 1024, 0xFFFE7BE5, "vax_ka750_bin_new", "From ROM set: E40A9, E41A9, E42A9, E43A9 (Boots: A=DD, B=DB, C=DU"}, {"VAX/ka750_old.bin", "VAX/vax_ka750_bin_old.h", 1024, 0xFFFEBAA5, "vax_ka750_bin_old", "From ROM set: 990A9, 948A9, 906A9, 905A9 (Boots: A=DD, B=DM, C=DL, D=DU"}, {"VAX/vcb02.bin", "VAX/vax_vcb02_bin.h", 16384, 0xFFF1D2AD, "vax_vcb02_bin"}, diff --git a/sim_scsi.c b/sim_scsi.c new file mode 100644 index 00000000..93963689 --- /dev/null +++ b/sim_scsi.c @@ -0,0 +1,1577 @@ +/* sim_scsi.c: SCSI bus simulation + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. +*/ + +#include "sim_scsi.h" +#include "sim_disk.h" +#include "sim_tape.h" + +/* SCSI commands */ + +#define CMD_TESTRDY 0x00 /* test unit ready */ +#define CMD_INQUIRY 0x12 /* inquiry */ +#define CMD_REQSENSE 0x03 /* request sense */ +#define CMD_MODESEL6 0x15 /* mode select (6 bytes) */ +#define CMD_MODESEL10 0x55 /* mode select (10 bytes) */ +#define CMD_MODESENSE6 0x1A /* mode sense (6 bytes) */ +#define CMD_MODESENSE10 0x5A /* mode sense (10 bytes) */ +#define CMD_STARTSTOP 0x1B /* start/stop unit */ +#define CMD_PREVALLOW 0x1E /* prevent/allow medium removal */ +#define CMD_RDCAP 0x25 /* read capacity */ +#define CMD_READ6 0x08 /* read (6 bytes) */ +#define CMD_READ10 0x28 /* read (10 bytes) */ +#define CMD_RDLONG 0x3E /* read long */ +#define CMD_WRITE6 0x0A /* write (6 bytes) */ +#define CMD_WRITE10 0x2A /* write (10 bytes) */ +#define CMD_ERASE 0x19 /* erase */ +#define CMD_RESERVE 0x16 /* reserve unit */ +#define CMD_RELEASE 0x17 /* release unit */ +#define CMD_REWIND 0x01 /* rewind */ +#define CMD_SNDDIAG 0x1D /* send diagnostic */ +#define CMD_SPACE 0x11 /* space */ +#define CMD_WRFMARK 0x10 /* write filemarks */ + +/* SCSI status codes */ + +#define STS_OK 0 /* good */ +#define STS_CHK 2 /* check condition */ + +/* SCSI sense keys */ + +#define KEY_OK 0 /* no sense */ +#define KEY_NOTRDY 2 /* not ready */ +#define KEY_ILLREQ 5 /* illegal request */ +#define KEY_PROT 7 /* data protect */ +#define KEY_BLANK 8 /* blank check */ +#define KEY_M_ILI 0x20 /* incorrent length indicator */ + +/* Additional sense codes */ + +#define ASC_OK 0 /* no additional sense information */ +#define ASC_INVCOM 0x20 /* invalid command operation code */ +#define ASC_INVCDB 0x24 /* invalid field in cdb */ +#define ASC_NOMEDIA 0x3A /* media not present */ + +#define PUTL(b,x,v) b[x] = (v >> 24) & 0xFF; \ + b[x+1] = (v >> 16) & 0xFF; \ + b[x+2] = (v >> 8) & 0xFF; \ + b[x+3] = v & 0xFF +#define PUTW(b,x,v) b[x] = (v >> 8) & 0xFF; \ + b[x+1] = v & 0xFF +#define GETL(b,x) ((b[x] << 24) | \ + (b[x+1] << 16) | \ + (b[x+2] << 8) | \ + b[x+3]) +#define GETW(b,x) ((b[x] << 8)|b[x+1]) + +static const char *scsi_phases[] = { + "DATO", /* data out */ + "DATI", /* data in */ + "CMD", /* command */ + "STS", /* status */ + "", /* invalid*/ + "", /* invalid*/ + "MSGO", /* message out */ + "MSGI" /* message in */ + }; + +/* Arbitrate for control of the bus */ + +t_bool scsi_arbitrate (SCSI_BUS *bus, uint32 initiator) +{ +if (bus->initiator < 0) { /* bus free? */ + sim_debug (SCSI_DBG_BUS, bus->dptr, + "Initiator %d won arbitration\n", initiator); + bus->initiator = initiator; /* won arbitration */ + return TRUE; + } +sim_debug (SCSI_DBG_BUS, bus->dptr, + "Initiator %d lost arbitration\n", initiator); +return FALSE; /* lost arbitration */ +} + +/* Release control of the bus */ + +void scsi_release (SCSI_BUS *bus) +{ +if (bus->initiator < 0) /* already free? */ + return; +sim_debug (SCSI_DBG_BUS, bus->dptr, + "Initiator %d released bus\n", bus->initiator); +bus->phase = SCSI_DATO; /* bus free state */ +bus->initiator = -1; +bus->target = -1; +bus->buf_t = bus->buf_b = 0; +} + +/* Assert the attention signal */ + +void scsi_set_atn (SCSI_BUS *bus) +{ +sim_debug (SCSI_DBG_BUS, bus->dptr, + "Attention signal asserted\n"); +bus->atn = TRUE; /* assert ATN */ +if (bus->target != -1) /* target selected? */ + bus->phase = SCSI_MSGO; /* go to msg out phase */ +} + +/* Clear the attention signal */ + +void scsi_release_atn (SCSI_BUS *bus) +{ +sim_debug (SCSI_DBG_BUS, bus->dptr, + "Attention signal cleared\n"); +bus->atn = FALSE; /* release ATN */ +} + +/* Assert the request signal */ + +void scsi_set_req (SCSI_BUS *bus) +{ +if (bus->req == FALSE) { + sim_debug (SCSI_DBG_BUS, bus->dptr, + "Request signal asserted\n"); + bus->req = TRUE; /* assert REQ */ + } +} + +/* Clear the attention signal */ + +void scsi_release_req (SCSI_BUS *bus) +{ +if (bus->req == TRUE) { + sim_debug (SCSI_DBG_BUS, bus->dptr, + "Request signal cleared\n"); + bus->req = FALSE; /* release REQ */ + } +} + +void scsi_set_phase (SCSI_BUS *bus, uint32 phase) +{ +if (bus->phase != phase) { + sim_debug (SCSI_DBG_BUS, bus->dptr, + "Phase changed to %s\n", scsi_phases[phase]); + bus->phase = phase; + } +} + +/* Attempt to select a target device */ + +t_bool scsi_select (SCSI_BUS *bus, uint32 target) +{ +UNIT *uptr = bus->dev[target]; + +if (bus->initiator < 0) { + sim_debug (SCSI_DBG_BUS, bus->dptr, + "SCSI: Attempted to select a target without arbitration\n"); + return FALSE; + } +if (bus->target >= 0) { + sim_debug (SCSI_DBG_BUS, bus->dptr, + "SCSI: Attempted to select a target when a target is already selected\n"); + return FALSE; + } +if ((uptr->flags & UNIT_DIS) == 0) { /* unit enabled? */ + sim_debug (SCSI_DBG_BUS, bus->dptr, + "Select target %d%s\n", target, (bus->atn ? " with attention" : "")); + if (bus->atn) + scsi_set_phase (bus, SCSI_MSGO); /* message out */ + else + scsi_set_phase (bus, SCSI_CMD); /* command */ + bus->target = target; + scsi_set_req (bus); /* request data */ + return TRUE; + } +sim_debug (SCSI_DBG_BUS, bus->dptr, + "Select timeout for target %d\n", target); +scsi_release (bus); +return FALSE; +} + +/* Process a SCSI message */ + +uint32 scsi_message (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +uint32 used; + +if (data[0] & 0x80) { /* identify */ + bus->lun = (data[0] & 0xF); + sim_debug (SCSI_DBG_MSG, bus->dptr, + "Identify, LUN = %d\n", bus->lun); + scsi_set_req (bus); /* request data */ + used = 1; /* message length */ + } +else if (data[0] == 0x1) { /* extended message */ + if (len < 2) + return 0; /* need more */ + if (len < (data[1] + 2u)) + return 0; /* need more */ + sim_debug (SCSI_DBG_MSG, bus->dptr, + "Extended message\n"); + scsi_set_req (bus); /* request data */ + used = data[1] + 2; /* extended message length */ + } +else if (data[0] == 0x6) { /* abort */ + sim_debug (SCSI_DBG_MSG, bus->dptr, + "Abort\n"); + scsi_release (bus); /* disconnect */ + used = 1; + } +else if (data[0] == 0xc) { + sim_debug (SCSI_DBG_MSG, bus->dptr, + "Bus device reset\n"); + scsi_release (bus); /* disconnect */ + used = 1; + } +else { + sim_printf ("SCSI: Unknown Message %02X\n", data[0]); + used = len; /* discard all bytes */ + } +scsi_set_phase (bus, SCSI_CMD); /* command phase next */ +return used; +} + +/* Send status to the initiator immediately */ + +void scsi_status (SCSI_BUS *bus, uint32 sts, uint32 key, uint32 asc) +{ +bus->sense_key = key; +bus->sense_code = asc; +bus->buf[0] = sts; /* status code */ +bus->buf_b = 1; +scsi_set_phase (bus, SCSI_STS); /* status phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Send status to the initiator at the end of transaction */ + +void scsi_status_deferred (SCSI_BUS *bus, uint32 sts, uint32 key, uint32 asc) +{ +bus->status = sts; +bus->sense_key = key; +bus->sense_code = asc; +} + +/* Decode the command group to get the command length */ + +uint32 scsi_decode_group (uint8 data) +{ +uint32 group = (data >> 5) & 0x7; + +switch (group) { + case 0: /* 6 byte commands */ + return 6; + + case 1: /* 10 byte commands */ + case 2: + return 10; + + case 3: /* 12 byte commands */ + return 12; + + default: /* vendor specific or reserved */ + return 0; + } +} + +/* Translate sim_tape status to SCSI status */ + +void scsi_tape_status (SCSI_BUS *bus, t_stat st) +{ +switch (st) { + + case MTSE_OK: + scsi_status_deferred (bus, STS_OK, KEY_OK, ASC_OK); + break; + + case MTSE_TMK: + scsi_status_deferred (bus, STS_CHK, (KEY_OK | 0x80), ASC_OK); + bus->sense_qual = 1; /* filemark detected */ + break; + + case MTSE_RECE: /* record in error */ + case MTSE_INVRL: /* invalid rec lnt */ + case MTSE_IOERR: /* IO error */ + scsi_status_deferred (bus, STS_CHK, KEY_OK, ASC_OK); + break; + + case MTSE_FMT: + case MTSE_UNATT: + case MTSE_EOM: /* end of medium */ + scsi_status_deferred (bus, STS_CHK, (KEY_BLANK | 0x40), ASC_OK); + break; + + case MTSE_BOT: /* reverse into BOT */ + scsi_status_deferred (bus, STS_CHK, (KEY_OK | 0x40), ASC_OK); + break; + + case MTSE_WRP: /* write protect */ + scsi_status_deferred (bus, STS_CHK, KEY_PROT, ASC_OK); + break; + } + +return; +} + +/* Limit the transfer count to the allocation specified + by the SCSI command */ + +void scsi_check_alloc (SCSI_BUS *bus, uint32 alloc) +{ +if (bus->buf_b > alloc) /* check allocation */ + bus->buf_b = alloc; +} + +/* Command - Test Unit Ready */ + +void scsi_test_ready (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Test Unit Ready\n"); + +if (uptr->flags & UNIT_ATT) /* attached? */ + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); /* unit is ready */ +else + scsi_status (bus, STS_CHK, KEY_NOTRDY, ASC_NOMEDIA); /* no media present */ +} + +/* Command - Inquiry */ + +void scsi_inquiry (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Inquiry\n"); + +if ((bus->lun != 0) || (uptr->flags & UNIT_DIS)) { + memset (&bus->buf[0], 0, 36); /* no such device or lun */ + bus->buf[0] = 0x7f; + bus->buf_b += 36; +// scsi_status (bus, STS_CHK, KEY_ILLREQ, ASC_INVCOM); + } +else { + bus->buf[bus->buf_b++] = (dev->pqual << 5) | dev->devtype; /* device class */ +#if 0 + if (data[0] & 0x01) { /* vital product data */ + + switch (data[2]) { /* page code */ + + case 0x00: /* list of supported pages */ + bus->buf[bus->buf_b++] = 0x00; /* page code */ + bus->buf[bus->buf_b++] = 0x00; /* reserved */ + bus->buf[bus->buf_b++] = 0x02; /* page length */ + bus->buf[bus->buf_b++] = 0x00; /* page 0 is supported. */ + bus->buf[bus->buf_b++] = 0x80; /* page 0x80 is supported. */ + break; + + case 0x80: /* unit serial # page */ + bus->buf[bus->buf_b++] = 0x80; /* page code */ + bus->buf[bus->buf_b++] = 0x00; /* reserved */ + bus->buf[bus->buf_b++] = 4; /* serial number length */ + sprintf (&bus->buf[l], "%-4s", "1234"); + l += 4; + break; + + default: + sim_printf ("SCSI: Vital product data page %02x not implemented\n", data[2]); + } + } +#endif + if (dev->removeable) + bus->buf[bus->buf_b++] = 0x80; /* removeable */ + else + bus->buf[bus->buf_b++] = 0; /* fixed */ + bus->buf[bus->buf_b++] = dev->scsiver; /* versions */ + bus->buf[bus->buf_b++] = dev->scsiver; /* respose data format */ + bus->buf[bus->buf_b++] = 31; /* additional length */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + bus->buf[bus->buf_b++] = 0; + + sprintf ((char *)&bus->buf[bus->buf_b], "%-8s", dev->manufacturer); + bus->buf_b += 8; + sprintf ((char *)&bus->buf[bus->buf_b], "%-16s", dev->product); + bus->buf_b += 16; + sprintf ((char *)&bus->buf[bus->buf_b], "%-4s", dev->rev); + bus->buf_b += 4; + } + +scsi_check_alloc (bus, data[4]); /* check allocation */ +scsi_set_phase (bus, SCSI_DATI); /* data in phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Request Sense */ + +void scsi_req_sense (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +sim_debug (SCSI_DBG_CMD, bus->dptr, "Request Sense\n"); + +bus->buf[bus->buf_b++] = (0x70 | 0x80); /* current error, valid */ +bus->buf[bus->buf_b++] = 0; /* segment # */ +bus->buf[bus->buf_b++] = bus->sense_key; /* sense key */ +bus->buf[bus->buf_b++] = (bus->sense_info >> 24) & 0xFF; /* information */ +bus->buf[bus->buf_b++] = (bus->sense_info >> 16) & 0xFF; +bus->buf[bus->buf_b++] = (bus->sense_info >> 8) & 0xFF; +bus->buf[bus->buf_b++] = bus->sense_info & 0xFF; +bus->buf[bus->buf_b++] = 10; /* additional length */ +bus->buf[bus->buf_b++] = 0; /* cmd specific info */ +bus->buf[bus->buf_b++] = 0; +bus->buf[bus->buf_b++] = 0; +bus->buf[bus->buf_b++] = 0; +bus->buf[bus->buf_b++] = bus->sense_code; /* ASC */ +bus->buf[bus->buf_b++] = bus->sense_qual; /* ASCQ */ +bus->buf[bus->buf_b++] = 0; /* FRU code */ +bus->buf[bus->buf_b++] = 0; /* sense key specific */ +bus->buf[bus->buf_b++] = 0; +bus->buf[bus->buf_b++] = 0; + +bus->sense_key = 0; /* no sense */ +bus->sense_code = 0; /* no additional sense information */ +bus->sense_qual = 0; +bus->sense_info = 0; + +scsi_check_alloc (bus, data[4]); /* check allocation */ +scsi_set_phase (bus, SCSI_DATI); /* data in phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Mode Select (6 byte command) */ + +void scsi_mode_sel6 (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +if (bus->phase == SCSI_CMD) { + sim_debug (SCSI_DBG_CMD, bus->dptr, "Mode Select(6) - CMD\n"); + memcpy (&bus->cmd[0], &data[0], 6); + bus->buf_b = bus->cmd[4]; + scsi_set_phase (bus, SCSI_DATO); /* data out phase next */ + scsi_set_req (bus); /* request data */ + } +else if (bus->phase == SCSI_DATO) { + sim_debug (SCSI_DBG_CMD, bus->dptr, "Mode Select(6) - DATO\n"); + /* Not currently implemented so just return + good status for now */ + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); + } +} + +/* Command - Mode Select (10 byte command) */ + +void scsi_mode_sel10 (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +if (bus->phase == SCSI_CMD) { + sim_debug (SCSI_DBG_CMD, bus->dptr, "Mode Select(10) - CMD\n"); + memcpy (&bus->cmd[0], &data[0], 10); + bus->buf_b = GETW (data, 7); + scsi_set_phase (bus, SCSI_DATO); /* data out phase next */ + scsi_set_req (bus); /* request data */ + } +else if (bus->phase == SCSI_DATO) { + sim_debug (SCSI_DBG_CMD, bus->dptr, "Mode Select(6) - DATO\n"); + /* Not currently implemented so just return + good status for now */ + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); + } +} + +/* Mode Sense common fields */ + +void scsi_mode_sense (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +uint32 pc, pctl; + +pc = data[2] & 0x3F; /* page code */ +pctl = (data[2] >> 6) & 0x3F; /* page control */ + +bus->buf[bus->buf_b++] = 0x00; /* density code */ +bus->buf[bus->buf_b++] = ((uptr->capac - 1) >> 16) & 0xFF; /* # blocks (23:16) */ +bus->buf[bus->buf_b++] = ((uptr->capac - 1) >> 8) & 0xFF; /* # blocks (15:8) */ +bus->buf[bus->buf_b++] = (uptr->capac - 1) & 0xFF; /* # blocks (7:0) */ +bus->buf[bus->buf_b++] = 0x00; /* reserved */ +bus->buf[bus->buf_b++] = (dev->block_size >> 16) & 0xFF; +bus->buf[bus->buf_b++] = (dev->block_size >> 8) & 0xFF; +bus->buf[bus->buf_b++] = (dev->block_size >> 0) & 0xFF; + +if ((pc == 0x1) || (pc == 0x3F)) { + bus->buf[bus->buf_b++] = 0x1; /* R/W error recovery page */ + bus->buf[bus->buf_b++] = 0xA; /* page length */ + bus->buf[bus->buf_b++] = 0x26; /* TB, PER, DTE */ + bus->buf[bus->buf_b++] = 0x8; /* read retry count */ + bus->buf[bus->buf_b++] = 0x78; /* correction span */ + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0x8; /* write retry count */ + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + } +if ((pc == 0x2) || (pc == 0x3F)) { + bus->buf[bus->buf_b++] = 0x2; /* disconnect-reconnect page */ + bus->buf[bus->buf_b++] = 0xE; /* page length */ + bus->buf[bus->buf_b++] = 0x10; /* buffer full ratio */ + bus->buf[bus->buf_b++] = 0x10; /* buffer empty ratio */ + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + } +if ((pc == 0x3) || (pc == 0x3F)) { + bus->buf[bus->buf_b++] = 0x3; /* format device page */ + bus->buf[bus->buf_b++] = 0x16; /* page length */ + bus->buf[bus->buf_b++] = 0; /* tracks per zone (15:8) */ + bus->buf[bus->buf_b++] = 1; /* tracks per zone (7:0) */ + bus->buf[bus->buf_b++] = 0; /* alt sectors per zone (15:8) */ + bus->buf[bus->buf_b++] = 1; /* alt sectors per zone (7:0) */ + bus->buf[bus->buf_b++] = 0; /* alt tracks per zone (15:8) */ + bus->buf[bus->buf_b++] = 0; /* alt tracks per zone (7:0) */ + bus->buf[bus->buf_b++] = 0; /* alt tracks per unit (15:8) */ + bus->buf[bus->buf_b++] = 0; /* alt tracks per unit (7:0) */ + bus->buf[bus->buf_b++] = 0; /* sectors per track (15:8) */ + bus->buf[bus->buf_b++] = 0x21; /* sectors per track (7:0) */ + bus->buf[bus->buf_b++] = 0x2; /* bytes per sector (15:8) */ + bus->buf[bus->buf_b++] = 0; /* bytes per sector (7:0) */ + bus->buf[bus->buf_b++] = 0; /* interleave (15:8) */ + bus->buf[bus->buf_b++] = 0; /* interleave (7:0) */ + bus->buf[bus->buf_b++] = 0; /* track skew factor (15:8) */ + bus->buf[bus->buf_b++] = 0; /* track skew factor (7:0) */ + bus->buf[bus->buf_b++] = 0; /* cyl skew factor (15:8) */ + bus->buf[bus->buf_b++] = 0; /* cyl skew factor (7:0) */ + bus->buf[bus->buf_b++] = 0x40; /* flags */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + } +if ((pc == 0x4) || (pc == 0x3F)) { + bus->buf[bus->buf_b++] = 0x4; /* rigid disk geometry page */ + bus->buf[bus->buf_b++] = 0x16; /* page length */ + bus->buf[bus->buf_b++] = 0; /* # cyls (23:16) */ + bus->buf[bus->buf_b++] = 0x4; /* # cyls (15:8) */ + bus->buf[bus->buf_b++] = 0; /* # cyls (7:0) */ + bus->buf[bus->buf_b++] = 0x2; /* # heads */ + bus->buf[bus->buf_b++] = 0; /* start cyl for write precomp (23:16) */ + bus->buf[bus->buf_b++] = 0x4; /* start cyl for write precomp (15:8) */ + bus->buf[bus->buf_b++] = 0; /* start cyl for write precomp (7:0) */ + bus->buf[bus->buf_b++] = 0; /* start cyl for reduced write current (23:16) */ + bus->buf[bus->buf_b++] = 0x4; /* start cyl for reduced write current (15:8) */ + bus->buf[bus->buf_b++] = 0; /* start cyl for reduced write current (7:0) */ + bus->buf[bus->buf_b++] = 0; /* drive step rate (15:8) */ + bus->buf[bus->buf_b++] = 0x1; /* drive step rate (7:0) */ + bus->buf[bus->buf_b++] = 0; /* landing zone cyl (23:16) */ + bus->buf[bus->buf_b++] = 0x4; /* landing zone cyl (15:8) */ + bus->buf[bus->buf_b++] = 0; /* landing zone cyl (7:0) */ + bus->buf[bus->buf_b++] = 0; /* reserved, RPL */ + bus->buf[bus->buf_b++] = 0; /* rotational offet */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + bus->buf[bus->buf_b++] = 0x1C; /* medium rotation rate (15:8) */ + bus->buf[bus->buf_b++] = 0x20; /* medium rotation rate (7:0) */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + bus->buf[bus->buf_b++] = 0; /* reserved */ + } +if ((pc == 0xA) || (pc == 0x3F)) { + bus->buf[bus->buf_b++] = 0xA; /* control mode page */ + bus->buf[bus->buf_b++] = 0x6; /* page length */ + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + bus->buf[bus->buf_b++] = 0; + } +} + +/* Command - Mode Sense (6 byte command) */ + +void scsi_mode_sense6 (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +uint32 pc, pctl; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Mode Sense(6)\n"); + +pc = data[2] & 0x3F; /* page code */ +pctl = (data[2] >> 6) & 0x3F; /* page control */ + +if (pc == 0x8) { + scsi_status (bus, STS_CHK, KEY_ILLREQ, ASC_INVCDB); + return; + } + +memset (&bus->buf[0], 0, data[4]); /* allocation len */ +bus->buf[bus->buf_b++] = 0x0; /* mode data length */ +bus->buf[bus->buf_b++] = 0x0; /* medium type */ +if (dev->devtype == SCSI_CDROM) + bus->buf[bus->buf_b++] = 0x80; /* dev specific param */ +else + bus->buf[bus->buf_b++] = 0x0; /* dev specific param */ +bus->buf[bus->buf_b++] = 0x8; /* block descriptor len */ + +scsi_mode_sense (bus, data, len); /* get common data */ + +bus->buf[0] = bus->buf_b - 1; /* mode data length */ + +scsi_check_alloc (bus, data[4]); /* check allocation */ +scsi_set_phase (bus, SCSI_DATI); +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Mode Sense (10 byte command) */ + +void scsi_mode_sense10 (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +uint32 pc, pctl; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Mode Sense(10)\n"); + +pc = data[2] & 0x3F; /* page code */ +pctl = (data[2] >> 6) & 0x3F; /* page control */ + +if (pc == 0x8) { + scsi_status (bus, STS_CHK, KEY_ILLREQ, ASC_INVCDB); + return; + } + +memset (&bus->buf[0], 0, GETW (data, 7)); /* allocation len */ +bus->buf[bus->buf_b++] = 0x0; /* mode data length (15:8) */ +bus->buf[bus->buf_b++] = 0x0; /* mode data length (7:0) */ +bus->buf[bus->buf_b++] = 0x0; /* medium type */ +bus->buf[bus->buf_b++] = 0x0; /* dev specific param */ +bus->buf[bus->buf_b++] = 0x0; /* reserved */ +bus->buf[bus->buf_b++] = 0x0; /* reserved */ +bus->buf[bus->buf_b++] = 0x0; /* block descriptor len (15:8) */ +bus->buf[bus->buf_b++] = 0x8; /* block descriptor len (7:0) */ + +scsi_mode_sense (bus, data, len); /* get common data */ + +PUTW (bus->buf, 0, (bus->buf_b - 1)); /* mode data length */ + +scsi_check_alloc (bus, GETW (data, 7)); /* check allocation */ +scsi_set_phase (bus, SCSI_DATI); +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Start/Stop Unit */ + +void scsi_start_stop (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +sim_debug (SCSI_DBG_CMD, bus->dptr, "Start/Stop Unit\n"); +scsi_status (bus, STS_OK, KEY_OK, ASC_OK); +} + +/* Command - Prevent/Allow Medium Removal */ + +void scsi_prev_allow (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +sim_debug (SCSI_DBG_CMD, bus->dptr, "Prevent/Allow Medium Removal\n"); +scsi_status (bus, STS_OK, KEY_OK, ASC_OK); +} + +/* Command - Read Capacity */ + +void scsi_read_capacity (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Read Capacity, pmi = %d\n", (data[8] & 0x1)); + +if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */ + scsi_status (bus, STS_CHK, KEY_NOTRDY, ASC_NOMEDIA); + return; + } + +PUTL (bus->buf, 0, (uptr->capac - 1)); /* # blocks */ +PUTL (bus->buf, 4, dev->block_size); /* block size */ + +bus->buf_b = 8; +scsi_set_phase (bus, SCSI_DATI); /* data in phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Read (6 byte command), disk version */ + +void scsi_read6_disk (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +t_lba lba; +t_seccnt sects, sectsread; +t_stat r; + +lba = GETW (data, 2) | ((data[1] & 0x1F) << 16); +sects = data[4]; +if (sects == 0) + sects = 256; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Read(6) lba %d blks %d\n", lba, sects); + +if (uptr->flags & UNIT_ATT) + r = sim_disk_rdsect (uptr, lba, &bus->buf[0], §sread, sects); +else { + memset (&bus->buf[0], 0, (sects * dev->block_size)); + sectsread = sects; + } + +bus->buf_b = (sectsread * dev->block_size); +scsi_set_phase (bus, SCSI_DATI); /* data in phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Read (6 byte command), tape version */ + +void scsi_read6_tape (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +t_seccnt sects, sectsread; +t_stat r; + +if ((data[1] & 0x3) == 0x3) { /* SILI and FIXED? */ + scsi_status (bus, STS_CHK, KEY_ILLREQ, ASC_INVCDB); + return; + } + +sects = GETW (data, 3) | (data[2] << 16); +sectsread = 0; + +if (sects == 0) { /* no data to read */ + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); + return; + } + +sim_debug (SCSI_DBG_CMD, bus->dptr, + "Read(6) blks %d fixed %d\n", sects, (data[1] & 0x1)); + +if (uptr->flags & UNIT_ATT) { + if (data[1] & 0x1) { + r = sim_tape_rdrecf (uptr, &bus->buf[0], §sread, (sects * dev->block_size)); + sim_debug (SCSI_DBG_CMD, bus->dptr, + "Read tape blk %d, read %d, r = %d\n", sects, sectsread, r); + } + else { + r = sim_tape_rdrecf (uptr, &bus->buf[0], §sread, sects); + sim_debug (SCSI_DBG_CMD, bus->dptr, + "Read tape max %d, read %d, r = %d\n", sects, sectsread, r); + if (r == MTSE_INVRL) { /* overlength condition */ + sim_debug (SCSI_DBG_CMD, bus->dptr, + "Overlength\n"); + if ((data[1] & 0x2) && (dev->block_size == 0)) { /* SILI set */ + sim_debug (SCSI_DBG_CMD, bus->dptr, + "SILI set\n"); + } + else { + sim_debug (SCSI_DBG_CMD, bus->dptr, + "SILI not set - check condition\n"); + scsi_status (bus, STS_CHK, (KEY_OK | KEY_M_ILI), ASC_OK); + return; + } + } + else if ((r == MTSE_OK) && (sectsread < sects)) { /* underlength condition */ + sim_debug (SCSI_DBG_CMD, bus->dptr, + "Underlength\n"); + if (data[1] & 0x2) { /* SILI set */ + sim_debug (SCSI_DBG_CMD, bus->dptr, + "SILI set\n"); + } + else { + sim_debug (SCSI_DBG_CMD, bus->dptr, + "SILI not set - check condition\n"); + scsi_status_deferred (bus, STS_CHK, (KEY_OK | KEY_M_ILI), ASC_OK); + bus->sense_info = (sects - sectsread); + } + } + } + + if (r != MTSE_OK) { + sim_debug (SCSI_DBG_CMD, bus->dptr, + "Read error, r = %d\n", r); + } + scsi_tape_status (bus, r); + } +else { + memset (&bus->buf[0], 0, (sects * dev->block_size)); + sectsread = (sects * dev->block_size); + } + +if (sectsread > 0) { + bus->buf_b = sectsread; + scsi_set_phase (bus, SCSI_DATI); /* data in phase next */ + } +else { + bus->buf[bus->buf_b++] = bus->status; /* status code */ + scsi_set_phase (bus, SCSI_STS); /* status phase next */ + } +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Read (10 byte command), disk version */ + +void scsi_read10_disk (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +t_lba lba; +t_seccnt sects, sectsread; +t_stat r; + +lba = GETL (data, 2); +sects = GETW (data, 7); + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Read(10) lba %d blks %d\n", lba, sects); + +if (sects == 0) { /* no data to read */ + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); + return; + } + +if (uptr->flags & UNIT_ATT) + r = sim_disk_rdsect (uptr, lba, &bus->buf[0], §sread, sects); +else { + memset (&bus->buf[0], 0, (sects * dev->block_size)); + sectsread = sects; + } + +bus->buf_b = (sectsread * dev->block_size); +scsi_set_phase (bus, SCSI_DATI); /* data in phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Read Long */ +/* This command is needed by VMS for host-based volume shadowing */ +/* See DKDRIVER */ + +void scsi_read_long (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +t_lba lba; +t_seccnt sects, sectsread; +t_stat r; + +lba = GETL (data, 2); +sects = GETW (data, 7); + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Read Long lba %d bytes %d\n", lba, sects); + +if (uptr->flags & UNIT_ATT) + r = sim_disk_rdsect (uptr, lba, &bus->buf[0], §sread, ((sects >> 9) + 1)); +else { + memset (&bus->buf[0], 0, sects); + } + +bus->buf_b = sects; +scsi_set_phase (bus, SCSI_DATI); /* data in phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Write (6 byte command), disk version */ + +void scsi_write6_disk (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +t_lba lba; +t_seccnt sects, sectswritten; +t_stat r; + +if (bus->phase == SCSI_CMD) { + sim_debug (SCSI_DBG_CMD, bus->dptr, "Write(6) - CMD\n"); + memcpy (&bus->cmd[0], &data[0], 6); + sects = bus->cmd[4]; + if (sects == 0) sects = 256; + bus->buf_b = (sects * dev->block_size); + scsi_set_phase (bus, SCSI_DATO); /* data out phase next */ + scsi_set_req (bus); /* request data */ + } +else if (bus->phase == SCSI_DATO) { + sects = bus->cmd[4]; + if (sects == 0) sects = 256; + lba = GETW (bus->cmd, 2) | ((bus->cmd[1] & 0x1F) << 16); + sim_debug (SCSI_DBG_CMD, bus->dptr, "Write(6) - DATO, lba %d bytes %d\n", lba, sects); + + if (uptr->flags & UNIT_ATT) + r = sim_disk_wrsect (uptr, lba, &bus->buf[0], §swritten, sects); + + memset (&bus->cmd[0], 0, 10); + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); + } +} + +/* Command - Write (10 byte command), disk version */ + +void scsi_write10_disk (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +t_lba lba; +t_seccnt sects, sectswritten; +t_stat r; + +if (bus->phase == SCSI_CMD) { + sim_debug (SCSI_DBG_CMD, bus->dptr, "Write(10) - CMD\n"); + memcpy (&bus->cmd[0], &data[0], 10); + sects = GETW (bus->cmd, 7); + if (sects == 0) /* no data to write */ + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); + else { + bus->buf_b = (sects * dev->block_size); + scsi_set_phase (bus, SCSI_DATO); /* data out phase next */ + scsi_set_req (bus); /* request data */ + } + } +else if (bus->phase == SCSI_DATO) { + sects = GETW (bus->cmd, 7); + lba = GETL (bus->cmd, 2); + sim_debug (SCSI_DBG_CMD, bus->dptr, "Write(10) - DATO, lba %d bytes %d\n", lba, sects); + + if (uptr->flags & UNIT_ATT) + r = sim_disk_wrsect (uptr, lba, &bus->buf[0], §swritten, sects); + + memset (&bus->cmd[0], 0, 10); + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); + } +} + +/* Command - Erase */ + +void scsi_erase (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +t_stat r; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Erase\n"); + +if (data[1] & 0x1) /* LONG bit set? */ + r = sim_tape_wreom (uptr); /* erase to EOT */ +else + r = sim_tape_wrgap (uptr, dev->gaplen); /* write gap */ + +scsi_tape_status (bus, r); +scsi_status (bus, bus->status, bus->sense_key, bus->sense_code); +} + +/* Command - Reserve Unit */ + +void scsi_reserve_unit (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +sim_debug (SCSI_DBG_CMD, bus->dptr, "Reserve Unit\n"); +scsi_status (bus, STS_OK, KEY_OK, ASC_OK); /* GOOD status */ +} + +/* Command - Release Unit */ + +void scsi_release_unit (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +sim_debug (SCSI_DBG_CMD, bus->dptr, "Release Unit\n"); +scsi_status (bus, STS_OK, KEY_OK, ASC_OK); /* GOOD status */ +} + +/* Command - Rewind */ + +void scsi_rewind (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +t_stat r; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Rewind\n"); + +r = sim_tape_rewind (uptr); + +scsi_tape_status (bus, r); +scsi_status (bus, bus->status, bus->sense_key, bus->sense_code); +} + +/* Command - Send Diagnostic */ + +void scsi_send_diag (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +sim_debug (SCSI_DBG_CMD, bus->dptr, "Send Diagnostic\n"); + +if (data[1] & 0x4) /* selftest */ + scsi_status (bus, STS_OK, KEY_OK, ASC_OK); /* GOOD status */ +else + scsi_status (bus, STS_CHK, KEY_ILLREQ, ASC_INVCDB); +} + +/* Command - Space */ + +void scsi_space (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +uint32 code, skipped; +t_seccnt sects; +t_stat r; + +code = data[1] & 0x7; +sects = GETW (data, 3) | (data[2] << 16); + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Space %d %s\n", sects, ((code == 0) ? "records" : "files")); + +switch (code) { + + case 0: /* blocks */ + if (sects & 0x800000) { /* reverse */ + sects = 0x1000000 - sects; + r = sim_tape_sprecsr (uptr, sects, &skipped); + } + else /* forwards */ + r = sim_tape_sprecsf (uptr, sects, &skipped); + break; + + case 1: /* filemarks */ + if (sects & 0x800000) { /* reverse */ + sects = 0x1000000 - sects; + r = sim_tape_spfiler (uptr, sects, &skipped); + } + else /* forwards */ + r = sim_tape_spfilef (uptr, sects, &skipped); + break; + } + +scsi_tape_status (bus, r); +bus->buf[bus->buf_b++] = bus->status; /* status code */ +scsi_set_phase (bus, SCSI_STS); /* status phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Command - Write Filemarks */ + +void scsi_wrfmark (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +uint32 i; +t_seccnt sects; +t_stat r; + +sim_debug (SCSI_DBG_CMD, bus->dptr, "Write Filemarks\n"); + +sects = GETW (data, 3) | (data[2] << 16); + +for (i = 0; i < sects; i++) { + r = sim_tape_wrtmk (uptr); + if (r != MTSE_OK) break; + } + +scsi_tape_status (bus, r); +bus->buf[bus->buf_b++] = bus->status; /* status code */ +scsi_set_phase (bus, SCSI_STS); /* status phase next */ +scsi_set_req (bus); /* request to send data */ +} + +/* Process a SCSI command for a direct-access device */ + +void scsi_disk_command (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +switch (data[0]) { + + /* FIXME: FORMAT UNIT */ + + case CMD_INQUIRY: /* mandatory */ + scsi_inquiry (bus, data, len); + break; + + case CMD_MODESEL6: /* optional */ + scsi_mode_sel6 (bus, data, len); + break; + + case CMD_MODESEL10: /* optional */ + scsi_mode_sel10 (bus, data, len); + break; + + case CMD_MODESENSE6: /* optional */ + scsi_mode_sense6 (bus, data, len); + break; + + case CMD_MODESENSE10: /* optional */ + scsi_mode_sense10 (bus, data, len); + break; + + case CMD_PREVALLOW: /* optional */ + scsi_prev_allow (bus, data, len); + break; + + case CMD_READ6: /* mandatory */ + scsi_read6_disk (bus, data, len); + break; + + case CMD_READ10: /* mandatory */ + scsi_read10_disk (bus, data, len); + break; + + case CMD_RDCAP: /* mandatory */ + scsi_read_capacity (bus, data, len); + break; + + case CMD_RDLONG: /* optional - needed by VMS volume shadowing */ + scsi_read_long (bus, data, len); + break; + + case CMD_RELEASE: /* mandatory */ + scsi_release_unit (bus, data, len); + break; + + case CMD_REQSENSE: /* mandatory */ + scsi_req_sense (bus, data, len); + break; + + case CMD_RESERVE: /* mandatory */ + scsi_reserve_unit (bus, data, len); + break; + + case CMD_SNDDIAG: /* mandatory */ + scsi_send_diag (bus, data, len); + break; + + case CMD_STARTSTOP: /* optional */ + scsi_start_stop (bus, data, len); + break; + + case CMD_TESTRDY: /* mandatory */ + scsi_test_ready (bus, data, len); + break; + + case CMD_WRITE6: /* optional */ + scsi_write6_disk (bus, data, len); + break; + + case CMD_WRITE10: /* optional */ + scsi_write10_disk (bus, data, len); + break; + + default: + sim_printf ("SCSI: unknown disk command %02X\n", data[0]); + scsi_status (bus, STS_CHK, KEY_ILLREQ, ASC_INVCOM); + break; + } +} + +/* Process a SCSI command for a sequential-access device */ + +void scsi_tape_command (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +switch (data[0]) { + + case CMD_ERASE: /* mandatory */ + scsi_erase (bus, data, len); + break; + + case CMD_INQUIRY: /* mandatory */ + scsi_inquiry (bus, data, len); + break; + + case CMD_MODESEL6: /* mandatory */ + scsi_mode_sel6 (bus, data, len); + break; + + case CMD_MODESEL10: /* optional */ + scsi_mode_sel10 (bus, data, len); + break; + + case CMD_MODESENSE6: /* mandatory */ + scsi_mode_sense6 (bus, data, len); + break; + + case CMD_MODESENSE10: /* optional */ + scsi_mode_sense10 (bus, data, len); + break; + + case CMD_PREVALLOW: /* optional */ + scsi_prev_allow (bus, data, len); + break; + + case CMD_READ6: /* mandatory */ + scsi_read6_tape (bus, data, len); + break; + + /* FIXME: READ BLOCK LIMITS */ + + case CMD_RELEASE: /* mandatory */ + scsi_release_unit (bus, data, len); + break; + + case CMD_REQSENSE: /* mandatory */ + scsi_req_sense (bus, data, len); + break; + + case CMD_RESERVE: /* mandatory */ + scsi_reserve_unit (bus, data, len); + break; + + case CMD_REWIND: /* mandatory */ + scsi_rewind (bus, data, len); + break; + + case CMD_SNDDIAG: /* mandatory */ + scsi_send_diag (bus, data, len); + break; + + case CMD_SPACE: /* mandatory */ + scsi_space (bus, data, len); + break; + + case CMD_TESTRDY: /* mandatory */ + scsi_test_ready (bus, data, len); + break; + + /* FIXME: WRITE6 */ + + case CMD_WRFMARK: /* mandatory */ + scsi_wrfmark (bus, data, len); + break; + + default: + sim_printf ("SCSI: unknown tape command %02X\n", data[0]); + scsi_status (bus, STS_CHK, KEY_ILLREQ, ASC_INVCOM); + break; + } +} + +/* Process data for CMD phase */ + +uint32 scsi_command (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +UNIT *uptr = bus->dev[bus->target]; +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; +uint32 cmd_len; + +cmd_len = scsi_decode_group (data[0]); + +if (len < cmd_len) /* all command bytes received? */ + return 0; /* no, need more */ +bus->status = STS_OK; + +switch (dev->devtype) { + + case SCSI_DISK: + scsi_disk_command (bus, data, len); + break; + + case SCSI_TAPE: + scsi_tape_command (bus, data, len); + break; + + default: + sim_printf ("SCSI: commands unimplemented for device type %d\n", dev->devtype); + break; + } + +return cmd_len; +} + +/* Process data for DATO phase */ + +uint32 scsi_data (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +uint32 i; + +for (i = 0; ((i < len) && (bus->buf_t != bus->buf_b)); i++, bus->buf_t++) + bus->buf[bus->buf_t] = data[i]; +if (bus->buf_t == bus->buf_b) { + bus->buf_t = 0; + scsi_command (bus, &bus->cmd[0], bus->buf_b); + } +else + scsi_set_req (bus); /* request data */ +return i; +} + +/* Write data to the SCSI bus */ + +uint32 scsi_write (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +uint32 left = len; +uint32 bc; +uint8 *buf; + +scsi_release_req (bus); /* assume done */ +for (buf = data; left > 0; buf += bc, left -= bc) { + switch (bus->phase) { + case SCSI_DATO: + bc = scsi_data (bus, buf, left); + break; + case SCSI_MSGO: + bc = scsi_message (bus, buf, left); + break; + case SCSI_CMD: + bc = scsi_command (bus, buf, left); + break; + default: + return (len - left); + } + if (bc == 0) { /* no data processed? */ + scsi_set_req (bus); /* request more */ + return (len - left); + } + } +switch (bus->phase) { /* new phase */ + case SCSI_DATI: /* data in */ + case SCSI_STS: /* status */ + case SCSI_MSGI: /* message in */ + if (bus->buf_t != bus->buf_b) /* data to return? */ + scsi_set_req (bus); /* let initiator know */ + break; + default: + break; + } +return (len - left); +} + +/* Read data from the SCSI bus */ + +uint32 scsi_read (SCSI_BUS *bus, uint8 *data, uint32 len) +{ +uint32 i; + +if (len == 0) { + *data = bus->buf[bus->buf_t]; + return 0; + } +scsi_release_req (bus); /* assume done */ +for (i = 0; ((i < len) && (bus->buf_t != bus->buf_b)); i++, bus->buf_t++) + data[i] = bus->buf[bus->buf_t]; +if (bus->buf_t == bus->buf_b) { + bus->buf_t = bus->buf_b = 0; + switch (bus->phase) { + case SCSI_DATI: /* data in */ + scsi_set_phase (bus, SCSI_STS); + bus->buf[bus->buf_b++] = bus->status; /* status code */ + scsi_set_req (bus); + break; + case SCSI_STS: /* status */ + scsi_set_phase (bus, SCSI_MSGI); + bus->buf[bus->buf_b++] = 0; /* command complete */ + scsi_set_req (bus); + break; +// case SCSI_MSGI: /* message in */ +// scsi_release (bus); +// break; + default: + break; + } + } +else + scsi_set_req (bus); +return i; +} + +/* Get the state of the given SCSI device */ + +uint32 scsi_state (SCSI_BUS *bus, uint32 id) +{ +if (bus->initiator == id) + return SCSI_INIT; /* device is initiator */ +if (bus->target == id) + return SCSI_TARG; /* device is target */ +return SCSI_DISC; /* device is disconnected */ +} + +/* Add a unit to the SCSI bus */ + +void scsi_add_unit (SCSI_BUS *bus, uint32 id, UNIT *uptr) +{ +bus->dev[id] = uptr; +} + +/* Set the SCSI device parameters for a unit */ + +void scsi_set_unit (SCSI_BUS *bus, UNIT *uptr, SCSI_DEV *dev) +{ +uptr->up7 = (void *)dev; +} + +/* Reset a unit */ + +void scsi_reset_unit (UNIT *uptr) +{ +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; + +if (dev == NULL) + return; + +switch (dev->devtype) { + case SCSI_DISK: + case SCSI_WORM: + case SCSI_CDROM: + sim_disk_reset (uptr); + break; + case SCSI_TAPE: + sim_tape_rewind (uptr); + break; + } +} + +/* Reset the SCSI bus */ + +void scsi_reset (SCSI_BUS *bus) +{ +sim_debug (SCSI_DBG_BUS, bus->dptr, "Bus reset\n"); +bus->phase = SCSI_DATO; +bus->buf_t = bus->buf_b = 0; +bus->atn = FALSE; +bus->initiator = -1; +bus->target = -1; +bus->lun = 0; +//bus->sense_key = 6; /* UNIT ATTENTION */ +//bus->sense_code = 0x29; /* POWER ON, RESET, OR BUS DEVICE RESET OCCURRED */ +bus->sense_key = 0; +bus->sense_code = 0; +bus->sense_qual = 0; +bus->sense_info = 0; +} + +/* Initial setup of SCSI bus */ + +t_stat scsi_init (SCSI_BUS *bus, uint32 maxfr) +{ +if (bus->buf == NULL) + bus->buf = (uint8 *)calloc (maxfr, sizeof(uint8)); +if (bus->buf == NULL) + return SCPE_MEM; +return SCPE_OK; +} + +/* Set device file format */ + +t_stat scsi_set_fmt (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; + +if (dev == NULL) + return SCPE_NOFNC; + +switch (dev->devtype) { + case SCSI_DISK: + case SCSI_WORM: + case SCSI_CDROM: + return sim_disk_set_fmt (uptr, val, cptr, desc); + case SCSI_TAPE: + return sim_tape_set_fmt (uptr, val, cptr, desc); + default: + return SCPE_NOFNC; + } +} + +/* Show device file format */ + +t_stat scsi_show_fmt (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; + +if (dev == NULL) + return SCPE_NOFNC; + +switch (dev->devtype) { + case SCSI_DISK: + case SCSI_WORM: + case SCSI_CDROM: + return sim_disk_show_fmt (st, uptr, val, desc); + case SCSI_TAPE: + return sim_tape_show_fmt (st, uptr, val, desc); + default: + return SCPE_OK; + } +} + +/* Set/clear hardware write lock */ + +t_stat scsi_set_wlk (UNIT *uptr, int32 val, CONST char *cptr, void *desc) +{ +return SCPE_OK; +} + +/* Show write lock status */ + +t_stat scsi_show_wlk (FILE *st, UNIT *uptr, int32 val, CONST void *desc) +{ +return SCPE_OK; +} + +/* Attach device */ + +t_stat scsi_attach (UNIT *uptr, CONST char *cptr) +{ +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; + +if (dev == NULL) + return SCPE_NOFNC; + +switch (dev->devtype) { + case SCSI_DISK: + case SCSI_WORM: + case SCSI_CDROM: + return sim_disk_attach (uptr, cptr, dev->block_size, sizeof (uint8), (uptr->flags & SCSI_NOAUTO), SCSI_DBG_DSK, dev->name, 0, 0); + case SCSI_TAPE: + return sim_tape_attach (uptr, cptr); + default: + return SCPE_NOFNC; + } +} + +/* Dettach device */ + +t_stat scsi_detach (UNIT *uptr) +{ +SCSI_DEV *dev = (SCSI_DEV *)uptr->up7; + +if (dev == NULL) + return SCPE_NOFNC; + +switch (dev->devtype) { + case SCSI_DISK: + case SCSI_WORM: + case SCSI_CDROM: + return sim_disk_detach (uptr); /* detach unit */ + case SCSI_TAPE: + return sim_tape_detach (uptr); /* detach unit */ + default: + return SCPE_NOFNC; + } +} + +/* Show common SCSI help */ + +t_stat scsi_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr) +{ +fprintf (st, "\nDisk drives on the SCSI bus can be attached to simulated storage in the\n"); +fprintf (st, "following ways:\n\n"); +sim_disk_attach_help (st, dptr, uptr, flag, cptr); +fprintf (st, "\nTape drives on the SCSI bus can be attached to simulated storage in the\n"); +fprintf (st, "following ways:\n\n"); +sim_tape_attach_help (st, dptr, uptr, flag, cptr); +return SCPE_OK; +} diff --git a/sim_scsi.h b/sim_scsi.h new file mode 100644 index 00000000..fe00e1bc --- /dev/null +++ b/sim_scsi.h @@ -0,0 +1,133 @@ +/* sim_scsi.h: SCSI bus simulation + + Copyright (c) 2019, Matt Burke + + Permission is hereby granted, free of charge, to any person obtaining a + copy of this software and associated documentation files (the "Software"), + to deal in the Software without restriction, including without limitation + the rights to use, copy, modify, merge, publish, distribute, sublicense, + and/or sell copies of the Software, and to permit persons to whom the + Software is furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be included in + all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + Except as contained in this notice, the name of the author shall not be + used in advertising or otherwise to promote the sale, use or other dealings + in this Software without prior written authorization from the author. +*/ + +#ifndef _SIM_SCSI_H_ +#define _SIM_SCSI_H_ 0 + +#include "sim_defs.h" + +/* SCSI device states */ + +#define SCSI_DISC 0 /* disconnected */ +#define SCSI_TARG 1 /* target mode */ +#define SCSI_INIT 2 /* initiator mode */ + +/* SCSI device types */ + +#define SCSI_DISK 0 /* direct access device */ +#define SCSI_TAPE 1 /* sequential access device */ +#define SCSI_PRINT 2 /* printer */ +#define SCSI_PROC 3 /* processor */ +#define SCSI_WORM 4 /* write-once device */ +#define SCSI_CDROM 5 /* CD-ROM */ +#define SCSI_SCAN 6 /* scanner */ +#define SCSI_OPTI 7 /* optical */ +#define SCSI_JUKE 8 /* jukebox */ +#define SCSI_COMM 9 /* communications device */ + +/* SCSI bus phases */ + +#define SCSI_DATO 0 /* data out */ +#define SCSI_DATI 1 /* data in */ +#define SCSI_CMD 2 /* command */ +#define SCSI_STS 3 /* status */ +#define SCSI_MSGO 6 /* message out */ +#define SCSI_MSGI 7 /* message in */ + +/* Debugging bitmaps */ + +#define SCSI_DBG_CMD 0x01000000 /* SCSI commands */ +#define SCSI_DBG_MSG 0x02000000 /* SCSI messages */ +#define SCSI_DBG_BUS 0x04000000 /* bus activity */ +#define SCSI_DBG_DSK 0x08000000 /* disk activity */ + +#define SCSI_V_WLK (UNIT_V_UF + 5) /* hwre write lock */ +#define SCSI_V_NOAUTO (UNIT_V_UF + 6) /* noautosize */ +#define SCSI_V_UF (UNIT_V_UF + 7) +#define SCSI_WLK (1 << SCSI_V_WLK) +#define SCSI_NOAUTO (1 << SCSI_V_NOAUTO) + + +struct scsi_dev_t { + uint8 devtype; /* device type */ + uint8 pqual; /* peripheral qualifier */ + uint32 scsiver; /* SCSI version */ + t_bool removeable; /* removable flag */ + uint32 block_size; /* device block size */ + uint32 lbn; /* device size (blocks) */ + const char *manufacturer; /* manufacturer string */ + const char *product; /* product string */ + const char *rev; /* revision string */ + const char *name; /* gap length for tapes */ + uint32 gaplen; + }; + +struct scsi_bus_t { + DEVICE *dptr; /* SCSI device */ + UNIT *dev[8]; /* target units */ + int32 initiator; /* current initiator */ + int32 target; /* current target */ + t_bool atn; /* attention flag */ + t_bool req; /* request flag */ + uint8 *buf; /* transfer buffer */ + uint8 cmd[10]; /* command buffer */ + uint32 buf_b; /* buffer bottom ptr */ + uint32 buf_t; /* buffer top ptr */ + uint32 phase; /* current bus phase */ + uint32 lun; /* selected lun */ + uint32 status; + uint32 sense_key; + uint32 sense_code; + uint32 sense_qual; + uint32 sense_info; +}; + +typedef struct scsi_bus_t SCSI_BUS; +typedef struct scsi_dev_t SCSI_DEV; + +t_bool scsi_arbitrate (SCSI_BUS *bus, uint32 initiator); +void scsi_release (SCSI_BUS *bus); +void scsi_set_atn (SCSI_BUS *bus); +void scsi_release_atn (SCSI_BUS *bus); +t_bool scsi_select (SCSI_BUS *bus, uint32 target); +uint32 scsi_write (SCSI_BUS *bus, uint8 *data, uint32 len); +uint32 scsi_read (SCSI_BUS *bus, uint8 *data, uint32 len); +uint32 scsi_state (SCSI_BUS *bus, uint32 id); +void scsi_add_unit (SCSI_BUS *bus, uint32 id, UNIT *uptr); +void scsi_set_unit (SCSI_BUS *bus, UNIT *uptr, SCSI_DEV *dev); +void scsi_reset_unit (UNIT *uptr); +void scsi_reset (SCSI_BUS *bus); +t_stat scsi_init (SCSI_BUS *bus, uint32 maxfr); + +t_stat scsi_set_fmt (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat scsi_set_wlk (UNIT *uptr, int32 val, CONST char *cptr, void *desc); +t_stat scsi_show_fmt (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +t_stat scsi_show_wlk (FILE *st, UNIT *uptr, int32 val, CONST void *desc); +t_stat scsi_attach (UNIT *uptr, CONST char *cptr); +t_stat scsi_detach (UNIT *uptr); +t_stat scsi_help (FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr); + +#endif