diff --git a/IBMPC-Systems/common/i8088.c b/IBMPC-Systems/common/i8088.c index b43e0f0b..af8ad790 100644 --- a/IBMPC-Systems/common/i8088.c +++ b/IBMPC-Systems/common/i8088.c @@ -291,7 +291,7 @@ uint32 sysmode = 0; /* prefix flags */ #define SYSMODE_SEGOVR_ES 0x08 #define SYSMODE_SEGOVR_SS 0x10 #define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | SYSMODE_SEGOVR_CS | \ - SYSMODE_SEGOVR_DS | SYSMODE_SEGOVR_ES | SYSMODE_SEGOVR_SS) + SYSMODE_SEGOVR_DS | SYSMODE_SEGOVR_ES | SYSMODE_SEGOVR_SS) #define SYSMODE_PREFIX_REPE 0x20 #define SYSMODE_PREFIX_REPNE 0x40 @@ -474,7 +474,7 @@ uint8 xor_3_tab[] = { 0, 1, 1, 0 }; int32 IP; -static const char *opcode[] = { +static const char *opcode[256] = { "ADD\t", "ADD\t", "ADD\t", "ADD\t", /* 0x00 */ "ADD\tAL,", "ADD\tAX,", "PUSH\tES", "POP\tES", "OR\t", "OR\t", "OR\t", "OR\t", @@ -542,7 +542,7 @@ static const char *opcode[] = { }; /* -0 = 1 byte opcaode +0 = 1 byte opcode 1 = DATA8 2 = DATA16 3 = IP-INC8 @@ -579,7 +579,7 @@ int32 sim_instr (void) { extern int32 sim_interval; int32 IR, OP, DAR, reason, hi, lo, carry, i, adr; - int32 MRR, REG, EA, MOD, RM, DISP, VAL, DATA, OFF, SEG, INC, VAL1; + int32 MRR, REG, EA, MOD, RM, DISP, VAL, DATA, OFF, SEG, INC, VAL1, MAR; IP = saved_PC & ADDRMASK16; /* load local IP */ reason = 0; /* clear stop reason */ @@ -3152,6 +3152,9 @@ int32 sim_instr (void) case 4: //IP-INC16 sim_printf(" 0%04XH", EA); break; + case 5: //MAR + sim_printf(" 0%02XH", MAR); + break; default: break; } @@ -4784,7 +4787,7 @@ t_stat fprint_sym (FILE *of, t_addr addr, t_value *val, t_stat parse_sym (const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw) { - int32 cflag, i = 0, j, r; + int32 cflag, i = 0, j, r, fflag = 1; char gbuf[CBUFSIZE]; cflag = (uptr == NULL) || (uptr == &i8088_unit); @@ -4845,9 +4848,9 @@ t_stat parse_sym (const char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 /* find opcode in table */ for (j = 0; j < 256; j++) { if (strcmp(gbuf, opcode[j]) == 0) - break; + fflag = 0; } - if (j > 255) /* not found */ + if (fflag) /* not found */ return SCPE_ARG; val[0] = j; /* store opcode */ diff --git a/IBMPC-Systems/common/i8237.c b/IBMPC-Systems/common/i8237.c index 601eed39..49d13cf9 100644 --- a/IBMPC-Systems/common/i8237.c +++ b/IBMPC-Systems/common/i8237.c @@ -375,7 +375,6 @@ DEVICE i8237_dev = { t_stat i8237_svc(UNIT *uptr) { - sim_printf("uptr=%08X\n", (long) uptr); sim_activate (&i8237_unit[uptr->u6], i8237_unit[uptr->u6].wait); return SCPE_OK; } diff --git a/IBMPC-Systems/ibmpc/ibmpc.c b/IBMPC-Systems/ibmpc/ibmpc.c index b8f298ab..ef56affc 100644 --- a/IBMPC-Systems/ibmpc/ibmpc.c +++ b/IBMPC-Systems/ibmpc/ibmpc.c @@ -100,6 +100,7 @@ uint8 dmapag0(t_bool io, uint8 data) dmapagreg0 = data; //sim_printf("dmapag0: dmapagreg0=%04X\n", data); } + return 0; } uint8 dmapag1(t_bool io, uint8 data) @@ -110,6 +111,7 @@ uint8 dmapag1(t_bool io, uint8 data) dmapagreg1 = data; //sim_printf("dmapag1: dmapagreg1=%04X\n", data); } + return 0; } uint8 dmapag2(t_bool io, uint8 data) @@ -120,6 +122,7 @@ uint8 dmapag2(t_bool io, uint8 data) dmapagreg2 = data; //sim_printf("dmapag2: dmapagreg2=%04X\n", data); } + return 0; } uint8 dmapag3(t_bool io, uint8 data) @@ -131,6 +134,7 @@ uint8 dmapag3(t_bool io, uint8 data) dmapagreg3 = data; //sim_printf("dmapag3: dmapagreg3=%04X\n", data); } + return 0; } uint8 enbnmi(t_bool io, uint8 data) @@ -146,6 +150,7 @@ uint8 enbnmi(t_bool io, uint8 data) //sim_printf("enbnmi: NMI disabled\n"); } } + return 0; } /* get a byte from memory - handle RAM, ROM, I/O, and pcbus memory */ diff --git a/IBMPC-Systems/ibmpc/system_defs.h b/IBMPC-Systems/ibmpc/system_defs.h index 7f5fd8cc..5b1990c4 100644 --- a/IBMPC-Systems/ibmpc/system_defs.h +++ b/IBMPC-Systems/ibmpc/system_defs.h @@ -28,7 +28,7 @@ #include #include -#include "sim_defs.h" /* simulator defns */ +#include "sim_defs.h" /* simulator defns */ /* set the base I/O address and device count for the 8237 */ #define I8237_BASE_0 0x000 @@ -70,24 +70,24 @@ /* xtbus interrupt definitions */ -#define INT_0 0x01 -#define INT_1 0x02 -#define INT_2 0x04 -#define INT_3 0x08 -#define INT_4 0x10 -#define INT_5 0x20 -#define INT_6 0x40 -#define INT_7 0x80 +#define INT_0 0x01 +#define INT_1 0x02 +#define INT_2 0x04 +#define INT_3 0x08 +#define INT_4 0x10 +#define INT_5 0x20 +#define INT_6 0x40 +#define INT_7 0x80 /* Memory */ -#define ADDRMASK16 0xFFFF -#define ADDRMASK20 0xFFFFF -#define MAXMEMSIZE20 0xFFFFF /* 8080 max memory size */ +#define ADDRMASK16 0xFFFF +#define ADDRMASK20 0xFFFFF +#define MAXMEMSIZE20 0xFFFFF /* 8080 max memory size */ -#define MEMSIZE (i8088_unit.capac) /* 8088 actual memory size */ -#define ADDRMASK (MAXMEMSIZE - 1) /* 8088 address mask */ -#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) +#define MEMSIZE (i8088_unit.capac) /* 8088 actual memory size */ +#define ADDRMASK (MAXMEMSIZE - 1) /* 8088 address mask */ +#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE) /* debug definitions */ @@ -102,10 +102,10 @@ /* Simulator stop codes */ -#define STOP_RSRV 1 /* must be 1 */ -#define STOP_HALT 2 /* HALT */ -#define STOP_IBKPT 3 /* breakpoint */ -#define STOP_OPCODE 4 /* Invalid Opcode */ -#define STOP_IO 5 /* I/O error */ -#define STOP_MEM 6 /* Memory error */ +#define STOP_RSRV 1 /* must be 1 */ +#define STOP_HALT 2 /* HALT */ +#define STOP_IBKPT 3 /* breakpoint */ +#define STOP_OPCODE 4 /* Invalid Opcode */ +#define STOP_IO 5 /* I/O error */ +#define STOP_MEM 6 /* Memory error */