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AltairZ80: Improved resource mapping diagnostics.

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This commit is contained in:
Peter Schorn 2020-05-27 10:30:47 +02:00
parent b9297e185f
commit f8a1e56637
30 changed files with 339 additions and 413 deletions
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276
AltairZ80/altairz80_cpu.c
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@ -99,8 +99,7 @@
if (cond) { \
PCQ_ENTRY(PCX); \
PC = GET_WORD(PC); \
} \
else { \
} else { \
PC += 2; \
} \
}
@ -113,8 +112,7 @@
PCQ_ENTRY(PCX); \
PC = adrr; \
tStates += 17; \
} \
else { \
} else { \
PC += 2; \
tStates += (chiptype == CHIP_TYPE_8080 ? 11 : 10); \
} \
@ -191,12 +189,14 @@ uint32 getClockFrequency(void);
void setClockFrequency(const uint32 Value);
uint32 getCommon(void);
uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
void PutBYTEExtended(register uint32 Addr, const register uint32 Value);
uint32 GetBYTEExtended(register uint32 Addr);
void cpu_raise_interrupt(uint32 irq);
const char* handlerNameForPort(const int32 port);
/* CPU data structures
cpu_dev CPU device descriptor
cpu_unit CPU unit descriptor
@ -281,10 +281,11 @@ uint32 m68k_registers[M68K_REG_CPU_TYPE + 1]; /* M68K CPU registers */
/* data structure for IN/OUT instructions */
struct idev {
int32 (*routine)(const int32, const int32, const int32);
const char* name;
};
static int32 switcherPort = SWITCHCPU_DEFAULT;
static struct idev oldSwitcherDevice = { NULL };
static struct idev oldSwitcherDevice = { NULL, NULL };
// CPU_INDEX_8080 is defined in altairz80_defs.h
#define CPU_INDEX_8086 26
@ -578,72 +579,76 @@ DEVICE cpu_dev = {
address is here, 'nulldev' means no device is available
*/
static struct idev dev_table[256] = {
{&nulldev}, {&nulldev}, {&sio0d}, {&sio0s}, /* 00 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04 */
{&dsk10}, {&dsk11}, {&dsk12}, {&nulldev}, /* 08 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C */
{&sio0s}, {&sio0d}, {&sio1s}, {&sio1d}, /* 10 */
{&sio0s}, {&sio0d}, {&sio0s}, {&sio0d}, /* 14 */
{&sio0s}, {&sio0d}, {&nulldev}, {&nulldev}, /* 18 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 20 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 24 */
{&netStatus},{&netData},{&netStatus},{&netData}, /* 28 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2C */
{&nulldev}, {&nulldev}, {&netStatus},{&netData}, /* 30 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 34 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 38 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 40 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 44 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 48 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 4C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 50 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 54 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 58 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 5C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 60 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 64 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 68 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 6C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 70 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 74 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 78 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 7C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 80 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 84 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 88 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 8C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 90 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 94 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 98 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 9C */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* A0 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* A4 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* A8 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* AC */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* B0 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* B4 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* B8 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* BC */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* C0 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* C4 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* C8 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* CC */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* D0 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* D4 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* D8 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* DC */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* E0 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* E4 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* E8 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* EC */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* F0 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* F4 */
{&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* F8 */
{&nulldev}, {&hdsk_io}, {&simh_dev}, {&sr_dev} /* FC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&sio0d, "sio0d"}, {&sio0s, "sio0s"}, /* 00 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 04 */
{&dsk10, "dsk10"}, {&dsk11, "dsk11"}, {&dsk12, "dsk12"}, {&nulldev, "nulldev"}, /* 08 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 0C */
{&sio0s, "sio0s"}, {&sio0d, "sio0d"}, {&sio1s, "sio1s"}, {&sio1d, "sio1d"}, /* 10 */
{&sio0s, "sio0s"}, {&sio0d, "sio0d"}, {&sio0s, "sio0s"}, {&sio0d, "sio0d"}, /* 14 */
{&sio0s, "sio0s"}, {&sio0d, "sio0d"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 18 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 1C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 20 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 24 */
{&netStatus, "netStatus"}, {&netData, "netData"}, {&netStatus, "netStatus"}, {&netData, "netData"}, /* 28 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 2C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&netStatus, "netStatus"},{&netData, "netData"}, /* 30 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 34 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 38 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 3C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 40 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 44 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 48 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 4C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 50 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 54 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 58 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 5C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 60 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 64 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 68 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 6C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 70 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 74 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 78 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 7C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 80 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 84 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 88 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 8C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 90 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 94 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 98 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* 9C */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* A0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* A4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* A8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* AC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* B0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* B4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* B8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* BC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* C0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* C4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* C8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* CC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* D0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* D4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* D8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* DC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* E0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* E4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* E8 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* EC */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* F0 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* F4 */
{&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, {&nulldev, "nulldev"}, /* F8 */
{&nulldev, "nulldev"}, {&hdsk_io, "hdsk_io"}, {&simh_dev,"simh_dev"},{&sr_dev, "sr_dev"} /* FC */
};
const char* handlerNameForPort(const int32 port) {
return dev_table[port & 0xff].name;
}
static int32 ramtype = 0;
#define MAX_RAM_TYPE 3
@ -652,13 +657,13 @@ ChipType chiptype = CHIP_TYPE_8080;
void out(const uint32 Port, const uint32 Value) {
if ((cpu_dev.dctrl & OUT_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" OUT(port=0x%04x [%5d], value=0x%04x [%5d])\n", PCX, Port, Port, Value, Value);
" OUT(port=0x%04x [%5d] %s, value=0x%04x [%5d])\n", PCX, Port, Port, dev_table[Port & 0xff].name, Value, Value);
fflush(sim_deb);
}
dev_table[Port & 0xff].routine(Port, 1, Value);
if ((cpu_dev.dctrl & OUT_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" OUT(port=0x%04x [%5d], value=0x%04x [%5d]) done\n", PCX, Port, Port, Value, Value);
" OUT(port=0x%04x [%5d] %s, value=0x%04x [%5d]) done\n", PCX, Port, Port, dev_table[Port & 0xff].name, Value, Value);
fflush(sim_deb);
}
}
@ -667,13 +672,13 @@ uint32 in(const uint32 Port) {
uint32 result;
if ((cpu_dev.dctrl & IN_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" IN(port=0x%04x [%5d])\n", PCX, Port, Port);
" IN(port=0x%04x [%5d] %s)\n", PCX, Port, Port, dev_table[Port & 0xff].name);
fflush(sim_deb);
}
result = dev_table[Port & 0xff].routine(Port, 0, 0);
if ((cpu_dev.dctrl & IN_MSG) && sim_deb) {
fprintf(sim_deb, "CPU: " ADDRESS_FORMAT
" IN(port=0x%04x [%5d]) = 0x%04x [%5d]\n", PCX, Port, Port, result, result);
" IN(port=0x%04x [%5d] %s) = 0x%04x [%5d]\n", PCX, Port, Port, dev_table[Port & 0xff].name, result, result);
fflush(sim_deb);
}
return result;
@ -1767,16 +1772,17 @@ typedef struct { /* Structure to describe a 2^LOG2PAGESIZE byte page of address
uint32 isRAM;
uint32 isEmpty;
int32 (*routine)(const int32, const int32, const int32);
const char *name; /* name of handler routine */
} MDEV;
static MDEV ROM_PAGE = {FALSE, FALSE, NULL}; /* this makes a page ROM */
static MDEV RAM_PAGE = {TRUE, FALSE, NULL}; /* this makes a page RAM */
static MDEV EMPTY_PAGE = {FALSE, TRUE, NULL}; /* this is non-existing memory */
static MDEV ROM_PAGE = {FALSE, FALSE, NULL, "ROM"}; /* this makes a page ROM */
static MDEV RAM_PAGE = {TRUE, FALSE, NULL, "RAM"}; /* this makes a page RAM */
static MDEV EMPTY_PAGE = {FALSE, TRUE, NULL, "NONEXIST"}; /* this is non-existing memory */
static MDEV mmu_table[MAXMEMORY >> LOG2PAGESIZE];
/* Memory and I/O Resource Mapping and Unmapping routine. */
uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap) {
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap) {
uint32 page, i, addr;
if (resource_type == RESOURCE_TYPE_MEMORY) {
for (i = 0; i < (size >> LOG2PAGESIZE); i++) {
@ -1785,8 +1791,8 @@ uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
addr |= bankSelect << MAXBANKSIZELOG2;
page = addr >> LOG2PAGESIZE;
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("%s memory 0x%05x, handler=%p\n", unmap ? "Unmapping" : " Mapping",
addr, routine);
sim_printf("%s memory 0x%05x, handler=%s\n", unmap ? "Unmapping" : " Mapping",
addr, name);
if (unmap) {
if (mmu_table[page].routine == routine) { /* unmap only if it was mapped */
if (MEMORYSIZE < MAXBANKSIZE)
@ -1797,10 +1803,10 @@ uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
else
mmu_table[page] = RAM_PAGE;
}
}
else {
} else {
mmu_table[page] = ROM_PAGE;
mmu_table[page].routine = routine;
mmu_table[page].name = name;
}
}
} else if (resource_type == RESOURCE_TYPE_IO) {
@ -1808,14 +1814,15 @@ uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
if (unmap) {
if (dev_table[i & 0xff].routine == routine) {
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("Unmapping IO %04x, handler=%p\n", i, routine);
sim_printf("Unmapping IO %04x, handler=%s\n", i, dev_table[i & 0xff].name);
dev_table[i & 0xff].routine = &nulldev;
dev_table[i & 0xff].name = "nulldev";
}
}
else {
} else {
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf(" Mapping IO %04x, handler=%p\n", i, routine);
sim_printf(" Mapping IO %04x, handler=%s\n", i, name);
dev_table[i & 0xff].routine = routine;
dev_table[i & 0xff].name = name;
}
} else {
sim_printf("%s: cannot map unknown resource type %d\n", __FUNCTION__, resource_type);
@ -2116,8 +2123,7 @@ static t_stat sim_instr_mmu (void) {
if (rtc_avail) {
startTime = sim_os_msec();
tStatesInSlice = sliceLength * clockFrequency;
}
else /* make sure that sim_os_msec() is not called later */
} else /* make sure that sim_os_msec() is not called later */
clockFrequency = startTime = tStatesInSlice = 0;
/* main instruction fetch/decode loop */
@ -2135,8 +2141,7 @@ static t_stat sim_instr_mmu (void) {
if (rtc_avail) {
startTime = sim_os_msec();
tStatesInSlice = sliceLength * clockFrequency;
}
else /* make sure that sim_os_msec() is not called later */
} else /* make sure that sim_os_msec() is not called later */
clockFrequency = startTime = tStatesInSlice = 0;
}
specialProcessing = clockFrequency | timerInterrupt | keyboardInterrupt | sim_brk_summ;
@ -2159,8 +2164,7 @@ static t_stat sim_instr_mmu (void) {
if ((GetBYTE(PC) == HALTINSTRUCTION) && ((cpu_unit.flags & UNIT_CPU_STOPONHALT) == 0)) {
PUSH(PC + 1);
PCQ_ENTRY(PC);
}
else {
} else {
PUSH(PC);
PCQ_ENTRY(PC - 1);
}
@ -2175,8 +2179,7 @@ static t_stat sim_instr_mmu (void) {
if ((GetBYTE(PC) == HALTINSTRUCTION) && ((cpu_unit.flags & UNIT_CPU_STOPONHALT) == 0)) {
PUSH(PC + 1);
PCQ_ENTRY(PC);
}
else {
} else {
PUSH(PC);
PCQ_ENTRY(PC - 1);
}
@ -2307,8 +2310,7 @@ static t_stat sim_instr_mmu (void) {
PCQ_ENTRY(PCX);
PC += (int8) GetBYTE(PC) + 1;
tStates += 13;
}
else {
} else {
PC++;
tStates += 8;
}
@ -2414,8 +2416,7 @@ static t_stat sim_instr_mmu (void) {
if (TSTFLAG(Z)) {
PC++;
tStates += 7;
}
else {
} else {
PCQ_ENTRY(PCX);
PC += (int8) GetBYTE(PC) + 1;
tStates += 12;
@ -2476,8 +2477,7 @@ static t_stat sim_instr_mmu (void) {
}
if (hd)
acu -= 0x160; /* adjust high digit */
}
else { /* last operation was an add */
} else { /* last operation was an add */
if (TSTFLAG(H) || (temp > 9)) { /* adjust low digit */
SETFLAG(H, (temp > 9));
acu += 6;
@ -2496,8 +2496,7 @@ static t_stat sim_instr_mmu (void) {
PCQ_ENTRY(PCX);
PC += (int8) GetBYTE(PC) + 1;
tStates += 12;
}
else {
} else {
PC++;
tStates += 7;
}
@ -2555,8 +2554,7 @@ static t_stat sim_instr_mmu (void) {
if (TSTFLAG(C)) {
PC++;
tStates += 7;
}
else {
} else {
PCQ_ENTRY(PCX);
PC += (int8) GetBYTE(PC) + 1;
tStates += 12;
@ -2617,8 +2615,7 @@ static t_stat sim_instr_mmu (void) {
PCQ_ENTRY(PCX);
PC += (int8) GetBYTE(PC) + 1;
tStates += 12;
}
else {
} else {
PC++;
tStates += 7;
}
@ -3491,8 +3488,7 @@ static t_stat sim_instr_mmu (void) {
case 0xc0: /* RET NZ */
if (TSTFLAG(Z)) {
tStates += 5; /* RNZ 5 */
}
else {
} else {
CHECK_BREAK_WORD(SP);
PCQ_ENTRY(PCX);
POP(PC);
@ -3547,8 +3543,7 @@ static t_stat sim_instr_mmu (void) {
PCQ_ENTRY(PCX);
POP(PC);
tStates += 11; /* RZ 11 */
}
else {
} else {
tStates += 5; /* RZ 5 */
}
break;
@ -3569,8 +3564,7 @@ static t_stat sim_instr_mmu (void) {
if (cpu_unit.flags & UNIT_CPU_OPSTOP) {
reason = STOP_OPCODE;
goto end_decode;
}
else {
} else {
JPC(1);
break;
}
@ -3771,8 +3765,7 @@ static t_stat sim_instr_mmu (void) {
case 0xd0: /* RET NC */
if (TSTFLAG(C)) {
tStates += 5; /* RNC 5 */
}
else {
} else {
CHECK_BREAK_WORD(SP);
PCQ_ENTRY(PCX);
POP(PC);
@ -3828,8 +3821,7 @@ static t_stat sim_instr_mmu (void) {
PCQ_ENTRY(PCX);
POP(PC);
tStates += 11; /* RC 11 */
}
else {
} else {
tStates += 5; /* RC 5 */
}
break;
@ -3878,8 +3870,7 @@ static t_stat sim_instr_mmu (void) {
if (cpu_unit.flags & UNIT_CPU_OPSTOP) {
reason = STOP_OPCODE;
goto end_decode;
}
else {
} else {
CALLC(1); /* also updates tStates */
break;
}
@ -4618,8 +4609,7 @@ static t_stat sim_instr_mmu (void) {
case 0xe0: /* RET PO */
if (TSTFLAG(P)) {
tStates += 5; /* RPO 5 */
}
else {
} else {
CHECK_BREAK_WORD(SP);
PCQ_ENTRY(PCX);
POP(PC);
@ -4674,8 +4664,7 @@ static t_stat sim_instr_mmu (void) {
PCQ_ENTRY(PCX);
POP(PC);
tStates += 11; /* RPE 11 */
}
else {
} else {
tStates += 5; /* RPE 5 */
}
break;
@ -4706,8 +4695,7 @@ static t_stat sim_instr_mmu (void) {
if (cpu_unit.flags & UNIT_CPU_OPSTOP) {
reason = STOP_OPCODE;
goto end_decode;
}
else {
} else {
CALLC(1); /* also updates tStates */
break;
}
@ -5339,8 +5327,7 @@ static t_stat sim_instr_mmu (void) {
case 0xf0: /* RET P */
if (TSTFLAG(S)) {
tStates += 5; /* RP 5 */
}
else {
} else {
CHECK_BREAK_WORD(SP);
PCQ_ENTRY(PCX);
POP(PC);
@ -5392,8 +5379,7 @@ static t_stat sim_instr_mmu (void) {
PCQ_ENTRY(PCX);
POP(PC);
tStates += 11; /* RM 11 */
}
else {
} else {
tStates += 5; /* RM 5 */
}
break;
@ -5421,8 +5407,7 @@ static t_stat sim_instr_mmu (void) {
if (cpu_unit.flags & UNIT_CPU_OPSTOP) {
reason = STOP_OPCODE;
goto end_decode;
}
else {
} else {
CALLC(1); /* also updates tStates */
break;
}
@ -6544,8 +6529,7 @@ static t_stat cpu_set_banked(UNIT *uptr, int32 value, CONST char *cptr, void *de
MEMORYSIZE = MAXMEMORY;
cpu_dev.awidth = MAXBANKSIZELOG2 + MAXBANKSLOG2;
cpu_clear();
}
else if (chiptype == CHIP_TYPE_8086) {
} else if (chiptype == CHIP_TYPE_8086) {
sim_printf("Cannot use banked memory for 8086 CPU.\n");
return SCPE_ARG;
}
@ -6736,7 +6720,7 @@ static t_stat cpu_set_switcher(UNIT *uptr, int32 value, CONST char *cptr, void *
struct idev safe;
switcherPort &= 0xff;
safe = dev_table[switcherPort];
if (sim_map_resource(switcherPort, 1, RESOURCE_TYPE_IO, &switchcpu_io, FALSE)) {
if (sim_map_resource(switcherPort, 1, RESOURCE_TYPE_IO, &switchcpu_io, "switchcpu_io", FALSE)) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, switcherPort);
return SCPE_ARG;
}
@ -6745,7 +6729,7 @@ static t_stat cpu_set_switcher(UNIT *uptr, int32 value, CONST char *cptr, void *
}
static t_stat cpu_reset_switcher(UNIT *uptr, int32 value, CONST char *cptr, void *desc) {
if (sim_map_resource(switcherPort, 1, RESOURCE_TYPE_IO, oldSwitcherDevice.routine, FALSE)) {
if (sim_map_resource(switcherPort, 1, RESOURCE_TYPE_IO, oldSwitcherDevice.routine, oldSwitcherDevice.name, FALSE)) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, switcherPort);
return SCPE_ARG;
}
@ -6764,17 +6748,17 @@ static t_stat cpu_set_ramtype(UNIT *uptr, int32 value, CONST char *cptr, void *d
case 1:
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("Unmapping NorthStar HRAM\n");
sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, TRUE);
sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, "bankseldev", TRUE);
break;
case 2:
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("Unmapping Vector RAM\n");
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, TRUE);
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, "bankseldev", TRUE);
break;
case 3:
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("Unmapping Cromemco RAM\n");
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, TRUE);
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, "bankseldev", TRUE);
break;
case 0:
default:
@ -6787,17 +6771,17 @@ static t_stat cpu_set_ramtype(UNIT *uptr, int32 value, CONST char *cptr, void *d
case 1:
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("NorthStar HRAM Selected\n");
sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, FALSE);
sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, "bankseldev", FALSE);
break;
case 2:
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("Vector RAM Selected\n");
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, FALSE);
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, "bankseldev", FALSE);
break;
case 3:
if (cpu_unit.flags & UNIT_CPU_VERBOSE)
sim_printf("Cromemco RAM Selected\n");
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, FALSE);
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, "bankseldev", FALSE);
break;
case 0:
default:
@ -6938,8 +6922,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
if ((r != SCPE_OK) || (lnt == 0)) {
return SCPE_ARG;
}
}
else {
} else {
lnt = hst_lnt;
}
@ -6965,8 +6948,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
HIGH_REGISTER(h->af), h->bc, h->de, h->hl, h->sp, h->pc);
fprint_sym (st, h->pc, h->op, &cpu_unit, SWMASK ('M'));
fprintf(st, "\n");
}
else { /* Z80 */
} else { /* Z80 */
/*
** Use DDT/Z output:
*/
@ -7063,8 +7045,7 @@ t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag) {
return SCPE_IOERR;
}
sim_printf("%d byte%s dumped [%x - %x] to %s.\n", PLURAL(hi + 1 - lo), lo, hi, fnam);
}
else {
} else {
if (*cptr == 0)
addr = (chiptype == CHIP_TYPE_8086) ? PCX_S : PC_S;
else {
@ -7072,8 +7053,7 @@ t_stat sim_load(FILE *fileref, CONST char *cptr, CONST char *fnam, int flag) {
if (strcmp(gbuf, "ROM") == 0) {
addr = (chiptype == CHIP_TYPE_8086) ? PCX_S : PC_S;
makeROM = TRUE;
}
else {
} else {
addr = strtotv(cptr, &result, 16) & ADDRMASKEXTENDED;
if (cptr == result)
return SCPE_ARG;

9
AltairZ80/altairz80_cpu_nommu.c
View file

@ -84,8 +84,7 @@
#define JPC(cond) { \
if (cond) { \
PC = GET_WORD(PC); \
} \
else { \
} else { \
PC += 2; \
} \
}
@ -95,8 +94,7 @@
register uint32 adrr = GET_WORD(PC); \
PUSH(PC + 2); \
PC = adrr; \
} \
else { \
} else { \
PC += 2; \
} \
}
@ -1256,8 +1254,7 @@ t_stat sim_instr_nommu(void) {
}
if (hd)
acu -= 0x160; /* adjust high digit */
}
else { /* last operation was an add */
} else { /* last operation was an add */
if (TSTFLAG(H) || (temp > 9)) { /* adjust low digit */
SETFLAG(H, (temp > 9));
acu += 6;

20
AltairZ80/altairz80_dsk.c
View file

@ -170,7 +170,7 @@ extern uint32 PCX;
extern t_stat install_bootrom(const int32 bootrom[], const int32 size, const int32 addr, const int32 makeROM);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
void install_ALTAIRbootROM(void);
extern int32 find_unit_index(UNIT *uptr);
@ -391,9 +391,9 @@ static t_stat dsk_reset(DEVICE *dptr) {
current_disk = NUM_OF_DSK;
in9_count = 0;
in9_message = FALSE;
sim_map_resource(0x08, 1, RESOURCE_TYPE_IO, &dsk10, dptr->flags & DEV_DIS);
sim_map_resource(0x09, 1, RESOURCE_TYPE_IO, &dsk11, dptr->flags & DEV_DIS);
sim_map_resource(0x0A, 1, RESOURCE_TYPE_IO, &dsk12, dptr->flags & DEV_DIS);
sim_map_resource(0x08, 1, RESOURCE_TYPE_IO, &dsk10, "dsk10", dptr->flags & DEV_DIS);
sim_map_resource(0x09, 1, RESOURCE_TYPE_IO, &dsk11, "dsk11", dptr->flags & DEV_DIS);
sim_map_resource(0x0A, 1, RESOURCE_TYPE_IO, &dsk12, "dsk12", dptr->flags & DEV_DIS);
return SCPE_OK;
}
/* dsk_attach - determine type of drive attached based on disk image size */
@ -440,8 +440,7 @@ static t_stat dsk_boot(int32 unitno, DEVICE *dptr) {
(bootrom_dsk[UNIT_NO_OFFSET_2 - 1] == LDA_INSTRUCTION)) {
bootrom_dsk[UNIT_NO_OFFSET_1] = unitno & 0xff; /* LD A,<unitno> */
bootrom_dsk[UNIT_NO_OFFSET_2] = 0x80 | (unitno & 0xff); /* LD a,80h | <unitno> */
}
else { /* Attempt to modify non LD A,<> instructions is refused. */
} else { /* Attempt to modify non LD A,<> instructions is refused. */
sim_printf("Incorrect boot ROM offsets detected.\n");
return SCPE_IERR;
}
@ -483,8 +482,7 @@ static void writebuf(void) {
current_disk, PCX, current_track[current_disk],
current_sector[current_disk], rtn);
}
}
else if ( (dsk_dev.dctrl & VERBOSE_MSG) && (warnLock[current_disk] < warnLevelDSK) ) {
} else if ( (dsk_dev.dctrl & VERBOSE_MSG) && (warnLock[current_disk] < warnLevelDSK) ) {
/* write locked - print warning message if required */
warnLock[current_disk]++;
sim_debug(VERBOSE_MSG, &dsk_dev,
@ -547,8 +545,7 @@ int32 dsk10(const int32 port, const int32 io, const int32 data) {
current_disk, PCX, current_disk);
}
current_disk = NUM_OF_DSK;
}
else {
} else {
current_sector[current_disk] = 0xff; /* reset internal counters */
current_byte[current_disk] = 0xff;
if (data & 0x80) /* disable drive? */
@ -716,8 +713,7 @@ int32 dsk12(const int32 port, const int32 io, const int32 data) {
current_byte[current_disk] = 0;
}
return dskbuf[current_byte[current_disk]++] & 0xff;
}
else {
} else {
if (current_byte[current_disk] >= DSK_SECTSIZE)
writebuf(); /* from above we have that current_disk < NUM_OF_DSK */
else {

15
AltairZ80/altairz80_hdsk.c
View file

@ -81,7 +81,7 @@ extern int32 bootrom_dsk[];
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern int32 find_unit_index(UNIT *uptr);
static t_stat hdsk_boot(int32 unitno, DEVICE *dptr);
@ -373,10 +373,10 @@ DEVICE hdsk_dev = {
static t_stat hdsk_reset(DEVICE *dptr) {
PNP_INFO *pnp = (PNP_INFO *)dptr -> ctxt;
if (dptr -> flags & DEV_DIS) {
sim_map_resource(pnp -> io_base, pnp -> io_size, RESOURCE_TYPE_IO, &hdsk_io, TRUE);
sim_map_resource(pnp -> io_base, pnp -> io_size, RESOURCE_TYPE_IO, &hdsk_io, "hdsk_io", TRUE);
} else {
/* Connect HDSK at base address */
if (sim_map_resource(pnp -> io_base, pnp -> io_size, RESOURCE_TYPE_IO, &hdsk_io, FALSE) != 0) {
if (sim_map_resource(pnp -> io_base, pnp -> io_size, RESOURCE_TYPE_IO, &hdsk_io, "hdsk_io", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp -> mem_base);
dptr -> flags |= DEV_DIS;
return SCPE_ARG;
@ -500,8 +500,7 @@ static t_stat hdsk_attach(UNIT *uptr, CONST char *cptr) {
if (uptr -> HDSK_SECTOR_SIZE == 0)
uptr -> HDSK_SECTOR_SIZE = 128;
}
}
else { /* Case 2: disk parameter block found */
} else { /* Case 2: disk parameter block found */
uptr -> HDSK_SECTORS_PER_TRACK = dpb[uptr -> HDSK_FORMAT_TYPE].spt >> dpb[uptr -> HDSK_FORMAT_TYPE].psh;
uptr -> HDSK_SECTOR_SIZE = (128 << dpb[uptr -> HDSK_FORMAT_TYPE].psh);
}
@ -929,8 +928,7 @@ int32 hdsk_write(void) {
return hdskStatus;
}
}
}
else {
} else {
sim_debug(VERBOSE_MSG, &hdsk_dev, "HDSK%d: " ADDRESS_FORMAT
" Could not write to locked disk Sector=%06d Track=%04d.\n",
selectedDisk, PCX, selectedSector, selectedTrack);
@ -995,8 +993,7 @@ static int32 hdsk_out(const int32 port, const int32 data) {
current = dpb[uptr -> HDSK_FORMAT_TYPE];
parameterBlock[17] = uptr -> HDSK_SECTOR_SIZE & 0xff;
parameterBlock[18] = (uptr -> HDSK_SECTOR_SIZE >> 8) & 0xff;
}
else {
} else {
current = dpb[0];
parameterBlock[17] = 128;
parameterBlock[18] = 0;

23
AltairZ80/altairz80_mhdsk.c
View file

@ -163,7 +163,7 @@ static void doWrite(const int32 port, const int32 data, const uint32 command);
static t_stat dsk_reset(DEVICE *dptr);
static const char* cmdTranslate(const int32 cmd);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
static const char* mhdsk_description(DEVICE *dptr);
/* 88DSK Standard I/O Data Structures */
@ -267,14 +267,14 @@ static const char* cmdTranslate(const int32 cmd) {
----------------------------------------------------------------------------------*/
static t_stat dsk_reset(DEVICE *dptr) {
sim_map_resource(0xA0, 1, RESOURCE_TYPE_IO, &hdReturnReady, dptr->flags & DEV_DIS);
sim_map_resource(0xA1, 1, RESOURCE_TYPE_IO, &hdCstat, dptr->flags & DEV_DIS);
sim_map_resource(0xA2, 1, RESOURCE_TYPE_IO, &hdReturnReady, dptr->flags & DEV_DIS);
sim_map_resource(0xA3, 1, RESOURCE_TYPE_IO, &hdAcmd, dptr->flags & DEV_DIS);
sim_map_resource(0xA4, 1, RESOURCE_TYPE_IO, &hdReturnReady, dptr->flags & DEV_DIS);
sim_map_resource(0xA5, 1, RESOURCE_TYPE_IO, &hdCdata, dptr->flags & DEV_DIS);
sim_map_resource(0xA6, 1, RESOURCE_TYPE_IO, &hdReturnReady, dptr->flags & DEV_DIS);
sim_map_resource(0xA7, 1, RESOURCE_TYPE_IO, &hdAdata, dptr->flags & DEV_DIS);
sim_map_resource(0xA0, 1, RESOURCE_TYPE_IO, &hdReturnReady, "hdReturnReady", dptr->flags & DEV_DIS);
sim_map_resource(0xA1, 1, RESOURCE_TYPE_IO, &hdCstat, "hdCstat", dptr->flags & DEV_DIS);
sim_map_resource(0xA2, 1, RESOURCE_TYPE_IO, &hdReturnReady, "hdReturnReady", dptr->flags & DEV_DIS);
sim_map_resource(0xA3, 1, RESOURCE_TYPE_IO, &hdAcmd, "hdAcmd", dptr->flags & DEV_DIS);
sim_map_resource(0xA4, 1, RESOURCE_TYPE_IO, &hdReturnReady, "hdReturnReady", dptr->flags & DEV_DIS);
sim_map_resource(0xA5, 1, RESOURCE_TYPE_IO, &hdCdata, "hdCdata", dptr->flags & DEV_DIS);
sim_map_resource(0xA6, 1, RESOURCE_TYPE_IO, &hdReturnReady, "hdReturnReady", dptr->flags & DEV_DIS);
sim_map_resource(0xA7, 1, RESOURCE_TYPE_IO, &hdAdata, "hdAdata", dptr->flags & DEV_DIS);
selectedSector = 0; // current sector
selectedTrack = 0; // current track
@ -388,7 +388,7 @@ static int32 hdAcmd(const int32 port, const int32 io, const int32 data)
"Track = %i. Sector = %i. Head = %i. Buffer = %i. "
"No file attached.\n", selectedDisk, PCX, port, data, cmdTranslate(command),
selectedTrack, selectedSector, selectedHead, selectedBuffer);
} else if (command == CMD_WRITE_SEC)
} else if (command == CMD_WRITE_SEC)
doWrite(port, data, command);
else // CMD_READ_SEC or CMD_READ_UNFMT
doRead(port, data, command);
@ -548,8 +548,7 @@ static void doWrite(const int32 port, const int32 data, const uint32 command)
else if (sim_fwrite(diskBuf[selectedBuffer], 1, HDSK_SECTOR_SIZE, uptr->fileref) !=
HDSK_SECTOR_SIZE)
cstat = CSTAT_NOT_READY; /* write error */
}
else
} else
cstat = CSTAT_WRITE_PROTECT;
sim_debug(WRITE_MSG, &mhdsk_dev, "MHDSK%i: " ADDRESS_FORMAT
" OUT(%02X = ACMD) = %02x. CMD = %s. "

27
AltairZ80/altairz80_net.c
View file

@ -50,7 +50,7 @@ int32 netData (const int32 port, const int32 io, const int32 data)
static const char* net_description(DEVICE *dptr);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
#define MAX_CONNECTIONS 2 /* maximal number of server connections */
#define BUFFER_LENGTH 512 /* length of input and output buffer */
@ -147,9 +147,9 @@ static t_stat net_reset(DEVICE *dptr) {
for (i = 0; i <= MAX_CONNECTIONS; i++) {
serviceDescriptor_reset(i);
sim_map_resource(serviceDescriptor[i].Z80StatusPort, 1,
RESOURCE_TYPE_IO, &netStatus, dptr->flags & DEV_DIS);
RESOURCE_TYPE_IO, &netStatus, "netStatus", dptr->flags & DEV_DIS);
sim_map_resource(serviceDescriptor[i].Z80DataPort, 1,
RESOURCE_TYPE_IO, &netData, dptr->flags & DEV_DIS);
RESOURCE_TYPE_IO, &netData, "netData", dptr->flags & DEV_DIS);
}
return SCPE_OK;
}
@ -168,8 +168,7 @@ static t_stat net_attach(UNIT *uptr, CONST char *cptr) {
serviceDescriptor[1].masterSocket = sim_master_sock(cptr, NULL);
if (serviceDescriptor[1].masterSocket == INVALID_SOCKET)
return SCPE_IOERR;
}
else {
} else {
net_unit.wait = NET_INIT_POLL_CLIENT;
serviceDescriptor[0].ioSocket = sim_connect_sock_ex(NULL, cptr, "localhost", "3000", SIM_SOCK_OPT_NODELAY);
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
@ -214,8 +213,7 @@ static t_stat net_svc(UNIT *uptr) {
sim_debug(ACCEPT_MSG, &net_dev, "NET: " ADDRESS_FORMAT " Accepted connection %i with socket %i.\n", PCX, i, s);
}
}
}
else if (serviceDescriptor[0].ioSocket == 0) {
} else if (serviceDescriptor[0].ioSocket == 0) {
serviceDescriptor[0].ioSocket = sim_connect_sock(net_unit.filename, "localhost", "3000");
if (serviceDescriptor[0].ioSocket == INVALID_SOCKET)
return SCPE_IOERR;
@ -233,8 +231,7 @@ static t_stat net_svc(UNIT *uptr) {
serviceDescriptor[i].ioSocket = 0;
serviceDescriptor_reset(i);
continue;
}
else {
} else {
for (j = 0; j < r; j++) {
serviceDescriptor[i].inputBuffer[serviceDescriptor[i].inputPosWrite++] = svcBuffer[j];
if (serviceDescriptor[i].inputPosWrite == BUFFER_LENGTH)
@ -256,8 +253,7 @@ static t_stat net_svc(UNIT *uptr) {
serviceDescriptor[i].outputPosRead += r;
if (serviceDescriptor[i].outputPosRead >= BUFFER_LENGTH)
serviceDescriptor[i].outputPosRead -= BUFFER_LENGTH;
}
else
} else
sim_printf("write %i" NLP, r);
}
}
@ -291,8 +287,7 @@ int32 netData(const int32 port, const int32 io, const int32 data) {
sim_printf("re-read from %i" NLP, port);
result = serviceDescriptor[i].inputBuffer[serviceDescriptor[i].inputPosRead > 0 ?
serviceDescriptor[i].inputPosRead - 1 : BUFFER_LENGTH - 1];
}
else {
} else {
result = serviceDescriptor[i].inputBuffer[serviceDescriptor[i].inputPosRead++];
if (serviceDescriptor[i].inputPosRead == BUFFER_LENGTH)
serviceDescriptor[i].inputPosRead = 0;
@ -300,14 +295,12 @@ int32 netData(const int32 port, const int32 io, const int32 data) {
}
sim_debug(IN_MSG, &net_dev, "NET: " ADDRESS_FORMAT " IN(%i)=%03xh (%c)\n", PCX, port, (result & 0xff), (32 <= (result & 0xff)) && ((result & 0xff) <= 127) ? (result & 0xff) : '?');
return result;
}
else { /* OUT */
} else { /* OUT */
if (serviceDescriptor[i].outputSize == BUFFER_LENGTH) {
sim_printf("over-write %i to %i" NLP, data, port);
serviceDescriptor[i].outputBuffer[serviceDescriptor[i].outputPosWrite > 0 ?
serviceDescriptor[i].outputPosWrite - 1 : BUFFER_LENGTH - 1] = data;
}
else {
} else {
serviceDescriptor[i].outputBuffer[serviceDescriptor[i].outputPosWrite++] = data;
if (serviceDescriptor[i].outputPosWrite== BUFFER_LENGTH)
serviceDescriptor[i].outputPosWrite = 0;

125
AltairZ80/altairz80_sio.c
View file

@ -158,13 +158,14 @@ extern void setBankSelect(const int32 b);
extern uint32 getCommon(void);
extern uint8 GetBYTEWrapper(const uint32 Addr);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern uint32 getClockFrequency(void);
extern void setClockFrequency(const uint32 Value);
extern uint32 PCX;
extern int32 SR;
extern UNIT cpu_unit;
extern const char* handlerNameForPort(const int32 port);
/* Debug Flags */
static DEBTAB generic_dt[] = {
@ -576,16 +577,16 @@ static t_stat ptr_reset(DEVICE *dptr) {
ptr_unit.buf = 0;
if (ptr_unit.flags & UNIT_ATT) /* attached? */
rewind(ptr_unit.fileref);
sim_map_resource(0x12, 1, RESOURCE_TYPE_IO, &sio1s, dptr->flags & DEV_DIS);
sim_map_resource(0x13, 1, RESOURCE_TYPE_IO, &sio1d, dptr->flags & DEV_DIS);
sim_map_resource(0x12, 1, RESOURCE_TYPE_IO, &sio1s, "sio1s", dptr->flags & DEV_DIS);
sim_map_resource(0x13, 1, RESOURCE_TYPE_IO, &sio1d, "sio1d", dptr->flags & DEV_DIS);
return SCPE_OK;
}
static t_stat ptp_reset(DEVICE *dptr) {
sim_debug(VERBOSE_MSG, &ptp_dev, "PTP: " ADDRESS_FORMAT " Reset\n", PCX);
resetSIOWarningFlags();
sim_map_resource(0x12, 1, RESOURCE_TYPE_IO, &sio1s, dptr->flags & DEV_DIS);
sim_map_resource(0x13, 1, RESOURCE_TYPE_IO, &sio1d, dptr->flags & DEV_DIS);
sim_map_resource(0x12, 1, RESOURCE_TYPE_IO, &sio1s, "sio1s", dptr->flags & DEV_DIS);
sim_map_resource(0x13, 1, RESOURCE_TYPE_IO, &sio1d, "sio1d", dptr->flags & DEV_DIS);
return SCPE_OK;
}
@ -595,8 +596,7 @@ static int32 mapCharacter(int32 ch) {
if (sio_unit.flags & UNIT_SIO_BS) {
if (ch == BACKSPACE_CHAR)
return DELETE_CHAR;
}
else if (ch == DELETE_CHAR)
} else if (ch == DELETE_CHAR)
return BACKSPACE_CHAR;
if (sio_unit.flags & UNIT_SIO_UPPER)
return toupper(ch);
@ -757,8 +757,7 @@ static int32 sio0sCore(const int32 port, const int32 io, const int32 data) {
if (ch == EOF) {
sio_detach(&sio_unit); /* detach file and switch to keyboard input */
return spi.sio_cannot_read | spi.sio_can_write;
}
else {
} else {
sio_unit.u3 = TRUE; /* indicate character available */
sio_unit.buf = ch; /* store character in buffer */
return spi.sio_can_read | spi.sio_can_write;
@ -805,8 +804,7 @@ int32 sio0s(const int32 port, const int32 io, const int32 data) {
if (io == 0) {
sim_debug(IN_MSG, &sio_dev, "\tSIO_S: " ADDRESS_FORMAT
" IN(0x%03x) = 0x%02x\n", PCX, port, result);
}
else if (io) {
} else if (io) {
sim_debug(OUT_MSG, &sio_dev, "\tSIO_S: " ADDRESS_FORMAT
" OUT(0x%03x) = 0x%02x\n", PCX, port, data);
}
@ -836,8 +834,7 @@ static int32 sio0dCore(const int32 port, const int32 io, const int32 data) {
if ((sio_unit.flags & UNIT_ATT) && (!sio_unit.u4)) { /* attached to a port and not to a file */
tmxr_putc_ln(&TerminalLines[spi.terminalLine], ch); /* status ignored */
tmxr_poll_tx(&altairTMXR); /* poll xmt */
}
else
} else
sim_putchar(ch);
}
}
@ -858,8 +855,7 @@ int32 sio0d(const int32 port, const int32 io, const int32 data) {
if (io == 0) {
sim_debug(IN_MSG, &sio_dev, "\tSIO_D: " ADDRESS_FORMAT
" IN(0x%03x) = 0x%02x%s\n", PCX, port, result, printable(buffer, result, TRUE));
}
else if (io) {
} else if (io) {
sim_debug(OUT_MSG, &sio_dev, "\tSIO_D: " ADDRESS_FORMAT
" OUT(0x%03x) = 0x%02x%s\n", PCX, port, data, printable(buffer, data, FALSE));
}
@ -899,8 +895,7 @@ int32 sio1s(const int32 port, const int32 io, const int32 data) {
" IN(0x%02x) = 0x%02x\n", PCX, port, result);
sim_debug(IN_MSG, &ptp_dev, "PTP_S: " ADDRESS_FORMAT
" IN(0x%02x) = 0x%02x\n", PCX, port, result);
}
else if (io) {
} else if (io) {
sim_debug(OUT_MSG, &ptr_dev, "PTR_S: " ADDRESS_FORMAT
" OUT(0x%02x) = 0x%02x\n", PCX, port, data);
sim_debug(OUT_MSG, &ptp_dev, "PTP_S: " ADDRESS_FORMAT
@ -953,13 +948,12 @@ int32 sio1d(const int32 port, const int32 io, const int32 data) {
" IN(0x%02x) = 0x%02x\n", PCX, port, result);
sim_debug(IN_MSG, &ptp_dev, "PTP_D: " ADDRESS_FORMAT
" IN(0x%02x) = 0x%02x\n", PCX, port, result);
}
else if (io) {
} else if (io) {
sim_debug(OUT_MSG, &ptr_dev, "PTR_D: " ADDRESS_FORMAT
" OUT(0x%02x) = 0x%02x\n", PCX, port, data);
sim_debug(OUT_MSG, &ptp_dev, "PTP_D: " ADDRESS_FORMAT
" OUT(0x%02x) = 0x%02x\n", PCX, port, data);
}
}
return result;
}
@ -978,15 +972,17 @@ static t_stat toBool(char tf, int32 *result) {
static void show_sio_port_info(FILE *st, SIO_PORT_INFO sip) {
if (sio_unit.flags & UNIT_SIO_VERBOSE)
fprintf(st, "(Port=%02x/Terminal=%1i/Read=0x%02x/NotRead=0x%02x/"
"Write=0x%02x/Reset?=%s/Reset=0x%02x/Data?=%s)",
"Write=0x%02x/Reset?=%s/Reset=0x%02x/Data?=%s), %s",
sip.port, sip.terminalLine, sip.sio_can_read, sip.sio_cannot_read,
sip.sio_can_write, sip.hasReset ? "True" : "False", sip.sio_reset,
sip.hasOUT ? "True" : "False");
sip.hasOUT ? "True" : "False",
handlerNameForPort(sip.port));
else
fprintf(st, "(%02x/%1i/%02x/%02x/%02x/%s/%02x/%s)",
fprintf(st, "(%02x/%1i/%02x/%02x/%02x/%s/%02x/%s), %s",
sip.port, sip.terminalLine, sip.sio_can_read, sip.sio_cannot_read,
sip.sio_can_write, sip.hasReset ? "T" : "F", sip.sio_reset,
sip.hasOUT ? "T" : "F");
sip.hasOUT ? "T" : "F",
handlerNameForPort(sip.port));
}
static uint32 equalSIP(SIO_PORT_INFO x, SIO_PORT_INFO y) {
@ -998,7 +994,7 @@ static uint32 equalSIP(SIO_PORT_INFO x, SIO_PORT_INFO y) {
}
static t_stat sio_dev_set_port(UNIT *uptr, int32 value, CONST char *cptr, void *desc) {
int32 result, n, position;
int32 result, n, position, isDataPort;
SIO_PORT_INFO sip = { 0 }, old;
char hasReset, hasOUT;
if (cptr == NULL)
@ -1014,7 +1010,7 @@ static t_stat sio_dev_set_port(UNIT *uptr, int32 value, CONST char *cptr, void *
port_table[position] = port_table[position + 1];
position++;
} while (port_table[position].port != -1);
sim_map_resource(sip.port, 1, RESOURCE_TYPE_IO, &nulldev, FALSE);
sim_map_resource(sip.port, 1, RESOURCE_TYPE_IO, &nulldev, "nulldev", FALSE);
if (sio_unit.flags & UNIT_SIO_VERBOSE) {
sim_printf("Removing mapping for port 0x%02x.\n\t", sip.port);
show_sio_port_info(stdout, old);
@ -1036,6 +1032,8 @@ static t_stat sio_dev_set_port(UNIT *uptr, int32 value, CONST char *cptr, void *
sim_printf("Truncating port 0x%x to 0x%02x.\n", sip.port, sip.port & 0xff);
sip.port &= 0xff;
}
isDataPort = (sip.hasOUT || ((sip.sio_can_read == 0) && (sip.sio_cannot_read == 0) &&
(sip.sio_can_write == 0)));
old = lookupPortInfo(sip.port, &position);
if (old.port == sip.port) {
if (sio_unit.flags & UNIT_SIO_VERBOSE) {
@ -1044,10 +1042,9 @@ static t_stat sio_dev_set_port(UNIT *uptr, int32 value, CONST char *cptr, void *
sim_printf("-> ");
show_sio_port_info(stdout, sip);
if (equalSIP(sip, old))
sim_printf("[identical]");
sim_printf("[same definition, %s]", (isDataPort && (strcmp(handlerNameForPort(old.port), "sio0d") == 0)) || (!isDataPort && (strcmp(handlerNameForPort(old.port), "sio0s") == 0)) ? "same handler" : "different handler");
}
}
else {
} else {
port_table[position + 1] = old;
if (sio_unit.flags & UNIT_SIO_VERBOSE) {
sim_printf("Adding mapping for port 0x%02x.\n\t", sip.port);
@ -1057,9 +1054,8 @@ static t_stat sio_dev_set_port(UNIT *uptr, int32 value, CONST char *cptr, void *
if (sio_unit.flags & UNIT_SIO_VERBOSE)
sim_printf("\n");
port_table[position] = sip;
sim_map_resource(sip.port, 1, RESOURCE_TYPE_IO, (sip.hasOUT ||
((sip.sio_can_read == 0) && (sip.sio_cannot_read == 0) &&
(sip.sio_can_write == 0))) ? &sio0d : &sio0s, FALSE);
sim_map_resource(sip.port, 1, RESOURCE_TYPE_IO,
isDataPort ? &sio0d : &sio0s, isDataPort ? "sio0d" : "sio0s", FALSE);
return SCPE_OK;
}
@ -1103,7 +1099,8 @@ static void mapAltairPorts(void) {
do {
spi = port_table[i++];
if ((0x02 <= spi.port) && (spi.port <= 0x19))
sim_map_resource(spi.port, 1, RESOURCE_TYPE_IO, spi.hasOUT ? &sio0d : &sio0s, FALSE);
sim_map_resource(spi.port, 1, RESOURCE_TYPE_IO,
spi.hasOUT ? &sio0d : &sio0s, spi.hasOUT ? "sio0d" : "sio0s", FALSE);
} while (spi.port >= 0);
}
@ -1266,7 +1263,7 @@ static int32 showAvailability;
static int32 isInReadPhase;
static t_stat simh_dev_reset(DEVICE *dptr) {
sim_map_resource(0xfe, 1, RESOURCE_TYPE_IO, &simh_dev, dptr->flags & DEV_DIS);
sim_map_resource(0xfe, 1, RESOURCE_TYPE_IO, &simh_dev, "simh_dev", dptr->flags & DEV_DIS);
currentTimeValid = FALSE;
ClockZSDOSDelta = 0;
setClockZSDOSPos = 0;
@ -1421,12 +1418,10 @@ static int32 simh_in(const int32 port) {
urlResult = NULL;
lastCommand = 0;
}
}
else if (resultPointer < resultLength)
} else if (resultPointer < resultLength)
result = urlResult[resultPointer++];
showAvailability = 1 - showAvailability;
}
else
} else
lastCommand = 0;
break;
@ -1435,16 +1430,14 @@ static int32 simh_in(const int32 port) {
if (currentName == NULL) {
deleteNameList();
lastCommand = 0;
}
else if (firstPathCharacterIndex <= lastPathSeparatorIndex)
} else if (firstPathCharacterIndex <= lastPathSeparatorIndex)
result = cpmCommandLine[firstPathCharacterIndex++];
else {
result = currentName -> name[currentNameIndex];
if (result == 0) {
currentName = currentName -> next;
firstPathCharacterIndex = currentNameIndex = 0;
}
else
} else
currentNameIndex++;
}
}
@ -1549,8 +1542,7 @@ static int32 simh_in(const int32 port) {
if (getCommonPos == 0) {
result = getCommon() & 0xff;
getCommonPos = 1;
}
else {
} else {
result = (getCommon() >> 8) & 0xff;
getCommonPos = lastCommand = 0;
}
@ -1560,8 +1552,7 @@ static int32 simh_in(const int32 port) {
if (getClockFrequencyPos == 0) {
result = getClockFrequency() & 0xff;
getClockFrequencyPos = 1;
}
else {
} else {
result = (getClockFrequency() >> 8) & 0xff;
getClockFrequencyPos = lastCommand = 0;
}
@ -1576,8 +1567,7 @@ static int32 simh_in(const int32 port) {
if (getStopWatchDeltaPos == 0) {
result = stopWatchDelta & 0xff;
getStopWatchDeltaPos = 1;
}
else {
} else {
result = (stopWatchDelta >> 8) & 0xff;
getStopWatchDeltaPos = lastCommand = 0;
}
@ -1615,8 +1605,7 @@ static int32 simh_out(const int32 port, const int32 data) {
if (data) {
if (urlPointer < URL_MAX_LENGTH - 1)
urlStore[urlPointer++] = data & 0xff;
}
else {
} else {
if (urlResult != NULL)
free(urlResult);
urlStore[urlPointer] = 0;
@ -1632,8 +1621,7 @@ static int32 simh_out(const int32 port, const int32 data) {
if (setClockZSDOSPos == 0) {
setClockZSDOSAdr = data;
setClockZSDOSPos = 1;
}
else {
} else {
setClockZSDOSAdr |= (data << 8);
setClockZSDOS();
setClockZSDOSPos = lastCommand = 0;
@ -1644,8 +1632,7 @@ static int32 simh_out(const int32 port, const int32 data) {
if (setClockCPM3Pos == 0) {
setClockCPM3Adr = data;
setClockCPM3Pos = 1;
}
else {
} else {
setClockCPM3Adr |= (data << 8);
setClockCPM3();
setClockCPM3Pos = lastCommand = 0;
@ -1656,8 +1643,7 @@ static int32 simh_out(const int32 port, const int32 data) {
if (setClockFrequencyPos == 0) {
newClockFrequency = data;
setClockFrequencyPos = 1;
}
else {
} else {
setClockFrequency((data << 8) | newClockFrequency);
setClockFrequencyPos = lastCommand = 0;
}
@ -1677,8 +1663,7 @@ static int32 simh_out(const int32 port, const int32 data) {
if (setTimerDeltaPos == 0) {
timerDelta = data;
setTimerDeltaPos = 1;
}
else {
} else {
timerDelta |= (data << 8);
setTimerDeltaPos = lastCommand = 0;
if (timerDelta == 0) {
@ -1694,8 +1679,7 @@ static int32 simh_out(const int32 port, const int32 data) {
if (setTimerInterruptAdrPos == 0) {
timerInterruptHandler = data;
setTimerInterruptAdrPos = 1;
}
else {
} else {
timerInterruptHandler |= (data << 8);
setTimerInterruptAdrPos = lastCommand = 0;
}
@ -1758,8 +1742,8 @@ static int32 simh_out(const int32 port, const int32 data) {
markTime[markTimeSP++] = sim_os_msec();
else
sim_printf("SIMH: " ADDRESS_FORMAT " Timer stack overflow." NLP, PCX);
else
warnNoRealTimeClock();
else
warnNoRealTimeClock();
break;
case stopTimerCmd: /* stop timer on top of stack and show time difference */
@ -1767,11 +1751,10 @@ static int32 simh_out(const int32 port, const int32 data) {
if (markTimeSP > 0) {
uint32 delta = sim_os_msec() - markTime[--markTimeSP];
sim_printf("SIMH: " ADDRESS_FORMAT " Timer stopped. Elapsed time in milliseconds = %d." NLP, PCX, delta);
}
else
} else
sim_printf("SIMH: " ADDRESS_FORMAT " No timer active." NLP, PCX);
else
warnNoRealTimeClock();
else
warnNoRealTimeClock();
break;
case resetPTRCmd: /* reset ptr device */
@ -1844,11 +1827,10 @@ static int32 simh_out(const int32 port, const int32 data) {
if (markTimeSP > 0) {
uint32 delta = sim_os_msec() - markTime[markTimeSP - 1];
sim_printf("SIMH: " ADDRESS_FORMAT " Timer running. Elapsed in milliseconds = %d." NLP, PCX, delta);
}
else
} else
sim_printf("SIMH: " ADDRESS_FORMAT " No timer active." NLP, PCX);
else
warnNoRealTimeClock();
else
warnNoRealTimeClock();
break;
case attachPTPCmd: /* attach ptp to the file with name at beginning of CP/M command line */
@ -1915,8 +1897,7 @@ int32 simh_dev(const int32 port, const int32 io, const int32 data) {
port, result, result,
(32 <= (result & 0xff)) && ((result & 0xff) <= 127) ? (result & 0xff) : '?');
}
else {
} else {
sim_debug(OUT_MSG, &simh_device, "SIMH: " ADDRESS_FORMAT
" OUT(0x%02x) <- %i (0x%02x, '%c')\n", PCX,
port, data, data,

51
AltairZ80/altairz80_sys.c
View file

@ -420,8 +420,7 @@ static int32 DAsm(char *S, const uint32 *val, const int32 useZ80Mnemonics, const
Offset = val[B++];
J = 1;
T = MnemonicsXCB[val[B++]];
}
else
} else
T = MnemonicsXX[val[B++]];
break;
@ -437,8 +436,7 @@ static int32 DAsm(char *S, const uint32 *val, const int32 useZ80Mnemonics, const
printHex2(H, val[B++]);
strlcat(R, H, sizeof (R));
strlcat(R, T1 + 1, sizeof (R)); /* ok, since T1 is a short sub-string coming from one of the tables */
}
else
} else
strlcpy(R, T, sizeof (R)); /* ok, since T is a short string coming from one of the tables */
if ( (P = strchr(R, '%')) ) {
*P = C;
@ -452,8 +450,7 @@ static int32 DAsm(char *S, const uint32 *val, const int32 useZ80Mnemonics, const
printHex2(H, val[B++]);
strcat(S, H);
strcat(S, P + 1);
}
else if ( (P = strchr(R, '@')) ) {
} else if ( (P = strchr(R, '@')) ) {
strncpy(S, R, P - R);
S[P - R] = '\0';
if (!J)
@ -463,24 +460,21 @@ static int32 DAsm(char *S, const uint32 *val, const int32 useZ80Mnemonics, const
printHex2(H, J);
strcat(S, H);
strcat(S, P + 1);
}
else if ( (P = strchr(R, '$')) ) {
} else if ( (P = strchr(R, '$')) ) {
strncpy(S, R, P - R);
S[P - R] = '\0';
Offset = val[B++];
printHex4(H, (addr + 2 + (Offset & 0x80 ? (Offset - 256) : Offset)) & 0xFFFF);
strcat(S, H);
strcat(S, P + 1);
}
else if ( (P = strchr(R, '#')) ) {
} else if ( (P = strchr(R, '#')) ) {
strncpy(S, R, P - R);
S[P - R] = '\0';
printHex4(H, val[B] + 256 * val[B + 1]);
strcat(S, H);
strcat(S, P + 1);
B += 2;
}
else
} else
strcpy(S, R);
return(B);
}
@ -557,8 +551,7 @@ static int32 numok(char ch, const char **numString, const int32 minvalue,
else if (ch == '-') {
sign = -1;
ch = *(*numString)++;
}
else
} else
return FALSE;
}
if (!(base = checkbase(ch, *numString)))
@ -676,28 +669,23 @@ static int32 parse_X80(const char *cptr, const int32 addr, uint32 *val, const ch
val[1] = (0xff) & number;
val[2] = (0xff) & (number >> 8);
return -2; /* two additional bytes returned */
}
else if (star >= 0) {
} else if (star >= 0) {
val[1] = (0xff) & star;
return -1; /* one additional byte returned */
}
else if (at > -129)
} else if (at > -129)
if ((-128 <= at) && (at <= 127)) {
val[1] = (int8)(at);
return -1; /* one additional byte returned */
}
else
} else
return SCPE_ARG;
else if (dollar >= 0) {
dollar -= addr + 2; /* relative translation */
if ((-128 <= dollar) && (dollar <= 127)) {
val[1] = (int8)(dollar);
return -1; /* one additional byte returned */
}
else
} else
return SCPE_ARG;
}
else
} else
return SCPE_OK;
}
}
@ -720,8 +708,7 @@ static int32 parse_X80(const char *cptr, const int32 addr, uint32 *val, const ch
val[2] = (0xff) & number;
val[3] = (0xff) & (number >> 8);
return -3; /* three additional bytes returned */
}
else
} else
return -1; /* one additional byte returned */
}
}
@ -738,21 +725,17 @@ static int32 parse_X80(const char *cptr, const int32 addr, uint32 *val, const ch
val[2] = (0xff) & number;
val[3] = (0xff) & (number >> 8);
return -3; /* three additional bytes returned */
}
else if ((star >= 0) && (hat >= 0)) {
} else if ((star >= 0) && (hat >= 0)) {
val[2] = (0xff) & hat;
val[3] = (0xff) & star;
return -3; /* three additional bytes returned */
}
else if (star >= 0) {
} else if (star >= 0) {
val[2] = (0xff) & star;
return -2; /* two additional bytes returned */
}
else if (hat >= 0) {
} else if (hat >= 0) {
val[2] = (0xff) & hat;
return -2; /* two additional bytes returned */
}
else
} else
return -1; /* one additional byte returned */
}
}

14
AltairZ80/flashwriter2.c
View file

@ -52,7 +52,7 @@
extern int32 sio0s(const int32 port, const int32 io, const int32 data);
extern int32 sio0d(const int32 port, const int32 io, const int32 data);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
static char ansibuf[32];
@ -145,17 +145,17 @@ static t_stat fw2_attach(UNIT *uptr, CONST char *cptr)
fw2_info[i]->uptr = uptr;
fw2_info[i]->uptr->u3 = baseaddr;
if(sim_map_resource(baseaddr, FW2_CAPACITY, RESOURCE_TYPE_MEMORY, &fw2dev, FALSE) != 0) {
if(sim_map_resource(baseaddr, FW2_CAPACITY, RESOURCE_TYPE_MEMORY, &fw2dev, "fw2dev", FALSE) != 0) {
sim_printf("%s: error mapping MEM resource at 0x%04x\n", __FUNCTION__, baseaddr);
return SCPE_ARG;
}
if(sim_map_resource(0x00, 1, RESOURCE_TYPE_IO, &sio0s, FALSE) != 0) {
if(sim_map_resource(0x00, 1, RESOURCE_TYPE_IO, &sio0s, "sio0s", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, 0x00);
return SCPE_ARG;
}
if(sim_map_resource(0x01, 1, RESOURCE_TYPE_IO, &sio0d, FALSE) != 0) {
if(sim_map_resource(0x01, 1, RESOURCE_TYPE_IO, &sio0d, "sio0d", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, 0x01);
return SCPE_ARG;
}
@ -187,9 +187,9 @@ static t_stat fw2_detach(UNIT *uptr)
return SCPE_ARG;
/* Disconnect FlashWriter2: unmap memory and I/O resources */
sim_map_resource(fw2_info[i]->uptr->u3, FW2_CAPACITY, RESOURCE_TYPE_MEMORY, &fw2dev, TRUE);
sim_map_resource(0x00, 1, RESOURCE_TYPE_IO, &sio0s, TRUE);
sim_map_resource(0x01, 1, RESOURCE_TYPE_IO, &sio0d, TRUE);
sim_map_resource(fw2_info[i]->uptr->u3, FW2_CAPACITY, RESOURCE_TYPE_MEMORY, &fw2dev, "fw2dev", TRUE);
sim_map_resource(0x00, 1, RESOURCE_TYPE_IO, &sio0s, "sio0s", TRUE);
sim_map_resource(0x01, 1, RESOURCE_TYPE_IO, &sio0d, "sio0d", TRUE);
if(fw2_info[i]) {
free(fw2_info[i]);

6
AltairZ80/i8272.c
View file

@ -132,7 +132,7 @@ extern uint32 PCX;
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
/* These are needed for DMA. PIO Mode has not been implemented yet. */
extern void PutByteDMA(const uint32 Addr, const uint32 Value);
@ -235,10 +235,10 @@ static t_stat i8272_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &i8272dev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &i8272dev, "i8272dev", TRUE);
} else {
/* Connect I/O Ports at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &i8272dev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &i8272dev, "i8272dev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

6
AltairZ80/mfdc.c
View file

@ -66,7 +66,7 @@ extern uint32 PCX;
extern t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern int32 find_unit_index(UNIT *uptr);
static void MFDC_Command(uint8 cData);
@ -218,13 +218,13 @@ static t_stat mfdc_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) {
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &mdskdev, TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &mdskdev, "mdskdev", TRUE);
} else {
/* Connect MFDC at base address */
for(i = 0; i < MFDC_MAX_DRIVES; i++) {
mfdc_info->drive[i].uptr = &mfdc_dev.units[i];
}
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &mdskdev, FALSE) != 0) {
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &mdskdev, "mdskdev", FALSE) != 0) {
sim_printf("%s: error mapping resource at 0x%04x\n", __FUNCTION__, pnp->mem_base);
dptr->flags |= DEV_DIS;
return SCPE_ARG;

10
AltairZ80/n8vem.c
View file

@ -78,7 +78,7 @@ extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern uint32 PCX;
extern int32 find_unit_index (UNIT *uptr);
@ -170,18 +170,18 @@ static t_stat n8vem_reset(DEVICE *dptr)
sim_debug(VERBOSE_MSG, &n8vem_dev, "N8VEM: Reset.\n");
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &n8vemdev, TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &n8vem_mem, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &n8vemdev, "n8vemdev", TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &n8vem_mem, "n8vem_mem", TRUE);
free(n8vem_info->ram);
free(n8vem_info->rom);
} else {
/* Connect N8VEM at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &n8vemdev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &n8vemdev, "n8vemdev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
/* Connect N8VEM Memory (512K RAM, 1MB FLASH) */
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &n8vem_mem, FALSE) != 0) {
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &n8vem_mem, "n8vem_mem", FALSE) != 0) {
sim_printf("%s: error mapping MEM resource at 0x%04x\n", __FUNCTION__, pnp->mem_base);
return SCPE_ARG;
}

28
AltairZ80/s100_64fdc.c
View file

@ -86,7 +86,7 @@ extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
static t_stat cromfdc_svc (UNIT *uptr);
@ -1472,52 +1472,52 @@ static t_stat cromfdc_reset(DEVICE *dptr)
if(dptr->flags & DEV_DIS) { /* Disconnect ROM and I/O Ports */
if (cromfdc_hasProperty(UNIT_CROMFDC_ROM)) {
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &cromfdcrom, TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &cromfdcrom, "cromfdcrom", TRUE);
}
/* Unmap I/O Ports (0x3-4,0x5-9,0x34,0x40 */
sim_map_resource(0x03, 2, RESOURCE_TYPE_IO, &cromfdc_ext, TRUE);
sim_map_resource(0x05, 5, RESOURCE_TYPE_IO, &cromfdc_timer, TRUE);
sim_map_resource(0x34, 1, RESOURCE_TYPE_IO, &cromfdc_control, TRUE);
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &cromfdc_banksel, TRUE);
sim_map_resource(0x03, 2, RESOURCE_TYPE_IO, &cromfdc_ext, "cromfdc_ext", TRUE);
sim_map_resource(0x05, 5, RESOURCE_TYPE_IO, &cromfdc_timer, "cromfdc_timer", TRUE);
sim_map_resource(0x34, 1, RESOURCE_TYPE_IO, &cromfdc_control, "cromfdc_control", TRUE);
sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &cromfdc_banksel, "cromfdc_banksel", TRUE);
if(crofdc_type == 50) { /* CCS2422 */
sim_map_resource(0x26, 1, RESOURCE_TYPE_IO, &ccs2810_uart_status, TRUE);
sim_map_resource(0x26, 1, RESOURCE_TYPE_IO, &ccs2810_uart_status, "ccs2810_uart_status", TRUE);
}
} else {
/* Connect CROMFDC ROM at base address */
if (cromfdc_hasProperty(UNIT_CROMFDC_ROM)) {
if(cromfdc_hasProperty(UNIT_CROMFDC_ROM)) {
sim_debug(VERBOSE_MSG, &cromfdc_dev, "CROMFDC: ROM Enabled.\n");
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &cromfdcrom, FALSE) != 0) {
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &cromfdcrom, "cromfdcrom", FALSE) != 0) {
sim_printf("%s: error mapping MEM resource at 0x%04x" NLP, __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
} else
sim_debug(VERBOSE_MSG, &cromfdc_dev, "CROMFDC: ROM Disabled.\n");
/* Connect CROMFDC Interrupt, and Aux Disk Registers */
if(sim_map_resource(0x03, 0x02, RESOURCE_TYPE_IO, &cromfdc_ext, FALSE) != 0) {
if(sim_map_resource(0x03, 0x02, RESOURCE_TYPE_IO, &cromfdc_ext, "cromfdc_ext", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x" NLP, __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
/* Connect CROMFDC Timer Registers */
if(sim_map_resource(0x05, 0x05, RESOURCE_TYPE_IO, &cromfdc_timer, FALSE) != 0) {
if(sim_map_resource(0x05, 0x05, RESOURCE_TYPE_IO, &cromfdc_timer, "cromfdc_timer", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x" NLP, __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
/* Connect CROMFDC Disk Flags and Control Register */
if(sim_map_resource(0x34, 0x01, RESOURCE_TYPE_IO, &cromfdc_control, FALSE) != 0) {
if(sim_map_resource(0x34, 0x01, RESOURCE_TYPE_IO, &cromfdc_control, "cromfdc_control", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x" NLP, __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
/* Connect CROMFDC Bank Select Register */
if(sim_map_resource(0x40, 0x1, RESOURCE_TYPE_IO, &cromfdc_banksel, FALSE) != 0) {
if(sim_map_resource(0x40, 0x1, RESOURCE_TYPE_IO, &cromfdc_banksel, "cromfdc_banksel", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x" NLP, __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
/* Connect CCS 2810 UART Status Register (needed by MOSS 2.2 Monitor */
if(sim_map_resource(0x26, 0x01, RESOURCE_TYPE_IO, &ccs2810_uart_status, FALSE) != 0) {
if(sim_map_resource(0x26, 0x01, RESOURCE_TYPE_IO, &ccs2810_uart_status, "ccs2810_uart_status", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x" NLP, __FUNCTION__, pnp->io_base);
return SCPE_ARG;
} else {

22
AltairZ80/s100_adcs6.c
View file

@ -86,7 +86,7 @@ extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
static t_stat adcs6_svc (UNIT *uptr);
@ -399,18 +399,18 @@ static t_stat adcs6_reset(DEVICE *dptr)
if(dptr->flags & DEV_DIS) { /* Disconnect ROM and I/O Ports */
if (adcs6_hasProperty(UNIT_ADCS6_ROM)) {
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &adcs6rom, TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &adcs6rom, "adcs6rom", TRUE);
}
/* Unmap I/O Ports (0x3-4,0x5-9,0x34,0x40 */
sim_map_resource(0x10, 4, RESOURCE_TYPE_IO, &adcs6_dma, TRUE);
sim_map_resource(0x04, 8, RESOURCE_TYPE_IO, &adcs6_timer, TRUE);
sim_map_resource(0x14, 1, RESOURCE_TYPE_IO, &adcs6_control, TRUE);
sim_map_resource(0x15, 7, RESOURCE_TYPE_IO, &adcs6_banksel, TRUE);
sim_map_resource(0x10, 4, RESOURCE_TYPE_IO, &adcs6_dma, "adcs6_dma", TRUE);
sim_map_resource(0x04, 8, RESOURCE_TYPE_IO, &adcs6_timer, "adcs6_timer", TRUE);
sim_map_resource(0x14, 1, RESOURCE_TYPE_IO, &adcs6_control, "adcs6_control", TRUE);
sim_map_resource(0x15, 7, RESOURCE_TYPE_IO, &adcs6_banksel, "adcs6_banksel", TRUE);
} else {
/* Connect ADCS6 ROM at base address */
if (adcs6_hasProperty(UNIT_ADCS6_ROM)) {
sim_debug(VERBOSE_MSG, &adcs6_dev, "ADCS6: ROM Enabled.\n");
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &adcs6rom, FALSE) != 0) {
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &adcs6rom, "adcs6rom", FALSE) != 0) {
sim_printf("%s: error mapping MEM resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
@ -421,7 +421,7 @@ static t_stat adcs6_reset(DEVICE *dptr)
}
/* Connect ADCS6 FDC Synchronization / Drive / Density Register */
if(sim_map_resource(0x14, 0x01, RESOURCE_TYPE_IO, &adcs6_control, FALSE) != 0) {
if(sim_map_resource(0x14, 0x01, RESOURCE_TYPE_IO, &adcs6_control, "adcs6_control", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
@ -429,19 +429,19 @@ static t_stat adcs6_reset(DEVICE *dptr)
#ifdef ADCS6
/* Connect ADCS6 Interrupt, and Aux Disk Registers */
if(sim_map_resource(0x10, 0x04, RESOURCE_TYPE_IO, &adcs6_dma, FALSE) != 0) {
if(sim_map_resource(0x10, 0x04, RESOURCE_TYPE_IO, &adcs6_dma, "adcs6_dma", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
/* Connect ADCS6 Timer Registers */
if(sim_map_resource(0x04, 0x08, RESOURCE_TYPE_IO, &adcs6_timer, FALSE) != 0) {
if(sim_map_resource(0x04, 0x08, RESOURCE_TYPE_IO, &adcs6_timer, "adcs6_timer", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
#endif
/* Connect ADCS6 Memory Management / Bank Select Register */
if(sim_map_resource(0x15, 0x7, RESOURCE_TYPE_IO, &adcs6_banksel, FALSE) != 0) {
if(sim_map_resource(0x15, 0x7, RESOURCE_TYPE_IO, &adcs6_banksel, "adcs6_banksel", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

10
AltairZ80/s100_disk1a.c
View file

@ -76,7 +76,7 @@ extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern void raise_ss1_interrupt(uint8 intnum);
@ -719,18 +719,18 @@ static t_stat disk1a_reset(DEVICE *dptr)
if(dptr->flags & DEV_DIS) { /* Disconnect ROM and I/O Ports */
if (disk1a_hasProperty(UNIT_DISK1A_ROM))
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &disk1arom, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk1adev, TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &disk1arom, "disk1arom", TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk1adev, "disk1adev", TRUE);
} else {
/* Connect DISK1A ROM at base address */
if (disk1a_hasProperty(UNIT_DISK1A_ROM))
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &disk1arom, FALSE) != 0) {
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &disk1arom, "disk1arom", FALSE) != 0) {
sim_printf("%s: error mapping MEM resource at 0x%04x\n", __FUNCTION__, pnp->mem_base);
return SCPE_ARG;
}
/* Connect DISK1A at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk1adev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk1adev, "disk1adev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

6
AltairZ80/s100_disk2.c
View file

@ -116,7 +116,7 @@ extern uint32 PCX;
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern int32 selchan_dma(uint8 *buf, uint32 len);
extern int32 find_unit_index(UNIT *uptr);
extern void raise_ss1_interrupt(uint8 intnum);
@ -211,10 +211,10 @@ static t_stat disk2_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk2dev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk2dev, "disk2dev", TRUE);
} else {
/* Connect DISK2 at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk2dev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk2dev, "disk2dev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

8
AltairZ80/s100_disk3.c
View file

@ -173,7 +173,7 @@ extern uint32 PCX;
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern int32 find_unit_index(UNIT *uptr);
extern void raise_ss1_interrupt(uint8 intnum);
@ -253,7 +253,7 @@ static DEBTAB disk3_dt[] = {
{ "SEEK", SEEK_MSG, "Seek messages" },
{ "CMD", CMD_MSG, "Command messages" },
{ "READ", RD_DATA_MSG, "Read messages" },
{ "WRITE", WR_DATA_MSG, "Write messages" },
{ "WRITE", WR_DATA_MSG, "Write messages" },
{ "IRQ", IRQ_MSG, "IRQ messages" },
{ "VERBOSE", VERBOSE_MSG, "Verbose messages" },
{ "SPECIFY", SPECIFY_MSG, "Specify messages" },
@ -275,10 +275,10 @@ static t_stat disk3_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk3dev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk3dev, "disk3dev", TRUE);
} else {
/* Connect DISK3 at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk3dev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &disk3dev, "disk3dev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

6
AltairZ80/s100_fif.c
View file

@ -47,7 +47,7 @@ static const char* fif_description(DEVICE *dptr);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern uint8 GetBYTEWrapper(const uint32 Addr);
extern void PutBYTEWrapper(const uint32 Addr, const uint32 Value);
@ -155,10 +155,10 @@ static t_stat fif_reset(DEVICE *dptr)
current_disk = NUM_OF_DSK;
if(dptr->flags & DEV_DIS) {
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &fif_io, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &fif_io, "fif_io", TRUE);
} else {
/* Connect HDSK at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &fif_io, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &fif_io, "fif_io", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->mem_base);
dptr->flags |= DEV_DIS;
return SCPE_ARG;

6
AltairZ80/s100_hdc1001.c
View file

@ -93,7 +93,7 @@ extern uint32 PCX;
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern int32 find_unit_index(UNIT *uptr);
/* These are needed for DMA. */
@ -169,10 +169,10 @@ static t_stat hdc1001_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &hdc1001dev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &hdc1001dev, "hdc1001dev", TRUE);
} else {
/* Connect HDC1001 at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &hdc1001dev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &hdc1001dev, "hdc1001dev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

6
AltairZ80/s100_if3.c
View file

@ -74,7 +74,7 @@ static IF3_INFO if3_info_data = { { 0x0, 0, 0x10, 8 } };
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern uint32 PCX;
extern int32 sio0d(const int32 port, const int32 io, const int32 data);
@ -177,10 +177,10 @@ static t_stat if3_reset(DEVICE *dptr)
for(i=0;i<IF3_MAX_BOARDS;i++)
sim_cancel(&if3_unit[i]);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &if3dev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &if3dev, "if3dev", TRUE);
} else {
/* Connect IF3 at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &if3dev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &if3dev, "if3dev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

16
AltairZ80/s100_jadedd.c
View file

@ -195,7 +195,7 @@ extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern int32 find_unit_index(UNIT *uptr);
#define JADE_MAX_ADAPTERS 1
@ -534,22 +534,22 @@ t_stat jade_reset(DEVICE *dptr)
JADE_INFO *pInfo = (JADE_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pInfo->prom_base, pInfo->prom_size, RESOURCE_TYPE_MEMORY, &jadeprom, TRUE);
sim_map_resource(pInfo->mem_base, pInfo->mem_size, RESOURCE_TYPE_MEMORY, &jademem, TRUE);
sim_map_resource(pInfo->io_base, pInfo->io_size, RESOURCE_TYPE_IO, &jadedev, TRUE);
sim_map_resource(pInfo->prom_base, pInfo->prom_size, RESOURCE_TYPE_MEMORY, &jadeprom, "jadeprom", TRUE);
sim_map_resource(pInfo->mem_base, pInfo->mem_size, RESOURCE_TYPE_MEMORY, &jademem, "jademem", TRUE);
sim_map_resource(pInfo->io_base, pInfo->io_size, RESOURCE_TYPE_IO, &jadedev, "jadedev", TRUE);
} else {
if(pInfo->pe) {
if(sim_map_resource(pInfo->prom_base, pInfo->prom_size, RESOURCE_TYPE_MEMORY, &jadeprom, FALSE) != 0) {
if(sim_map_resource(pInfo->prom_base, pInfo->prom_size, RESOURCE_TYPE_MEMORY, &jadeprom, "jadeprom", FALSE) != 0) {
sim_debug(ERROR_MSG, &jade_dev, JADE_SNAME ": Error mapping MEM resource at 0x%04x" NLP, pInfo->prom_base);
return SCPE_ARG;
}
}
if(sim_map_resource(pInfo->mem_base, pInfo->mem_size, RESOURCE_TYPE_MEMORY, &jademem, FALSE) != 0) {
if(sim_map_resource(pInfo->mem_base, pInfo->mem_size, RESOURCE_TYPE_MEMORY, &jademem, "jademem", FALSE) != 0) {
sim_debug(ERROR_MSG, &jade_dev, JADE_SNAME ": Error mapping MEM resource at 0x%04x" NLP, pInfo->mem_base);
return SCPE_ARG;
}
/* Connect I/O Ports at base address */
if(sim_map_resource(pInfo->io_base, pInfo->io_size, RESOURCE_TYPE_IO, &jadedev, FALSE) != 0) {
if(sim_map_resource(pInfo->io_base, pInfo->io_size, RESOURCE_TYPE_IO, &jadedev, "jadedev", FALSE) != 0) {
sim_debug(ERROR_MSG, &jade_dev, JADE_SNAME ": Error mapping I/O resource at 0x%02x" NLP, pInfo->io_base);
return SCPE_ARG;
}
@ -739,7 +739,7 @@ static t_stat jade_set_prom(UNIT *uptr, int32 value, CONST char *cptr, void *des
/*
** Map/Unmap PROM
*/
sim_map_resource(pInfo->prom_base, pInfo->prom_size, RESOURCE_TYPE_MEMORY, &jadeprom, !value);
sim_map_resource(pInfo->prom_base, pInfo->prom_size, RESOURCE_TYPE_MEMORY, &jadeprom, "jadeprom", !value);
if (uptr->flags & UNIT_JADE_VERBOSE) {
sim_printf(JADE_SNAME ": PROM %s" NLP, (value) ? "enabled" : "disabled");

6
AltairZ80/s100_mdriveh.c
View file

@ -71,7 +71,7 @@ extern uint32 PCX;
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
#define UNIT_V_MDRIVEH_WLK (UNIT_V_UF + 0) /* write locked */
#define UNIT_MDRIVEH_WLK (1 << UNIT_V_MDRIVEH_WLK)
@ -151,10 +151,10 @@ static t_stat mdriveh_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect ROM and I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &mdrivehdev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &mdrivehdev, "mdrivehdev", TRUE);
} else {
/* Connect MDRIVEH at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &mdrivehdev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &mdrivehdev, "mdrivehdev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

6
AltairZ80/s100_mdsa.c
View file

@ -36,7 +36,7 @@ extern uint32 PCX;
extern t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
#define MDSA_MAX_DRIVES 3
#define MDSA_SECTOR_LEN 256
@ -210,11 +210,11 @@ t_stat mdsa_reset(DEVICE *dptr)
if(dptr->flags & DEV_DIS) {
sim_map_resource(pnp->mem_base, pnp->mem_size,
RESOURCE_TYPE_MEMORY, &mdsadev, TRUE);
RESOURCE_TYPE_MEMORY, &mdsadev, "mdsadev", TRUE);
} else {
/* Connect MDSA at base address */
if(sim_map_resource(pnp->mem_base, pnp->mem_size,
RESOURCE_TYPE_MEMORY, &mdsadev, FALSE) != 0) {
RESOURCE_TYPE_MEMORY, &mdsadev, "mdsadev", FALSE) != 0) {
printf("%s: error mapping resource at 0x%04x\n",
__FUNCTION__, pnp->mem_base);
dptr->flags |= DEV_DIS;

6
AltairZ80/s100_mdsad.c
View file

@ -65,7 +65,7 @@ extern uint32 PCX;
extern t_stat set_membase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
#define MDSAD_MAX_DRIVES 4
#define MDSAD_SECTOR_LEN 512
@ -274,11 +274,11 @@ static t_stat mdsad_reset(DEVICE *dptr)
if(dptr->flags & DEV_DIS) {
sim_map_resource(pnp->mem_base, pnp->mem_size,
RESOURCE_TYPE_MEMORY, &mdsaddev, TRUE);
RESOURCE_TYPE_MEMORY, &mdsaddev, "mdsaddev", TRUE);
} else {
/* Connect MDSAD at base address */
if(sim_map_resource(pnp->mem_base, pnp->mem_size,
RESOURCE_TYPE_MEMORY, &mdsaddev, FALSE) != 0) {
RESOURCE_TYPE_MEMORY, &mdsaddev, "mdsaddev", FALSE) != 0) {
sim_printf("%s: error mapping resource at 0x%04x\n",
__FUNCTION__, pnp->mem_base);
dptr->flags |= DEV_DIS;

10
AltairZ80/s100_scp300f.c
View file

@ -76,7 +76,7 @@ extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern uint32 PCX;
extern int32 find_unit_index (UNIT *uptr);
@ -138,16 +138,16 @@ static t_stat scp300f_reset(DEVICE *dptr)
sim_debug(VERBOSE_MSG, &scp300f_dev, "SCP300F: Reset.\n");
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &scp300fdev, TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &scp300f_mem, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &scp300fdev, "scp300fdev", TRUE);
sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &scp300f_mem, "scp300f_mem", TRUE);
} else {
/* Connect SCP300F at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &scp300fdev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &scp300fdev, "scp300fdev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}
/* Connect SCP300F Memory (512K RAM, 1MB FLASH) */
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &scp300f_mem, FALSE) != 0) {
if(sim_map_resource(pnp->mem_base, pnp->mem_size, RESOURCE_TYPE_MEMORY, &scp300f_mem, "scp300f_mem", FALSE) != 0) {
sim_printf("%s: error mapping MEM resource at 0x%04x\n", __FUNCTION__, pnp->mem_base);
return SCPE_ARG;
}

6
AltairZ80/s100_selchan.c
View file

@ -70,7 +70,7 @@ int32 selchan_dma(uint8 *buf, uint32 len);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern uint32 PCX;
/* These are needed for DMA. */
@ -125,10 +125,10 @@ static t_stat selchan_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, "selchandev", TRUE);
} else {
/* Connect SELCHAN at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, "selchandev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

6
AltairZ80/s100_ss1.c
View file

@ -72,7 +72,7 @@ static SS1_INFO ss1_info_data = { { 0x0, 0, 0x50, 16 } };
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern uint32 PCX;
static t_stat ss1_reset(DEVICE *ss1_dev);
@ -236,10 +236,10 @@ static t_stat ss1_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, "ss1dev", TRUE);
} else {
/* Connect SS1 at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, "ss1dev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
} else {

10
AltairZ80/s100_tarbell.c
View file

@ -42,7 +42,7 @@ extern t_stat show_membase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
#define TARBELL_MAX_ADAPTERS 1
#define TARBELL_MAX_DRIVES 4
@ -316,15 +316,15 @@ t_stat tarbell_reset(DEVICE *dptr)
UNIT *sio_uptr;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pInfo->pnp.mem_base, pInfo->pnp.mem_size, RESOURCE_TYPE_MEMORY, &tarbellprom, TRUE);
sim_map_resource(pInfo->pnp.io_base, pInfo->pnp.io_size, RESOURCE_TYPE_IO, &tarbelldev, TRUE);
sim_map_resource(pInfo->pnp.mem_base, pInfo->pnp.mem_size, RESOURCE_TYPE_MEMORY, &tarbellprom, "tarbellprom", TRUE);
sim_map_resource(pInfo->pnp.io_base, pInfo->pnp.io_size, RESOURCE_TYPE_IO, &tarbelldev, "tarbelldev", TRUE);
} else {
if(sim_map_resource(pInfo->pnp.mem_base, pInfo->pnp.mem_size, RESOURCE_TYPE_MEMORY, &tarbellprom, FALSE) != 0) {
if(sim_map_resource(pInfo->pnp.mem_base, pInfo->pnp.mem_size, RESOURCE_TYPE_MEMORY, &tarbellprom, "tarbellprom", FALSE) != 0) {
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": Error mapping MEM resource at 0x%04x" NLP, pInfo->pnp.mem_base);
return SCPE_ARG;
}
/* Connect I/O Ports at base address */
if(sim_map_resource(pInfo->pnp.io_base, pInfo->pnp.io_size, RESOURCE_TYPE_IO, &tarbelldev, FALSE) != 0) {
if(sim_map_resource(pInfo->pnp.io_base, pInfo->pnp.io_size, RESOURCE_TYPE_IO, &tarbelldev, "tarbelldev", FALSE) != 0) {
sim_debug(ERROR_MSG, &tarbell_dev, TARBELL_SNAME ": Error mapping I/O resource at 0x%02x" NLP, pInfo->pnp.io_base);
return SCPE_ARG;
}

6
AltairZ80/vfdhd.c
View file

@ -135,7 +135,7 @@ extern uint32 PCX;
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
#define UNIT_V_VFDHD_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
#define UNIT_VFDHD_VERBOSE (1 << UNIT_V_VFDHD_VERBOSE)
@ -209,10 +209,10 @@ static t_stat vfdhd_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) {
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &vfdhddev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &vfdhddev, "vfdhddev", TRUE);
} else {
/* Connect MFDC at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &vfdhddev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &vfdhddev, "vfdhddev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}

6
AltairZ80/wd179x.c
View file

@ -146,7 +146,7 @@ extern uint32 PCX;
extern t_stat set_iobase(UNIT *uptr, int32 val, CONST char *cptr, void *desc);
extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, CONST void *desc);
extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,
int32 (*routine)(const int32, const int32, const int32), uint8 unmap);
int32 (*routine)(const int32, const int32, const int32), const char* name, uint8 unmap);
extern int32 find_unit_index (UNIT *uptr);
t_stat wd179x_svc (UNIT *uptr);
@ -270,10 +270,10 @@ static t_stat wd179x_reset(DEVICE *dptr)
PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;
if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &wd179xdev, TRUE);
sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &wd179xdev, "wd179xdev", TRUE);
} else {
/* Connect I/O Ports at base address */
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &wd179xdev, FALSE) != 0) {
if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &wd179xdev, "wd179xdev", FALSE) != 0) {
sim_printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);
return SCPE_ARG;
}