Added new VAX750 simulator from Matt Burke

VAX/vax730_defs.h

@@ -124,6 +124,9 @@
 #define INITMEMSIZE     (1 << MAXMEMWIDTH)              /* initial memory size */
 #define MEMSIZE         (cpu_unit.capac)
 #define ADDR_IS_MEM(x)  (((uint32) (x)) < MEMSIZE)
+#define MEM_MODIFIERS   { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }
 
 /* Unibus I/O registers */
 

VAX/vax750_cmi.c

@@ -0,0 +1,736 @@
+/* vax750_cmi.c: VAX 11/750 CMI
+
+   Copyright (c) 2010-2011, Matt Burke
+   This module incorporates code from SimH, Copyright (c) 2004-2011, Robert M Supnik
+
+   Permission is hereby granted, free of charge, to any person obtaining a
+   copy of this software and associated documentation files (the "Software"),
+   to deal in the Software without restriction, including without limitation
+   the rights to use, copy, modify, merge, publish, distribute, sublicense,
+   and/or sell copies of the Software, and to permit persons to whom the
+   Software is furnished to do so, subject to the following conditions:
+
+   The above copyright notice and this permission notice shall be included in
+   all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+   THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+   Except as contained in this notice, the name(s) of the author(s) shall not be
+   used in advertising or otherwise to promote the sale, use or other dealings
+   in this Software without prior written authorization from the author(s).
+
+   This module contains the VAX 11/750 system-specific registers and devices.
+
+   cmi                  bus controller
+
+   21-Oct-2012  MB      First Version
+*/
+
+#include "vax_defs.h"
+
+/* 11/750 specific IPRs */
+
+#define CMIERR_CRD            0x00000001
+#define CMIERR_LEB            0x00000002
+#define CMIERR_RDS            0x00000004
+#define CMIERR_ME             0x00000008
+#define CMIERR_TBH            0x00000010
+#define CMIERR_TBG0DE         0x00000100
+#define CMIERR_TBG1DE         0x00000200
+#define CMIERR_TBG0TE         0x00000400
+#define CMIERR_TBG1TE         0x00000800
+#define CMIERR_V_MODE         16
+#define CMIERR_M_MODE         0x3
+#define CMIERR_MODE           (CMIERR_M_MODE << CMIERR_V_MODE)
+#define CMIERR_REF            0x00040000
+#define CMIERR_RM             0x00080000
+#define CMIERR_EN             0x00100000
+
+/* System registers */
+
+/* VAX-11/750 boot device definitions */
+
+struct boot_dev {
+    char                *name;
+    int32               code;
+    int32               let;
+    };
+
+uint32 nexus_req[NEXUS_HLVL];                           /* nexus int req */
+uint32 cmi_err = 0;
+uint32 cmi_cadr = 0;
+char cpu_boot_cmd[CBUFSIZE]  = { 0 };                   /* boot command */
+
+static t_stat (*nexusR[NEXUS_NUM])(int32 *dat, int32 ad, int32 md);
+static t_stat (*nexusW[NEXUS_NUM])(int32 dat, int32 ad, int32 md);
+
+static struct boot_dev boot_tab[] = {
+    { "RP", BOOT_MB, 0 },
+    { "HK", BOOT_HK, 0 },
+    { "RL", BOOT_RL, 0 },
+    { "RQ", BOOT_UDA, 1 << 24 },
+    { "TQ", BOOT_TK, 1 << 24 },
+    { "TD", BOOT_TD, 0 },
+    { NULL }
+    };
+
+extern int32 R[16];
+extern int32 PSL;
+extern int32 ASTLVL, SISR;
+extern int32 mapen, pme, trpirq;
+extern int32 in_ie;
+extern int32 mchk_va, mchk_ref;
+extern int32 crd_err, mem_err, hlt_pin;
+extern int32 tmr_int, tti_int, tto_int, csi_int, cso_int;
+extern jmp_buf save_env;
+extern int32 p1;
+extern int32 sim_switches;
+extern DEVICE *sim_devices[];
+extern FILE *sim_log;
+extern CTAB *sim_vm_cmd;
+
+t_stat cmi_reset (DEVICE *dptr);
+void cmi_set_tmo (void);
+t_stat vax750_boot (int32 flag, char *ptr);
+t_stat vax750_boot_parse (int32 flag, char *ptr);
+t_stat cpu_boot (int32 unitno, DEVICE *dptr);
+
+extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
+extern int32 iccs_rd (void);
+extern int32 nicr_rd (void);
+extern int32 icr_rd (t_bool interp);
+extern int32 todr_rd (void);
+extern int32 rxcs_rd (void);
+extern int32 rxdb_rd (void);
+extern int32 txcs_rd (void);
+extern int32 csrs_rd (void);
+extern int32 csrd_rd (void);
+extern int32 csts_rd (void);
+extern void iccs_wr (int32 dat);
+extern void nicr_wr (int32 dat);
+extern void todr_wr (int32 dat);
+extern void rxcs_wr (int32 dat);
+extern void txcs_wr (int32 dat);
+extern void txdb_wr (int32 dat);
+extern void csrs_wr (int32 dat);
+extern void csts_wr (int32 dat);
+extern void cstd_wr (int32 dat);
+extern void init_mbus_tab (void);
+extern void init_ubus_tab (void);
+extern t_stat build_mbus_tab (DEVICE *dptr, DIB *dibp);
+extern t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp);
+extern void uba_eval_int (void);
+extern int32 uba_get_ubvector (int32 lvl);
+extern void uba_ioreset (void);
+
+/* CMI data structures
+
+   cmi_dev      CMI device descriptor
+   cmi_unit     CMI unit
+   cmi_reg      CMI register list
+*/
+
+UNIT cmi_unit = { UDATA (NULL, 0, 0) };
+
+REG cmi_reg[] = {
+    { HRDATA (NREQ14, nexus_req[0], 16) },
+    { HRDATA (NREQ15, nexus_req[1], 16) },
+    { HRDATA (NREQ16, nexus_req[2], 16) },
+    { HRDATA (NREQ17, nexus_req[3], 16) },
+    { HRDATA (CMIERR, cmi_err, 32) },
+    { NULL }
+    };
+
+DEVICE cmi_dev = {
+    "CMI", &cmi_unit, cmi_reg, NULL,
+    1, 16, 16, 1, 16, 8,
+    NULL, NULL, &cmi_reset,
+    NULL, NULL, NULL,
+    NULL, 0
+    };
+
+/* Special boot command, overrides regular boot */
+
+CTAB vax750_cmd[] = {
+    { "BOOT", &vax750_boot, RU_BOOT,
+      "bo{ot} <device>{/R5:flg} boot device\n" },
+    { NULL }
+    };
+
+/* The VAX 11/750 has three sources of interrupts
+
+   - internal device interrupts (CPU, console, clock)
+   - nexus interupts (e.g., memory controller, MBA, UBA)
+   - external device interrupts (Unibus)
+
+   Internal devices vector to fixed SCB locations.
+
+   Nexus interrupts vector to an SCB location based on this
+   formula: SCB_NEXUS + ((IPL - 0x14) * 0x40) + (TR# * 0x4)
+
+   External device interrupts do not vector directly.
+   Instead, the interrupt handler for a given UBA IPL
+   reads a vector register that contains the Unibus vector
+   for that IPL.
+
+/* Find highest priority vectorable interrupt */
+
+int32 eval_int (void)
+{
+int32 ipl = PSL_GETIPL (PSL);
+int32 i, t;
+
+static const int32 sw_int_mask[IPL_SMAX] = {
+    0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0,                     /* 0 - 3 */
+    0xFFE0, 0xFFC0, 0xFF80, 0xFF00,                     /* 4 - 7 */
+    0xFE00, 0xFC00, 0xF800, 0xF000,                     /* 8 - B */
+    0xE000, 0xC000, 0x8000                              /* C - E */
+    };
+
+if (hlt_pin)                                            /* hlt pin int */
+    return IPL_HLTPIN;
+if ((ipl < IPL_MEMERR) && mem_err)                      /* mem err int */
+    return IPL_MEMERR;
+if ((ipl < IPL_CRDERR) && crd_err)                      /* crd err int */
+    return IPL_CRDERR;
+if ((ipl < IPL_CLKINT) && tmr_int)                      /* clock int */
+    return IPL_CLKINT;
+uba_eval_int ();                                        /* update UBA */
+for (i = IPL_HMAX; i >= IPL_HMIN; i--) {                /* chk hwre int */
+    if (i <= ipl)                                       /* at ipl? no int */
+        return 0;
+    if (nexus_req[i - IPL_HMIN])                        /* req != 0? int */
+        return i;
+    }
+if ((ipl < IPL_TTINT) && (tti_int || tto_int || csi_int || cso_int))          /* console int */
+    return IPL_TTINT;
+if (ipl >= IPL_SMAX)                                    /* ipl >= sw max? */
+    return 0;
+if ((t = SISR & sw_int_mask[ipl]) == 0)
+    return 0;       /* eligible req */
+for (i = IPL_SMAX; i > ipl; i--) {                      /* check swre int */
+    if ((t >> i) & 1)                                    /* req != 0? int */
+        return i;
+    }
+return 0;
+}
+
+/* Return vector for highest priority hardware interrupt at IPL lvl */
+
+int32 get_vector (int32 lvl)
+{
+int32 i, l;
+
+if (lvl == IPL_MEMERR) {                                /* mem error? */
+    mem_err = 0;
+    return SCB_MEMERR;
+    }
+if (lvl == IPL_CRDERR) {                                /* CRD error? */
+    crd_err = 0;
+    return SCB_CRDERR;
+    }
+if (lvl == IPL_CLKINT) {                                /* clock? */
+    tmr_int = 0;                                        /* clear req */
+    return SCB_INTTIM;                                  /* return vector */
+    }
+if (lvl > IPL_HMAX) {                                   /* error req lvl? */
+    ABORT (STOP_UIPL);                                  /* unknown intr */
+    }
+if ((lvl <= IPL_HMAX) && (lvl >= IPL_HMIN)) {           /* nexus? */
+    l = lvl - IPL_HMIN;
+    if (nexus_req[l] & (1u << TR_UBA)) {                /* unibus int? */
+        nexus_req[l] = nexus_req[l] & ~(1u << TR_UBA);
+        return uba_get_ubvector(l);
+        }
+    for (i = 0; nexus_req[l] && (i < NEXUS_NUM); i++) {
+        if ((nexus_req[l] >> i) & 1) {
+            nexus_req[l] = nexus_req[l] & ~(1u << i);
+            return SCB_NEXUS + (l << 6) + (i << 2);     /* return vector */
+            }
+        }
+    }
+if (lvl == IPL_TTINT) {                                 /* console? */
+    if (tti_int) {                                      /* input? */
+        tti_int = 0;                                    /* clear req */
+        return SCB_TTI;                                 /* return vector */
+        }
+    if (tto_int) {                                      /* output? */
+        tto_int = 0;                                    /* clear req */
+        return SCB_TTO;                                 /* return vector */
+        }
+    if (csi_int) {                                      /* input? */
+        csi_int = 0;                                    /* clear req */
+        return SCB_CSI;                                 /* return vector */
+        }
+    if (cso_int) {                                      /* output? */
+        cso_int = 0;                                    /* clear req */
+        return SCB_CSO;                                 /* return vector */
+        }
+    }
+return 0;
+}
+
+/* Read 750-specific IPR's */
+
+int32 ReadIPR (int32 rg)
+{
+int32 val;
+
+switch (rg) {
+
+    case MT_ICCS:                                       /* ICCS */
+        val = iccs_rd ();
+        break;
+
+    case MT_NICR:                                       /* NICR */
+        val = nicr_rd ();
+        break;
+
+    case MT_ICR:                                        /* ICR */
+        val = icr_rd (FALSE);
+        break;
+
+    case MT_TODR:                                       /* TODR */
+        val = todr_rd ();
+        break;
+
+    case MT_ACCS:                                       /* ACCS (not impl) */
+        val = 0;
+        break;
+
+    case MT_RXCS:                                       /* RXCS */
+        val = rxcs_rd ();
+        break;
+
+    case MT_RXDB:                                       /* RXDB */
+        val = rxdb_rd ();
+        break;
+
+    case MT_TXCS:                                       /* TXCS */
+        val = txcs_rd ();
+        break;
+
+    case MT_CADR:                                       /* CADR */
+        val = cmi_cadr;
+        break;
+
+    case MT_CAER:                                       /* CAER (not impl) */
+        val = 0;
+        break;
+
+    case MT_MCESR:                                      /* MCESR (not impl) */
+        val = 0;
+        break;
+
+    case MT_CMIE:                                       /* CMIE */
+        val = cmi_err;
+        break;
+
+    case MT_CSRS:                                       /* CSRS */
+        val = csrs_rd ();
+        break;
+        
+    case MT_CSRD:                                       /* CSRD */
+        val = csrd_rd ();
+        break;
+        
+    case MT_CSTS:                                       /* CSTS */
+        val = csts_rd ();
+        break;
+
+    case MT_TBDR:                                       /* TBDR */
+        val = 0;
+        break;
+
+    case MT_SID:                                        /* SID */
+        val = VAX750_SID | VAX750_MICRO | VAX750_HWREV;
+        break;
+
+    default:
+        RSVD_OPND_FAULT;
+        }
+
+return val;
+}
+
+/* Write 750-specific IPR's */
+
+void WriteIPR (int32 rg, int32 val)
+{
+switch (rg) {
+
+    case MT_ICCS:                                       /* ICCS */
+        iccs_wr (val);
+        break;
+
+    case MT_NICR:                                       /* NICR */
+        nicr_wr (val);
+        break;
+
+    case MT_TODR:                                       /* TODR */
+        todr_wr (val);
+        break;
+
+    case MT_ACCS:                                       /* ACCS (not impl) */
+        break;
+
+    case MT_RXCS:                                       /* RXCS */
+        rxcs_wr (val);
+        break;
+
+    case MT_TXCS:                                       /* TXCS */
+        txcs_wr (val);
+        break;
+
+    case MT_TXDB:                                       /* TXDB */
+        txdb_wr (val);
+        break;
+
+    case MT_CADR:                                       /* CADR */
+        cmi_cadr = (val & 0x1);
+        break;
+
+    case MT_CAER:                                       /* CAER (not impl) */
+        break;
+
+    case MT_MCESR:                                      /* MCESR (not impl) */
+        break;
+
+    case MT_IORESET:                                    /* IORESET */
+        uba_ioreset ();
+        break;
+
+    case MT_CSRS:                                       /* CSRS */
+        csrs_wr (val);
+        break;
+        
+    case MT_CSTS:                                       /* CSTS */
+        csts_wr (val);
+        break;
+        
+    case MT_CSTD:                                       /* CSTD */
+        cstd_wr (val);
+        break;
+
+    case MT_TBDR:                                       /* TBDR */
+        break;
+
+    default:
+        RSVD_OPND_FAULT;
+        }
+
+return;
+}
+
+/* ReadReg - read register space
+
+   Inputs:
+        pa      =       physical address
+        lnt     =       length (BWLQ)
+   Output:
+        longword of data
+*/
+
+int32 ReadReg (int32 pa, int32 lnt)
+{
+int32 nexus, val;
+
+if (ADDR_IS_REG (pa)) {                                 /* reg space? */
+    nexus = NEXUS_GETNEX (pa);                          /* get nexus */
+    if (nexusR[nexus] &&                                /* valid? */
+        (nexusR[nexus] (&val, pa, lnt) == SCPE_OK)) {
+        SET_IRQL;
+        return val;
+        }
+    }
+cmi_set_tmo ();                                         /* timeout */
+MACH_CHECK (MCHK_BPE);                                  /* machine check */
+return 0;
+} 
+
+/* WriteReg - write register space
+
+   Inputs:
+        pa      =       physical address
+        val     =       data to write, right justified in 32b longword
+        lnt     =       length (BWLQ)
+   Outputs:
+        none
+*/
+
+void WriteReg (int32 pa, int32 val, int32 lnt)
+{
+int32 nexus;
+
+if (ADDR_IS_REG (pa)) {                                 /* reg space? */
+    nexus = NEXUS_GETNEX (pa);                          /* get nexus */
+    if (nexusW[nexus] &&                                /* valid? */
+        (nexusW[nexus] (val, pa, lnt) == SCPE_OK)) {
+        SET_IRQL;
+        return;
+        }
+    }
+cmi_set_tmo ();                                         /* timeout */
+mem_err = 1;                                            /* interrupt */
+SET_IRQL;
+return;
+}
+
+/* Set CMI timeout */
+
+void cmi_set_tmo ()
+{
+if ((cmi_err & CMIERR_ME) == 0) {                       /* not yet set? */
+    if (mchk_ref == REF_V)                              /* virt? add mode */
+        cmi_err |= CMIERR_REF | (PSL_GETCUR (PSL) << CMIERR_V_MODE);
+    cmi_err |= CMIERR_ME;                               /* set tmo flag */
+    }
+else cmi_err |= CMIERR_LEB;                             /* yes, multiple */
+return;
+}
+
+/* Machine check
+
+   Error status word format
+   <2:0> =      ASTLVL
+   <3> =        PME
+   <6:4> =      arith trap code
+   Rest will be zero
+*/
+
+int32 machine_check (int32 p1, int32 opc, int32 cc, int32 delta)
+{
+int32 acc, err;
+err = (GET_TRAP (trpirq) << 4) | (pme << 3) | ASTLVL;   /* error word */
+if (p1 == MCHK_BPE)                                     /* bus error? */
+    cc = intexc (SCB_MCHK, cc, 0, IE_EXC);              /* take normal exception */
+else
+    cc = intexc (SCB_MCHK, cc, 0, IE_SVE);              /* take severe exception */
+acc = ACC_MASK (KERN);                                  /* in kernel mode */
+in_ie = 1;
+SP = SP - 44;                                           /* push 11 words */
+Write (SP, 40, L_LONG, WA);                             /* # bytes */
+Write (SP + 4, p1, L_LONG, WA);                         /* error code */
+Write (SP + 8, mchk_va, L_LONG, WA);                    /* VA register */
+Write (SP + 12, 0, L_LONG, WA);                         /* Fault PC */
+Write (SP + 16, 0, L_LONG, WA);                         /* MDR */
+Write (SP + 20, 0, L_LONG, WA);                         /* saved mode reg */
+Write (SP + 24, 0, L_LONG, WA);                         /* read lock timeout */
+Write (SP + 28, 0, L_LONG, WA);                         /* TB group parity error reg */
+Write (SP + 32, 0, L_LONG, WA);                         /* cache error reg */
+Write (SP + 36, cmi_err, L_LONG, WA);                   /* bus error reg */
+Write (SP + 40, 0, L_LONG, WA);                         /* MCESR */
+in_ie = 0;
+cmi_err = cmi_err & ~CMIERR_ME;                         /* clr CMIERR<me> etc */
+return cc;
+}
+
+/* Console entry - only reached if CONHALT is set (AUTORESTART is set) */
+
+int32 con_halt (int32 code, int32 cc)
+{
+if ((cpu_boot_cmd[0] == 0) ||                           /* saved boot cmd? */
+    (vax750_boot_parse (0, cpu_boot_cmd) != SCPE_OK) || /* reparse the boot cmd */ 
+    (reset_all (0) != SCPE_OK) ||                       /* reset the world */
+    (cpu_boot (0, NULL) != SCPE_OK))                    /* set up boot code */
+    ABORT (STOP_BOOT);                                  /* any error? */
+printf ("Rebooting...\n");
+if (sim_log)
+    fprintf (sim_log, "Rebooting...\n");
+return cc;
+}
+
+/* Special boot command - linked into SCP by initial reset
+
+   Syntax: BOOT <device>{/R5:val}
+
+   Sets up R0-R5, calls SCP boot processor with effective BOOT CPU
+*/
+
+t_stat vax750_boot (int32 flag, char *ptr)
+{
+t_stat r;
+
+r = vax750_boot_parse (flag, ptr);                      /* parse the boot cmd */
+if (r != SCPE_OK)                                       /* error? */
+    return r;
+strncpy (cpu_boot_cmd, ptr, CBUFSIZE);                  /* save for reboot */
+return run_cmd (flag, "CPU");
+}
+
+/* Parse boot command, set up registers - also used on reset */
+
+t_stat vax750_boot_parse (int32 flag, char *ptr)
+{
+char gbuf[CBUFSIZE];
+char *slptr, *regptr;
+int32 i, r5v, unitno;
+DEVICE *dptr;
+UNIT *uptr;
+DIB *dibp;
+uint32 ba;
+t_stat r;
+
+regptr = get_glyph (ptr, gbuf, 0);                      /* get glyph */
+if (slptr = strchr (gbuf, '/')) {                       /* found slash? */
+    regptr = strchr (ptr, '/');                         /* locate orig */
+    *slptr = 0;                                         /* zero in string */
+    }
+dptr = find_unit (gbuf, &uptr);                         /* find device */
+if ((dptr == NULL) || (uptr == NULL))
+    return SCPE_ARG;
+dibp = (DIB *) dptr->ctxt;                              /* get DIB */
+if (dibp == NULL)
+    ba = 0;
+else
+    ba = dibp->ba;
+unitno = (int32) (uptr - dptr->units);
+r5v = 0;
+if ((strncmp (regptr, "/R5:", 4) == 0) ||
+    (strncmp (regptr, "/R5=", 4) == 0) ||
+    (strncmp (regptr, "/r5:", 4) == 0) ||
+    (strncmp (regptr, "/r5=", 4) == 0)) {
+    r5v = (int32) get_uint (regptr + 4, 16, LMASK, &r);
+    if (r != SCPE_OK)
+        return r;
+    }
+else if (*regptr != 0)
+    return SCPE_ARG;
+for (i = 0; boot_tab[i].name != NULL; i++) {
+    if (strcmp (dptr->name, boot_tab[i].name) == 0) {
+        R[0] = boot_tab[i].code;
+        if (dptr->flags & DEV_MBUS) {
+            R[1] = (NEXUSBASE + (TR_MBA0 * NEXUSSIZE));
+            R[2] = unitno;
+            }
+        else {
+            R[1] = ba;
+            R[2] = (ba & UBADDRMASK);
+            }
+        R[3] = unitno;
+        R[4] = 0;
+        R[5] = r5v;
+        return SCPE_OK;
+        }
+    }
+return SCPE_NOFNC;
+}
+
+/* Bootstrap - finish up bootstrap process */
+
+t_stat cpu_boot (int32 unitno, DEVICE *dptr)
+{
+t_stat r;
+
+printf ("Loading boot code from vmb.exe\n");
+if (sim_log) fprintf (sim_log, 
+    "Loading boot code from vmb.exe\n");
+r = load_cmd (0, "-O vmb.exe 200");
+if (r != SCPE_OK)
+    return r;
+SP = PC = 512;
+return SCPE_OK;
+}
+
+/* CMI reset */
+
+t_stat cmi_reset (DEVICE *dptr)
+{
+sim_vm_cmd = vax750_cmd;
+cmi_err = CMIERR_EN;
+cmi_cadr = 0;
+return SCPE_OK;
+}
+
+/* Show nexus */
+
+t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc)
+{
+fprintf (st, "nexus=%d", val);
+return SCPE_OK;
+}
+
+/* Init nexus tables */
+
+void init_nexus_tab (void)
+{
+uint32 i;
+
+for (i = 0; i < NEXUS_NUM; i++) {
+    nexusR[i] = NULL;
+    nexusW[i] = NULL;
+    }
+return;
+}
+
+/* Build nexus tables
+
+   Inputs:
+        dptr    =       pointer to device
+        dibp    =       pointer to DIB
+   Outputs:
+        status
+*/
+
+
+t_stat build_nexus_tab (DEVICE *dptr, DIB *dibp)
+{
+uint32 idx;
+
+if ((dptr == NULL) || (dibp == NULL))
+    return SCPE_IERR;
+idx = dibp->ba;
+if (idx >= NEXUS_NUM)
+    return SCPE_IERR;
+if ((nexusR[idx] && dibp->rd &&                         /* conflict? */
+    (nexusR[idx] != dibp->rd)) ||
+    (nexusW[idx] && dibp->wr &&
+    (nexusW[idx] != dibp->wr))) {
+    printf ("Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba);
+    if (sim_log)
+        fprintf (sim_log, "Nexus %s conflict at %d\n", sim_dname (dptr), dibp->ba);
+    return SCPE_STOP;
+    }
+if (dibp->rd)                                           /* set rd dispatch */
+    nexusR[idx] = dibp->rd;
+if (dibp->wr)                                           /* set wr dispatch */
+    nexusW[idx] = dibp->wr;
+return SCPE_OK;
+}
+
+/* Build dib_tab from device list */
+
+t_stat build_dib_tab (void)
+{
+uint32 i;
+DEVICE *dptr;
+DIB *dibp;
+t_stat r;
+
+init_nexus_tab ();
+init_ubus_tab ();
+init_mbus_tab ();
+for (i = 0; (dptr = sim_devices[i]) != NULL; i++) {     /* loop thru dev */
+    dibp = (DIB *) dptr->ctxt;                          /* get DIB */
+    if (dibp && !(dptr->flags & DEV_DIS)) {             /* defined, enabled? */
+        if (dptr->flags & DEV_NEXUS) {                  /* Nexus? */
+            if (r = build_nexus_tab (dptr, dibp))       /* add to dispatch table */
+                return r;
+            }
+        else if (dptr->flags & DEV_MBUS) {              /* Massbus? */
+            if (r = build_mbus_tab (dptr, dibp))
+                return r;
+            }
+        else {                                          /* no, Unibus device */
+            if (r = build_ubus_tab (dptr, dibp))        /* add to dispatch tab */
+                return r;
+            }                                           /* end else */
+        }                                               /* end if enabled */
+    }                                                   /* end for */
+return SCPE_OK;
+}

VAX/vax750_defs.h

@@ -0,0 +1,453 @@
+/* vax750_defs.h: VAX 750 model-specific definitions file
+
+   Copyright (c) 2010-2011, Matt Burke
+   This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
+
+   Permission is hereby granted, free of charge, to any person obtaining a
+   copy of this software and associated documentation files (the "Software"),
+   to deal in the Software without restriction, including without limitation
+   the rights to use, copy, modify, merge, publish, distribute, sublicense,
+   and/or sell copies of the Software, and to permit persons to whom the
+   Software is furnished to do so, subject to the following conditions:
+
+   The above copyright notice and this permission notice shall be included in
+   all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+   THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+   Except as contained in this notice, the name(s) of the author(s) shall not be
+   used in advertising or otherwise to promote the sale, use or other dealings
+   in this Software without prior written authorization from the author(s).
+
+   21-Oct-2012  MB      First Version
+
+   This file covers the VAX 11/750, the second VAX.
+
+   System memory map
+
+          00 0000 - 7F FFFF             main memory
+          80 0000 - EF FFFF             reserved
+          F0 0000 - F0 FFFF             writeable control store
+          F1 0000 - F1 FFFF             reserved
+          F2 0000 - F2 0010             memory controller
+          F2 0400 - F2 07FF             bootstrap ROM
+          F2 8000 - F2 88FF             Massbus adapter 0
+          F2 A000 - F2 A8FF             Massbus adapter 1
+          F2 C000 - F2 C8FF             Massbus adapter 2
+          F3 0000 - F3 09FF             Unibus adapter 0
+          F3 2000 - F3 29FF             Unibus adapter 1
+*/
+
+#ifndef FULL_VAX
+#define FULL_VAX        1
+#endif
+
+#ifndef _VAX_750_DEFS_H_
+#define _VAX_750_DEFS_H_        1
+
+/* Microcode constructs */
+
+#define VAX750_SID      (2 << 24)                       /* system ID */
+#define VAX750_MICRO    (99 << 8)                       /* ucode revision */
+#define VAX750_HWREV    (156)                           /* hw revision */
+#define CON_HLTPIN      0x0200                          /* external CPU halt */
+#define CON_HLTINS      0x0600                          /* HALT instruction */
+#define MCHK_CSPE       0x01                            /* control store parity error */
+#define MCHK_BPE        0x02                            /* bus error or tb/cache parity error */
+#define VER_FPLA        0x0C                            /* FPLA version */
+#define VER_WCSP        (VER_FPLA)                      /* WCS primary version */
+#define VER_WCSS        0x12                            /* WCS secondary version */
+#define VER_PCS         ((VER_WCSS >> 4) & 0x3)         /* PCS version */
+
+/* Interrupts */
+
+#define IPL_HMAX        0x17                            /* highest hwre level */
+#define IPL_HMIN        0x14                            /* lowest hwre level */
+#define IPL_HLVL        (IPL_HMAX - IPL_HMIN + 1)       /* # hardware levels */
+#define IPL_SMAX        0xF                             /* highest swre level */
+
+/* Nexus constants */
+
+#define NEXUS_NUM       16                              /* number of nexus */
+#define MCTL_NUM        2                               /* number of mem ctrl */
+#define MBA_NUM         2                               /* number of MBA's */
+#define TR_MCTL         0                               /* nexus assignments */
+#define TR_MBA0         4
+#define TR_MBA1         5
+#define TR_UBA          8
+#define TR_CI           15
+#define NEXUS_HLVL      (IPL_HMAX - IPL_HMIN + 1)
+#define SCB_NEXUS       0x100                           /* nexus intr base */
+#define SBI_FAULTS      0xFC000000                      /* SBI fault flags */
+
+/* Internal I/O interrupts - relative except for clock and console */
+
+#define IPL_CLKINT      0x18                            /* clock IPL */
+#define IPL_TTINT       0x14                            /* console IPL */
+
+#define IPL_MCTL0       (0x15 - IPL_HMIN)
+#define IPL_MCTL1       (0x15 - IPL_HMIN)
+#define IPL_UBA         (0x15 - IPL_HMIN)
+#define IPL_MBA0        (0x15 - IPL_HMIN)
+#define IPL_MBA1        (0x15 - IPL_HMIN)
+#define IPL_CI          (0x15 - IPL_HMIN)
+
+/* Nexus interrupt macros */
+
+#define SET_NEXUS_INT(dv)       nexus_req[IPL_##dv] |= (1 << TR_##dv)
+#define CLR_NEXUS_INT(dv)       nexus_req[IPL_##dv] &= ~(1 << TR_##dv)
+
+/* Machine specific IPRs */
+
+#define MT_CSRS         28                              /* Console storage */
+#define MT_CSRD         29
+#define MT_CSTS         30
+#define MT_CSTD         31
+#define MT_CMIE         23                              /* CMI error */
+#define MT_TBDR         36                              /* TB disable */
+#define MT_CADR         37                              /* Cache disable */
+#define MT_MCESR        38                              /* MCHK err sts */
+#define MT_CAER         39                              /* Cache error */
+#define MT_ACCS         40                              /* FPA control */
+#define MT_IORESET      55                              /* Unibus Init */
+
+/* Machine specific reserved operand tests */
+
+/* 780 microcode patch 37 - only test LR<23:0> for appropriate length */
+
+#define ML_LR_TEST(r)   if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT
+
+/* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */
+
+#define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \
+                            ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT
+#define ML_SBR_TEST(r)  if ((((uint32)(r)) & 0xC0000003) != 0) RSVD_OPND_FAULT
+
+/* 780 microcode patch 78 - only test xCBB<1:0> = 0 */
+
+#define ML_PA_TEST(r)   if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT
+
+#define LP_AST_TEST(r)  if ((r) > AST_MAX) RSVD_OPND_FAULT
+#define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT
+#define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT
+
+/* Memory */
+
+#define MAXMEMWIDTH     21                              /* max mem, 16k chips */
+#define MAXMEMSIZE      (1 << MAXMEMWIDTH)
+#define MAXMEMWIDTH_X   23                              /* max mem, 64k chips */
+#define MAXMEMSIZE_X    (1 << MAXMEMWIDTH_X)
+#define INITMEMSIZE     (1 << MAXMEMWIDTH)              /* initial memory size */
+#define MEMSIZE         (cpu_unit.capac)
+#define ADDR_IS_MEM(x)  (((uint32) (x)) < MEMSIZE)
+#define MEM_MODIFIERS   { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }
+
+/* Unibus I/O registers */
+
+#define UBADDRWIDTH     18                              /* Unibus addr width */
+#define UBADDRSIZE      (1u << UBADDRWIDTH)             /* Unibus addr length */
+#define UBADDRMASK      (UBADDRSIZE - 1)                /* Unibus addr mask */
+#define IOPAGEAWIDTH    13                              /* IO addr width */
+#define IOPAGESIZE      (1u << IOPAGEAWIDTH)            /* IO page length */
+#define IOPAGEMASK      (IOPAGESIZE - 1)                /* IO addr mask */
+#define UBADDRBASE      0xFC0000                        /* Unibus addr base */
+#define IOPAGEBASE      0xFFE000                        /* IO page base */
+#define ADDR_IS_IO(x)   ((((uint32) (x)) >= UBADDRBASE) && \
+                        (((uint32) (x)) < (UBADDRBASE + UBADDRSIZE)))
+#define ADDR_IS_IOP(x)  (((uint32) (x)) >= IOPAGEBASE)
+
+/* Nexus register space */
+
+#define REGAWIDTH       19                              /* REG addr width */
+#define REG_V_NEXUS     13                              /* nexus number */
+#define REG_M_NEXUS     0xF
+#define REG_V_OFS       2                               /* register number */
+#define REG_M_OFS       0x7FF   
+#define REGSIZE         (1u << REGAWIDTH)               /* REG length */
+#define REGBASE         0xF00000                        /* REG addr base */
+#define ADDR_IS_REG(x)  ((((uint32) (x)) >= REGBASE) && \
+                        (((uint32) (x)) < (REGBASE + REGSIZE)))
+#define NEXUSBASE       (REGBASE + 0x20000)
+#define NEXUSSIZE       0x2000
+#define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS)
+#define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS)
+
+/* ROM address space in memory controllers */
+
+#define ROMAWIDTH       12                              /* ROM addr width */
+#define ROMSIZE         (1u << ROMAWIDTH)               /* ROM size */
+#define ROMBASE         (REGBASE + (TR_MCTL << REG_V_NEXUS) + 0x400)
+#define ADDR_IS_ROM(x)  ((((uint32) (x)) >= ROMBASE) && \
+                        (((uint32) (x)) < (ROMBASE + ROMSIZE)))
+
+/* Other address spaces */
+
+#define ADDR_IS_CDG(x)  (0)
+#define ADDR_IS_NVR(x)  (0)
+
+/* Unibus I/O modes */
+
+#define READ            0                               /* PDP-11 compatibility */
+#define WRITE           (L_WORD)
+#define WRITEB          (L_BYTE)
+
+/* Common CSI flags */
+
+#define CSR_V_GO        0                               /* go */
+#define CSR_V_IE        6                               /* interrupt enable */
+#define CSR_V_DONE      7                               /* done */
+#define CSR_V_BUSY      11                              /* busy */
+#define CSR_V_ERR       15                              /* error */
+#define CSR_GO          (1u << CSR_V_GO)
+#define CSR_IE          (1u << CSR_V_IE)
+#define CSR_DONE        (1u << CSR_V_DONE)
+#define CSR_BUSY        (1u << CSR_V_BUSY)
+#define CSR_ERR         (1u << CSR_V_ERR)
+
+/* Timers */
+
+#define TMR_CLK         0                               /* 100Hz clock */
+
+/* I/O system definitions */
+
+#define DZ_MUXES        4                               /* max # of DZV muxes */
+#define DZ_LINES        8                               /* lines per DZV mux */
+#define VH_MUXES        4                               /* max # of DHQ muxes */
+#define DLX_LINES       16                              /* max # of KL11/DL11's */
+#define DCX_LINES       16                              /* max # of DC11's */
+#define MT_MAXFR        (1 << 16)                       /* magtape max rec */
+
+#define DEV_V_UBUS      (DEV_V_UF + 0)                  /* Unibus */
+#define DEV_V_MBUS      (DEV_V_UF + 1)                  /* Massbus */
+#define DEV_V_NEXUS     (DEV_V_UF + 2)                  /* Nexus */
+#define DEV_V_FLTA      (DEV_V_UF + 3)                  /* flt addr */
+#define DEV_V_CI        (DEV_V_UF + 4)                  /* CI */
+#define DEV_V_FFUF      (DEV_V_UF + 5)                  /* first free flag */
+#define DEV_UBUS        (1u << DEV_V_UBUS)
+#define DEV_MBUS        (1u << DEV_V_MBUS)
+#define DEV_NEXUS       (1u << DEV_V_NEXUS)
+#define DEV_CI          (1u << DEV_V_CI)
+#define DEV_FLTA        (1u << DEV_V_FLTA)
+#define DEV_QBUS        (0)
+#define DEV_Q18         (0)
+
+#define UNIBUS          TRUE                            /* Unibus only */
+
+#define DEV_RDX         16                              /* default device radix */
+
+/* Device information block 
+
+   For Massbus devices,
+        ba      =       Massbus number
+        lnt     =       Massbus ctrl type
+        ack[0]  =       abort routine
+
+   For Nexus devices,
+        ba      =       Nexus number
+        lnt     =       number of consecutive nexi */
+
+#define VEC_DEVMAX      4                               /* max device vec */
+
+typedef struct {
+    uint32              ba;                             /* base addr */
+    uint32              lnt;                            /* length */
+    t_stat              (*rd)(int32 *dat, int32 ad, int32 md);
+    t_stat              (*wr)(int32 dat, int32 ad, int32 md);
+    int32               vnum;                           /* vectors: number */
+    int32               vloc;                           /* locator */
+    int32               vec;                            /* value */
+    int32               (*ack[VEC_DEVMAX])(void);       /* ack routine */
+    } DIB;
+
+/* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's
+   Massbus devices (RP, TU) do not appear in the Unibus IO page */
+
+#define IOBA_DZ         (IOPAGEBASE + 000100)           /* DZ11 */
+#define IOLN_DZ         010
+#define IOBA_XUB        (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))
+#define IOLN_XUB        010
+#define IOBA_RQB        (IOPAGEBASE + 000334 +  (020 * (DZ_MUXES / 2)))
+#define IOLN_RQB        004
+#define IOBA_RQC        (IOPAGEBASE + IOBA_RQB + IOLN_RQB)
+#define IOLN_RQC        004
+#define IOBA_RQD        (IOPAGEBASE + IOBA_RQC + IOLN_RQC)
+#define IOLN_RQD        004
+#define IOBA_RQ         (IOPAGEBASE + 012150)           /* UDA50 */
+#define IOLN_RQ         004
+#define IOBA_TS         (IOPAGEBASE + 012520)           /* TS11 */
+#define IOLN_TS         004
+#define IOBA_RL         (IOPAGEBASE + 014400)           /* RL11 */
+#define IOLN_RL         012
+#define IOBA_XQ         (IOPAGEBASE + 014440)           /* DEQNA/DELQA */
+#define IOLN_XQ         020
+#define IOBA_XQB        (IOPAGEBASE + 014460)           /* 2nd DEQNA/DELQA */
+#define IOLN_XQB        020
+#define IOBA_TQ         (IOPAGEBASE + 014500)           /* TMSCP */
+#define IOLN_TQ         004
+#define IOBA_XU         (IOPAGEBASE + 014510)           /* DEUNA/DELUA */
+#define IOLN_XU         010
+#define IOBA_CR         (IOPAGEBASE + 017160)           /* CD/CR/CM */
+#define IOLN_CR         010
+#define IOBA_RX         (IOPAGEBASE + 017170)           /* RX11 */
+#define IOLN_RX         004
+#define IOBA_RY         (IOPAGEBASE + 017170)           /* RXV21 */
+#define IOLN_RY         004
+#define IOBA_QDSS       (IOPAGEBASE + 017400)           /* QDSS */
+#define IOLN_QDSS       002
+#define IOBA_HK         (IOPAGEBASE + 017440)           /* RK611 */
+#define IOLN_HK         040
+#define IOBA_LPT        (IOPAGEBASE + 017514)           /* LP11 */
+#define IOLN_LPT        004
+#define IOBA_PTR        (IOPAGEBASE + 017550)           /* PC11 reader */
+#define IOLN_PTR        004
+#define IOBA_PTP        (IOPAGEBASE + 017554)           /* PC11 punch */
+#define IOLN_PTP        004
+
+/* Interrupt assignments; within each level, priority is right to left */
+
+#define INT_V_DZRX      0                               /* BR5 */
+#define INT_V_DZTX      1
+#define INT_V_HK        2
+#define INT_V_RL        3
+#define INT_V_RQ        4
+#define INT_V_TQ        5
+#define INT_V_TS        6
+#define INT_V_RY        7
+#define INT_V_XU        8
+
+#define INT_V_LPT       0                               /* BR4 */
+#define INT_V_PTR       1
+#define INT_V_PTP       2
+#define INT_V_CR        3
+
+#define INT_DZRX        (1u << INT_V_DZRX)
+#define INT_DZTX        (1u << INT_V_DZTX)
+#define INT_HK          (1u << INT_V_HK)
+#define INT_RL          (1u << INT_V_RL)
+#define INT_RQ          (1u << INT_V_RQ)
+#define INT_TQ          (1u << INT_V_TQ)
+#define INT_TS          (1u << INT_V_TS)
+#define INT_RY          (1u << INT_V_RY)
+#define INT_XU          (1u << INT_V_XU)
+#define INT_LPT         (1u << INT_V_LPT)
+#define INT_PTR         (1u << INT_V_PTR)
+#define INT_PTP         (1u << INT_V_PTP)
+#define INT_CR          (1u << INT_V_CR)
+
+#define IPL_DZRX        (0x15 - IPL_HMIN)
+#define IPL_DZTX        (0x15 - IPL_HMIN)
+#define IPL_HK          (0x15 - IPL_HMIN)
+#define IPL_RL          (0x15 - IPL_HMIN)
+#define IPL_RQ          (0x15 - IPL_HMIN)
+#define IPL_TQ          (0x15 - IPL_HMIN)
+#define IPL_TS          (0x15 - IPL_HMIN)
+#define IPL_RY          (0x15 - IPL_HMIN)
+#define IPL_XU          (0x15 - IPL_HMIN)
+#define IPL_LPT         (0x14 - IPL_HMIN)
+#define IPL_PTR         (0x14 - IPL_HMIN)
+#define IPL_PTP         (0x14 - IPL_HMIN)
+#define IPL_CR          (0x14 - IPL_HMIN)
+
+/* Device vectors */
+
+#define VEC_QBUS        0
+#define VEC_Q           0x200
+#define VEC_PTR         (VEC_Q + 0070)
+#define VEC_PTP         (VEC_Q + 0074)
+#define VEC_XQ          (VEC_Q + 0120)
+#define VEC_XU          (VEC_Q + 0120)
+#define VEC_RQ          (VEC_Q + 0154)
+#define VEC_RL          (VEC_Q + 0160)
+#define VEC_LPT         (VEC_Q + 0200)
+#define VEC_HK          (VEC_Q + 0210)
+#define VEC_TS          (VEC_Q + 0224)
+#define VEC_CR          (VEC_Q + 0230)
+#define VEC_TQ          (VEC_Q + 0260)
+#define VEC_RX          (VEC_Q + 0264)
+#define VEC_RY          (VEC_Q + 0264)
+#define VEC_DZRX        (VEC_Q + 0300)
+#define VEC_DZTX        (VEC_Q + 0304)
+
+/* Interrupt macros */
+
+#define IVCL(dv)        ((IPL_##dv * 32) + INT_V_##dv)
+#define NVCL(dv)        ((IPL_##dv * 32) + TR_##dv)
+#define IREQ(dv)        int_req[IPL_##dv]
+#define SET_INT(dv)     int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
+#define CLR_INT(dv)     int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
+#define IORETURN(f,v)   ((f)? (v): SCPE_OK)             /* cond error return */
+
+/* Logging */
+
+#define LOG_CPU_I       0x1                             /* intexc */
+#define LOG_CPU_R       0x2                             /* REI */
+#define LOG_CPU_P       0x4                             /* context */
+
+/* Massbus definitions */
+
+#define MBA_RP          (TR_MBA0 - TR_MBA0)             /* MBA for RP */
+#define MBA_TU          (TR_MBA1 - TR_MBA0)             /* MBA for TU */
+#define MBA_RMASK       0x1F                            /* max 32 reg */
+#define MBE_NXD         1                               /* nx drive */
+#define MBE_NXR         2                               /* nx reg */
+#define MBE_GOE         3                               /* err on GO */
+
+/* Boot definitions */
+
+#define BOOT_MB         0                               /* device codes */
+#define BOOT_HK         1                               /* for VMB */
+#define BOOT_RL         2
+#define BOOT_UDA        17
+#define BOOT_TK         18
+#define BOOT_CI         32
+#define BOOT_TD         64
+
+/* Function prototypes for virtual memory interface */
+
+int32 Read (uint32 va, int32 lnt, int32 acc);
+void Write (uint32 va, int32 val, int32 lnt, int32 acc);
+
+/* Function prototypes for physical memory interface (inlined) */
+
+SIM_INLINE int32 ReadB (uint32 pa);
+SIM_INLINE int32 ReadW (uint32 pa);
+SIM_INLINE int32 ReadL (uint32 pa);
+SIM_INLINE int32 ReadLP (uint32 pa);
+SIM_INLINE void WriteB (uint32 pa, int32 val);
+SIM_INLINE void WriteW (uint32 pa, int32 val);
+SIM_INLINE void WriteL (uint32 pa, int32 val);
+void WriteLP (uint32 pa, int32 val);
+
+/* Function prototypes for I/O */
+
+int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
+int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
+int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);
+int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);
+
+int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf);
+int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf);
+int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf);
+int32 mba_get_bc (uint32 mbus);
+void mba_upd_ata (uint32 mbus, uint32 val);
+void mba_set_exc (uint32 mbus);
+void mba_set_don (uint32 mbus);
+void mba_set_enbdis (uint32 mbus, t_bool dis);
+t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc);
+
+t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);
+
+void sbi_set_errcnf (void);
+int32 clk_cosched (int32 wait);
+
+#include "pdp11_io_lib.h"
+
+#endif

VAX/vax750_mem.c

@@ -0,0 +1,207 @@
+/* vax750_mem.c: VAX 11/750 memory controllers
+
+   Copyright (c) 2010-2012, Matt Burke
+
+   Permission is hereby granted, free of charge, to any person obtaining a
+   copy of this software and associated documentation files (the "Software"),
+   to deal in the Software without restriction, including without limitation
+   the rights to use, copy, modify, merge, publish, distribute, sublicense,
+   and/or sell copies of the Software, and to permit persons to whom the
+   Software is furnished to do so, subject to the following conditions:
+
+   The above copyright notice and this permission notice shall be included in
+   all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+   THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+   Except as contained in this notice, the name of the author shall not be
+   used in advertising or otherwise to promote the sale, use or other dealings
+   in this Software without prior written authorization from the author.
+
+   mctl               MS750 memory controller
+
+   21-Oct-2012  MB      First Version
+*/
+
+#include "vax_defs.h"
+
+/* Memory adapter register 0 */
+
+#define MCSR0_OF        0x00
+#define MCSR0_ES        0x0000007F                      /* Error syndrome */
+#define MCSR0_V_EP      9
+#define MCSR0_M_EP      0x7FFF
+#define MCSR0_EP        (MCSR0_M_EP << MCSR0_V_EP)      /* Error page */
+#define MCSR0_CRD       0x20000000                      /* Corrected read data */
+#define MCSR0_RDSH      0x40000000                      /* Read data subs high */
+#define MCSR0_RDS       0x80000000                      /* Read data substitute */
+#define MCSR0_RS        (MCSR0_CRD | MCSR0_RDSH | MCSR0_RDS)
+
+/* Memory adapter register 1 */
+
+#define MCSR1_OF        0x01
+#define MCSR1_CS        0x0000007F                      /* Check syndrome */
+#define MCSR1_V_EP      9
+#define MCSR1_M_EP      0x7FFF
+#define MCSR1_EP        (MCSR1_M_EP << MCSR1_V_EP)      /* Page mode address */
+#define MCSR1_ECCD      0x02000000                      /* ECC disable */
+#define MCSR1_DIAG      0x04000000                      /* Diag mode */
+#define MCSR1_PM        0x08000000                      /* Page mode */
+#define MCSR1_CRE       0x10000000                      /* CRD enable */
+#define MCSR1_RW        (MCSR1_CS | MCSR1_ECCD | MCSR1_DIAG | \
+                         MCSR1_PM | MCSR1_CRE)
+
+/* Memory adapter register 2 */
+
+#define MCSR2_OF        0x02
+#define MCSR2_M_MAP     0xFFFF                          /* Memory present */
+#define MCSR2_INIT      0x00010000                      /* Cold/warm restart flag */
+#define MCSR2_V_SA      17
+#define MCSR2_M_SA      0x7F                            /* Start address */
+#define MCSR2_V_CS      24
+#define MCSR2_CS        (1u << MCSR2_V_CS)              /* Chip size */
+#define MCSR2_MBZ       0xFF000000
+
+/* Debug switches */
+
+#define MCTL_DEB_RRD     0x01                            /* reg reads */
+#define MCTL_DEB_RWR     0x02                            /* reg writes */
+
+#define MEM_SIZE_16K    (1u << 17)                       /* Board size (16k chips) */
+#define MEM_SIZE_64K    (1u << 19)                       /* Board size (64k chips) */
+#define MEM_BOARD_MASK(x,y)  ((1u << (uint32)(x/y)) - 1)
+#define MEM_64K_MASK     0x5555
+
+extern UNIT cpu_unit;
+extern FILE *sim_log, *sim_deb;
+
+uint32 mcsr0 = 0;
+uint32 mcsr1 = 0;
+uint32 mcsr2 = 0;
+
+t_stat mctl_reset (DEVICE *dptr);
+t_stat mctl_rdreg (int32 *val, int32 pa, int32 mode);
+t_stat mctl_wrreg (int32 val, int32 pa, int32 mode);
+
+/* MCTL data structures
+
+   mctl_dev    MCTL device descriptor
+   mctl_unit   MCTL unit
+   mctl_reg    MCTL register list
+*/
+
+DIB mctl_dib[] = { TR_MCTL, 0, &mctl_rdreg, &mctl_wrreg, 0 };
+
+UNIT mctl_unit = { UDATA (NULL, 0, 0) };
+
+REG mctl_reg[] = {
+    { NULL }
+    };
+
+MTAB mctl_mod[] = {
+    { MTAB_XTD|MTAB_VDV, TR_MCTL, "NEXUS", NULL,
+      NULL, &show_nexus },
+    { 0 }
+    };
+
+DEBTAB mctl_deb[] = {
+    { "REGREAD", MCTL_DEB_RRD },
+    { "REGWRITE", MCTL_DEB_RWR },
+    { NULL, 0 }
+    };
+
+DEVICE mctl_dev = {
+    "MCTL", &mctl_unit, mctl_reg, mctl_mod,
+    1, 16, 16, 1, 16, 8,
+    NULL, NULL, &mctl_reset,
+    NULL, NULL, NULL,
+    &mctl_dib, DEV_NEXUS | DEV_DEBUG, 0,
+    mctl_deb, 0, 0
+    };
+
+/* Memory controller register read */
+
+t_stat mctl_rdreg (int32 *val, int32 pa, int32 lnt)
+{
+int32 ofs;
+ofs = NEXUS_GETOFS (pa);                                /* get offset */
+
+switch (ofs) {                                          /* case on offset */
+
+    case MCSR0_OF:                                      /* CSR0 */
+        *val = mcsr0;
+        break;
+
+    case MCSR1_OF:                                      /* CSR1 */
+        *val = mcsr1;
+        break;
+
+    case MCSR2_OF:                                      /* CSR2 */
+        *val = mcsr2 & ~MCSR2_MBZ;
+        break;
+
+    default:
+        return SCPE_NXM;
+    }
+
+if (DEBUG_PRI (mctl_dev, MCTL_DEB_RRD))
+    fprintf (sim_deb, ">>MCTL: reg %d read, value = %X\n", ofs, *val);
+
+return SCPE_OK;
+}
+
+/* Memory controller register write */
+
+t_stat mctl_wrreg (int32 val, int32 pa, int32 lnt)
+{
+int32 ofs;
+
+ofs = NEXUS_GETOFS (pa);                                /* get offset */
+
+switch (ofs) {                                          /* case on offset */
+
+    case MCSR0_OF:                                      /* CSR0 */
+        mcsr0 = mcsr0 & ~(MCSR0_RS & val);
+        break;
+
+    case MCSR1_OF:                                      /* CSR1 */
+        mcsr1 = val & MCSR1_RW;
+        break;
+
+    case MCSR2_OF:                                      /* CSR2 */
+        break;
+
+    default:
+        return SCPE_NXM;
+    }
+
+if (DEBUG_PRI (mctl_dev, MCTL_DEB_RWR))
+    fprintf (sim_deb, ">>MCTL: reg %d write, value = %X\n", ofs, val);
+
+return SCPE_OK;
+}
+
+/* Used by CPU */
+
+void rom_wr_B (int32 pa, int32 val)
+{
+return;
+}
+
+/* Memory controller reset */
+
+t_stat mctl_reset (DEVICE *dptr)
+{
+mcsr0 = 0;
+mcsr1 = 0;
+if (MEMSIZE > MAXMEMSIZE)                               /* More than 2MB? */
+    mcsr2 = MCSR2_INIT | (MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_64K) & MEM_64K_MASK) | MCSR2_CS;  /* Use 64k chips */
+else
+    mcsr2 = MCSR2_INIT | MEM_BOARD_MASK(MEMSIZE, MEM_SIZE_16K);  /* Use 16k chips */
+return SCPE_OK;
+}

VAX/vax750_syslist.c

@@ -0,0 +1,125 @@
+/* vax750_syslist.c: VAX 11/750 device list
+
+   Copyright (c) 2010-2012, Matt Burke
+   This module incorporates code from SimH, Copyright (c) 1998-2008, Robert M Supnik
+
+   Permission is hereby granted, free of charge, to any person obtaining a
+   copy of this software and associated documentation files (the "Software"),
+   to deal in the Software without restriction, including without limitation
+   the rights to use, copy, modify, merge, publish, distribute, sublicense,
+   and/or sell copies of the Software, and to permit persons to whom the
+   Software is furnished to do so, subject to the following conditions:
+
+   The above copyright notice and this permission notice shall be included in
+   all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+   THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+   Except as contained in this notice, the name(s) of the author(s) shall not be
+   used in advertising or otherwise to promote the sale, use or other dealings
+   in this Software without prior written authorization from the author(s).
+
+   21-Oct-2012  MB      First Version
+*/
+
+#include "vax_defs.h"
+
+char sim_name[] = "VAX750";
+
+extern DEVICE cpu_dev;
+extern DEVICE tlb_dev;
+extern DEVICE cmi_dev;
+extern DEVICE mctl_dev;
+extern DEVICE uba_dev;
+extern DEVICE mba_dev[MBA_NUM];
+extern DEVICE clk_dev;
+extern DEVICE tmr_dev;
+extern DEVICE tti_dev, tto_dev;
+extern DEVICE td_dev;
+extern DEVICE cr_dev;
+extern DEVICE lpt_dev;
+extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev;
+extern DEVICE rl_dev;
+extern DEVICE hk_dev;
+extern DEVICE rp_dev;
+extern DEVICE ry_dev;
+extern DEVICE ts_dev;
+extern DEVICE tq_dev;
+extern DEVICE tu_dev;
+extern DEVICE dz_dev;
+extern DEVICE xu_dev, xub_dev;
+
+extern int32 sim_switches;
+extern UNIT cpu_unit;
+extern void WriteB (uint32 pa, int32 val);
+
+DEVICE *sim_devices[] = { 
+    &cpu_dev,
+    &tlb_dev,
+    &cmi_dev,
+    &mctl_dev,
+    &uba_dev,
+    &mba_dev[0],
+    &mba_dev[1],
+    &clk_dev,
+    &tmr_dev,
+    &tti_dev,
+    &tto_dev,
+    &td_dev,
+    &dz_dev,
+    &cr_dev,
+    &lpt_dev,
+    &rp_dev,
+    &rl_dev,
+    &hk_dev,
+    &rq_dev,
+    &rqb_dev,
+    &rqc_dev,
+    &rqd_dev,
+    &ry_dev,
+    &tu_dev,
+    &ts_dev,
+    &tq_dev,
+    &xu_dev,
+    &xub_dev,
+    NULL
+    };
+
+/* Binary loader
+
+   The binary loader handles absolute system images, that is, system
+   images linked /SYSTEM.  These are simply a byte stream, with no
+   origin or relocation information.
+
+   -o           for memory, specify origin
+*/
+
+t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)
+{
+t_stat r;
+int32 val;
+uint32 origin, limit;
+
+if (flag)                                               /* dump? */
+    return SCPE_ARG;
+origin = 0;                                             /* memory */
+limit = (uint32) cpu_unit.capac;
+if (sim_switches & SWMASK ('O')) {                      /* origin? */
+    origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r);
+    if (r != SCPE_OK)
+        return SCPE_ARG;
+    }
+
+while ((val = getc (fileref)) != EOF) {                 /* read byte stream */
+    if (origin >= limit)                                /* NXM? */
+        return SCPE_NXM;
+    WriteB (origin, val);                               /* memory */
+    origin = origin + 1;
+    }
+return SCPE_OK;
+}

VAX/vax750_uba.c

@@ -0,0 +1,687 @@
+/* vax750_uba.c: VAX 11/750 Unibus adapter
+
+   Copyright (c) 2010-2011, Matt Burke
+   This module incorporates code from SimH, Copyright (c) 2004-2008, Robert M Supnik
+
+   Permission is hereby granted, free of charge, to any person obtaining a
+   copy of this software and associated documentation files (the "Software"),
+   to deal in the Software without restriction, including without limitation
+   the rights to use, copy, modify, merge, publish, distribute, sublicense,
+   and/or sell copies of the Software, and to permit persons to whom the
+   Software is furnished to do so, subject to the following conditions:
+
+   The above copyright notice and this permission notice shall be included in
+   all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+   THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+   Except as contained in this notice, the name(s) of the author(s) shall not be
+   used in advertising or otherwise to promote the sale, use or other dealings
+   in this Software without prior written authorization from the author(s).
+
+   uba                  DW750 Unibus adapter
+
+   21-Oct-2012  MB      First Version
+*/
+
+#include "vax_defs.h"
+
+/* Unibus adapter */
+
+#define UBA_NDPATH      16                              /* number of data paths */
+#define UBA_NMAPR       496                             /* number of map reg */
+
+/* Unibus adapter configuration register */
+
+#define UBACNF_OF       0x00
+#define UBACNF_CODE     0x00000028                      /* adapter code */
+
+/* Control/Status registers */
+
+#define UBACSR1_OF        0x01
+#define UBACSR2_OF        0x02
+#define UBACSR3_OF        0x03
+#define UBACSR_PUR       0x00000001                     /* Purge request */
+#define UBACSR_UCE       0x20000000                     /* Uncorrectable err */
+#define UBACSR_NXM       0x40000000                     /* NXM */
+#define UBACSR_ERR       0x80000000                     /* Error flag */
+#define UBACSR_RD        (UBACSR_PUR | UBACSR_UCE | UBACSR_NXM | \
+                          UBACSR_ERR)
+#define UBACSR_WR        0
+
+/* Map registers */
+
+#define UBAMAP_OF       0x200
+#define UBAMAP_VLD      0x80000000                      /* valid */
+#define UBAMAP_LWAE     0x04000000                      /* LW access enb - ni */
+#define UBAMAP_ODD      0x02000000                      /* odd byte */
+#define UBAMAP_V_DP     21                              /* data path */
+#define UBAMAP_M_DP     0xF
+#define UBAMAP_DP       (UBAMAP_M_DP << UBAMAP_V_DP)
+#define UBAMAP_GETDP(x) (((x) >> UBAMAP_V_DP) & UBAMAP_M_DP)
+#define UBAMAP_PAG      0x001FFFFF
+#define UBAMAP_RD       (0x86000000 | UBAMAP_DP | UBAMAP_PAG)
+#define UBAMAP_WR       (UBAMAP_RD)
+
+/* Debug switches */
+
+#define UBA_DEB_RRD     0x01                            /* reg reads */
+#define UBA_DEB_RWR     0x02                            /* reg writes */
+#define UBA_DEB_MRD     0x04                            /* map reads */
+#define UBA_DEB_MWR     0x08                            /* map writes */
+#define UBA_DEB_XFR     0x10                            /* transfers */
+#define UBA_DEB_ERR     0x20                            /* errors */
+
+int32 int_req[IPL_HLVL] = { 0 };                        /* intr, IPL 14-17 */
+uint32 uba_csr1 = 0;                                    /* csr reg 1 */
+uint32 uba_csr2 = 0;                                    /* csr reg 2 */
+uint32 uba_csr3 = 0;                                    /* csr reg 3 */
+uint32 uba_int = 0;                                     /* UBA interrupt */
+uint32 uba_map[UBA_NMAPR] = { 0 };                      /* map registers */
+int32 autcon_enb = 1;                                   /* autoconfig enable */
+
+extern int32 trpirq;
+extern int32 autcon_enb;
+extern jmp_buf save_env;
+extern DEVICE *sim_devices[];
+extern UNIT cpu_unit;
+extern uint32 nexus_req[NEXUS_HLVL];
+extern int32 sim_switches;
+extern FILE *sim_log, *sim_deb;
+extern int32 p1;
+extern int32 fault_PC;                                  /* fault PC */
+extern int32 mem_err;
+
+t_stat uba_reset (DEVICE *dptr);
+t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
+t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
+t_stat uba_rdreg (int32 *val, int32 pa, int32 mode);
+t_stat uba_wrreg (int32 val, int32 pa, int32 lnt);
+int32 uba_get_ubvector (int32 lvl);
+void uba_eval_int (void);
+void uba_ioreset (void);
+t_bool uba_map_addr (uint32 ua, uint32 *ma);
+t_stat set_autocon (UNIT *uptr, int32 val, char *cptr, void *desc);
+t_stat show_autocon (FILE *st, UNIT *uptr, int32 val, void *desc);
+t_stat show_iospace (FILE *st, UNIT *uptr, int32 val, void *desc);
+t_stat uba_show_virt (FILE *st, UNIT *uptr, int32 val, void *desc);
+
+extern int32 eval_int (void);
+extern t_stat build_dib_tab (void);
+extern void cmi_set_tmo (void);
+
+/* Unibus IO page dispatches */
+
+t_stat (*iodispR[IOPAGESIZE >> 1])(int32 *dat, int32 ad, int32 md);
+t_stat (*iodispW[IOPAGESIZE >> 1])(int32 dat, int32 ad, int32 md);
+
+/* Unibus interrupt request to interrupt action map */
+
+int32 (*int_ack[IPL_HLVL][32])();                       /* int ack routines */
+
+/* Unibus interrupt request to vector map */
+
+int32 int_vec[IPL_HLVL][32];                            /* int req to vector */
+
+/* Unibus adapter data structures
+
+   uba_dev      UBA device descriptor
+   uba_unit     UBA units
+   uba_reg      UBA register list
+*/
+
+DIB uba_dib = { TR_UBA, 0, &uba_rdreg, &uba_wrreg, 0, 0 };
+
+UNIT uba_unit = { UDATA (0, 0, 0) };
+
+REG uba_reg[] = {
+    { HRDATA (IPL14, int_req[0], 32), REG_RO },
+    { HRDATA (IPL15, int_req[1], 32), REG_RO },
+    { HRDATA (IPL16, int_req[2], 32), REG_RO },
+    { HRDATA (IPL17, int_req[3], 32), REG_RO },
+    { HRDATA (CSR1, uba_csr1, 32) },
+    { HRDATA (CSR2, uba_csr2, 32) },
+    { HRDATA (CSR3, uba_csr3, 32) },
+    { FLDATA (INT, uba_int, 0) },
+    { FLDATA (NEXINT, nexus_req[IPL_UBA], TR_UBA) },
+    { BRDATA (MAP, uba_map, 16, 32, 496) },
+    { FLDATA (AUTOCON, autcon_enb, 0), REG_HRO },
+    { NULL }
+    };
+
+MTAB uba_mod[] = {
+    { MTAB_XTD|MTAB_VDV, TR_UBA, "NEXUS", NULL,
+      NULL, &show_nexus },
+    { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "IOSPACE", NULL,
+      NULL, &show_iospace },
+    { MTAB_XTD|MTAB_VDV, 1, "AUTOCONFIG", "AUTOCONFIG",
+      &set_autocon, &show_autocon },
+    { MTAB_XTD|MTAB_VDV, 0, NULL, "NOAUTOCONFIG",
+      &set_autocon, NULL },
+    { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
+      NULL, &uba_show_virt },
+    { 0 }
+    };
+
+DEBTAB uba_deb[] = {
+    { "REGREAD", UBA_DEB_RRD },
+    { "REGWRITE", UBA_DEB_RWR },
+    { "MAPREAD", UBA_DEB_MRD },
+    { "MAPWRITE", UBA_DEB_MWR },
+    { "XFER", UBA_DEB_XFR },
+    { "ERROR", UBA_DEB_ERR },
+    { NULL, 0 }
+    };
+
+DEVICE uba_dev = {
+    "UBA", &uba_unit, uba_reg, uba_mod,
+    1, 16, UBADDRWIDTH, 2, 16, 16,
+    &uba_ex, &uba_dep, &uba_reset,
+    NULL, NULL, NULL,
+    &uba_dib, DEV_NEXUS | DEV_DEBUG, 0,
+    uba_deb, 0, 0
+    };
+
+/* Read Unibus adapter register - aligned lw only */
+
+t_stat uba_rdreg (int32 *val, int32 pa, int32 lnt)
+{
+int32 idx, ofs;
+
+if ((pa & 3) || (lnt != L_LONG)) {                      /* unaligned or not lw? */
+    printf (">>UBA: invalid adapter read mask, pa = %X, lnt = %d\r\n", pa, lnt);
+    /* FIXME: set appropriate error bits */
+    return SCPE_OK;
+    }
+ofs = NEXUS_GETOFS (pa);                                /* get offset */
+if (ofs >= UBAMAP_OF) {                                 /* map? */
+    idx = ofs - UBAMAP_OF;
+    if (idx >= UBA_NMAPR)                               /* valid? */
+        return SCPE_NXM;
+    *val = uba_map[idx] & UBAMAP_RD;
+    if (DEBUG_PRI (uba_dev, UBA_DEB_MRD))
+        fprintf (sim_deb, ">>UBA: map %d read, value = %X at PC = %08X\n", idx, *val, fault_PC);
+    return SCPE_OK;
+    }
+
+switch (ofs) {                                          /* case on offset */
+
+    case UBACNF_OF:                                     /* Config Reg */
+        *val = UBACNF_CODE;
+        break;
+        
+    case UBACSR1_OF:                                    /* CSR1 */
+        *val = (uba_csr1 & UBACSR_RD);
+        break;
+
+    case UBACSR2_OF:                                    /* CSR2 */
+        *val = (uba_csr2 & UBACSR_RD);
+        break;
+
+    case UBACSR3_OF:                                    /* CSR3 */
+        *val = (uba_csr3 & UBACSR_RD);
+        break;
+
+    default:
+        return SCPE_NXM;
+        }
+
+if (DEBUG_PRI (uba_dev, UBA_DEB_RRD))
+    fprintf (sim_deb, ">>UBA: reg %d read, value = %X at PC = %08X\n", ofs, *val, fault_PC);
+return SCPE_OK;
+}
+
+/* Write Unibus adapter register */
+
+t_stat uba_wrreg (int32 val, int32 pa, int32 lnt)
+{
+int32 idx, ofs;
+
+if ((pa & 3) || (lnt != L_LONG)) {                      /* unaligned or not lw? */
+    printf (">>UBA: invalid adapter write mask, pa = %X, lnt = %d\r\n", pa, lnt);
+    /* FIXME: set appropriate error bits */
+    return SCPE_OK;
+    }
+ofs = NEXUS_GETOFS (pa);                                /* get offset */
+if (ofs >= UBAMAP_OF) {                                 /* map? */
+    idx = ofs - UBAMAP_OF;
+    if (idx >= UBA_NMAPR)                               /* valid? */
+        return SCPE_NXM;
+    uba_map[idx] = val & UBAMAP_WR;
+    if (DEBUG_PRI (uba_dev, UBA_DEB_MWR))
+        fprintf (sim_deb, ">>UBA: map %d write, value = %X at PC = %08X\n", idx, val, fault_PC);
+    return SCPE_OK;
+    }
+
+switch (ofs) {                                          /* case on offset */
+
+    case UBACNF_OF:                                     /* Config Reg */
+        break;
+
+    case UBACSR1_OF:                                    /* CSR1 */
+        uba_csr1 = (val & UBACSR_WR);
+        break;
+
+    case UBACSR2_OF:                                    /* CSR2 */
+        uba_csr2 = (val & UBACSR_WR);
+        break;
+
+    case UBACSR3_OF:                                    /* CSR3 */
+        uba_csr3 = (val & UBACSR_WR);
+        break;
+
+    default:
+        return SCPE_NXM;
+        break;
+    }
+
+if (DEBUG_PRI (uba_dev, UBA_DEB_RWR))
+    fprintf (sim_deb, ">>UBA: reg %d write, value = %X at PC = %08X\n", ofs, val, fault_PC);
+return SCPE_OK;
+}
+
+/* Read and write Unibus I/O space */
+
+int32 ReadUb (uint32 pa)
+{
+int32 idx, val;
+
+if (ADDR_IS_IOP (pa)) {                                 /* iopage,!init */
+    idx = (pa & IOPAGEMASK) >> 1;
+    if (iodispR[idx]) {
+        iodispR[idx] (&val, pa, READ);
+        return val;
+        }
+    }
+cmi_set_tmo();
+MACH_CHECK(MCHK_BPE);
+return 0;
+}
+
+void WriteUb (uint32 pa, int32 val, int32 mode)
+{
+int32 idx;
+
+if (ADDR_IS_IOP (pa)) {                                 /* iopage,!init */
+    idx = (pa & IOPAGEMASK) >> 1;
+    if (iodispW[idx]) {
+        iodispW[idx] (val, pa, mode);
+        return;
+        }
+    }
+cmi_set_tmo();
+mem_err = 1;                                            /* interrupt */
+SET_IRQL;
+return;
+}
+
+/* ReadIO - read from IO - UBA only responds to byte, aligned word
+
+   Inputs:
+        pa      =       physical address
+        lnt     =       length (BWLQ)
+   Output:
+        longword of data
+*/
+
+int32 ReadIO (uint32 pa, int32 lnt)
+{
+uint32 iod;
+
+if ((lnt == L_BYTE) ||                                  /* byte? */
+    ((lnt == L_WORD) && ((pa & 1) == 0))) {             /* aligned word? */
+    iod = ReadUb (pa);                                  /* DATI from Unibus */
+    if (pa & 2)                                         /* position */
+        iod = iod << 16;
+    }
+else {
+    printf (">>UBA: invalid read mask, pa = %x, lnt = %d\n", pa, lnt);
+    /* FIXME: set appropriate error bits */
+    iod = 0;
+    }
+SET_IRQL;
+return iod;
+}
+
+/* WriteIO - write to IO - UBA only responds to byte, aligned word
+
+   Inputs:
+        pa      =       physical address
+        val     =       data to write, right justified in 32b longword
+        lnt     =       length (BWL)
+   Outputs:
+        none
+*/
+
+void WriteIO (uint32 pa, int32 val, int32 lnt)
+{
+if (lnt == L_BYTE)                                      /* byte? DATOB */
+    WriteUb (pa, val, WRITEB);
+else if ((lnt == L_WORD) && ((pa & 1) == 0))            /* aligned word? */
+     WriteUb (pa, val, WRITE);                          /* DATO */
+else {
+    printf (">>UBA: invalid write mask, pa = %x, lnt = %d\n", pa, lnt);
+    /* FIXME: set appropriate error bits */
+    }
+SET_IRQL;                                               /* update ints */
+return;
+}
+
+/* Update UBA nexus interrupts */
+
+void uba_eval_int (void)
+{
+int32 i;
+
+for (i = 0; i < (IPL_HMAX - IPL_HMIN); i++)             /* clear all UBA req */
+    nexus_req[i] &= ~(1 << TR_UBA);
+for (i = 0; i < (IPL_HMAX - IPL_HMIN); i++) {
+    if (int_req[i])
+        nexus_req[i] |= (1 << TR_UBA);
+    }
+if (uba_int)                                            /* adapter int? */
+    SET_NEXUS_INT (UBA);
+return;
+}
+
+/* Return vector for Unibus interrupt at relative IPL level [0-3] */
+
+int32 uba_get_ubvector (int32 lvl)
+{
+int32 i, vec;
+
+vec = 0;
+if ((lvl == (IPL_UBA - IPL_HMIN)) && uba_int) {         /* UBA lvl, int? */
+    uba_int = 0;                                        /* clear int */
+    }
+for (i = 0; int_req[lvl] && (i < 32); i++) {
+    if ((int_req[lvl] >> i) & 1) {
+        int_req[lvl] = int_req[lvl] & ~(1u << i);
+        if (int_ack[lvl][i])
+            return (vec | int_ack[lvl][i]());
+        return (vec | int_vec[lvl][i]);
+        }
+    }
+return vec;
+}
+
+/* Unibus I/O buffer routines
+
+   Map_ReadB    -       fetch byte buffer from memory
+   Map_ReadW    -       fetch word buffer from memory
+   Map_WriteB   -       store byte buffer into memory
+   Map_WriteW   -       store word buffer into memory
+*/
+
+int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf)
+{
+int32 i, j, pbc;
+uint32 ma, dat;
+
+ba = ba & UBADDRMASK;                                   /* mask UB addr */
+for (i = 0; i < bc; i = i + pbc) {                      /* loop by pages */
+    if (!uba_map_addr (ba + i, &ma))                    /* page inv or NXM? */
+        return (bc - i);
+    pbc = VA_PAGSIZE - VA_GETOFF (ma);                  /* left in page */
+    if (pbc > (bc - i))                                  /* limit to rem xfr */
+        pbc = bc - i;
+    if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
+        fprintf (sim_deb, ">>UBA: 8b read, ma = %X, bc = %X\n", ma, pbc);
+    if ((ma | pbc) & 3) {                               /* aligned LW? */
+        for (j = 0; j < pbc; ma++, j++) {               /* no, do by bytes */
+            *buf++ = ReadB (ma);
+            }
+        }
+    else {                                              /* yes, do by LW */
+        for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
+            dat = ReadL (ma);                           /* get lw */
+            *buf++ = dat & BMASK;                       /* low 8b */
+            *buf++ = (dat >> 8) & BMASK;                /* next 8b */
+            *buf++ = (dat >> 16) & BMASK;               /* next 8b */
+            *buf++ = (dat >> 24) & BMASK;
+            }
+        }
+    }
+return 0;
+}
+
+int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf)
+{
+int32 i, j, pbc;
+uint32 ma, dat;
+
+ba = ba & UBADDRMASK;                                   /* mask UB addr */
+bc = bc & ~01;
+for (i = 0; i < bc; i = i + pbc) {                      /* loop by pages */
+    if (!uba_map_addr (ba + i, &ma))                    /* page inv or NXM? */
+        return (bc - i);
+    pbc = VA_PAGSIZE - VA_GETOFF (ma);                  /* left in page */
+    if (pbc > (bc - i))                                 /* limit to rem xfr */
+        pbc = bc - i;
+    if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
+        fprintf (sim_deb, ">>UBA: 16b read, ma = %X, bc = %X\n", ma, pbc);
+    if ((ma | pbc) & 1) {                               /* aligned word? */
+        for (j = 0; j < pbc; ma++, j++) {               /* no, do by bytes */
+            if ((i + j) & 1) {                          /* odd byte? */
+                *buf = (*buf & BMASK) | (ReadB (ma) << 8);
+                buf++;
+                }
+            else *buf = (*buf & ~BMASK) | ReadB (ma);
+            }
+        }
+    else if ((ma | pbc) & 3) {                          /* aligned LW? */
+        for (j = 0; j < pbc; ma = ma + 2, j = j + 2) {  /* no, words */
+            *buf++ = ReadW (ma);                        /* get word */
+            }
+        }
+    else {                                              /* yes, do by LW */
+        for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
+            dat = ReadL (ma);                           /* get lw */
+            *buf++ = dat & WMASK;                       /* low 16b */
+            *buf++ = (dat >> 16) & WMASK;               /* high 16b */
+            }
+        }
+    }
+return 0;
+}
+
+int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf)
+{
+int32 i, j, pbc;
+uint32 ma, dat;
+
+ba = ba & UBADDRMASK;                                   /* mask UB addr */
+for (i = 0; i < bc; i = i + pbc) {                      /* loop by pages */
+    if (!uba_map_addr (ba + i, &ma))                    /* page inv or NXM? */
+        return (bc - i);
+    pbc = VA_PAGSIZE - VA_GETOFF (ma);                  /* left in page */
+    if (pbc > (bc - i))                                 /* limit to rem xfr */
+        pbc = bc - i;
+    if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
+        fprintf (sim_deb, ">>UBA: 8b write, ma = %X, bc = %X\n", ma, pbc);
+    if ((ma | pbc) & 3) {                               /* aligned LW? */
+        for (j = 0; j < pbc; ma++, j++) {               /* no, do by bytes */
+            WriteB (ma, *buf);
+            buf++;
+            }
+        }
+    else {                                              /* yes, do by LW */
+        for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
+            dat = (uint32) *buf++;                      /* get low 8b */
+            dat = dat | (((uint32) *buf++) << 8);       /* merge next 8b */
+            dat = dat | (((uint32) *buf++) << 16);      /* merge next 8b */
+            dat = dat | (((uint32) *buf++) << 24);      /* merge hi 8b */
+            WriteL (ma, dat);                           /* store lw */
+            }
+        }
+    }
+return 0;
+}
+
+int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf)
+{
+int32 i, j, pbc;
+uint32 ma, dat;
+
+ba = ba & UBADDRMASK;                                   /* mask UB addr */
+bc = bc & ~01;
+for (i = 0; i < bc; i = i + pbc) {                      /* loop by pages */
+    if (!uba_map_addr (ba + i, &ma))                    /* page inv or NXM? */
+        return (bc - i);
+    pbc = VA_PAGSIZE - VA_GETOFF (ma);                  /* left in page */
+    if (pbc > (bc - i))                                 /* limit to rem xfr */
+        pbc = bc - i;
+    if (DEBUG_PRI (uba_dev, UBA_DEB_XFR))
+        fprintf (sim_deb, ">>UBA: 16b write, ma = %X, bc = %X\n", ma, pbc);
+    if ((ma | pbc) & 1) {                               /* aligned word? */
+        for (j = 0; j < pbc; ma++, j++) {               /* no, bytes */
+            if ((i + j) & 1) {
+                WriteB (ma, (*buf >> 8) & BMASK);
+                buf++;
+                }
+            else WriteB (ma, *buf & BMASK);
+            }
+        }
+    else if ((ma | pbc) & 3) {                          /* aligned LW? */
+        for (j = 0; j < pbc; ma = ma + 2, j = j + 2) {  /* no, words */
+            WriteW (ma, *buf);                          /* write word */
+            buf++;
+            }
+        }
+    else {                                              /* yes, do by LW */
+        for (j = 0; j < pbc; ma = ma + 4, j = j + 4) {
+            dat = (uint32) *buf++;                      /* get low 16b */
+            dat = dat | (((uint32) *buf++) << 16);      /* merge hi 16b */
+            WriteL (ma, dat);                           /* store LW */
+            }
+        }
+    }
+return 0;
+}
+
+/* Map an address via the translation map */
+
+t_bool uba_map_addr (uint32 ua, uint32 *ma)
+{
+uint32 ublk, umap;
+
+ublk = ua >> VA_V_VPN;                                  /* Unibus blk */
+if (ublk >= UBA_NMAPR)                                  /* unimplemented? */
+    return FALSE;
+umap = uba_map[ublk];                                   /* get map */
+if (umap & UBAMAP_VLD) {                                /* valid? */
+    *ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua);
+    if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD))      /* buffered dp? */
+        *ma = *ma + 1;                                  /* byte offset? */
+    return (ADDR_IS_MEM (*ma));                         /* legit addr */
+    }
+return FALSE;
+}
+
+/* Map an address via the translation map - console version (no status changes) */
+
+t_bool uba_map_addr_c (uint32 ua, uint32 *ma)
+{
+uint32 ublk, umap;
+
+ublk = ua >> VA_V_VPN;                                  /* Unibus blk */
+if (ublk >= UBA_NMAPR)                                  /* unimplemented? */
+    return FALSE;
+umap = uba_map[ublk];                                   /* get map */
+if (umap & UBAMAP_VLD) {                                /* valid? */
+    *ma = ((umap & UBAMAP_PAG) << VA_V_VPN) + VA_GETOFF (ua);
+    if ((umap & UBAMAP_DP) && (umap & UBAMAP_ODD))      /* buffered dp? */
+        *ma = *ma + 1;                                  /* byte offset? */
+    return TRUE;                                        /* legit addr */
+    }
+return FALSE;
+}
+
+/* Reset Unibus devices */
+
+void uba_ioreset (void)
+{
+int32 i;
+DEVICE *dptr;
+
+for (i = 0; sim_devices[i] != NULL; i++) {              /* reset Unibus */
+    dptr = sim_devices[i];
+    if (dptr->reset && (dptr->flags & DEV_UBUS))
+        dptr->reset (dptr);
+    }
+return;
+}
+
+/* Reset Unibus adapter */
+
+t_stat uba_reset (DEVICE *dptr)
+{
+int32 i;
+
+for (i = 0; i < IPL_HLVL; i++) {
+    nexus_req[i] &= ~(1 << TR_UBA);
+    int_req[i] = 0;
+    }
+for (i = 0; i < UBA_NMAPR; i++)
+    uba_map[i] = 0;
+uba_csr1 = 0;
+uba_csr2 = 0;
+uba_csr3 = 0;
+return SCPE_OK;
+}
+
+/* Memory examine via map (word only) */
+
+t_stat uba_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw)
+{
+uint32 ua = (uint32) exta, pa;
+
+if ((vptr == NULL) || (ua >= UBADDRSIZE))
+    return SCPE_ARG;
+if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) {
+    *vptr = (uint32) ReadW (pa);
+    return SCPE_OK;
+    }
+return SCPE_NXM;
+}
+
+/* Memory deposit via map (word only) */
+
+t_stat uba_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw)
+{
+uint32 ua = (uint32) exta, pa;
+
+if (ua >= UBADDRSIZE)
+    return SCPE_ARG;
+if (uba_map_addr_c (ua, &pa) && ADDR_IS_MEM (pa)) {
+    WriteW (pa, (int32) val);
+    return SCPE_OK;
+    }
+return SCPE_NXM;
+}
+
+/* Show UBA virtual address */
+
+t_stat uba_show_virt (FILE *of, UNIT *uptr, int32 val, void *desc)
+{
+t_stat r;
+char *cptr = (char *) desc;
+uint32 ua, pa;
+
+if (cptr) {
+    ua = (uint32) get_uint (cptr, 16, UBADDRSIZE - 1, &r);
+    if (r == SCPE_OK) {
+        if (uba_map_addr_c (ua, &pa))
+            fprintf (of, "Unibus %-X = physical %-X\n", ua, pa);
+        else fprintf (of, "Unibus %-X: invalid mapping\n", ua);
+        return SCPE_OK;
+        }
+    }
+fprintf (of, "Invalid argument\n");
+return SCPE_OK;
+}

VAX/vax780_defs.h

@@ -150,6 +150,12 @@
 #define INITMEMSIZE     (1 << MAXMEMWIDTH)              /* initial memory size */
 #define MEMSIZE         (cpu_unit.capac)
 #define ADDR_IS_MEM(x)  (((uint32) (x)) < MEMSIZE)
+#define MEM_MODIFIERS   { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }
 
 /* Unibus I/O registers */
 

VAX/vax7x0_mba.c

@@ -1,4 +1,4 @@
-/* vax780_mba.c: VAX 11/780 Massbus adapter
+/* vax7x0_mba.c: VAX 11/780 snf VAX 11/750 Massbus adapter
 
    Copyright (c) 2004-2008, Robert M Supnik
 
@@ -272,7 +272,9 @@ t_stat r;
 mb = NEXUS_GETNEX (pa) - TR_MBA0;                       /* get MBA */
 if ((pa & 3) || (lnt != L_LONG)) {                      /* unaligned or not lw? */
     printf (">>MBA%d: invalid adapter read mask, pa = %X, lnt = %d\r\n", mb, pa, lnt);
+#if defined(VAX_780)
     sbi_set_errcnf ();                                  /* err confirmation */
+#endif
     return SCPE_OK;
     }
 if (mb >= MBA_NUM)                                      /* valid? */
@@ -365,7 +367,9 @@ t_bool cs1dt;
 mb = NEXUS_GETNEX (pa) - TR_MBA0;                       /* get MBA */
 if ((pa & 3) || (lnt != L_LONG)) {                      /* unaligned or not lw? */
     printf (">>MBA%d: invalid adapter write mask, pa = %X, lnt = %d\r\n", mb, pa, lnt);
+#if defined(VAX_780)
     sbi_set_errcnf ();                                  /* err confirmation */
+#endif
     return SCPE_OK;
     }
 if (mb >= MBA_NUM)                                      /* valid? */

VAX/vax_cpu.c

@@ -473,21 +473,7 @@ MTAB cpu_mod[] = {
     { UNIT_CONH, UNIT_CONH, "HALT to console", "CONHALT", NULL },
     { MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &cpu_set_idle, &cpu_show_idle },
     { MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
-#if defined (VAX_730)
-    { UNIT_MSIZE, (1u << 20), NULL, "1M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 21), NULL, "2M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 22), NULL, "4M", &cpu_set_size },
-#endif
-    { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size },
-#if !defined (VAX_780)
-    { UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size },
-    { UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size },
-#endif
+    MEM_MODIFIERS,   /* Model specific memory modifiers from vaxXXX_defs.h */
     { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
       &cpu_set_hist, &cpu_show_hist },
     { MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,

VAX/vax_defs.h

@@ -721,6 +721,8 @@ enum opcodes {
 
 #if defined (VAX_780)
 #include "vax780_defs.h"
+#elif defined (VAX_750)
+#include "vax750_defs.h"
 #elif defined (VAX_730)
 #include "vax730_defs.h"
 #else

VAX/vaxmod_defs.h

@@ -117,6 +117,15 @@
 #define INITMEMSIZE     (1 << 24)                       /* initial memory size */
 #define MEMSIZE         (cpu_unit.capac)
 #define ADDR_IS_MEM(x)  (((uint32) (x)) < MEMSIZE)
+#define MEM_MODIFIERS   { UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size }, \
+                        { UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size }
+
 
 /* Cache diagnostic space */
 

Visual Studio Projects/Simh.sln

@@ -70,6 +70,11 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX730", "VAX730.vcproj", "
 		{D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8}
 	EndProjectSection
 EndProject
+Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "VAX750", "VAX750.vcproj", "{43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}"
+	ProjectSection(ProjectDependencies) = postProject
+		{D40F3AF1-EEE7-4432-9807-2AD287B490F8} = {D40F3AF1-EEE7-4432-9807-2AD287B490F8}
+	EndProjectSection
+EndProject
 Global
 	GlobalSection(SolutionConfigurationPlatforms) = preSolution
 		Debug|Win32 = Debug|Win32
@@ -196,6 +201,10 @@ Global
 		{C526F7F2-9476-44BC-B1E9-9522B693BEA7}.Debug|Win32.Build.0 = Debug|Win32
 		{C526F7F2-9476-44BC-B1E9-9522B693BEA7}.Release|Win32.ActiveCfg = Release|Win32
 		{C526F7F2-9476-44BC-B1E9-9522B693BEA7}.Release|Win32.Build.0 = Release|Win32
+		{43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Debug|Win32.ActiveCfg = Debug|Win32
+		{43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Debug|Win32.Build.0 = Debug|Win32
+		{43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Release|Win32.ActiveCfg = Release|Win32
+		{43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}.Release|Win32.Build.0 = Release|Win32
 	EndGlobalSection
 	GlobalSection(SolutionProperties) = preSolution
 		HideSolutionNode = FALSE

Visual Studio Projects/VAX730.vcproj

@@ -428,17 +428,13 @@
 				>
 			</File>
 			<File
-				RelativePath="..\VAX\VAX730_defs.h"
+				RelativePath="..\VAX\vax730_defs.h"
 				>
 			</File>
 			<File
 				RelativePath="..\VAX\vax_defs.h"
 				>
 			</File>
-			<File
-				RelativePath="..\VAX\vaxmod_defs.h"
-				>
-			</File>
 		</Filter>
 		<Filter
 			Name="Resource Files"

Visual Studio Projects/VAX750.vcproj

@@ -0,0 +1,455 @@
+<?xml version="1.0" encoding="Windows-1252"?>
+<VisualStudioProject
+	ProjectType="Visual C++"
+	Version="9.00"
+	Name="VAX750"
+	ProjectGUID="{43A9CF64-5705-4FB7-B837-ED9AAFF97DAC}"
+	RootNamespace="VAX750"
+	Keyword="Win32Proj"
+	TargetFrameworkVersion="131072"
+	>
+	<Platforms>
+		<Platform
+			Name="Win32"
+		/>
+	</Platforms>
+	<ToolFiles>
+	</ToolFiles>
+	<Configurations>
+		<Configuration
+			Name="Debug|Win32"
+			OutputDirectory="..\BIN\NT\$(PlatformName)-$(ConfigurationName)"
+			IntermediateDirectory="..\BIN\NT\Project\simh\VAX750\$(PlatformName)-$(ConfigurationName)"
+			ConfigurationType="1"
+			InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"
+			CharacterSet="2"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+				Description="Build Dependent ROM include File(s) &amp; Check for required build dependencies"
+				CommandLine="pushd ..&#x0D;&#x0A;$(TargetDir)BuildROMs&#x0D;&#x0A;popd&#x0D;&#x0A;&#x0D;&#x0A;if not exist ../../windows-build/winpcap/Wpdpack/Include/pcap.h goto _notice&#x0D;&#x0A;if not exist ../../windows-build/pthreads/pthread.h goto _notice&#x0D;&#x0A;goto _good&#x0D;&#x0A;&#x0D;&#x0A;:_notice&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo **  The required build support is not available.  **&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;type 0ReadMe_Projects.txt&#x0D;&#x0A;exit 1&#x0D;&#x0A;&#x0D;&#x0A;:_good&#x0D;&#x0A;"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="0"
+				AdditionalIncludeDirectories="./;../;../VAX/;../pdp11/;&quot;../../windows-build/winpcap/Wpdpack/Include&quot;;&quot;../../windows-build/pthreads&quot;"
+				PreprocessorDefinitions="USE_INT64;USE_ADDR64;VM_VAX;VAX_750;USE_SHARED;_CRT_NONSTDC_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;PTW32_STATIC_LIB;USE_READER_THREAD;SIM_ASYNCH_IO"
+				MinimalRebuild="true"
+				BasicRuntimeChecks="0"
+				RuntimeLibrary="1"
+				UsePrecompiledHeader="0"
+				WarningLevel="3"
+				Detect64BitPortabilityProblems="false"
+				DebugInformationFormat="3"
+				CompileAs="1"
+				ShowIncludes="false"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalOptions="/fixed:no"
+				AdditionalDependencies="wpcap.lib packet.lib wsock32.lib winmm.lib"
+				OutputFile="$(OutDir)\VAX750.exe"
+				LinkIncremental="1"
+				AdditionalLibraryDirectories="../../winpcap/Wpdpack/Lib/;&quot;../../pthreads/Pre-built.2/lib/&quot;"
+				GenerateDebugInformation="true"
+				ProgramDatabaseFile="$(OutDir)\VAX750.pdb"
+				SubSystem="1"
+				RandomizedBaseAddress="1"
+				DataExecutionPrevention="0"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+			/>
+		</Configuration>
+		<Configuration
+			Name="Release|Win32"
+			OutputDirectory="..\BIN\NT\$(PlatformName)-$(ConfigurationName)"
+			IntermediateDirectory="..\BIN\NT\Project\simh\VAX750\$(PlatformName)-$(ConfigurationName)"
+			ConfigurationType="1"
+			InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"
+			CharacterSet="2"
+			>
+			<Tool
+				Name="VCPreBuildEventTool"
+				Description="Build Dependent ROM include File(s) &amp; Check for required build dependencies"
+				CommandLine="pushd ..&#x0D;&#x0A;$(TargetDir)BuildROMs&#x0D;&#x0A;popd&#x0D;&#x0A;&#x0D;&#x0A;if not exist ../../windows-build/winpcap/Wpdpack/Include/pcap.h goto _notice&#x0D;&#x0A;if not exist ../../windows-build/pthreads/pthread.h goto _notice&#x0D;&#x0A;goto _good&#x0D;&#x0A;&#x0D;&#x0A;:_notice&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo **  The required build support is not available.  **&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;echo ****************************************************&#x0D;&#x0A;type 0ReadMe_Projects.txt&#x0D;&#x0A;exit 1&#x0D;&#x0A;&#x0D;&#x0A;:_good&#x0D;&#x0A;"
+			/>
+			<Tool
+				Name="VCCustomBuildTool"
+			/>
+			<Tool
+				Name="VCXMLDataGeneratorTool"
+			/>
+			<Tool
+				Name="VCWebServiceProxyGeneratorTool"
+			/>
+			<Tool
+				Name="VCMIDLTool"
+			/>
+			<Tool
+				Name="VCCLCompilerTool"
+				Optimization="2"
+				InlineFunctionExpansion="2"
+				EnableIntrinsicFunctions="true"
+				FavorSizeOrSpeed="1"
+				OmitFramePointers="true"
+				AdditionalIncludeDirectories="./;../;../VAX/;../pdp11/;&quot;../../windows-build/winpcap/Wpdpack/Include&quot;;&quot;../../windows-build/pthreads&quot;"
+				PreprocessorDefinitions="USE_INT64;USE_ADDR64;VM_VAX;VAX_750;USE_SHARED;_CRT_NONSTDC_NO_WARNINGS;_CRT_SECURE_NO_WARNINGS;PTW32_STATIC_LIB;USE_READER_THREAD;SIM_ASYNCH_IO"
+				StringPooling="true"
+				RuntimeLibrary="0"
+				EnableFunctionLevelLinking="true"
+				UsePrecompiledHeader="0"
+				WarningLevel="3"
+				Detect64BitPortabilityProblems="false"
+				DebugInformationFormat="3"
+				CompileAs="1"
+			/>
+			<Tool
+				Name="VCManagedResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCResourceCompilerTool"
+			/>
+			<Tool
+				Name="VCPreLinkEventTool"
+			/>
+			<Tool
+				Name="VCLinkerTool"
+				AdditionalOptions="/fixed:no"
+				AdditionalDependencies="wpcap.lib packet.lib wsock32.lib winmm.lib"
+				OutputFile="$(OutDir)\VAX750.exe"
+				LinkIncremental="1"
+				AdditionalLibraryDirectories="../../winpcap/Wpdpack/Lib/;&quot;../../pthreads/Pre-built.2/lib/&quot;"
+				GenerateDebugInformation="true"
+				SubSystem="1"
+				OptimizeReferences="2"
+				EnableCOMDATFolding="2"
+				RandomizedBaseAddress="1"
+				DataExecutionPrevention="0"
+				TargetMachine="1"
+			/>
+			<Tool
+				Name="VCALinkTool"
+			/>
+			<Tool
+				Name="VCManifestTool"
+			/>
+			<Tool
+				Name="VCXDCMakeTool"
+			/>
+			<Tool
+				Name="VCBscMakeTool"
+			/>
+			<Tool
+				Name="VCFxCopTool"
+			/>
+			<Tool
+				Name="VCAppVerifierTool"
+			/>
+			<Tool
+				Name="VCPostBuildEventTool"
+			/>
+		</Configuration>
+	</Configurations>
+	<References>
+	</References>
+	<Files>
+		<Filter
+			Name="Source Files"
+			Filter="cpp;c;cxx;def;odl;idl;hpj;bat;asm"
+			>
+			<File
+				RelativePath="..\PDP11\pdp11_cr.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_dz.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_hk.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_io_lib.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_lp.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_rl.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_rp.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_rq.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_ry.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_tq.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_ts.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_tu.c"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_xu.c"
+				>
+			</File>
+			<File
+				RelativePath="..\..\windows-build\pthreads\pthread.c"
+				>
+				<FileConfiguration
+					Name="Debug|Win32"
+					>
+					<Tool
+						Name="VCCLCompilerTool"
+						PreprocessorDefinitions="HAVE_PTW32_CONFIG_H;PTW32_BUILD_INLINED;PTW32_STATIC_LIB;__CLEANUP_C;$(NOINHERIT)"
+					/>
+				</FileConfiguration>
+				<FileConfiguration
+					Name="Release|Win32"
+					>
+					<Tool
+						Name="VCCLCompilerTool"
+						PreprocessorDefinitions="HAVE_PTW32_CONFIG_H;PTW32_BUILD_INLINED;PTW32_STATIC_LIB;__CLEANUP_C;$(NOINHERIT)"
+					/>
+				</FileConfiguration>
+			</File>
+			<File
+				RelativePath="..\scp.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_console.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_disk.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_ether.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_fio.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_sock.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_tape.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_timer.c"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_tmxr.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax750_cmi.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax750_mem.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax750_stddev.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax750_syslist.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax750_uba.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax7x0_mba.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_cis.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_cmode.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_cpu.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_cpu1.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_fpa.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_mmu.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_octa.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_sys.c"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_syscm.c"
+				>
+			</File>
+		</Filter>
+		<Filter
+			Name="Header Files"
+			Filter="h;hpp;hxx;hm;inl;inc"
+			>
+			<File
+				RelativePath="..\dec_dz.h"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_io_lib.h"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_mscp.h"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_uqssp.h"
+				>
+			</File>
+			<File
+				RelativePath="..\PDP11\pdp11_xu.h"
+				>
+			</File>
+			<File
+				RelativePath="..\scp.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_console.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_defs.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_disk.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_ether.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_fio.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_rev.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_sock.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_tape.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_timer.h"
+				>
+			</File>
+			<File
+				RelativePath="..\sim_tmxr.h"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax750_defs.h"
+				>
+			</File>
+			<File
+				RelativePath="..\VAX\vax_defs.h"
+				>
+			</File>
+		</Filter>
+		<Filter
+			Name="Resource Files"
+			Filter="rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe"
+			>
+		</Filter>
+	</Files>
+	<Globals>
+	</Globals>
+</VisualStudioProject>

Visual Studio Projects/VAX780.vcproj

@@ -314,10 +314,6 @@
 				RelativePath="..\VAX\vax780_fload.c"
 				>
 			</File>
-			<File
-				RelativePath="..\VAX\vax780_mba.c"
-				>
-			</File>
 			<File
 				RelativePath="..\VAX\vax780_mem.c"
 				>
@@ -338,6 +334,10 @@
 				RelativePath="..\VAX\vax780_uba.c"
 				>
 			</File>
+			<File
+				RelativePath="..\VAX\vax7x0_mba.c"
+				>
+			</File>
 			<File
 				RelativePath="..\VAX\vax_cis.c"
 				>
@@ -451,10 +451,6 @@
 				RelativePath="..\VAX\vax_defs.h"
 				>
 			</File>
-			<File
-				RelativePath="..\VAX\vaxmod_defs.h"
-				>
-			</File>
 		</Filter>
 		<Filter
 			Name="Resource Files"

descrip.mms

@@ -42,6 +42,7 @@
 #            SWTP            Just Build The SWTP.
 #            VAX             Just Build The DEC VAX.
 #            VAX730          Just Build The DEC VAX730.
+#            VAX750          Just Build The DEC VAX750.
 #            VAX780          Just Build The DEC VAX780.
 #            CLEAN           Will Clean Files Back To Base Kit.
 #
@@ -582,6 +583,36 @@ VAX730_OPTIONS = /INCL=($(SIMH_DIR),$(VAX730_DIR),$(PDP11_DIR)$(PCAP_INC))\
 VAX730_SIMH_LIB = $(SIMH_LIB)
 .ENDIF
 
+# Digital Equipment VAX750 Simulator Definitions.
+#
+VAX750_DIR = SYS$DISK:[.VAX]
+VAX750_LIB1 = $(LIB_DIR)VAX730L1-$(ARCH).OLB
+VAX750_SOURCE1 = $(VAX750_DIR)VAX_CPU.C,$(VAX750_DIR)VAX_CPU1.C,\
+                 $(VAX750_DIR)VAX_FPA.C,$(VAX750_DIR)VAX_CIS.C,\
+                 $(VAX750_DIR)VAX_OCTA.C,$(VAX750_DIR)VAX_CMODE.C,\
+                 $(VAX750_DIR)VAX_MMU.C,$(VAX750_DIR)VAX_SYS.C,\
+                 $(VAX750_DIR)VAX_SYSCM.C,$(VAX750_DIR)VAX750_STDDEV.C,\
+                 $(VAX750_DIR)VAX750_CMI.C,$(VAX750_DIR)VAX750_MEM.C,\
+                 $(VAX750_DIR)VAX750_UBA.C,$(VAX750_DIR)VAX7X0_MBA.C,\
+                 $(VAX750_DIR)VAX750_SYSLIST.C
+VAX750_LIB2 = $(LIB_DIR)VAX730L2-$(ARCH).OLB
+VAX750_SOURCE2 = $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\
+                 $(PDP11_DIR)PDP11_TS.C,$(PDP11_DIR)PDP11_DZ.C,\
+                 $(PDP11_DIR)PDP11_LP.C,$(PDP11_DIR)PDP11_TQ.C,\
+                 $(PDP11_DIR)PDP11_XU.C,$(PDP11_DIR)PDP11_RY.C,\
+                 $(PDP11_DIR)PDP11_CR.C,$(PDP11_DIR)PDP11_HK.C,\
+                 $(PDP11_DIR)PDP11_RP.C,$(PDP11_DIR)PDP11_TU.C,\
+                 $(PDP11_DIR)PDP11_IO_LIB.C
+.IFDEF ALPHA_OR_IA64
+VAX750_OPTIONS = /INCL=($(SIMH_DIR),$(VAX750_DIR),$(PDP11_DIR)$(PCAP_INC))\
+                 /DEF=($(CC_DEFS),"VM_VAX=1","USE_ADDR64=1","USE_INT64=1"$(PCAP_DEFS),"VAX_750=1")
+VAX750_SIMH_LIB = $(SIMH_LIB64)
+.ELSE
+VAX750_OPTIONS = /INCL=($(SIMH_DIR),$(VAX750_DIR),$(PDP11_DIR)$(PCAP_INC))\
+                 /DEF=($(CC_DEFS),"VM_VAX=1"$(PCAP_DEFS),"VAX_750=1")
+VAX750_SIMH_LIB = $(SIMH_LIB)
+.ENDIF
+
 # Digital Equipment VAX780 Simulator Definitions.
 #
 VAX780_DIR = SYS$DISK:[.VAX]
@@ -592,7 +623,7 @@ VAX780_SOURCE1 = $(VAX780_DIR)VAX_CPU.C,$(VAX780_DIR)VAX_CPU1.C,\
                  $(VAX780_DIR)VAX_MMU.C,$(VAX780_DIR)VAX_SYS.C,\
                  $(VAX780_DIR)VAX_SYSCM.C,$(VAX780_DIR)VAX780_STDDEV.C,\
                  $(VAX780_DIR)VAX780_SBI.C,$(VAX780_DIR)VAX780_MEM.C,\
-                 $(VAX780_DIR)VAX780_UBA.C,$(VAX780_DIR)VAX780_MBA.C,\
+                 $(VAX780_DIR)VAX780_UBA.C,$(VAX780_DIR)VAX7X0_MBA.C,\
                  $(VAX780_DIR)VAX780_FLOAD.C,$(VAX780_DIR)VAX780_SYSLIST.C
 VAX780_LIB2 = $(LIB_DIR)VAX780L2-$(ARCH).OLB
 VAX780_SOURCE2 = $(PDP11_DIR)PDP11_RL.C,$(PDP11_DIR)PDP11_RQ.C,\
@@ -628,7 +659,8 @@ I7094_OPTIONS = /INCL=($(SIMH_DIR),$(I7094_DIR))/DEF=($(CC_DEFS))
 #
 .IFDEF ALPHA_OR_IA64
 ALL : ALTAIR ALTAIRZ80 ECLIPSE GRI LGP H316 HP2100 I1401 I1620 IBM1130 ID16 \
-      ID32 NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP10 PDP11 PDP15 S3 VAX VAX730 VAX780 \
+      ID32 NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP10 PDP11 PDP15 S3 \
+      VAX VAX730 VAX750 VAX780 \
       SDS I7094 SWTP
         $! No further actions necessary
 .ELSE
@@ -636,7 +668,8 @@ ALL : ALTAIR ALTAIRZ80 ECLIPSE GRI LGP H316 HP2100 I1401 I1620 IBM1130 ID16 \
 # Else We Are On VAX And Build Everything EXCEPT the 64b simulators
 #
 ALL : ALTAIR ALTAIRZ80 GRI H316 HP2100 I1401 I1620 IBM1130 ID16 ID32 \
-      NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP11 PDP15 S3 VAX VAX780 SDS SWTP
+      NOVA PDP1 PDP4 PDP7 PDP8 PDP9 PDP11 PDP15 S3 \
+      VAX VAX730 VAX750 VAX780 SDS SWTP
         $! No further actions necessary
 .ENDIF
 
@@ -1064,6 +1097,28 @@ $(VAX730_LIB2) : $(VAX730_SOURCE2)
         $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ
         $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;*
 
+$(VAX750_LIB1) : $(VAX750_SOURCE1)
+        $!
+        $! Building The $(VAX750_LIB1) Library.
+        $!
+        $ $(CC)$(VAX750_OPTIONS)/OBJ=$(VAX750_DIR) -
+               /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST)
+        $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN -
+             LIBRARY/CREATE $(MMS$TARGET)
+        $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ
+        $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;*
+
+$(VAX750_LIB2) : $(VAX750_SOURCE2)
+        $!
+        $! Building The $(VAX750_LIB2) Library.
+        $!
+        $ $(CC)$(VAX750_OPTIONS)/OBJ=$(VAX750_DIR) -
+               /OBJ=$(BLD_DIR) $(MMS$CHANGED_LIST)
+        $ IF (F$SEARCH("$(MMS$TARGET)").EQS."") THEN -
+             LIBRARY/CREATE $(MMS$TARGET)
+        $ LIBRARY/REPLACE $(MMS$TARGET) $(BLD_DIR)*.OBJ
+        $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;*
+
 $(VAX780_LIB1) : $(VAX780_SOURCE1)
         $!
         $! Building The $(VAX780_LIB1) Library.
@@ -1469,6 +1524,21 @@ $(BIN_DIR)VAX730-$(ARCH).EXE : $(SIMH_MAIN) $(VAX730_SIMH_LIB) $(PCAP_LIBD) $(VA
                $(VAX730_SIMH_LIB)/LIBRARY$(PCAP_LIBR)
         $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;*
 
+VAX750 : $(BIN_DIR)VAX750-$(ARCH).EXE
+        $! VAX750 done
+
+$(BIN_DIR)VAX750-$(ARCH).EXE : $(SIMH_MAIN) $(VAX750_SIMH_LIB) $(PCAP_LIBD) $(VAX750_LIB1) $(VAX750_LIB2) $(PCAP_EXECLET)
+        $!
+        $! Building The $(BIN_DIR)VAX750-$(ARCH).EXE Simulator.
+        $!
+        $ $(CC)$(VAX750_OPTIONS)/OBJ=$(BLD_DIR) SCP.C
+        $ LINK $(LINK_DEBUG)$(LINK_SECTION_BINDING)-
+               /EXE=$(BIN_DIR)VAX750-$(ARCH).EXE -
+               $(BLD_DIR)SCP.OBJ,-
+               $(VAX750_LIB1)/LIBRARY,$(VAX750_LIB2)/LIBRARY,-
+               $(VAX750_SIMH_LIB)/LIBRARY$(PCAP_LIBR)
+        $ DELETE/NOLOG/NOCONFIRM $(BLD_DIR)*.OBJ;*
+
 VAX780 : $(BIN_DIR)VAX780-$(ARCH).EXE
         $! VAX780 done
 

makefile

@@ -331,11 +331,25 @@ VAX730 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \
 VAX730_OPT = -DVM_VAX -DVAX_730 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT}
 
 
+VAX750 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \
+	${VAXD}/vax_cis.c ${VAXD}/vax_octa.c  ${VAXD}/vax_cmode.c \
+	${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c  ${VAXD}/vax_syscm.c \
+	${VAXD}/vax750_stddev.c ${VAXD}/vax750_cmi.c \
+	${VAXD}/vax750_mem.c ${VAXD}/vax750_uba.c ${VAXD}/vax7x0_mba.c \
+	${VAXD}/vax750_syslist.c \
+	${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \
+	${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \
+	${PDP11D}/pdp11_xu.c ${PDP11D}/pdp11_ry.c ${PDP11D}/pdp11_cr.c \
+	${PDP11D}/pdp11_hk.c ${PDP11D}/pdp11_rp.c ${PDP11D}/pdp11_tu.c \
+	${PDP11D}/pdp11_io_lib.c
+VAX750_OPT = -DVM_VAX -DVAX_750 -DUSE_INT64 -DUSE_ADDR64 -I VAX -I ${PDP11D} ${NETWORK_OPT}
+
+
 VAX780 = ${VAXD}/vax_cpu.c ${VAXD}/vax_cpu1.c ${VAXD}/vax_fpa.c \
 	${VAXD}/vax_cis.c ${VAXD}/vax_octa.c  ${VAXD}/vax_cmode.c \
 	${VAXD}/vax_mmu.c ${VAXD}/vax_sys.c  ${VAXD}/vax_syscm.c \
 	${VAXD}/vax780_stddev.c ${VAXD}/vax780_sbi.c \
-	${VAXD}/vax780_mem.c ${VAXD}/vax780_uba.c ${VAXD}/vax780_mba.c \
+	${VAXD}/vax780_mem.c ${VAXD}/vax780_uba.c ${VAXD}/vax7x0_mba.c \
 	${VAXD}/vax780_fload.c ${VAXD}/vax780_syslist.c \
 	${PDP11D}/pdp11_rl.c ${PDP11D}/pdp11_rq.c ${PDP11D}/pdp11_ts.c \
 	${PDP11D}/pdp11_dz.c ${PDP11D}/pdp11_lp.c ${PDP11D}/pdp11_tq.c \
@@ -492,7 +506,7 @@ SWTP_OPT = -I ${SWTPD}
 # Build everything
 #
 ALL = pdp1 pdp4 pdp7 pdp8 pdp9 pdp15 pdp11 pdp10 \
-	vax vax730 vax780 nova eclipse hp2100 i1401 i1620 s3 \
+	vax vax730 vax750 vax780 nova eclipse hp2100 i1401 i1620 s3 \
 	altair altairz80 gri i7094 ibm1130 id16 \
 	id32 sds lgp h316 swtp
 
@@ -584,6 +598,12 @@ ${BIN}vax730${EXE} : ${VAX730} ${SIM} ${BUILD_ROMS}
 	${MKDIRBIN}
 	${CC} ${VAX730} ${SIM} ${VAX730_OPT} -o $@ ${LDFLAGS}
 
+vax750 : ${BIN}vax750${EXE}
+
+${BIN}vax750${EXE} : ${VAX750} ${SIM} ${BUILD_ROMS}
+	${MKDIRBIN}
+	${CC} ${VAX750} ${SIM} ${VAX750_OPT} -o $@ ${LDFLAGS}
+
 vax780 : ${BIN}vax780${EXE}
 
 ${BIN}vax780${EXE} : ${VAX780} ${SIM} ${BUILD_ROMS}