Declare output unit to facilitate proper character output completion
scheduling.
Proper completion scheduling removes the need to sleeping waiting for
character I/O completion.
This should fix#521 and #504
Newest Win32 include files changed the include file order as compared to the
Microsoft MS compilers.
This is arguably a bug in the MinGW codebase, but working around it is too trivial
to complain about.
Without this change, timer events don't get queued correctly when the
simulator isn't running (i.e. when at the command prompt or as a consequence
of a RESET command (or during boot preparation)).
This only affects when timers are asynchronous which is not the current
default.
- Throttling delays are self adjusting for specific speed throttling
(K cycles and M cycles and % cycles).
- Throttling starts after THROT_DELAY seconds of execution.
- THROT_DELAY is a register accessible via EXAMINE and DEPOSIT
once throttling has been enabled.
- Throttle sleep times are recalibrated every 10 seconds based on
execution performance for the prior 10 seconds if the current
execution rate differs from the desired rate by more than
THROT_DRIFT_PCT. THROT_DRIFT_PCT defaults to 5 and is a
register accessible via EXAMINE and DEPOSIT once throttling has
been enabled.
- Addressing details reported in #508
- Fixed screen alignments/scrolling between commands
- Add ncurses screen update support on non-windows platforms
- Add tests for new frontpanel APIs
- Add multiple panel startup and shutdown activity to test shutdown
- Add breakpoints to help debug VAX console ROM tests that have failed
- Cleanup session reading logic to properly handle all cases of TCP send
coalesced data.
- Use Remote Console EXECUTE Command to consolidate register query activity
when halted.
- Use -16 switch for EXAMINE and DEPOSIT commands to be sure to present data
in a reliable simulator independent way.
- Add sim_panel_halt_text and sim_panel_device_debug_mode APIs
- Better cleanup of simulator process during panel shutdown on Win32
- Properly set the Interval Register when a running timer is stopped
- Peoperly clear timer interrupt pending when CSR is updated
- Properly handle the case when the timer is started with the interval
register is 0.
- Properly stop the running timer when it is restarted or adjusted
with a new interval value.
- Better debug info
