Commit graph

8 commits

Author SHA1 Message Date
Mark Pizzolato
8b6c0b60c9 SAGE: Remove irrelevant platform #ifdefs and redundant includes 2023-05-27 14:57:46 -04:00
Holger Veit
3e54264253 SAGE: Fix flag setting with 33bit mask 2017-03-28 13:32:22 -07:00
Holger Veit
9a9b5deb9c PDQ-3, SAGE: Coverity Fixes
CID       Action
   1416081   changed variable answer to int
   1416082   checked returned values with ASSURE - read error means corrupted target code.
   1416088   added return
   1416109   This fallthru was intentional - duplicated code to make coverity happy
   1416111   This fallthru was intentional - duplicated code to make coverity happy
   1416116   This fallthru was intentional - duplicated code to make coverity happy
   1416117   This fallthru was intentional - duplicated code to make coverity happy
   1416124   protected against negative return
   1416142   added ASSURE, however this case won't happen since reg_intpending==true implies positive int level
   1416145   checked non-NULL, return SCPE_ARG if NULL
   1416150   since only 2 drives are supported, fdc_selected is decoded to 0 and 1 only (allowed 2 and 3 before)
   1416152   restrict to 2 drives only
   1416166   checked value with ASSURE

   1416101   typo: should have been resx
   1416106   unnecessary code removed
   1416110   this fallthru was intentional - duplicated code to make coverity happy
   1416112   this fallthru was intentional - duplicated code to make coverity happy
   1416148   change condition to check for negative value
   1416179   break was remainder from former logic - removed
   1415866   code was remainder from former unimplemented instruction trap - removed
2017-03-27 06:57:43 -07:00
Mark Pizzolato
5531ccb175 ALL: Massive 'const' cleanup
These changes facilitate more robust parameter type checking and helps
to identify unexpected coding errors.

Most simulators can now also be compiled with a C++ compiler without
warnings.

Additionally, these changes have also been configured to facilitate easier
backporting of simulator and device simulation modules to run under the
simh v3.9+ SCP framework.
2016-05-15 15:25:33 -07:00
Mark Pizzolato
66dba79418 ALPHA, ALTAIR, AltairZ80, I7094, NOVA, PDP1, PDP10, PDP11, PDP18B, PDP8, SAGE, sigma, swtp6800, TX-0, VAX: Change tabs to spaces which had crept in over time 2015-03-30 10:24:24 -07:00
Eric Scharff
af713b78e1 Fix off-by-one in reading cache address from memory
Commit a9ac7c153 properly avoided writing past the end of cache_line,
but in doing so introduced an error as to the first memory address that
should be written. This fix avoids writing past the cache_line by simply
reading the previous memory location.

Fixes the CP/M 68K simulation example and issue #181
2015-01-22 21:58:56 -05:00
Lioncash
a9ac7c1534 SAGE: Fix loop bounds in m68k_cpu
cache_line has a size of CACHE_SIZE (16), so starting at that index will be outside the bounds of the array.
2014-11-26 12:55:55 -05:00
Mark Pizzolato
e2524e7feb Beta Simulators (PDQ-3 and SAGE) from Holger Veit 2014-09-17 17:31:40 -07:00