- Periodic "python cmake/generate.py" to sync with makefile changes.
- Ensure that AIO_CCDEFS (makefile) and USES_AIO (CMake generate.py) are
present for PDP-10 simulators. Otherwise, user gets a warning message
when the simulator starts about network support and asynchronous I/O.
- Make sure that asynchronous mode can't be changed if devices using
sim_ether are already attached.
- Add missing DEV_ETHER type flag for the only sim_ether using device
that didn't already have it.
Issue #294: "apple silicon build problem(s?)": If the "--flavor/-f" flag
is not specified on the command line, then complain loudly, print help
and exit. The script used to default to "Unix Makefiles".
Updates:
- Add missing "-DHAVE_LIBPNG" compiler command line define when the PNG
library is detected/present for screen capture support.
- Add "clang64" to the list of MinGW64 platforms for which the
.travis/deps.sh script can install build dependencies.
- Add PThread4W_FOUND to the condition that sets async I/O for Win32
when using vcpkg for build dependencies.
- Add vs2022-x64, vs2019-x64 and vs2017-x64 build environments to
build 64-bit Windows executables.
- Use simulator AIO only where needed by the simulator (i.e., the
simulator calls/uses AIO_CHECK_EVENT in sim_instr())
- Add "USES_AIO" flag to add_simulator() to mark a simulator that
acutally uses asynchronous I/O.
- Build "_aio" SIMH core library variants that have AIO turned on,
link with the "_aio" variant when a simulator sets USES_AIO.
- Emit a warning message when WITH_ASYNC is False (CMake configuration
option) to notify the user/developer that some functionality will be
crippled.
Affected simulator builds: 3b2 family, PDP-6, PDP-11, VAX family,
IMLAC and TT2500. The makefile and cmake/generate.py also updated
to remain in sync with CMake.
N.B.: Simulators still link with the underlying platform's threading
library. SEL32 requires pthreads or equivalent threading library,
independent of AIO.
- cmake/cmake-builder.sh
- New "--no-aio" flag: Build simulators without async I/O.
- New "--no-aio-intrinsics" flag: Don't build async I/O using compiler
compare-exchange, atomic load intrinsics.
- cmake/cmake-builder.ps1
- New "-noaio" flag: Build simulators without async I/O.
- New "-noaiointrinsics" flag: Don't build async I/O using compiler
compare-exchange, atomic load intrinsics.
CMake 3.28.1 INTERFACE_LINK_LIBRARIES behavior change: The file name
must now be an absolute path. Relative paths no longer accepted.
Internally, SIMH enforces this if CMAKE_VERSION >= 3.19, when REAL_PATH
was first implemented.
* CMake build infrastructure
The squashed commit that builds and packages releases for the SIMH
simulator suite with CMake, version 3.14 or newer.
See README-CMake.md for documentation.
Adjust the RUNLIMIT to specify instructions instead of wall clock time.
On an unfettered system, the sel32 test completes after some 588 million
instructions. On a slow host system, the system clock tick processing will
add to the total instructions executed. Increase the limit to 750 million
instructions.
Take the version of the code from VAX/vax4nn_stddev.c and vax4xx_stddev.c,
and apply it to 730, 750, 780, 820 and 860.
If we can assume that clk_tps always remains 100, this can be simplified
further.
These devices start disabled and will be that way in essentially all
working systems, but there apparently was a DECnet Phase V
support for this device, so it is added to all systems. The DPV
should now be readily testable.
As mentioned in #1152. That PR will fix the DUP device.
This commit is explicitly released from any license restriction
mentioned in the LICENSE.txt of the github.com/simh/simh
master branch changes.
The actual contents of the input ROM binary files and the contents of the
created arrays are unchanged.
Multiple ROM image include files can be included in the same source module
without the need for any #undef BOOT_CODE_SIZE, etc.
Historically this functionality was reimplemented within each
DEVICE simulator often with slightly different implementations
and inconsistencies. Solving this globally within SCP required
changes in many places, but should henceforth be reasonably
managed.
As discussed in #1034
The CFGTST register MTYPE subfield should describe the additional memory
beyond 2MB on the processor board. Previous logic attempted to describe
the total system memory and the net result didn't fit into the 3 bit field and
thus said no additional memory is present.
The consequence of this new amount of memory is that ALL of it is tested
during the power on self test and thus it takes significantly longer to get to
the >>> prompt.
As reported in #944
- Only if backing store is used (i.e. OS Agnostic mode)
- Previously this was only done on a clean simulator exit. That could
result in inconsistent timing information in operating system images vs
the saved TODR baseline data
- Always return TODR values rounded to the TODR granularity (10ms).
This avoids a potential invalid pointer dereference when formatting
the return value from sim_instr() if it is < SCPE_BASE but greater
than the previously defined static array size.sizeof
Update simh.doc to reflect this generic change.
Array REGister definitions have been made consistent by passing the
name of the array object. This allows proper sizing assessment
to occur in the register validation logic.
Some previously described array REGister initializers were not really
arrays. Some were structures and others were merely pointers to
someplace in memory that it was desirable to view as a scalar array.
Structures or other blob data should now use SAVEDATA. Virtual
arrays intended to be interpret some part of memory as scalar data
now use VBRDATA initializers.
