910bbc2d7e
These devices start disabled and will be that way in essentially all working systems, but there apparently was a DECnet Phase V support for this device, so it is added to all systems. The DPV should now be readily testable. As mentioned in #1152. That PR will fix the DUP device. This commit is explicitly released from any license restriction mentioned in the LICENSE.txt of the github.com/simh/simh master branch changes.
480 lines
23 KiB
C
480 lines
23 KiB
C
/* vaxmod_defs.h: VAX model-specific definitions file
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Copyright (c) 1998-2019, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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05-May-19 RMS Added Qbus memory space to ADDR_IS_IO test
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18-May-17 RMS Added model-specific AST validation test
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20-Dec-13 RMS Added prototypes for unaligned IO and register handling
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11-Dec-11 RMS Moved all Qbus devices to BR4; deleted RP definitions
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25-Nov-11 RMS Added VEC_QBUS definition
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29-Apr-07 RMS Separated checks for PxBR and SBR
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17-May-06 RMS Added CR11/CD11 support
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10-May-06 RMS Added NOP'd reserved operand checking macros
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05-Oct-05 RMS Added XU definitions for autoconfigure
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15-Jun-05 RMS Added QDSS support
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12-Sep-04 RMS Removed map_address prototype
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16-Jun-04 RMS Added DHQ11 support
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21-Mar-04 RMS Added RXV21 support
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25-Jan-04 RMS Removed local debug logging support
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RMS,MP Added "KA655X" support
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29-Dec-03 RMS Added Q18 definition for PDP11 compatibility
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22-Dec-02 RMS Added BDR halt enable definition
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11-Nov-02 RMS Added log bits for XQ
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10-Oct-02 RMS Added DEQNA/DELQA, multiple RQ, autoconfigure support
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29-Sep-02 RMS Revamped bus support macros
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06-Sep-02 RMS Added TMSCP support
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14-Jul-02 RMS Added additional console halt codes
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28-Apr-02 RMS Fixed DZV vector base and number of lines
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This file covers the KA65x ("Mayfair") series of CVAX-based Qbus systems.
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The simulator defines an extended physical memory variant of the KA655,
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called the KA655X. It has a maximum memory size of 512MB instead of 64MB.
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System memory map
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0000 0000 - 03FF FFFF main memory (KA655)
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0400 0000 - 0FFF FFFF reserved (KA655), main memory (KA655X)
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1000 0000 - 13FF FFFF cache diagnostic space (KA655), main memory (KA655X)
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1400 0000 - 1FFF FFFF reserved (KA655), main memory (KA655X)
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2000 0000 - 2000 1FFF Qbus I/O page
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2000 2000 - 2003 FFFF reserved
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2004 0000 - 2005 FFFF ROM space, halt protected
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2006 0000 - 2007 FFFF ROM space, halt unprotected
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2008 0000 - 201F FFFF Local register space
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2020 0000 - 2FFF FFFF reserved
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3000 0000 - 303F FFFF Qbus memory space
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3400 0000 - 3FFF FFFF reserved
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*/
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#ifdef FULL_VAX /* subset VAX */
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#undef FULL_VAX
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#endif
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#ifdef CMPM_VAX
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#undef CMPM_VAX /* No Compatibility Mode */
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#endif
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#ifndef VAXMOD_DEFS_H_
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#define VAXMOD_DEFS_H_ 1
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/* Microcode constructs */
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#define CVAX_SID (10 << 24) /* system ID */
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#define CVAX_UREV 6 /* ucode revision */
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#define CON_HLTPIN 0x0200 /* external CPU halt */
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#define CON_PWRUP 0x0300 /* powerup code */
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#define CON_HLTINS 0x0600 /* HALT instruction */
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#define CON_BADPSL 0x4000 /* invalid PSL flag */
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#define CON_MAPON 0x8000 /* mapping on flag */
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#define MCHK_TBM_P0 0x05 /* PPTE in P0 */
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#define MCHK_TBM_P1 0x06 /* PPTE in P1 */
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#define MCHK_M0_P0 0x07 /* PPTE in P0 */
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#define MCHK_M0_P1 0x08 /* PPTE in P1 */
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#define MCHK_INTIPL 0x09 /* invalid ireq */
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#define MCHK_READ 0x80 /* read check */
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#define MCHK_WRITE 0x82 /* write check */
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/* Machine specific IPRs */
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#define MT_CADR 37
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#define MT_MSER 39
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#define MT_CONPC 42
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#define MT_CONPSL 43
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#define MT_IORESET 55
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#define MT_MAX 63 /* last valid IPR */
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/* Memory system error register */
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#define MSER_HM 0x80 /* hit/miss */
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#define MSER_CPE 0x40 /* CDAL par err */
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#define MSER_CPM 0x20 /* CDAL mchk */
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/* Cache disable register */
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#define CADR_RW 0xF3
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#define CADR_MBO 0x0C
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/* Memory */
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#define MAXMEMWIDTH 26 /* max mem, std KA655 */
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#define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */
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#define MAXMEMWIDTH_X 29 /* max mem, KA655X */
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#define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)
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#define INITMEMSIZE (1 << 24) /* initial memory size */
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#define MEMSIZE (cpu_unit.capac)
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#define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)
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#define MEM_MODIFIERS { UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size, NULL, NULL, "Set Memory to 16M bytes" }, \
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{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size, NULL, NULL, "Set Memory to 32M bytes" }, \
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{ UNIT_MSIZE, (1u << 25) + (1u << 24), NULL, "48M", &cpu_set_size, NULL, NULL, "Set Memory to 48M bytes" }, \
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{ UNIT_MSIZE, (1u << 26), NULL, "64M", &cpu_set_size, NULL, NULL, "Set Memory to 64M bytes" }, \
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{ UNIT_MSIZE, (1u << 27), NULL, "128M", &cpu_set_size, NULL, NULL, "Set Memory to 128M bytes" }, \
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{ UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size, NULL, NULL, "Set Memory to 256M bytes" }, \
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{ UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size, NULL, NULL, "Set Memory to 512M bytes" }, \
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "MEMORY", NULL, NULL, &cpu_show_memory, NULL, "Display memory configuration" }
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extern t_stat cpu_show_memory (FILE* st, UNIT* uptr, int32 val, CONST void* desc);
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#define CPU_MODEL_MODIFIERS { MTAB_XTD|MTAB_VDV, 0, "MODEL", "MODEL={VAXserver|MicroVAX|VAXstation}", \
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&cpu_set_model, &cpu_show_model, NULL, "Set/Display processor model" }, \
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{ MTAB_XTD|MTAB_VDV, 0, "AUTOBOOT", "AUTOBOOT", \
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&sysd_set_halt, &sysd_show_halt, NULL, "Enable autoboot (Disable Halt)" }, \
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 1, "NOAUTOBOOT", "NOAUTOBOOT", \
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&sysd_set_halt, &sysd_show_halt, NULL, "Disable autoboot (Enable Halt)" },
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/* Cache diagnostic space */
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#define CDAAWIDTH 16 /* cache dat addr width */
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#define CDASIZE (1u << CDAAWIDTH) /* cache dat length */
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#define CDAMASK (CDASIZE - 1) /* cache dat mask */
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#define CTGAWIDTH 10 /* cache tag addr width */
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#define CTGSIZE (1u << CTGAWIDTH) /* cache tag length */
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#define CTGMASK (CTGSIZE - 1) /* cache tag mask */
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#define CDGSIZE (CDASIZE * CTGSIZE) /* diag addr length */
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#define CDGBASE 0x10000000 /* diag addr base */
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#define CDG_GETROW(x) (((x) & CDAMASK) >> 2)
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#define CDG_GETTAG(x) (((x) >> CDAAWIDTH) & CTGMASK)
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#define CTG_V (1u << (CTGAWIDTH + 0)) /* tag valid */
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#define CTG_WP (1u << (CTGAWIDTH + 1)) /* wrong parity */
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#define ADDR_IS_CDG(x) ((((uint32) (x)) >= CDGBASE) && \
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(((uint32) (x)) < (CDGBASE + CDGSIZE)))
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/* Qbus I/O registers */
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#define IOPAGEAWIDTH 13 /* IO addr width */
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#define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */
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#define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */
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#define IOPAGEBASE 0x20000000 /* IO page base */
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#define ADDR_IS_IOP(x) ((((uint32) (x)) >= IOPAGEBASE) && \
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(((uint32) (x)) < (IOPAGEBASE + IOPAGESIZE)))
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/* Read only memory - appears twice */
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#define ROMAWIDTH 17 /* ROM addr width */
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#define ROMSIZE (1u << ROMAWIDTH) /* ROM length */
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#define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */
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#define ROMBASE 0x20040000 /* ROM base */
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#define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \
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(((uint32) (x)) < (ROMBASE + ROMSIZE + ROMSIZE)))
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/* Local register space */
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#define REGAWIDTH 19 /* REG addr width */
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#define REGSIZE (1u << REGAWIDTH) /* REG length */
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#define REGBASE 0x20080000 /* REG addr base */
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/* KA655 board registers */
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#define KAAWIDTH 3 /* KA reg width */
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#define KASIZE (1u << KAAWIDTH) /* KA reg length */
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#define KABASE (REGBASE + 0x4000) /* KA650 addr base */
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/* CQBIC registers */
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#define CQBICSIZE (5 << 2) /* 5 registers */
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#define CQBICBASE (REGBASE) /* CQBIC addr base */
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#define CQMAPASIZE 15 /* map addr width */
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#define CQMAPSIZE (1u << CQMAPASIZE) /* map length */
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#define CQMAPAMASK (CQMAPSIZE - 1) /* map addr mask */
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#define CQMAPBASE (REGBASE + 0x8000) /* map addr base */
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#define CQIPCSIZE 2 /* 2 bytes only */
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#define CQIPCBASE (REGBASE + 0x1F40) /* ipc reg addr */
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/* CMCTL registers */
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// #define CMCTLSIZE (18 << 2) /* 18 registers */
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#define CMCTLSIZE (19 << 2) /* KA655X extra reg */
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#define CMCTLBASE (REGBASE + 0x100) /* CMCTL addr base */
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/* SSC registers */
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#define SSCSIZE 0x150 /* SSC size */
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#define SSCBASE 0x20140000 /* SSC base */
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/* Non-volatile RAM - 1KB long */
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#define NVRAWIDTH 10 /* NVR addr width */
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#define NVRSIZE (1u << NVRAWIDTH) /* NVR length */
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#define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */
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#define NVRBASE 0x20140400 /* NVR base */
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#define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \
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(((uint32) (x)) < (NVRBASE + NVRSIZE)))
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/* CQBIC Qbus memory space (seen from CVAX) */
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#define CQMAWIDTH 22 /* Qmem addr width */
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#define CQMSIZE (1u << CQMAWIDTH) /* Qmem length */
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#define CQMAMASK (CQMSIZE - 1) /* Qmem addr mask */
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#define CQMBASE 0x30000000 /* Qmem base */
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#define ADDR_IS_CQM(x) ((((uint32) (x)) >= CQMBASE) && \
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(((uint32) (x)) < (CQMBASE + CQMSIZE)))
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/* Reflect to IO on either IO space or Qbus memory */
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#define ADDR_IS_IO(x) (ADDR_IS_IOP(x) || ADDR_IS_CQM(x))
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/* QVSS memory space */
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#define QVMAWIDTH 18 /* QVSS mem addr width */
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#define QVMSIZE (1u << QVMAWIDTH) /* QVSS mem length */
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#define QVMAMASK (QVMSIZE - 1) /* QVSS mem addr mask */
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#define QVMBASE (CQMBASE + CQMSIZE - QVMSIZE) /* QVSS mem base - end of Qbus memory space */
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#define ADDR_IS_QVM(x) (vc_buf && \
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(((uint32) (x)) >= QVMBASE) && \
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(((uint32) (x)) < (QVMBASE + QVMSIZE)))
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extern uint32 *vc_buf;
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/* Machine specific reserved operand tests (mostly NOPs) */
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#define ML_PA_TEST(r)
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#define ML_LR_TEST(r)
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#define ML_SBR_TEST(r)
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#define ML_PXBR_TEST(r)
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#define LP_AST_TEST(r)
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#define LP_MBZ84_TEST(r)
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#define LP_MBZ92_TEST(r)
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#define MT_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT(MT_AST_TEST)
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/* Qbus I/O modes */
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#define READ 0 /* PDP-11 compatibility */
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#define WRITE (L_WORD)
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#define WRITEB (L_BYTE)
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/* Common CSI flags */
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#define CSR_V_GO 0 /* go */
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#define CSR_V_IE 6 /* interrupt enable */
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#define CSR_V_DONE 7 /* done */
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#define CSR_V_BUSY 11 /* busy */
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#define CSR_V_ERR 15 /* error */
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#define CSR_GO (1u << CSR_V_GO)
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#define CSR_IE (1u << CSR_V_IE)
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#define CSR_DONE (1u << CSR_V_DONE)
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#define CSR_BUSY (1u << CSR_V_BUSY)
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#define CSR_ERR (1u << CSR_V_ERR)
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/* Timers */
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#define TMR_CLK 0 /* 100Hz clock */
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/* I/O system definitions */
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#define DZ_MUXES 4 /* default # of DZV muxes */
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#define VH_MUXES 4 /* max # of DHQ muxes */
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#define MT_MAXFR (1 << 16) /* magtape max rec */
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#define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */
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#define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */
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#define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */
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#define DEV_UBUS (1u << DEV_V_UBUS)
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#define DEV_QBUS (1u << DEV_V_QBUS)
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#define DEV_Q18 (1u << DEV_V_Q18)
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#define UNIBUS FALSE /* 22b only */
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#define DEV_RDX 16 /* default device radix */
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/* Device information block */
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#define VEC_DEVMAX 4 /* max device vec */
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typedef struct {
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uint32 ba; /* base addr */
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uint32 lnt; /* length */
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t_stat (*rd)(int32 *dat, int32 ad, int32 md);
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t_stat (*wr)(int32 dat, int32 ad, int32 md);
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int32 vnum; /* vectors: number */
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int32 vloc; /* locator */
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int32 vec; /* value */
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int32 (*ack[VEC_DEVMAX])(void); /* ack routine */
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uint32 ulnt; /* IO length per-device */
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/* Only need to be populated */
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/* when numunits != num devices */
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int32 numc; /* Number of controllers */
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/* this field handles devices */
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/* where multiple instances are */
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/* simulated through a single */
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/* DEVICE structure (e.g., DZ, VH, DL, DC). */
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/* Populated by auto-configure */
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DEVICE *dptr; /* back pointer to related device */
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/* Populated by auto-configure */
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} DIB;
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/* Qbus I/O page layout - see pdp11_io_lib.c for address layout details */
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#define IOBA_AUTO (0) /* Assigned by Auto Configure */
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/* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14;
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however, DEC Qbus controllers all interrupt on IPL 14
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Within each IPL, priority is right to left
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*/
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/* IPL 17 */
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/* IPL 16 */
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#define INT_V_CLK 0 /* clock */
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/* IPL 15 */
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/* IPL 14 - devices through RY are IPL 15 on Unibus systems */
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#define INT_V_RQ 0 /* RQDX3 */
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#define INT_V_RL 1 /* RLV12/RL02 */
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#define INT_V_DZRX 2 /* DZ11 */
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#define INT_V_DZTX 3
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#define INT_V_TS 4 /* TS11/TSV05 */
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#define INT_V_TQ 5 /* TMSCP */
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#define INT_V_XQ 6 /* DEQNA/DELQA */
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#define INT_V_RY 7 /* RXV21 */
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#define INT_V_TTI 8 /* console */
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#define INT_V_TTO 9
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#define INT_V_PTR 10 /* PC11 */
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#define INT_V_PTP 11
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#define INT_V_LPT 12 /* LP11 */
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#define INT_V_CSI 13 /* SSC cons UART */
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#define INT_V_CSO 14
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#define INT_V_TMR0 15 /* SSC timers */
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#define INT_V_TMR1 16
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#define INT_V_VHRX 17 /* DHQ11 */
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#define INT_V_VHTX 18
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#define INT_V_QDSS 19 /* QDSS */
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#define INT_V_CR 20
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#define INT_V_QVSS 21 /* QVSS */
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#define INT_V_DMCRX 22 /* DMC11 */
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#define INT_V_DMCTX 23
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#define INT_V_DUPRX 24 /* DPV11 */
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#define INT_V_DUPTX 25
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#define INT_V_TDRX 26 /* TU58 */
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#define INT_V_TDTX 27
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#define INT_CLK (1u << INT_V_CLK)
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#define INT_RQ (1u << INT_V_RQ)
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#define INT_RL (1u << INT_V_RL)
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#define INT_DZRX (1u << INT_V_DZRX)
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#define INT_DZTX (1u << INT_V_DZTX)
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#define INT_TS (1u << INT_V_TS)
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#define INT_TQ (1u << INT_V_TQ)
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#define INT_XQ (1u << INT_V_XQ)
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#define INT_RY (1u << INT_V_RY)
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#define INT_TTI (1u << INT_V_TTI)
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#define INT_TTO (1u << INT_V_TTO)
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#define INT_PTR (1u << INT_V_PTR)
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#define INT_PTP (1u << INT_V_PTP)
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#define INT_LPT (1u << INT_V_LPT)
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#define INT_CSI (1u << INT_V_CSI)
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#define INT_CSO (1u << INT_V_CSO)
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#define INT_TMR0 (1u << INT_V_TMR0)
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#define INT_TMR1 (1u << INT_V_TMR1)
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#define INT_VHRX (1u << INT_V_VHRX)
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#define INT_VHTX (1u << INT_V_VHTX)
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#define INT_QDSS (1u << INT_V_QDSS)
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#define INT_CR (1u << INT_V_CR)
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#define INT_QVSS (1u << INT_V_QVSS)
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#define INT_DMCRX (1u << INT_V_DMCRX)
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#define INT_DMCTX (1u << INT_V_DMCTX)
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#define INT_DUPRX (1u << INT_V_DUPRX)
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#define INT_DUPTX (1u << INT_V_DUPTX)
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#define INT_TDRX (1u << INT_V_TDRX)
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#define INT_TDTX (1u << INT_V_TDTX)
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#define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */
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#define IPL_RQ (0x14 - IPL_HMIN)
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#define IPL_RL (0x14 - IPL_HMIN)
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#define IPL_DZRX (0x14 - IPL_HMIN)
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#define IPL_DZTX (0x14 - IPL_HMIN)
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#define IPL_TS (0x14 - IPL_HMIN)
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#define IPL_TQ (0x14 - IPL_HMIN)
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#define IPL_XQ (0x14 - IPL_HMIN)
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#define IPL_RY (0x14 - IPL_HMIN)
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#define IPL_TTI (0x14 - IPL_HMIN)
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#define IPL_TTO (0x14 - IPL_HMIN)
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#define IPL_PTR (0x14 - IPL_HMIN)
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#define IPL_PTP (0x14 - IPL_HMIN)
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#define IPL_LPT (0x14 - IPL_HMIN)
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#define IPL_CSI (0x14 - IPL_HMIN)
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#define IPL_CSO (0x14 - IPL_HMIN)
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#define IPL_TMR0 (0x14 - IPL_HMIN)
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#define IPL_TMR1 (0x14 - IPL_HMIN)
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#define IPL_VHRX (0x14 - IPL_HMIN)
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#define IPL_VHTX (0x14 - IPL_HMIN)
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#define IPL_QDSS (0x14 - IPL_HMIN)
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#define IPL_CR (0x14 - IPL_HMIN)
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#define IPL_QVSS (0x14 - IPL_HMIN)
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#define IPL_DMCRX (0x14 - IPL_HMIN)
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#define IPL_DMCTX (0x14 - IPL_HMIN)
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#define IPL_DUPRX (0x14 - IPL_HMIN)
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#define IPL_DUPTX (0x14 - IPL_HMIN)
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#define IPL_TDRX (0x14 - IPL_HMIN)
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#define IPL_TDTX (0x14 - IPL_HMIN)
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#define IPL_HMAX 0x17 /* highest hwre level */
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#define IPL_HMIN 0x14 /* lowest hwre level */
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#define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */
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#define IPL_SMAX 0xF /* highest swre level */
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/* Device vectors */
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#define VEC_AUTO (0) /* Assigned by Auto Configure */
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#define VEC_FLOAT (0) /* Assigned by Auto Configure */
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#define VEC_QBUS 1 /* Qbus system */
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#define VEC_SET 0x201 /* Vector bits to set in Qbus vectors */
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/* Interrupt macros */
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#define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)
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#define IREQ(dv) int_req[IPL_##dv]
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#define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)
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#define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)
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#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */
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/* Function prototypes for I/O */
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int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);
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int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);
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int32 Map_WriteB (uint32 ba, int32 bc, const uint8 *buf);
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int32 Map_WriteW (uint32 ba, int32 bc, const uint16 *buf);
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#include "pdp11_io_lib.h"
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extern t_stat sysd_set_halt (UNIT *uptr, int32 val, CONST char *cptr, void *desc);
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extern t_stat sysd_show_halt (FILE *st, UNIT *uptr, int32 val, CONST void *desc);
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/* Function prototypes for system-specific unaligned support */
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int32 ReadIOU (uint32 pa, int32 lnt);
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int32 ReadRegU (uint32 pa, int32 lnt);
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void WriteIOU (uint32 pa, int32 val, int32 lnt);
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void WriteRegU (uint32 pa, int32 val, int32 lnt);
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/* Function prototypes for virtual and physical memory interface (inlined) */
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#include "vax_mmu.h"
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#endif
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