a9fd3dd518
The makefile now works for Linux and most Unix's. However, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.1.2 GRI - Added support for the GRI-99 processor. 1.1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 1.2 3.8-1 1.2.1 SCP and libraries - Added capability to set line connection order for terminal multiplexers. 1.2.2 HP2100 - Added support for 12620A/12936A privileged interrupt fence. - Added support for 12792C eight-channel asynchronous multiplexer. 1.3 3.8-2 1.3.1 SCP and libraries - Added line history capability for *nix hosts. - Added "SHOW SHOW" and "SHOW <dev> SHOW" commands. 1.3.2 1401 - Added "no rewind" option to magtape boot. 1.3.3 PDP-11 - Added RD32 support to RQ - Added debug support to RL 1.3.4 PDP-8 - Added FPP support (many thanks to Rick Murphy for debugging the code) 1.3.5 VAX-11/780 - Added AUTORESTART switch support, and VMS REBOOT command support 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
70 lines
3.7 KiB
Text
70 lines
3.7 KiB
Text
Bugs Found and Fixed During Simulator Debug
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1. CPU: MPY tested sign of AC instead of sign of MQ.
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2. CPU: VLM, VDP, VDH need alternate opcode decode points for large counts.
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3. CPU: STL not in decode table.
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4. CPU: Partial stores lacked initial read in decode table.
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5. CPU: PXD, PCD needed (t_uint64) cast.
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6. CPU: SXD, SCD needed (t_uint64) cast.
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7. CPU: SBM at wrong case offset.
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8. CPU: All transfers used IR<21:35> instead of calculated effective address.
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9. CPU: HPR, TRA need alternate negative opcodes.
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10. CPU: STT missing final write to memory.
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11. IO: Channel output process model incorrect, extensive revision required.
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12. IO: Channel connect test should not test channel state, only connection.
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13. IO: Channel opcode with nostore doesn't increment channel address.
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14. CDR: Card reader missing activate at end of state 2.
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15. SYS: Zero operand instructions printed with trailing space.
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16. CPU: Convert class count bit field start definition incorrect.
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17. CPU: CAQ cut and paste error from CVR.
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18. CPU: Shift count is 8b wide, not 9b.
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19. SYS: Mnemonic is LDQ not LMQ.
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20. SYS: RQL opcode incorrect in symbolic decode table.
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21. CPU: Multi-tag mode stores OR'd value of tags on any index read except normal
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effective address.
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22. CPU: Floating point trap does not write location 0 if trap suppressed.
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23. SYS: TRA instructions should have symbolic class MXN not MXR.
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24. CPU: Floating add instructions test for zero result only if normalization enabled.
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25. CPU: Floating add with unlike signs and equal magnitudes, result sign is sign
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of SR rather than sign of AC.
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26. CPU: Floating multiply does not test spill prior to normalization step.
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27. CPU: Channel activity proceeds under HALT.
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28. MT: Any read error should stop the channel and the tape controller.
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29. MT: EOR write flag cleared before testing.
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39. IO: EOR write flag set after data sent to device.
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40. IO: EOR write flag incorrect set on IOCP, IOCT, IOSP, IOST.
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41. MT: End of file errors not masked on backspace operations.
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42. CPU: LCHx, RCHx miscoded in decode table.
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43. IO: Only 7607 error completions (IOxT without new command) set trap.
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44. CPU: 7067 channel trap flags misdefined with extraneous decrement shift.
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45. CPU: pcq array misdeclared as uint32 instead of uint16.
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46. IO: SDC and SCD tested chan_flags instead of chan_dev.flags.
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47. SYS: 7907 opcodes defined incorrectly.
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48. SYS: TCH not decoding bit<19>.
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49. IO: CTL not clearing EOR after device end.
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50. DSK: Format code not incrementing track in writing all tracks in cylinder.
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51. DSK: THA mode overwrites record structure of first record.
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52. DSK: Write doesn't set channel request for initial word.
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53. DSK: Saved record number was command digits 3..8 instead of 5..10.
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54. CLK: Compute 60th's from location 5, so Chrono clock is in sync with interval clock.
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55. CPU: Enable Chronolog clock if CTSS.
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56. CPU: Read/write protection error not setting protection trap.
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57. CPU: SCHx not setting protection trap in user mode.
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58: CPU: Protection trap overwriting wrong location.
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59. CPU: Stop message reporting physical, not virtual, PC.
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60. IO: Test for "request another cycle" in channel processor was inverted.
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61. IO: Valid bit handling incorrect across multiple transfers.
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62. IO: BSR doesn't set EOF indicator.
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63. IO: 7607 channel modeled incorrectly, could stall.
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64. IO: All 7607 "effective NOP" conditions must be tested when a new command is
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decoded (wc == 0 for IOCx and IOSx, EOR set for IOSx and IORx).
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65. MT: BSR, BSF release the data channel in a few microseconds, like REW.
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66. CPU: Not all PSE and MSE variants are trapped in user mode.
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67. CPU: Storage nullification mask not recalculated at all points needed;
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replaced with macro.
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