1817504052
- removed cycle counting in CPU, the sim_interval issue - fixed the Console multiplexer logic; it now works with SET REMOTE TELNET= and SET CONSOLE TELNET= - commented testhdt.sim - changed run.cmd to try to execute either VStudio or mingw executable, in this order. - changed printf messages to use sim_printf Possible issues remaining: - timer device polling, not yet debugged, the rate of 1.25MHz is likely still incorrect, so UCSD wall clock is surely wrong - few instructions still to be trapped by opcode.debug - I haven't seen them in life code yet - HD device still not yet finished; I'll pick this up again soon
158 lines
3.2 KiB
Text
158 lines
3.2 KiB
Text
;**** some possible debugging options
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;set debug debug.log
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;set debug stdout
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;**** debugging of FDC
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;**** read/write operations, attach&detach, FDC service, IMD handling, DMA/verbose, FDC cmds
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;set fdc debug=read
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;set fdc debug=write
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;set fdc debug=verbose
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;set fdc debug=svc
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;set fdc debug=imd
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;set fdc debug=dma
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;set fdc debug=dmavb
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;set fdc debug=cmd
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;**** debugging of CPU: exceptions, tracing, memory read/write
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;**** opcode fetch, stack push/pull, concurrency
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;set cpu exc
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;set cpu debug=int
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;set cpu debug=trace
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;set cpu debug=write
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;set cpu debug=read
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;set cpu debug=fetch
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;set cpu debug=stack
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;set cpu debug=conc
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;**** debugging of console: read/write to registers
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;set con debug=read
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;set con debug=write
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;**** debugging of timer: read/write, service
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;set tim debug=read
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;set tim debug=write
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;set tim debug=svc
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;**** you should attach a telnet terminal emulator to PDQ-3 console
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;**** to avoid mess with SIMH's control panel
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set console telnet=8000
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;**** you might remote control SIMH's control panel
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;set remote telnet=7000,telnet=buffered
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;**** you need a boot disk
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att fdc0 master.imd
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;**** make this write protected currently while emulator is still being debugged
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set fdc0 wrtlck
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;**** disable the second FDC
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set fdc1 disable
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;************************************************************************
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;**** The following is pure f***ing magic - you must have the source code
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;**** and a commented object dump of boot loader, SYSTEM.PASCAL, SYSTEM.DRIVERS etc.
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; otherwise you won't understand where I had checkpoints for debugging.
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; HDT boot
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;break f418:368
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;break f418:36a
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;break f418:218
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; HDT:bootfd
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;break f418:e0
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; HDT CHK instruction: will fail if CPU serial is > 0x7fff
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;break 2018:067d
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;break 2018:070f
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; entering PASCALSY
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;break eb1e:10
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; problem main loop in syscode1
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;break dc26:1d0a
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;break d488:b1b
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;break d488:b55
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; bug in SPR(4), does not save SP in TIB?
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;break d488:bb8
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;break d488:bc7
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; problem with wait?
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;break d488:0917
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; interrupt debugging
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;break d078:4f
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;break d488:919
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;break d488:ebe
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;break dc26:ec3
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;break d1bd:79
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;break b80d:715
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;break dc26:1d35
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;break d488:806
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;break d488:915
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;break dc26:1d36
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; SHELL handling
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;break badf:98
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;break badf:51
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;break bbd2:1ba
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;break bbd2:1be
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;break bbd2:32a
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; Ser_RawEmit
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;break c964:5f2
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;break d488:d80
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;break c964:6be
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; ticker interrrupts
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;break d078:4f
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;break d1bd:6e
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; Start/Stop Process
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;break d488:7f0
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;break d488:92e
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;break d488:934
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;break d488:958
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;break d488:0dd9
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;break c964:756
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;break c964:a6
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;break c964:cf4
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; waiting for DSR sem
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;break c964:624
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; Ser_Read
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;break c964:466
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;break c964:4f9
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;break c964:4fa
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;break c964:327
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;break c964:59e
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;break c964:323
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;break d078:4c
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;break d078:4f
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;break d1bd:6a
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;break d1bd:6d
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;break d488:ed0
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;****
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;**** end of PFM section
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;************************************************************************
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;**** load the boot PROM code for HD support
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load hdt/CPU_C5.BIN
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;
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;**** set the INIT bit of SSR
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dep _ssr 80
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dep _ses 80
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;**** load some symbolic names for debuging (not needed in production)
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do names.sim
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;**** run
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boot cpu
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;**** reset debug mode to normal when boot fails.
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set debug stdout
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