701f0fe028
1. New Features
1.1 Directory and documentation
- Only common files (SCP and libraries) are in the top level
directory. Individual simulator files are in their individual
directories.
- simh_doc.txt has been split up. simh_doc.txt now documents
only SCP. The individual simulators are documented in separate
text files in their own directories.
- mingw_build.bat is a batch file for the MINGW/gcc environment
that will build all the simulators, assuming the root directory
structure is at c:\sim.
- Makefile is a UNIX make file for the gcc environment that will
build all the simulators, assuming the root directory is at
c:\sim.
1.2 SCP
- DO <file name> executes the SCP commands in the specified file.
- Replicated registers in unit structures can now be declared as
arrays for examine, modify, save, and restore. Most replicated
unit registers (for example, mag tape position registers) have
been changed to arrays.
- The ADD/REMOVE commands have been replaced by SET unit ONLINE
and SET unit OFFLINE, respectively.
- Register names that are unique within an entire simulator do
not have to be prefaced with the device name.
- The ATTACH command can attach files read only, either under
user option (-r), or because the attached file is ready only.
- The SET/SHOW capabilities have been extended. New forms include:
SET <dev> param{=value}{ param ...}
SET <unit> param{=value}{ param ...}
SHOW <dev> {param param ...}
SHOW <unit> {param param ...}
- Multiple breakpoints have been implemented. Breakpoints are
set/cleared/displayed by:
BREAK addr_list{[count]}
NOBREAK addr_list
SHOW BREAK addr_list
1.3 PDP-11 simulator
- Unibus map implemented, with 22b RP controller (URH70) or 18b
RP controller (URH11) (in debug).
- All DMA peripherals rewritten to use map.
- Many peripherals modified for source sharing with VAX.
- RQDX3 implemented.
- Bugs fixed in RK11 and RL11 write check.
1.4 PDP-10 simulator
- ITS 1-proceed implemented.
- Bugs fixed in ITS PC sampling and LPMR
1.5 18b PDP simulator
- Interrupts split out to multiple levels to allow easier
expansion.
1.5 IBM System 3 Simulator
- Written by Charles (Dutch) Owen.
1.6 VAX Simulator (in debug)
- Simulates MicroVAX 3800 (KA655) with 16MB-64MB memory, RQDX3,
RLV12, TSV11, DZV11, LPV11, PCV11.
- CDROM capability has been added to the RQDX3, to allow testing
with VMS hobbyist images.
1.7 SDS 940 Simulator (not tested)
- Simulates SDS 940, 16K-64K memory, fixed and moving head
disk, magtape, line printer, console.
1.8 Altair Z80
- Revised from Charles (Dutch) Owen's original by Peter Schorn.
- MITS 8080 with full Z80 simulation.
- 4K and 8K BASIC packages, Prolog package.
1.9 Interdata
The I4 simulator has been withdrawn for major rework. Look for
a complete 16b/32b Interdata simulator sometime next year.
2. Release Notes
2.1 SCP
SCP now allows replicated registers in unit structures to be
modelled as arrays. All replicated register declarations have
been replaced by register array declarations. As a result,
save files from prior revisions will generate errors after
restoring main memory.
2.2 PDP-11
The Unibus map code is in debug. The map was implemented primarily
to allow source sharing with the VAX, which requires a DMA map.
DMA devices work correctly with the Unibus map disabled.
The RQDX3 simulator has run a complete RSTS/E SYSGEN, with multiple
drives, and booted the completed system from scratch.
2.3 VAX
The VAX simulator will run the boot code up to the >>> prompt. It
can successfully process a SHOW DEVICE command. It runs the HCORE
instruction diagnostic. It can boot the hobbyist CD through SYSBOOT
and through the date/time dialog and restore the hobbyist CD, using
standalone backup. On the boot of the restored disk, it gets to the
date/time dialog, and then crashes.
2.4 SDS 940
The SDS 940 is untested, awaiting real code.
2.5 GCC Optimization
At -O2 and above, GCC does not correctly compile the simulators which
use setjmp-longjmp (PDP-11, PDP-10, VAX). A working hypothesis is
that optimized state maintained in registers is being used in the
setjmp processing routine. On the PDP-11 and PDP-10, all of this
state has been either made global, or volatile, to encourage GCC to
keep the state up to date in memory. The VAX is still vulnerable.
3. Work list
3.1 SCP
- Better ENABLE/DISABLE.
3.2 PDP-11 RQDX3
Software mapped mode, RCT read simulation, VMS debug.
472 lines
16 KiB
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472 lines
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The IBM System/3 simulator is configured as follows:
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CPU 5410 (Model 10) CPU with 64KB of memory.
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PKB 5471 Printer/Keyboard console.
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CDR 1442 Card Reader
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CDP 1442 Card Punch
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CDP2 1442 2nd stacker
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LPT 1403 Line Printer
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R1 5444 Top Drive (removeable)
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F1 5444 Top Drive (fixed)
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R2 5444 Bottom Drive (removeable)
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F2 5444 Bottom Drive (fixed
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The only CPU options are to set Model 15 mode (not implemented), DPF
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(Dual Programming Facility, not implemented), and the memory size 8K, 16K,
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32K, 48K, or 64K.
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CPU registers are the standard System/3 set:
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name size Description
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IAR-P1 16 Instruction Address Register for Program Level 1
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ARR-P2 16 Address Recall Register for Program Level 1
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IAR-P2 16 IAR for Program Level 2 (not implemented)
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ARR-P2 16 ARR for Program Level 2 (not implemented)
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AAR 16 A-Address Register
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BAR 16 B-Address Register
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PSR 16 Program Status Register
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XR1 16 Index Register 1
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XR2 16 Index Register 2
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IAR<0:7> 16 IAR for interrupt level 0 thru 7
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ARR<0:7> 16 ARR for interrupt level 0 thru 7
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Plus these simulator registers:
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IAR 16 Value of last IAR used.
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LEVEL 8 Current operating level (8=P1, 9=P2,
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0 thru 7 = Interrupt level)
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SR 16 Front Panel switches
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INT 16 Interrupt Request Flags
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WRU 8 Simulator Interrupt Character
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BREAK 17 Breakpoint Address
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DEBUG 16 Debugging bits:
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0x01: Write all instructions executed to
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file trace.log.
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0x02: Write details of all Disk I/O
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requests to trace.log.
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0x80: Breakpoint on first character
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written to 5471 printer.
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1 5471 Printer/Keyboard
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This is the operator console. It has the following registers:
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FLAG 5471 Flag Bytes
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IBUF: Input character from keyboard
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OBUF: Output character to printer
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POS: Number of characters printed
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TIME: Delay for device operation
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REQKEY: ASCII value of key mapped to 5471 REQUEST key
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RTNKEY: ASCII value of key mapped to 5471 RETURN key
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ENDKEY: ASCII value of key mapped to 5471 END key
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CANKEY: ASCII value of key mapped to 5471 CANCEL key
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2 1442 Card Reader. This reader reads 80-column cards; the input
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is usually an ASCII file which is translated to EBCDIC when read,
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but optionally can be a binary file in EBCDIC format (such as an
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object program).
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LAST Last card switch
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ERR Card Reader Error
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NOTRDY 1442 reader not ready (not attached or past EOF)
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DAR Data Address Register (shared with punch)
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LCR Length Count Register (shared with punch)
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EBCDIC EBCDIC mode flag: if 1, input is 80-col EBCDIC binary.
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(IPL from 1442 automatically sets this to 1).
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S2 Stacker 2 is selected when this is 1
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POS Number of cards read
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TIME Device Delay
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The real hardware 1442 had only 1 hopper for cards, whether
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these were used for blank cards for punching, or cards to be
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read. Cards could be read without a feed cycle, then
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punched. When punching cards, the SCP does a read of a card,
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makes sure it is blank, and then punches it. To simulate
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this without requiring that a stack of blank lines be attached
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to the card reader device, a special feature of the simulator
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is this: if no file is attached to the cdr device, but a file
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is attached to the cdp or the cdp2 devices, any read from the
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reader will return a blank card -- i.e. when punching, an
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unattached cdr device is assumed to be loaded with an unlimited
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supply of blank cards.
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3 1442 Card Punch. Normally cards are written to the attached
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disk file as ASCII with newline/cr delimiters. But an optional
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flag allows writing as 80-column binary EBCDIC.
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ERR Card Punch Error
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EBCDIC When this is 1, output will be 80-col EBCDIC.
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S2 When this is 1, output is placed in stacker 2
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NOTRDY 1442 punch not ready (not attached)
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DAR Data Address Register (shared with reader)
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LCR Length Count Register (shared with reader)
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POS Number of cards punched
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TIME Device Delay
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4 1442 Stacker 2. When cards are to be punched in stacker 2,
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attach a disk file to this device (cdp2) to hold that output.
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Note: When SCP punches cards, the default is to punch in
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stacker 2.
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POS0 Number of cards punched.
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5 1403 Printer. This is a 132-column output device, emulating
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the famous IBM 1403, models 2, 6, and N1. Output is always
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translated to ASCII with newline/CR delimiters. Page advance
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is output as a form feed.
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ERR 1403 error flags
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LPDAR Data Address Register
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LPFLR Forms Length Register
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LPIAR Image Address Register
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LINECT Current Line on form
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POS Number of lines printed
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6 5444 Disk Drives (R1, R2, F1, F2)
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The 5444 came as a set of two drives, each with two disks. The
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top disk in a drive was removable, the bottom fixed. The first
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drive consists of disks R1 and F1, the second drive R2 and F2.
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Each disk holds 2,467,600 bytes of user data, plus 3 alternate
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tracks and a CE track. Flagging of alternate tracks is not
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supported in this version of the simulator.
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NOTRDY Drive not ready (not attached)
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SEEK Drive is busy with a seek operation
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DAR Data Address Register
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CAR Control Address Register
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ERR Error Flags (16 bits)
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CYL Current Cylinder (0 thru 203)
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HEAD Current head (0 or 1)
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POS Current position in attached disk file
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TIME Device Delay
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7 Symbolic Display and Input
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The System/3 Simulator supports symbolic display and input.
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Display is controlled by command line switches:
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(none) display as hex EBCDIC
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-c display bytes as characters
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-m display instruction mnemonics.
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-a display a 256-byte block of memory in both hex and ASCII.
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The symbolic format contains the same elements as the machine
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language operation, but not always in the same order. The
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operation code frequently specifies both the opcode and the Q byte,
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and the top nybble of the opcode is determined by the format of the
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addresses.
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Addresses take two forms: the direct address in hex, or a relative
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address specified thusly: (byte,XRx) where 'byte' is a 1-byte
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offset, and XRx is either XR1 or XR2 for the two index registers.
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Use these formats when 'address' is indicated below:
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When 'reg' is mentioned, a mnemonic may be used for the register,
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thusly:
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IAR Instruction Address Register for the current program level
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ARR Address Recall Register for the current program level
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P1IAR IAR for Program Level 1
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P2IAR IAR for Program Level 2
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PSR Program Status Register
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XR1 Index Register 1
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XR2 Index Register 2
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IARx IAR for the interrupt level x (x = 0 thru 7)
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All other operands mentioned below are single-byte hex, except for
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the length (len) operand of the two-address instructions, which is a
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decimal length in the range 1-256.
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In operations where there is a source and a destination, the
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destination is always operand 1, the source is operand 2.
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No-address formats:
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------------------
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HPL hex,hex Halt Program Level, the operands are the
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Q and R bytes.
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One-address formats:
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-------------------
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A reg,address Add to register
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CLI address,byte Compare Logical Immediate
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MVI address,byte Move Immediate
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TBF address,mask Test Bits Off
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TBN address,mask Test Bits On
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SBF address,mask Set Bits Off
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SBN address,mask Set Bits On
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ST reg,address Store Register
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L reg,address Load Register
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LA reg,address Load Address (reg can only be XR1 or XR2)
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JC address,cond Jump on Condition
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BC address,cond Branch on Condition
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These operations do not specify a qbyte, it is implicit in the
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opcode:
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B address Unconditional branch to address
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BE address Branch Equal
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BNE address Branch Not Equal
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BH address Branch High
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BNH address Branch Not High
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BL address Branch Low
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BNL address Branch Not Low
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BT address Branch True
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BF address Branch False
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BP address Branch Plus
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BM address Branch Minus
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BNP address Branch Not Plus
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BNM address Branch Not Minus
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BZ address Branch Zero
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BNZ address Branch Not Zero
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BOZ address Branch Overflow Zoned
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BOL address Branch Overflow Logical
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BNOZ address Branch No Overflow Zoned
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BNOL address Branch No Overflow Logical
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NOPB address No - never branch
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(substitute J for B above for a set of Jumps -- 1-byte operand (not
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2), always jumps forward up to 255 bytes from the address following
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the Jump instruction. In this case, 'address' cannot be less than
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the current address, nor greater than the current address + 255)
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Two-address formats (first address is destination, len is decimal 1-256):
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-------------------
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MVC address,address,len Move Characters
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CLC address,address,len Compare Logical Characters
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ALC address,address,len Add Logical Characters
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SLC address,address,len Subtract Logical Characters
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ED address,address,len Edit
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ITC address,address,len Insert and Test Characters
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AZ address,address,len Add Zoned Decimal
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SZ address,address,len Subtract Zoned Decimal
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MNN address,address Move Numeric to Numeric
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MNZ address,address Move Numeric to Zone
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MZZ address,address Move Zone to Zone
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MZN address,address Move Zone to Numeric
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I/O Format
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----------
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In the I/O format, there are always 3 fields:
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da - Device Address 0-15 (decimal)
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m - Modifier 0-1
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n - Function 0-7
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The meaning of these is entirely defined by the device addressed.
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There may be an optional control byte, or an optional address (based
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on the type of instruction).
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SNS da,m,n,address Sense I/O
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LIO da,m,n,address Load I/O
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TIO da,m,n,address Test I/O
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SIO da,m,n,cc Start I/O -- cc is a control byte
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APL da,m,n Advance Program Level
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8 Device Programming.
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Note: On a model 15, interrupts are used for all devices. On
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other models, interrupts are only used for the printer/keyboard.
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This is a summary of the DA, M, N, and CC codes for all supported
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devices:
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5471 Printer Keyboard
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---------------------
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The PKB has 2 visible indicators: Proceed and Request
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Pending. It has a normal keyboard and 4 special keys:
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Request, Return, End, and Cancel.
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SIO 1,0,0,XX Start Keyboard Operation, bit masks for XX are:
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X'20': Request Pending Indicator On
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X'10': Proceed Indicator On
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X'04': Request Key Interrupts Enable (1) Disable (0)
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X'02': Other Key Interrupts Enable (1) Disable (0)
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X'01': Reset request key and other key interrupts
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SIO 1,1,0,XX Start Printer Operation, bit masks for XX are:
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X'80': Start Printing
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X'40': Start Carrier Return
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X'04': Printer Interrupt Enable(1) or Disable (0)
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X'01': Reset Printer Interrupt
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LIO 1,1,0,addr Load Printer Output Character
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addr is address of low-order (highest numbered)
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byte of two-byte field, and high-order byte
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(that is, addr - 1) is loaded into output
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register to print. Printing is done one character
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at a time.
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SNS 1,0,1,addr Sense Status Bytes 0 and 1:
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Byte 0 (leftmost) is the character typed in
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in EBCDIC.
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Byte 1 is status:
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X'80': Request key interrupt pending
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X'40': End or Cancel key interrupt pending
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X'20': Cancel key pressed
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X'10': End Key Pressed
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X'08': Return or data key interrupt pending
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X'04': Return key pressed
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SNS 1,0,3,addr Sense Status Bytes 2 and 3: returns 0000 in
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this sim.
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1442 Reader/Punch
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-----------------
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SIO 5,0,0,XX Feed Card without reading/punching
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XX is stacker select for all functions: 0 = stacker
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1 (normal), 1 = stacker 2.
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SIO 5,0,1,XX Read Card
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SIO 5,0,2,XX Punch and Feed
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SIO 5,0,3,XX Read Column Binary
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SIO 5,0,4,XX Punch with no feed
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TIO 5,0,0,addr Branch to addr if not ready or busy
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TIO 5,0,2,addr Branch to addr if busy
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TIO 5,0,5,addr (mod 15 only) branch if interrupt pending
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APL 5,0,0 Loop (or switch prog levels) if not ready/busy
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APL 5,0,2 Loop (or switch) if busy
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APL 5,0,5 Loop (or switch) if interrupt pending (mod 15 only)
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LIO 5,0,0,addr Load 2-byte field to Length Count Register
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LIO 5,0,4,addr Load 2-byte field to Data Address Register
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(DAR is incremented by a read/punch operation and must
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be reset every card)
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SNS 5,0,1,addr Sense CE indicators (0000 returned in this sim)
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SNS 5,0,2,addr Sense CE indicators (0000 returned in this sim)
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SNS 5,0,3,addr Sense Status Indicators: (only simulated bits shown)
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X'8000': Read Check
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X'4000': Last Card
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X'2000': Punch Check
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X'1000': Data Overrun
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X'0800': Not Ready
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1403 Printer
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------------
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SIO 14,0,0,XX Line space XX lines (0-3 valid in XX)
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SIO 14,0,2,XX Print a line space (0-3 valid in XX)
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SIO 14,0,4,XX Skip Only (line number 1-112 in XX)
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SIO 14,0,6,XX Print and Skip (line number 0-112 in XX)
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TIO 14,0,0,addr Branch to addr if not ready
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TIO 14,0,2,addr Branch to addr if buffer busy
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TIO 14,0,3,addr Branch to addr if interrupt pending (mod 15 only)
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TIO 14,0,4,addr Branch if carriage busy
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TIO 14,0,6,addr Branch if printer busy
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APL 14,0,0 Loop (or switch prog levels) if not ready/check
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APL 14,0,2 Loop (or switch) if buffer busy
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APL 14,0,3 Loop (or switch) if interrupt pending (mod 15 only)
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APL 14,0,4 Loop (or switch) if carriage busy
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APL 14,0,6 Loop (or switch) if printer busy
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LIO 14,0,0,addr Load 1 byte to Forms Length Reg at addr-1
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LIO 14,0,4,addr Load 2 bytes to Chain Image Address Register
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LIO 14,0,6,addr Load 2 bytes to Data Address Register
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SNS 14,0,0,addr Sense Character Count
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SNS 14,0,4,addr Sense LPIAR (Image Address Register)
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SNS 14,0,6,addr Sense LPDAR (data addres register)
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5444 Disk Drives
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----------------
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Each drive has two disks (upper and lower), each disk
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has two surfaces (upper and lower), each surface has
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24 256-byte sectors, sectors are number 0 thru 23 on
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upper surface, 32 thru 55 on lower.
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d = drive, 0 is R1/F1, 1 is R2/F2
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s = surface, 0 = upper (removable), 1 = lower (fixed)
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The Control register points to the leftmost byte of a 4-byte
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control field in memory with these bytes:
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F - Flag byte (not supported in this sim)
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C - Cylinder Address (0-203)
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S - Sector Number (0-23, or 32-55) in top 6 bits
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N - Number of sectors minus 1
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These have meaning for all operations except seek, seek uses
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the fields differently.
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SIO 1d,s,0,XX Seek, XX not used, control field is used:
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F - not used
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C - not used
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S - high bit is head to be used 0-upper 1-lower
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low bit is direction to move 0-back 1-forward
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N - number of cylinders to move
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SIO 1d,s,1,XX Read, values of XX are as follows:
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X'00': Read Data
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X'01': Read Identifier (updates control field, no
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data is read)
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X'02': Read Data Diagnostic
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X'03': Verify (does not read, but checks)
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SIO 1d,s,2,XX Write, values of XX are as follows:
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X'00': Write Data
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X'01': Write Identifier (24 sectors with byte at
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data address register)
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SIO 1d,s,3,XX Scan. All 256 bytes in memory at data
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address register are compared to disk
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sectors on current track, except those
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bytes of X'FF' are not compared. Values of
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XX are:
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X'00': Scan Equal
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X'01': Scan Low or Equal
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X'02': Scan High or Equal
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LIO 1d,0,4,addr Load Data Address Register
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LIO 1d,0,6,addr Load Disk Control Address Register
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TIO 1d,0,0,addr Branch if not ready/unit check
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TIO 1d,0,2,addr Branch if busy
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TIO 1d,0,4,addr Branch if Scan Found
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APL 1d,0,0 Loop if not ready/unit check
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APL 1d,0,2 Loop if busy
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APL 1d,0,4 Loop if scan found
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SNS 1d,0,2,addr Sense Status Bytes 0 and 1: (simulated
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bits only are shown, otehrs are 0):
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X'1000': equipment check
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X'0800': data check
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X'0400': No record found
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X'0100': Seek Check (past cyl 203)
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X'0080': Scan equal Hit
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X'0040': Cylinder 0
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X'0020': End of Cylinder
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X'0010': Seek Busy
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SNS 1d,0,3,addr Sense bytes 2 and 3 (0000 in this sim)
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SNS 1d,0,4,addr Sense Data Address Register
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SNS 1d,0,6,addr Sense Control Address Register
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