433 lines
16 KiB
C
433 lines
16 KiB
C
/*************************************************************************
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* *
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* Copyright (c) 2009-2022 Howard M. Harte. *
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* https://github.com/hharte *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining *
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* a copy of this software and associated documentation files (the *
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* "Software"), to deal in the Software without restriction, including *
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* without limitation the rights to use, copy, modify, merge, publish, *
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* distribute, sublicense, and/or sell copies of the Software, and to *
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* permit persons to whom the Software is furnished to do so, subject to *
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* the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be *
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* included in all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON- *
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* INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE *
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN *
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN *
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE *
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* SOFTWARE. *
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* *
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* Except as contained in this notice, the names of The Authors shall *
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* not be used in advertising or otherwise to promote the sale, use or *
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* other dealings in this Software without prior written authorization *
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* from the Authors. *
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* *
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* Module Description: *
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* TX-0 simulator interface: 4-bit opcode with index register. *
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* *
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*************************************************************************/
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#include "tx0_defs.h"
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#include <ctype.h>
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extern DEVICE cpu_dev;
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extern DEVICE petr_dev;
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extern DEVICE tto_dev;
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extern DEVICE tti_dev;
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extern DEVICE ptp_dev;
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#ifdef USE_DISPLAY
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extern DEVICE dpy_dev;
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#endif /* USE_DISPLAY */
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#ifdef USE_FPC
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extern DEVICE fpc_dev;
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#endif /* USE_FPC */
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extern UNIT cpu_unit;
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extern REG cpu_reg[];
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extern int32 M[];
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extern int32 PC;
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extern int32 ascii_to_flexo[], flexo_to_ascii[];
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extern int32 sc_map[];
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/* SCP data structures and interface routines
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sim_name simulator name string
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sim_PC pointer to saved PC register descriptor
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sim_emax number of words for examine
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sim_devices array of pointers to simulated devices
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sim_stop_messages array of pointers to stop messages
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sim_load binary loader
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*/
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char sim_name[] = "TX-0";
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REG *sim_PC = &cpu_reg[0];
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int32 sim_emax = 1;
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DEVICE *sim_devices[] = {
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&cpu_dev,
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&petr_dev,
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&tti_dev,
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&tto_dev,
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&ptp_dev,
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#ifdef USE_DISPLAY
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&dpy_dev,
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#endif/* USE_DISPLAY */
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#ifdef USE_FPC
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&fpc_dev,
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#endif /* USE_FPC */
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NULL
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};
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const char *sim_stop_messages[SCPE_BASE] = {
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"Unknown error",
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"Undefined instruction",
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"HALT instruction",
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"Breakpoint",
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"Nested XCT's",
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"Nested indirect addresses",
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"Infinite I/O wait state",
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"DECtape off reel"
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};
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int32 tx0_getw (FILE *inf)
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{
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int32 i, tmp, word;
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word = 0;
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for (i = 0; i < 3;) {
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if ((tmp = getc (inf)) == EOF) return -1;
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if (tmp & 0200) {
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word = (word << 6) | (tmp & 077);
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i++;
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}
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}
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return word;
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}
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/* Symbol tables */
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typedef struct {
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int32 opr;
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const char *mnemonic;
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const char *desc;
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} OPMAP;
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typedef struct {
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const char *mnemonic;
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const char *desc;
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} INSTMAP;
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const INSTMAP instmap[] = {
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/* Store Class */
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{ "sto", "Store AC" },
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{ "stx", "Store AC, Indexed" },
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{ "sxa", "Store XR in Address" },
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{ "ado", "Add One" },
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{ "slr", "Store LR" },
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{ "slx", "Store LR, Indexed" },
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{ "stz", "Store Zero" },
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{ "[!sto-nop]", "NOP" },
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/* Add Class */
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{ "add", "Add" },
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{ "adx", "Add, Indexed" },
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{ "ldx", "Load XR" },
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{ "aux", "Augment XR" },
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{ "llr", "Load LR" },
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{ "llx", "Load LR, Indexed" },
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{ "lda", "Load AC" },
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{ "lax", "Load AC, Indexed" },
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/* Transfer Class */
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{ "trn", "Transfer Negative" },
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{ "trz", "Transfer +/- Zero" },
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{ "tsx", "Transfer and set Index" },
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{ "tix", "Transfer and Index" },
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{ "tra", "Transfer" },
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{ "trx", "Transfer Indexed" },
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{ "tlv", "Transfer on external Level" },
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{ "[!tra-nop]", "NOP" }
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};
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const OPMAP opmap [] = {
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{ 0600000, "opr", "No operation" },
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{ 0600001, "xro", "Clear XR to +0" },
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{ 0600003, "lxr", "Place LR in XR" },
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{ 0600012, "cry", "Carry the contents of AC according to bits of LR" },
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{ 0600022, "lpd", "Logical exclusive or of AC is placed in AC (partial add)" },
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{ 0600032, "lad", "Add LR to AC" },
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{ 0600040, "com", "Compliment the AC" },
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{ 0600072, "lcd", "Contents of LR minus those of AC are placed in AC" },
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{ 0600130, "xad", "Add index register to accumulator" },
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{ 0600170, "xcd", "Contents of XR minus those of AC are placed in AC" },
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{ 0600200, "lro", "Clear LR to +0" },
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{ 0600300, "xlr", "Place XR in LR" },
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{ 0600303, "ixl", "Interchange XR and LR" },
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{ 0600400, "shr", "Shift accumulator right one place, bit 0 remains unchanged" },
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{ 0600600, "cyr", "Cycle AC right one place" },
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{ 0603000, "pen", "Contents of light pen and light cannon flip-flops replace contents of AC bits 0 and 1. The flip-flops are cleared." },
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{ 0604000, "bsr", "Backspace tape unit by one record" },
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{ 0604004, "rtb", "Read tape binary (odd parity)" },
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{ 0604004, "rds", "Select tape unit for reading a record" },
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{ 0604010, "rew", "Rewind tape unit" },
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{ 0604014, "wtb", "Write tape binary (odd parity)" },
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{ 0604014, "wrs", "Select tape unit for writing a record" },
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{ 0604024, "rtd", "Read tape decimal (even parity)" },
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{ 0604034, "wtd", "Write tape decimal (even parity)" },
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{ 0607000, "cpf", "The program flag is cleared" },
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{ 0620000, "cpy", "Transmit information between the live register and selected input-output unit" },
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{ 0622000, "dis", "Display point on CRT corresponding to contents of AC" },
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{ 0624000, "prt", "Print one on-line flexo character from bits 2, 5, etc." },
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{ 0624600, "pnt", "PRT, then cycle AC right once to set up another character" },
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{ 0625000, "typ", "Read one character from on-line flexowriter into LR bits 12-17" },
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{ 0626600, "p6h", "Punch one line of paper tape; 6 holes from bits 2, 5, etc. of AC then cycle right once." },
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{ 0627600, "p7h", "Same as p6h, but punch 7th hole" },
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{ 0630000, "hlt", "Stops computer" },
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{ 0631000, "cll", "Clear left half of AC to zero" },
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{ 0632000, "clr", "Clear right half of AC" },
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{ 0632022, "---", "CLR+PAD+LMB" },
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{ 0640001, "axr", "Place AC contents in XR" },
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{ 0640021, "axo", "AXR, then set AC to +0" },
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{ 0640030, "cyl", "Cycle AC left one place" },
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{ 0640031, "alx", "AXR, then cycle AC left once" },
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{ 0640040, "amz", "Add minus zero to AC" },
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{ 0640061, "axc", "AXR, then set AC to -0" },
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{ 0640200, "alr", "Place accumulator contents in live register" },
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{ 0640201, "---", "ALR+MBX, Place accumulator contents in live register, Transfer MBR to XR." },
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{ 0640203, "rax", "Place LR in XR, then place AC in LR" },
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{ 0640205, "orl", "Logical or of AC and LR is placed in LR" },
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{ 0640207, "anl", "Logical and of AC and LR is placed in LR" },
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{ 0640220, "alo", "ALR, then set AC to +0" },
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{ 0640230, "all", "ALR, then cycle left once" },
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{ 0640231, "---", "AMB+MBL+PAD+CRY+MBX" },
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{ 0640232, "iad", "Interchange and add AC contents are placed in the LR and the previous contents of the LR ar added to AC" },
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{ 0640260, "alc", "ALR, then set AC to -0" },
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{ 0640601, "arx", "AXR, then cycle AC right once" },
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{ 0647000, "spf", "Place AC in program flag register" },
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{ 0662020, "dso", "DIS, then clear AC" },
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{ 0664020, "pno", "PRT, then clear AC" },
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{ 0664060, "pnc", "PRT, then clear AC to -0" },
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{ 0666020, "p6o", "p6h then clear AC" },
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{ 0667020, "p7o", "p7h then clear AC" },
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{ 0700000, "cla", "Clear entire AC to +0" },
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{ 0700001, "cax", "Clear AC and XR to +0" },
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{ 0700012, "lal", "Place LR in AC cycled left once" },
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{ 0700022, "lac", "Place LR in AC" },
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{ 0700040, "clc", "Clear and complement: set AC to -0" },
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{ 0700062, "lcc", "Place complement of LR in AC" },
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{ 0700072, "laz", "Add LR to minus zero in AC" },
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{ 0700110, "xal", "XAC, then cycle AC left once" },
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{ 0700120, "xac", "Place index register in accumulator" },
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{ 0700160, "xcc", "Place complement of XR in accumulator" },
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{ 0700200, "cal", "Clear AC and LR to +0" },
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{ 0700322, "rxe", "Place LR in AC, then place XR in LR" },
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{ 0700622, "lar", "Place LR in AC cycled right once" },
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{ 0701000, "tac", "Contents of test accumulator are placed in AC" },
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{ 0702020, "tbr", "Contents of test buffer register are placed in AC" },
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{ 0703000, "---", "Clear AC and read light pen" },
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{ 0706020, "rpf", "The program flag register is placed in AC" },
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{ 0721000, "rlc", "Read one line paper tape into AC bits 0, 3, etc." },
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{ 0721600, "rlr", "rlc, then cycle AC right once" },
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{ 0723000, "r3c", "Read three lines of paper tape" },
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{ 0723032, "---", "R3C+LMB+PAD+CRY" },
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{ 0726000, "p6a", "Clear AC and punch a line of blank tape" },
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{ 0740025, "ora", "Logical or of AC and LR is placed in AC" },
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{ 0740027, "ana", "Logical and of AC and LR is placed in AC" },
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{ 0740207, "anc", "ANL, then clear AC" },
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{ 0740205, "oro", "ORL, then clear AC" },
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{ 0740222, "ial", "Interchange AC and LR" },
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{ 0763232, "---", "AMB+CLA+R3L+MBL+LMB+PAD+CRY" },
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{ 0766020, "p6b", "Punch a line of blank tape, but save AC" },
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{ 0000000, NULL, NULL }
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};
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/* Symbolic decode
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Inputs:
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*of = output stream
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addr = current PC
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*val = pointer to values
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*uptr = pointer to unit
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sw = switches
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Outputs:
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return = status code
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*/
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#define FMTASC(x) ((x) < 040)? "<%03o>": "%c", (x)
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#define SIXTOASC(x) flexo_to_ascii[x]
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#define ASCTOSIX(x) (ascii_to_flexo[x] & 077)
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extern int32 cpu_get_mode (void);
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extern t_stat fprint_sym_orig (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw);
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t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,
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UNIT *uptr, int32 sw)
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{
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int32 i, inst, op;
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if(!cpu_get_mode()) {
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return fprint_sym_orig (of, addr, val, uptr, sw);
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}
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inst = val[0];
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if (sw & SWMASK ('A')) { /* ASCII? */
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if (inst > 0377) return SCPE_ARG;
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fprintf (of, FMTASC (inst & 0177));
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return SCPE_OK;
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}
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if (sw & SWMASK ('F')) {
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fputc (flexo_to_ascii[inst & 077], of);
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return SCPE_OK;
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}
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if (sw & SWMASK ('C')) { /* character? */
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fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077));
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fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));
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fprintf (of, "%c", SIXTOASC (inst & 077));
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return SCPE_OK;
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}
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if (!(sw & SWMASK ('M'))) return SCPE_ARG;
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/* Instruction decode */
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op = (inst >> 13) & 037;
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if ((op & 030) != 030) /* sto, add, trn (not an opr) */
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{
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fprintf (of, "%s %05o (%s)", instmap[op].mnemonic, inst & 017777, instmap[op].desc);
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} else { /* opr */
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for(i=0;opmap[i].opr != 0;i++) {
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if(inst == opmap[i].opr) {
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fprintf (of, "opr %s (%s)", opmap[i].mnemonic, opmap[i].desc);
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}
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}
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}
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return SCPE_OK;
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}
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/* Get 18b signed number
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Inputs:
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*cptr = pointer to input string
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*sign = pointer to sign
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*status = pointer to error status
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Outputs:
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val = output value
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*/
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t_value get_sint (char *cptr, int32 *sign, t_stat *status)
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{
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*sign = 1;
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if (*cptr == '+') {
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*sign = 0;
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cptr++;
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}
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else if (*cptr == '-') {
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*sign = -1;
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cptr++;
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}
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return get_uint (cptr, 8, DMASK, status);
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}
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/* Symbolic input
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Inputs:
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*cptr = pointer to input string
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addr = current PC
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uptr = pointer to unit
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*val = pointer to output values
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sw = switches
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Outputs:
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status = error status
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*/
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t_stat parse_sym (CONST char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)
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{
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#if 0
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int32 cflag, d, i, j, k, sign;
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t_stat r;
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static int32 sc_enc[10] = { 0, 01, 03, 07, 017, 037, 077, 0177, 0377, 0777 };
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char gbuf[CBUFSIZE];
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cflag = (uptr == NULL) || (uptr == &cpu_unit);
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while (isspace (*cptr)) cptr++;
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for (i = 1; (i < 3) && (cptr[i] != 0); i++)
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if (cptr[i] == 0) for (j = i + 1; j <= 3; j++) cptr[j] = 0;
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if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */
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if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
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val[0] = (t_value) cptr[0];
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return SCPE_OK;
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}
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if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */
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if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */
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val[0] = ((ASCTOSIX (cptr[0]) & 077) << 12) |
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((ASCTOSIX (cptr[1]) & 077) << 6) |
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(ASCTOSIX (cptr[2]) & 077);
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return SCPE_OK;
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}
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cptr = get_glyph (cptr, gbuf, 0); /* get opcode */
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for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;
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if (opcode[i] == NULL) return SCPE_ARG;
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val[0] = opc_val[i] & DMASK; /* get value */
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j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */
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switch (j) { /* case on class */
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case I_V_LAW: /* LAW */
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cflag = 0; /* fall through */
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case I_V_MRF: case I_V_MRI: /* mem ref */
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cptr = get_glyph (cptr, gbuf, 0); /* get next field */
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if ((j != I_V_MRI) && strcmp (gbuf, "I") == 0) { /* indirect? */
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val[0] = val[0] | IA;
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cptr = get_glyph (cptr, gbuf, 0);
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}
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d = get_uint (gbuf, 8, AMASK, &r);
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if (r != SCPE_OK) return SCPE_ARG;
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if (d <= DAMASK) val[0] = val[0] | d;
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else if (cflag && (((addr ^ d) & EPCMASK) == 0))
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val[0] = val[0] | (d & DAMASK);
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else return SCPE_ARG;
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break;
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case I_V_SHF: /* shift */
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cptr = get_glyph (cptr, gbuf, 0);
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d = get_uint (gbuf, 10, 9, &r);
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if (r != SCPE_OK) return SCPE_ARG;
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val[0] = val[0] | sc_enc[d];
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break;
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case I_V_NPN: case I_V_IOT:
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case I_V_OPR: case I_V_SKP: case I_V_SPC:
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for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;
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cptr = get_glyph (cptr, gbuf, 0)) {
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for (i = 0; (opcode[i] != NULL) &&
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(strcmp (opcode[i], gbuf) != 0); i++) ;
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if (opcode[i] != NULL) {
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k = opc_val[i] & DMASK;
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if ((k != IA) && (((k ^ val[0]) & 0760000) != 0))
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return SCPE_ARG;
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val[0] = val[0] | k;
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}
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else {
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d = get_sint (gbuf, &sign, &r);
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if (r != SCPE_OK) return SCPE_ARG;
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if (sign == 0) val[0] = val[0] + d;
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else if (sign < 0) val[0] = val[0] - d;
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else val[0] = val[0] | d;
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}
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}
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break;
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} /* end case */
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if (*cptr != 0) return SCPE_ARG; /* junk at end? */
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#endif
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return SCPE_ARG;
|
|
}
|